forked from Minki/linux
arm64 fixes:
- Errata workarounds for Cortex-A510: broken hardware dirty bit management, detection code for the TRBE (tracing) bugs with the actual fixes going in via the CoreSight tree. - Cortex-X2 errata handling for TRBE (inheriting the workarounds from Cortex-A710). - Fix ex_handler_load_unaligned_zeropad() to use the correct struct members. - A couple of kselftest fixes for FPSIMD. - Silence the vdso "no previous prototype" warning. - Mark start_backtrace() notrace and NOKPROBE_SYMBOL. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAmH0PzkACgkQa9axLQDI XvHzjg//SNFO0czvwEgV2vwazoCNoxMLQ/FnbjqhuSrGlbChXafaAxt0/FmHIUHn NYF576mpSyu5Rr+/WD2VnbMUrsWVO62B1iAJVOolZZW8FeT2l9rcObkxROzGFzyC WqBobdRii9vhMr6Z4rtgXqJYVIDh+SIXp6K+sgWYrfuph/y352F0/fs+kFea/ZjW OeDBI6EOEcZQFt0breZnNzQRt8wipJ++sB/DjwgCOylVRSAeU215Sc6Kr2Zj4ZuN EGE4AZQNe1/FIeSYKUSQh86Mo6grQSnDc65j8xPQmvWTxftyjiJNH2HflhXsRKMy XMWlDdNtSv3fl02CZyQcgWERRlO8MgK33YG6QLrTErAGXGEYWorSPtDsd5vdVbuK BCycx04wgrMKT02GL40XJOtBlWA5UjEJDciOMLKSTbMjXFT8wCOSr5MeuoD5dBg3 Ux3AIe/ZJBXaQmu86rBErrzQtdXs+h1ozk185GtVbaYdeDdH8wi8Ru+2OIHcly7O 3tmHWT7cqf6vP5PHUq2gTdXWam3wzhVO7kszgh50h/QyW89h3VFoeFdBktd4Fgk1 vKz1gzbGaZqaTWxBUJJEyKyhlnQvKPDMEdqMsOQXAWDthbfMFQHmaJjSJPb89vVF jS3hSHE8XB+l9HFrXDVARCbeOt2rK9oWQC1voUBZHl4JE3J9zhY= =D11O -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Catalin Marinas: - Errata workarounds for Cortex-A510: broken hardware dirty bit management, detection code for the TRBE (tracing) bugs with the actual fixes going in via the CoreSight tree. - Cortex-X2 errata handling for TRBE (inheriting the workarounds from Cortex-A710). - Fix ex_handler_load_unaligned_zeropad() to use the correct struct members. - A couple of kselftest fixes for FPSIMD. - Silence the vdso "no previous prototype" warning. - Mark start_backtrace() notrace and NOKPROBE_SYMBOL. * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: cpufeature: List early Cortex-A510 parts as having broken dbm kselftest/arm64: Correct logging of FPSIMD register read via ptrace kselftest/arm64: Skip VL_INHERIT tests for unsupported vector types arm64: errata: Add detection for TRBE trace data corruption arm64: errata: Add detection for TRBE invalid prohibited states arm64: errata: Add detection for TRBE ignored system register writes arm64: Add Cortex-A510 CPU part definition arm64: extable: fix load_unaligned_zeropad() reg indices arm64: Mark start_backtrace() notrace and NOKPROBE_SYMBOL arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges arm64: Add Cortex-X2 CPU part definition arm64: vdso: Fix "no previous prototype" warning
This commit is contained in:
Linus Torvalds
commit
216e2aede2
@ -52,6 +52,12 @@ stable kernels.
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| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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@ -92,12 +98,18 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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@ -670,15 +670,25 @@ config ARM64_ERRATUM_1508412
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config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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bool
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config ARM64_ERRATUM_2051678
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bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
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help
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This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
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Affected Coretex-A510 might not respect the ordering rules for
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hardware update of the page table's dirty bit. The workaround
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is to not enable the feature on affected CPUs.
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If unsure, say Y.
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config ARM64_ERRATUM_2119858
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bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
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bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
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default y
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depends on CORESIGHT_TRBE
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select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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help
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This option adds the workaround for ARM Cortex-A710 erratum 2119858.
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This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
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Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
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Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
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data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
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the event of a WRAP event.
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@ -761,14 +771,14 @@ config ARM64_ERRATUM_2253138
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If unsure, say Y.
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config ARM64_ERRATUM_2224489
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bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
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bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
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depends on CORESIGHT_TRBE
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default y
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select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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help
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This option adds the workaround for ARM Cortex-A710 erratum 2224489.
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This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
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Affected Cortex-A710 cores might write to an out-of-range address, not reserved
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Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
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for TRBE. Under some conditions, the TRBE might generate a write to the next
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virtually addressed page following the last page of the TRBE address space
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(i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
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@ -778,6 +788,65 @@ config ARM64_ERRATUM_2224489
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If unsure, say Y.
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config ARM64_ERRATUM_2064142
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bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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default y
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help
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This option adds the workaround for ARM Cortex-A510 erratum 2064142.
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Affected Cortex-A510 core might fail to write into system registers after the
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TRBE has been disabled. Under some conditions after the TRBE has been disabled
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writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
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and TRBTRG_EL1 will be ignored and will not be effected.
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Work around this in the driver by executing TSB CSYNC and DSB after collection
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is stopped and before performing a system register write to one of the affected
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registers.
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If unsure, say Y.
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config ARM64_ERRATUM_2038923
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bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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default y
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help
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This option adds the workaround for ARM Cortex-A510 erratum 2038923.
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Affected Cortex-A510 core might cause an inconsistent view on whether trace is
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prohibited within the CPU. As a result, the trace buffer or trace buffer state
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might be corrupted. This happens after TRBE buffer has been enabled by setting
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TRBLIMITR_EL1.E, followed by just a single context synchronization event before
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execution changes from a context, in which trace is prohibited to one where it
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isn't, or vice versa. In these mentioned conditions, the view of whether trace
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is prohibited is inconsistent between parts of the CPU, and the trace buffer or
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the trace buffer state might be corrupted.
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Work around this in the driver by preventing an inconsistent view of whether the
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trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
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change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
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two ISB instructions if no ERET is to take place.
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If unsure, say Y.
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config ARM64_ERRATUM_1902691
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bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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default y
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help
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This option adds the workaround for ARM Cortex-A510 erratum 1902691.
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Affected Cortex-A510 core might cause trace data corruption, when being written
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into the memory. Effectively TRBE is broken and hence cannot be used to capture
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trace data.
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Work around this problem in the driver by just preventing TRBE initialization on
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affected cpus. The firmware must have disabled the access to TRBE for the kernel
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on such implementations. This will cover the kernel for any firmware that doesn't
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do this already.
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If unsure, say Y.
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config CAVIUM_ERRATUM_22375
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bool "Cavium erratum 22375, 24313"
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default y
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@ -73,7 +73,9 @@
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#define ARM_CPU_PART_CORTEX_A76 0xD0B
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#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
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#define ARM_CPU_PART_CORTEX_A77 0xD0D
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#define ARM_CPU_PART_CORTEX_A510 0xD46
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#define ARM_CPU_PART_CORTEX_A710 0xD47
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#define ARM_CPU_PART_CORTEX_X2 0xD48
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#define ARM_CPU_PART_NEOVERSE_N2 0xD49
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#define APM_CPU_PART_POTENZA 0x000
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@ -115,7 +117,9 @@
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#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
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#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
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#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
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#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
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#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
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#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
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#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2119858
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
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#endif
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{},
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};
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@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = {
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2224489
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
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#endif
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{},
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};
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@ -597,6 +599,33 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
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CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2064142
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{
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.desc = "ARM erratum 2064142",
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.capability = ARM64_WORKAROUND_2064142,
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/* Cortex-A510 r0p0 - r0p2 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2038923
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{
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.desc = "ARM erratum 2038923",
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.capability = ARM64_WORKAROUND_2038923,
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/* Cortex-A510 r0p0 - r0p2 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1902691
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{
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.desc = "ARM erratum 1902691",
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.capability = ARM64_WORKAROUND_1902691,
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/* Cortex-A510 r0p0 - r0p1 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
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},
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#endif
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{
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}
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@ -1645,6 +1645,9 @@ static bool cpu_has_broken_dbm(void)
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
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/* Kryo4xx Silver (rdpe => r1p0) */
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MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2051678
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MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
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#endif
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{},
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};
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@ -33,8 +33,8 @@
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*/
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static void start_backtrace(struct stackframe *frame, unsigned long fp,
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unsigned long pc)
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static notrace void start_backtrace(struct stackframe *frame, unsigned long fp,
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unsigned long pc)
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{
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frame->fp = fp;
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frame->pc = pc;
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@ -55,6 +55,7 @@ static void start_backtrace(struct stackframe *frame, unsigned long fp,
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frame->prev_fp = 0;
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frame->prev_type = STACK_TYPE_UNKNOWN;
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}
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NOKPROBE_SYMBOL(start_backtrace);
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/*
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* Unwind from one frame record (A) to the next frame record (B).
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@ -29,8 +29,11 @@ ldflags-y := -shared -soname=linux-vdso.so.1 --hash-style=sysv \
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ccflags-y := -fno-common -fno-builtin -fno-stack-protector -ffixed-x18
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ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO
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# -Wmissing-prototypes and -Wmissing-declarations are removed from
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# the CFLAGS of vgettimeofday.c to make possible to build the
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# kernel with CONFIG_WERROR enabled.
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CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) -Os $(CC_FLAGS_SCS) $(GCC_PLUGINS_CFLAGS) \
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$(CC_FLAGS_LTO)
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$(CC_FLAGS_LTO) -Wmissing-prototypes -Wmissing-declarations
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KASAN_SANITIZE := n
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KCSAN_SANITIZE := n
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UBSAN_SANITIZE := n
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@ -40,8 +40,8 @@ static bool
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ex_handler_load_unaligned_zeropad(const struct exception_table_entry *ex,
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struct pt_regs *regs)
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{
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int reg_data = FIELD_GET(EX_DATA_REG_DATA, ex->type);
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int reg_addr = FIELD_GET(EX_DATA_REG_ADDR, ex->type);
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int reg_data = FIELD_GET(EX_DATA_REG_DATA, ex->data);
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int reg_addr = FIELD_GET(EX_DATA_REG_ADDR, ex->data);
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unsigned long data, addr, offset;
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addr = pt_regs_read_reg(regs, reg_addr);
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@ -55,6 +55,9 @@ WORKAROUND_1418040
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WORKAROUND_1463225
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WORKAROUND_1508412
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WORKAROUND_1542419
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WORKAROUND_2064142
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WORKAROUND_2038923
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WORKAROUND_1902691
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WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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WORKAROUND_TSB_FLUSH_FAILURE
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WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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@ -261,7 +261,7 @@ static void ptrace_sve_fpsimd(pid_t child, const struct vec_type *type)
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}
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ksft_test_result((sve->flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD,
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"Set FPSIMD registers via %s\n", type->name);
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"Got FPSIMD registers via %s\n", type->name);
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if ((sve->flags & SVE_PT_REGS_MASK) != SVE_PT_REGS_FPSIMD)
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goto out;
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@ -557,7 +557,14 @@ static int do_parent(pid_t child)
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}
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/* prctl() flags */
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ptrace_set_get_inherit(child, &vec_types[i]);
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if (getauxval(vec_types[i].hwcap_type) & vec_types[i].hwcap) {
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ptrace_set_get_inherit(child, &vec_types[i]);
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} else {
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ksft_test_result_skip("%s SVE_PT_VL_INHERIT set\n",
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vec_types[i].name);
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ksft_test_result_skip("%s SVE_PT_VL_INHERIT cleared\n",
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vec_types[i].name);
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}
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/* Step through every possible VQ */
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for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; vq++) {
|
||||
|
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Loading…
Reference in New Issue
Block a user