leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge tag 'drm-intel-next-fixes-2022-03-24' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Browse Source 
- Reject unsupported TMDS rates on ICL+ (Ville Syrjälä)
- Treat SAGV block time 0 as SAGV disabled (Ville Syrjälä)
- Fix PSF GV point mask when SAGV is not possible (Ville Syrjälä)
- Fix renamed INTEL_INFO->media.arch/ver field (Lucas De Marchi)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YjwvgGzYNAX5rxHN@tursulin-mobl2
This commit is contained in:
Dave Airlie
2022-03-25 09:44:16 +10:00
parent c6e90a1c66 00f4150d27
commit 21050a39a3
4 changed files with 18 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/display/intel_bw.c
View File

@@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
* cause. * cause.
*/ */
if (!intel_can_enable_sagv(dev_priv, new_bw_state)) { if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
allowed_points = BIT(max_bw_point); allowed_points &= ADLS_PSF_PT_MASK;
allowed_points |= BIT(max_bw_point);
drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n", drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
max_bw_point); max_bw_point);
} }

9
drivers/gpu/drm/i915/display/intel_hdmi.c
View File

@@ -1836,6 +1836,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
bool has_hdmi_sink) bool has_hdmi_sink)
{ {
struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
if (clock < 25000) if (clock < 25000)
return MODE_CLOCK_LOW; return MODE_CLOCK_LOW;
@@ -1856,6 +1857,14 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
return MODE_CLOCK_RANGE; return MODE_CLOCK_RANGE;
/* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
return MODE_CLOCK_RANGE;
/* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
return MODE_CLOCK_RANGE;
/* /*
* SNPS PHYs' MPLLB table-based programming can only handle a fixed * SNPS PHYs' MPLLB table-based programming can only handle a fixed
* set of link rates. * set of link rates.

2
drivers/gpu/drm/i915/i915_drv.h
View File

@@ -947,7 +947,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
#define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver) #define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver)
#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.arch, \ #define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.ver, \
INTEL_INFO(i915)->media.rel) INTEL_INFO(i915)->media.rel)
#define IS_MEDIA_VER(i915, from, until) \ #define IS_MEDIA_VER(i915, from, until) \
(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))

10
drivers/gpu/drm/i915/intel_pm.c
View File

@@ -3698,8 +3698,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
MISSING_CASE(DISPLAY_VER(dev_priv)); MISSING_CASE(DISPLAY_VER(dev_priv));
} }
/* Default to an unusable block time */ dev_priv->sagv_block_time_us = 0;
dev_priv->sagv_block_time_us = -1;
} }
/* /*
@@ -5645,7 +5644,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1; result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
result->enable = true; result->enable = true;
if (DISPLAY_VER(dev_priv) < 12) if (DISPLAY_VER(dev_priv) < 12 && dev_priv->sagv_block_time_us)
result->can_sagv = latency >= dev_priv->sagv_block_time_us; result->can_sagv = latency >= dev_priv->sagv_block_time_us;
} }
@@ -5678,7 +5677,10 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0; struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;
struct skl_wm_level *levels = plane_wm->wm; struct skl_wm_level *levels = plane_wm->wm;
unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us; unsigned int latency = 0;
if (dev_priv->sagv_block_time_us)
latency = dev_priv->sagv_block_time_us + dev_priv->wm.skl_latency[0];
skl_compute_plane_wm(crtc_state, plane, 0, latency, skl_compute_plane_wm(crtc_state, plane, 0, latency,
wm_params, &levels[0], wm_params, &levels[0],