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drm/amd/display: Add a helper to map ODM/MPC/Multi-Plane resources

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[Why & How]
Add a helper to map ODM/MPC/Multi-Plane resources from DC

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jun Lei 2022-09-29 15:47:31 -04:00 committed by Alex Deucher
parent fa28030a83
commit 20dad3813b
5 changed files with 61 additions and 2 deletions
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49
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -1747,7 +1747,6 @@ bool dc_remove_plane_from_context(
for (i = 0; i < stream_status->plane_count; i++) {
if (stream_status->plane_states[i] == plane_state) {
dc_plane_state_release(stream_status->plane_states[i]);
break;
}
@ -3683,4 +3682,52 @@ bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)
(stream->timing.h_sync_width % 2 == 0);
}
return divisible;
}
bool dc_resource_acquire_secondary_pipe_for_mpc_odm(
const struct dc *dc,
struct dc_state *state,
struct pipe_ctx *pri_pipe,
struct pipe_ctx *sec_pipe,
bool odm)
{
int pipe_idx = sec_pipe->pipe_idx;
struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev;
const struct resource_pool *pool = dc->res_pool;
sec_top = sec_pipe->top_pipe;
sec_bottom = sec_pipe->bottom_pipe;
sec_next = sec_pipe->next_odm_pipe;
sec_prev = sec_pipe->prev_odm_pipe;
*sec_pipe = *pri_pipe;
sec_pipe->top_pipe = sec_top;
sec_pipe->bottom_pipe = sec_bottom;
sec_pipe->next_odm_pipe = sec_next;
sec_pipe->prev_odm_pipe = sec_prev;
sec_pipe->pipe_idx = pipe_idx;
sec_pipe->plane_res.mi = pool->mis[pipe_idx];
sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
sec_pipe->stream_res.dsc = NULL;
if (odm) {
if (!sec_pipe->top_pipe)
sec_pipe->stream_res.opp = pool->opps[pipe_idx];
else
sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
if (sec_pipe->stream->timing.flags.DSC == 1) {
dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
ASSERT(sec_pipe->stream_res.dsc);
if (sec_pipe->stream_res.dsc == NULL)
return false;
}
dcn20_build_mapped_resource(dc, state, sec_pipe->stream);
}
return true;
}

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -1191,6 +1191,8 @@ struct dc_plane_state {
enum dc_irq_source irq_source;
struct kref refcount;
struct tg_color visual_confirm_color;
bool is_statically_allocated;
};
struct dc_plane_info {

2
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@ -1372,7 +1372,7 @@ static struct pipe_ctx *dcn32_find_split_pipe(
return pipe;
}
static bool dcn32_split_stream_for_mpc_or_odm(
bool dcn32_split_stream_for_mpc_or_odm(
const struct dc *dc,
struct resource_context *res_ctx,
struct pipe_ctx *pri_pipe,

4
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -39,6 +39,8 @@
#include "panel_cntl.h"
#define MAX_CLOCK_SOURCES 7
#define MAX_SVP_PHANTOM_STREAMS 2
#define MAX_SVP_PHANTOM_PLANES 2
void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
uint32_t controller_id);
@ -492,6 +494,8 @@ struct dcn_bw_output {
struct dcn_watermark_set watermarks;
struct dcn_bw_writeback bw_writeback;
int compbuf_size_kb;
unsigned int legacy_svp_drr_stream_index;
bool legacy_svp_drr_stream_index_valid;
};
union bw_output {

6
drivers/gpu/drm/amd/display/dc/inc/resource.h
View File

@ -230,4 +230,10 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link,
bool is_h_timing_divisible_by_2(struct dc_stream_state *stream);
bool dc_resource_acquire_secondary_pipe_for_mpc_odm(
const struct dc *dc,
struct dc_state *state,
struct pipe_ctx *pri_pipe,
struct pipe_ctx *sec_pipe,
bool odm);
#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */