forked from Minki/linux
Highlights:
----------- - Following pen_release and boot_lock cleanup initiated by Russell King, .smp_prepare_cpus and .smp_boot_secondary STi callbacks must be reworked to keep secondary CPU's bringup. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJcG50AAAoJEMrHeC97M/+m1CMP+wYY5OagpvTabaJ5AJZA68Jn vLqGrrfch5XxaGe9OL5bxk0ndv3mmyD4ydAD9EwJBzwSbjM7QKH0E+8pTZcLVc2z i3R54Wdd49m2vX7NFPEZF/dMS+AZ+C7cmWiGYrNyJxktXPaTzhO5XwXoRr2yUyBV MBw4qOyhwqRPWGuEud0FTqXpQ46zoVFIwXDcMHwdvM1CyPiNCzYqFzyyy28RXqhX pr3VWHw9nRA7+1XqUVrU81Uu/Fyk/pidpmngM7xsG1NzdmZu6s//LlWoGRuH9u7k a6jiZ94HC5tmGoA3Fx32b95hS2eWvjewIDzj48t6kuzJjCDzwQOXGoOLunQUuY/8 jcg0BF+0d5Efq9GKXVJaZ4XHt15XomwG+CDsjhDyU3HDBN1muB8rF7/2oXzAc4NL D+OGebnrCZlWlFM8YpWcYc/2tZBoT2DhtpuiKFHe6ExLIw/dqk2KilFzghisyHt/ lZh21JJtqVTEcd2GaQVALbQlcJZj8VaRVVGjdniuysqdMBoMCfT4hAzIVzXjybzK qUrmR7wRAiidI0URCXPaMhhRGmvZbssQiPA8aI6LCauAkxuPDOFPfkDn+eX5KsXn SqPlfDNOEfEPz4gJOAclVRV/1kBBLmAe/iIE39Z5Gy8A9cNMdqn1KxrrEjSUJcwU GXzUvpyajj04OGCM2InI =QbVn -----END PGP SIGNATURE----- Merge tag 'sti-soc-for-v4.21-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/late Highlights: ----------- - Following pen_release and boot_lock cleanup initiated by Russell King, .smp_prepare_cpus and .smp_boot_secondary STi callbacks must be reworked to keep secondary CPU's bringup. * tag 'sti-soc-for-v4.21-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: ARM: sti: remove pen_release and boot_lock Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
2081076ac7
@ -1,2 +1,2 @@
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_ARCH_STI) += board-dt.o
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@ -1,43 +0,0 @@
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/*
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* arch/arm/mach-sti/headsmp.S
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*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* http://www.st.com
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*
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* Cloned from linux/arch/arm/mach-vexpress/headsmp.S
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*
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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/*
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* ST specific entry point for secondary CPUs. This provides
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* a "holding pen" into which all secondary cores are held until we're
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* ready for them to initialise.
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*/
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ENTRY(sti_secondary_startup)
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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add r6, r6, r4
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pen: ldr r7, [r6]
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cmp r7, r0
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(sti_secondary_startup)
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1: .long .
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.long pen_release
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@ -28,82 +28,33 @@
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#include "smp.h"
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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sync_cache_w(&pen_release);
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}
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static DEFINE_SPINLOCK(boot_lock);
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static void sti_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static u32 __iomem *cpu_strt_ptr;
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static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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unsigned long entry_pa = __pa_symbol(secondary_startup);
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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* Secondary CPU is initialised and started by a U-BOOTROM firmware.
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* Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.
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* Writing secondary_startup address at cpu_strt_ptr makes it to
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* jump directly to secondary_startup().
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*/
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spin_lock(&boot_lock);
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__raw_writel(entry_pa, cpu_strt_ptr);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(cpu_logical_map(cpu));
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/* wmb so that data is actually written before cache flush is done */
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smp_wmb();
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sync_cache_w(cpu_strt_ptr);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* it to jump to the secondary entrypoint.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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return 0;
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}
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static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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void __iomem *scu_base;
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u32 __iomem *cpu_strt_ptr;
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u32 release_phys;
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int cpu;
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unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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@ -131,8 +82,8 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
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}
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/*
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* holding pen is usually configured in SBC DMEM but can also be
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* in RAM.
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* cpu-release-addr is usually configured in SBC DMEM but can
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* also be in RAM.
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*/
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if (!memblock_is_memory(release_phys))
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@ -142,22 +93,11 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
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cpu_strt_ptr =
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(u32 __iomem *)phys_to_virt(release_phys);
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__raw_writel(entry_pa, cpu_strt_ptr);
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/*
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* wmb so that data is actually written
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* before cache flush is done
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*/
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smp_wmb();
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sync_cache_w(cpu_strt_ptr);
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if (!memblock_is_memory(release_phys))
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iounmap(cpu_strt_ptr);
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set_cpu_possible(cpu, true);
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}
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}
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const struct smp_operations sti_smp_ops __initconst = {
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.smp_prepare_cpus = sti_smp_prepare_cpus,
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.smp_secondary_init = sti_secondary_init,
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.smp_boot_secondary = sti_boot_secondary,
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};
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