forked from Minki/linux
Here are changes to add support for am33xx processors for the
clock, power, and voltagedomains. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJP8Am6AAoJEBvUPslcq6VzhVsP/31PxWaX0JboIbAP0VlmJ+GK J9gIxs2ohx3fDcx4D3da7rLlDue4E0oKmftbj0G4Iom22si2HrtmCnkq41anOkDA UA9hW8kYfQJr90BzHYuIvOncpb6w6mzjJu7QDSO3j2l1FssoG+rOcDrW0EUSdzhF 1pIaGairntUAsI/EE3Ja6r0reRgacV4CmWksatp3mzxpbyA2+m2zJj8IovY1ghPZ jq3zcLm4LCxDyiCDYcz6Jrt9fH9OA2cEQ/q0gHKspHvr2lsRu7gzN5gvi+700oML vIT42/rC6tppf72113arZ+vKluJfa9LhgD0G7JcDqCyRxmwe0w3cKZKWrVklolsZ sHATYxliWk4gB+pipw8W/hEHKGKPgPEPEAd60RN3g3/SDBo/fcQKvsF5/sZldC70 ngagTSseCKGUOQxWJ1+eRqG+I5WIzgorunNIbN/N9dGyxQ3C+zDAgDbdar24sWFn 1bA1wH7iwEYaqGOCEKfwodl+tSGAeuVXm4e2fR81sHRYY6eIFCKCdExZ/DPJrFTt FnbV2OgKKz9xYcw6MNmfVEk3TkMSNwFO+g+EtzM1km5oW6PIxkGoiDydxHGvN3fq gWfv7Y7AJCnbiqKBSahE1WkVADXYTlXk1ySzjHluPXJmqh/iUYDmpKKMYEFQYgyg ekpI3teAadGhu5ZIrqG5 =bc0b -----END PGP SIGNATURE----- Merge tag 'omap-devel-am33xx-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc From Tony Lindgren <tony@atomide.com>: Here are changes to add support for am33xx processors for the clock, power, and voltagedomains. * tag 'omap-devel-am33xx-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP AM33xx: clockdomains: Add clockdomain data and respective operations ARM: OMAP AM33xx: powerdomains: add AM335x support ARM: OMAP AM33xx: CM: Introduce AM33xx CM APIs and register level details ARM: OMAP AM33xx: PRM: add PRM support ARM: OMAP AM33xx: voltagedomain: Add voltage domain data ARM: OMAP2+: control: Add AM33XX control reg & sec clkctrl offset ARM: OMAP2+: am33xx: Add AM335XEVM machine support ARM: OMAP2+: am33xx: Add low level debugging support Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
2028103f90
@ -90,6 +90,7 @@ obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
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obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o
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# OMAP voltage domains
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voltagedomain-common := voltage.o vc.o vp.o
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@ -99,6 +100,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
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obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
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obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
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# OMAP powerdomain framework
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powerdomain-common += powerdomain.o powerdomain-common.o
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@ -113,6 +115,8 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
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obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
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obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
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# PRCM clockdomain control
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clockdomain-common += clockdomain.o
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@ -129,6 +133,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
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obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
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obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
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# Clock framework
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obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
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@ -112,6 +112,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
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MACHINE_END
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#endif
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#ifdef CONFIG_SOC_AM33XX
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static const char *am33xx_boards_compat[] __initdata = {
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"ti,am33xx",
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NULL,
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};
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DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
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.reserve = omap_reserve,
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.map_io = am33xx_map_io,
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.init_early = am33xx_init_early,
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.init_irq = omap_init_irq,
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.handle_irq = omap3_intc_handle_irq,
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.init_machine = omap_generic_init,
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.timer = &omap3_am33xx_timer,
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.dt_compat = am33xx_boards_compat,
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MACHINE_END
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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static const char *omap4_boards_compat[] __initdata = {
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"ti,omap4",
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@ -195,6 +195,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
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extern void __init omap242x_clockdomains_init(void);
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extern void __init omap243x_clockdomains_init(void);
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extern void __init omap3xxx_clockdomains_init(void);
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extern void __init am33xx_clockdomains_init(void);
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extern void __init omap44xx_clockdomains_init(void);
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extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
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extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
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@ -202,6 +203,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
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extern struct clkdm_ops omap2_clkdm_operations;
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extern struct clkdm_ops omap3_clkdm_operations;
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extern struct clkdm_ops omap4_clkdm_operations;
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extern struct clkdm_ops am33xx_clkdm_operations;
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extern struct clkdm_dep gfx_24xx_wkdeps[];
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extern struct clkdm_dep dsp_24xx_wkdeps[];
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74
arch/arm/mach-omap2/clockdomain33xx.c
Normal file
74
arch/arm/mach-omap2/clockdomain33xx.c
Normal file
@ -0,0 +1,74 @@
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/*
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* AM33XX clockdomain control
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include "clockdomain.h"
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#include "cm33xx.h"
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static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
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{
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am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
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return 0;
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}
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static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
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{
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am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
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return 0;
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}
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static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
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{
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am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
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}
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static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
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{
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am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
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}
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static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
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{
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if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
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return am33xx_clkdm_wakeup(clkdm);
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return 0;
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}
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static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
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if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
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am33xx_clkdm_sleep(clkdm);
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return 0;
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}
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struct clkdm_ops am33xx_clkdm_operations = {
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.clkdm_sleep = am33xx_clkdm_sleep,
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.clkdm_wakeup = am33xx_clkdm_wakeup,
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.clkdm_allow_idle = am33xx_clkdm_allow_idle,
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.clkdm_deny_idle = am33xx_clkdm_deny_idle,
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.clkdm_clk_enable = am33xx_clkdm_clk_enable,
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.clkdm_clk_disable = am33xx_clkdm_clk_disable,
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};
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196
arch/arm/mach-omap2/clockdomains33xx_data.c
Normal file
196
arch/arm/mach-omap2/clockdomains33xx_data.c
Normal file
@ -0,0 +1,196 @@
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/*
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* AM33XX Clock Domain data.
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "cm.h"
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#include "cm33xx.h"
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#include "cm-regbits-33xx.h"
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static struct clockdomain l4ls_am33xx_clkdm = {
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.name = "l4ls_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l3s_am33xx_clkdm = {
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.name = "l3s_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4fw_am33xx_clkdm = {
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.name = "l4fw_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l3_am33xx_clkdm = {
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.name = "l3_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4hs_am33xx_clkdm = {
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.name = "l4hs_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ocpwp_l3_am33xx_clkdm = {
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.name = "ocpwp_l3_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain pruss_ocp_am33xx_clkdm = {
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.name = "pruss_ocp_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
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.name = "cpsw_125mhz_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain lcdc_am33xx_clkdm = {
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.name = "lcdc_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain clk_24mhz_am33xx_clkdm = {
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.name = "clk_24mhz_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.cm_inst = AM33XX_CM_PER_MOD,
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.clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_wkup_am33xx_clkdm = {
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.name = "l4_wkup_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.cm_inst = AM33XX_CM_WKUP_MOD,
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.clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l3_aon_am33xx_clkdm = {
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.name = "l3_aon_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.cm_inst = AM33XX_CM_WKUP_MOD,
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.clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
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.name = "l4_wkup_aon_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.cm_inst = AM33XX_CM_WKUP_MOD,
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.clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mpu_am33xx_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.cm_inst = AM33XX_CM_MPU_MOD,
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.clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_rtc_am33xx_clkdm = {
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.name = "l4_rtc_clkdm",
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.pwrdm = { .name = "rtc_pwrdm" },
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.cm_inst = AM33XX_CM_RTC_MOD,
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.clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain gfx_l3_am33xx_clkdm = {
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.name = "gfx_l3_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.cm_inst = AM33XX_CM_GFX_MOD,
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.clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
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.name = "gfx_l4ls_gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.cm_inst = AM33XX_CM_GFX_MOD,
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.clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_cefuse_am33xx_clkdm = {
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.name = "l4_cefuse_clkdm",
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.pwrdm = { .name = "cefuse_pwrdm" },
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.cm_inst = AM33XX_CM_CEFUSE_MOD,
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.clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain *clockdomains_am33xx[] __initdata = {
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&l4ls_am33xx_clkdm,
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&l3s_am33xx_clkdm,
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&l4fw_am33xx_clkdm,
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&l3_am33xx_clkdm,
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&l4hs_am33xx_clkdm,
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&ocpwp_l3_am33xx_clkdm,
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&pruss_ocp_am33xx_clkdm,
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&cpsw_125mhz_am33xx_clkdm,
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&lcdc_am33xx_clkdm,
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&clk_24mhz_am33xx_clkdm,
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&l4_wkup_am33xx_clkdm,
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&l3_aon_am33xx_clkdm,
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&l4_wkup_aon_am33xx_clkdm,
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&mpu_am33xx_clkdm,
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&l4_rtc_am33xx_clkdm,
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&gfx_l3_am33xx_clkdm,
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&gfx_l4ls_gfx_am33xx_clkdm,
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&l4_cefuse_am33xx_clkdm,
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NULL,
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};
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void __init am33xx_clockdomains_init(void)
|
||||
{
|
||||
clkdm_register_platform_funcs(&am33xx_clkdm_operations);
|
||||
clkdm_register_clkdms(clockdomains_am33xx);
|
||||
clkdm_complete_init();
|
||||
}
|
||||
687
arch/arm/mach-omap2/cm-regbits-33xx.h
Normal file
687
arch/arm/mach-omap2/cm-regbits-33xx.h
Normal file
@ -0,0 +1,687 @@
|
||||
/*
|
||||
* AM33XX Power Management register bits
|
||||
*
|
||||
* This file is automatically generated from the AM33XX hardware databases.
|
||||
* Vaibhav Hiremath <hvaibhav@ti.com>
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
|
||||
|
||||
/*
|
||||
* Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
|
||||
* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
|
||||
#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
|
||||
#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
|
||||
#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
|
||||
|
||||
/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_CPSW_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_L4HS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_L4HS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
|
||||
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_PER_L4HS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
|
||||
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
|
||||
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
|
||||
|
||||
/* Used by CM_CEFUSE_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
|
||||
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_L3_AON_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_L3_AON_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_GFX_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
|
||||
#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_GFX_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
|
||||
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
|
||||
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
|
||||
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
|
||||
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
|
||||
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
|
||||
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
|
||||
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
|
||||
#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
|
||||
|
||||
/* Used by CM_PER_PRUSS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_PER_PRUSS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_PRUSS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
|
||||
|
||||
/* Used by CM_PER_L3S_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_L3_AON_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_L4FW_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_PER_L4HS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_CEFUSE_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_RTC_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
|
||||
#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
|
||||
|
||||
/* Used by CM_PER_LCDC_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_LCDC_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
|
||||
#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_MPU_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_RTC_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
|
||||
#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
|
||||
#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
|
||||
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
|
||||
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
|
||||
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
|
||||
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
|
||||
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
|
||||
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
|
||||
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
|
||||
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
|
||||
#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
|
||||
#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
|
||||
#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CLKSEL_GFX_FCLK */
|
||||
#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
|
||||
#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
|
||||
|
||||
/* Used by CM_CLKOUT_CTRL */
|
||||
#define AM33XX_CLKOUT2DIV_SHIFT 3
|
||||
#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3)
|
||||
|
||||
/* Used by CM_CLKOUT_CTRL */
|
||||
#define AM33XX_CLKOUT2EN_SHIFT 7
|
||||
#define AM33XX_CLKOUT2EN_MASK (1 << 7)
|
||||
|
||||
/* Used by CM_CLKOUT_CTRL */
|
||||
#define AM33XX_CLKOUT2SOURCE_SHIFT 0
|
||||
#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0)
|
||||
|
||||
/*
|
||||
* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
|
||||
* CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
|
||||
* CLKSEL_TIMER7_CLK
|
||||
*/
|
||||
#define AM33XX_CLKSEL_SHIFT 0
|
||||
#define AM33XX_CLKSEL_MASK (0x01 << 0)
|
||||
|
||||
/*
|
||||
* Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
|
||||
* CM_CPTS_RFT_CLKSEL
|
||||
*/
|
||||
#define AM33XX_CLKSEL_0_0_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
|
||||
|
||||
#define AM33XX_CLKSEL_0_1_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
|
||||
|
||||
/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
|
||||
#define AM33XX_CLKSEL_0_2_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
|
||||
|
||||
/* Used by CLKSEL_GFX_FCLK */
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
|
||||
* CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
|
||||
* CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
|
||||
* CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
|
||||
* CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
|
||||
* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
|
||||
*/
|
||||
#define AM33XX_CLKTRCTRL_SHIFT 0
|
||||
#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
|
||||
* CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
|
||||
* CM_SSC_DELTAMSTEP_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DELTAMSTEP_SHIFT 0
|
||||
#define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
|
||||
|
||||
/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
|
||||
|
||||
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
|
||||
|
||||
/*
|
||||
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
|
||||
* CM_DIV_M2_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
|
||||
* CM_CLKSEL_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_DIV_SHIFT 0
|
||||
#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
|
||||
|
||||
#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
|
||||
|
||||
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_DIV_0_7_SHIFT 0
|
||||
#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_EN_SHIFT 0
|
||||
#define AM33XX_DPLL_EN_MASK (0x7 << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
|
||||
#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
|
||||
* CM_CLKSEL_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_MULT_SHIFT 8
|
||||
#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
|
||||
|
||||
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
|
||||
#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_REGM4XEN_SHIFT 11
|
||||
#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
|
||||
|
||||
/* Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_SD_DIV_SHIFT 24
|
||||
#define AM33XX_DPLL_SD_DIV_MASK (24, 31)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_ACK_SHIFT 13
|
||||
#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_EN_SHIFT 12
|
||||
#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
|
||||
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
|
||||
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
|
||||
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
|
||||
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
|
||||
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
|
||||
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
|
||||
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
|
||||
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
|
||||
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
|
||||
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
|
||||
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
|
||||
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
|
||||
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
|
||||
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
|
||||
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
|
||||
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
|
||||
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
|
||||
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
|
||||
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
|
||||
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
|
||||
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
|
||||
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
|
||||
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
|
||||
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
|
||||
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
|
||||
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
|
||||
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
|
||||
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
|
||||
* CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
|
||||
* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_IDLEST_SHIFT 16
|
||||
#define AM33XX_IDLEST_MASK (0x3 << 16)
|
||||
#define AM33XX_IDLEST_VAL 0x3
|
||||
|
||||
/* Used by CM_MAC_CLKSEL */
|
||||
#define AM33XX_MII_CLK_SEL_SHIFT 2
|
||||
#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
|
||||
|
||||
/*
|
||||
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
|
||||
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
|
||||
* CM_SSC_MODFREQDIV_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
|
||||
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
|
||||
* CM_SSC_MODFREQDIV_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
|
||||
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
|
||||
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
|
||||
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
|
||||
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
|
||||
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
|
||||
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
|
||||
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
|
||||
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
|
||||
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
|
||||
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
|
||||
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
|
||||
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
|
||||
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
|
||||
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
|
||||
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
|
||||
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
|
||||
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
|
||||
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
|
||||
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
|
||||
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
|
||||
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
|
||||
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
|
||||
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
|
||||
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
|
||||
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
|
||||
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
|
||||
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
|
||||
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
|
||||
* CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
|
||||
* CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
|
||||
* CM_CEFUSE_CEFUSE_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_MODULEMODE_SHIFT 0
|
||||
#define AM33XX_MODULEMODE_MASK (0x3 << 0)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
|
||||
|
||||
/* Used by CM_WKUP_GPIO0_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO1_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO2_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO3_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO4_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO5_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO6_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
|
||||
* CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
|
||||
* CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
|
||||
* CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
|
||||
* CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
|
||||
* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_STBYST_SHIFT 18
|
||||
#define AM33XX_STBYST_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
|
||||
#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
|
||||
|
||||
/*
|
||||
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
|
||||
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_DPLL_CLK_SHIFT 0
|
||||
#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
|
||||
#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
|
||||
* CM_DIV_M2_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
|
||||
#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
|
||||
|
||||
/*
|
||||
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
|
||||
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_MN_BYPASS_SHIFT 8
|
||||
#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
|
||||
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
|
||||
|
||||
/* Used by CONTROL_SEC_CLK_CTRL */
|
||||
#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
|
||||
#endif
|
||||
313
arch/arm/mach-omap2/cm33xx.c
Normal file
313
arch/arm/mach-omap2/cm33xx.c
Normal file
@ -0,0 +1,313 @@
|
||||
/*
|
||||
* AM33XX CM functions
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Vaibhav Hiremath <hvaibhav@ti.com>
|
||||
*
|
||||
* Reference taken from from OMAP4 cminst44xx.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <plat/common.h>
|
||||
|
||||
#include "cm.h"
|
||||
#include "cm33xx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
#include "cm-regbits-33xx.h"
|
||||
#include "prm33xx.h"
|
||||
|
||||
/*
|
||||
* CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
|
||||
*
|
||||
* 0x0 func: Module is fully functional, including OCP
|
||||
* 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
|
||||
* abortion
|
||||
* 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
|
||||
* using separate functional clock
|
||||
* 0x3 disabled: Module is disabled and cannot be accessed
|
||||
*
|
||||
*/
|
||||
#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
|
||||
#define CLKCTRL_IDLEST_INTRANSITION 0x1
|
||||
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
|
||||
#define CLKCTRL_IDLEST_DISABLED 0x3
|
||||
|
||||
/* Private functions */
|
||||
|
||||
/* Read a register in a CM instance */
|
||||
static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
|
||||
{
|
||||
return __raw_readl(cm_base + inst + idx);
|
||||
}
|
||||
|
||||
/* Write into a register in a CM */
|
||||
static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
|
||||
{
|
||||
__raw_writel(val, cm_base + inst + idx);
|
||||
}
|
||||
|
||||
/* Read-modify-write a register in CM */
|
||||
static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_cm_read_reg(inst, idx);
|
||||
v &= ~mask;
|
||||
v |= bits;
|
||||
am33xx_cm_write_reg(v, inst, idx);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
|
||||
{
|
||||
return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
|
||||
}
|
||||
|
||||
static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
|
||||
{
|
||||
return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
|
||||
}
|
||||
|
||||
static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_cm_read_reg(inst, idx);
|
||||
v &= mask;
|
||||
v >>= __ffs(mask);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
/**
|
||||
* _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
|
||||
*
|
||||
* Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
|
||||
* bit 0.
|
||||
*/
|
||||
static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
|
||||
{
|
||||
u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
|
||||
v &= AM33XX_IDLEST_MASK;
|
||||
v >>= AM33XX_IDLEST_SHIFT;
|
||||
return v;
|
||||
}
|
||||
|
||||
/**
|
||||
* _is_module_ready - can module registers be accessed without causing an abort?
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
|
||||
*
|
||||
* Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
|
||||
* *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
|
||||
*/
|
||||
static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
|
||||
|
||||
return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
|
||||
v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
|
||||
* @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
*
|
||||
* @c must be the unshifted value for CLKTRCTRL - i.e., this function
|
||||
* will handle the shift itself.
|
||||
*/
|
||||
static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_cm_read_reg(inst, cdoffs);
|
||||
v &= ~AM33XX_CLKTRCTRL_MASK;
|
||||
v |= c << AM33XX_CLKTRCTRL_SHIFT;
|
||||
am33xx_cm_write_reg(v, inst, cdoffs);
|
||||
}
|
||||
|
||||
/* Public functions */
|
||||
|
||||
/**
|
||||
* am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
*
|
||||
* Returns true if the clockdomain referred to by (@inst, @cdoffs)
|
||||
* is in hardware-supervised idle mode, or 0 otherwise.
|
||||
*/
|
||||
bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_cm_read_reg(inst, cdoffs);
|
||||
v &= AM33XX_CLKTRCTRL_MASK;
|
||||
v >>= AM33XX_CLKTRCTRL_SHIFT;
|
||||
|
||||
return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
*
|
||||
* Put a clockdomain referred to by (@inst, @cdoffs) into
|
||||
* hardware-supervised idle mode. No return value.
|
||||
*/
|
||||
void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
|
||||
{
|
||||
_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
*
|
||||
* Put a clockdomain referred to by (@inst, @cdoffs) into
|
||||
* software-supervised idle mode, i.e., controlled manually by the
|
||||
* Linux OMAP clockdomain code. No return value.
|
||||
*/
|
||||
void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
|
||||
{
|
||||
_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
*
|
||||
* Put a clockdomain referred to by (@inst, @cdoffs) into idle
|
||||
* No return value.
|
||||
*/
|
||||
void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
|
||||
{
|
||||
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
*
|
||||
* Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
|
||||
* waking it up. No return value.
|
||||
*/
|
||||
void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
|
||||
{
|
||||
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
|
||||
*
|
||||
* Wait for the module IDLEST to be functional. If the idle state is in any
|
||||
* the non functional state (trans, idle or disabled), module and thus the
|
||||
* sysconfig cannot be accessed and will probably lead to an "imprecise
|
||||
* external abort"
|
||||
*/
|
||||
int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
if (!clkctrl_offs)
|
||||
return 0;
|
||||
|
||||
omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
|
||||
MAX_MODULE_READY_TIME, i);
|
||||
|
||||
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
|
||||
* state
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
|
||||
*
|
||||
* Wait for the module IDLEST to be disabled. Some PRCM transition,
|
||||
* like reset assertion or parent clock de-activation must wait the
|
||||
* module to be fully disabled.
|
||||
*/
|
||||
int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
if (!clkctrl_offs)
|
||||
return 0;
|
||||
|
||||
omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
|
||||
CLKCTRL_IDLEST_DISABLED),
|
||||
MAX_MODULE_READY_TIME, i);
|
||||
|
||||
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
|
||||
* @mode: Module mode (SW or HW)
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
|
||||
*
|
||||
* No return value.
|
||||
*/
|
||||
void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_cm_read_reg(inst, clkctrl_offs);
|
||||
v &= ~AM33XX_MODULEMODE_MASK;
|
||||
v |= mode << AM33XX_MODULEMODE_SHIFT;
|
||||
am33xx_cm_write_reg(v, inst, clkctrl_offs);
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_cm_module_disable - Disable the module inside CLKCTRL
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
|
||||
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
|
||||
*
|
||||
* No return value.
|
||||
*/
|
||||
void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_cm_read_reg(inst, clkctrl_offs);
|
||||
v &= ~AM33XX_MODULEMODE_MASK;
|
||||
am33xx_cm_write_reg(v, inst, clkctrl_offs);
|
||||
}
|
||||
420
arch/arm/mach-omap2/cm33xx.h
Normal file
420
arch/arm/mach-omap2/cm33xx.h
Normal file
@ -0,0 +1,420 @@
|
||||
/*
|
||||
* AM33XX CM offset macros
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Vaibhav Hiremath <hvaibhav@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#include "cm.h"
|
||||
#include "cm-regbits-33xx.h"
|
||||
#include "cm33xx.h"
|
||||
|
||||
/* CM base address */
|
||||
#define AM33XX_CM_BASE 0x44e00000
|
||||
|
||||
#define AM33XX_CM_REGADDR(inst, reg) \
|
||||
AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
|
||||
|
||||
/* CM instances */
|
||||
#define AM33XX_CM_PER_MOD 0x0000
|
||||
#define AM33XX_CM_WKUP_MOD 0x0400
|
||||
#define AM33XX_CM_DPLL_MOD 0x0500
|
||||
#define AM33XX_CM_MPU_MOD 0x0600
|
||||
#define AM33XX_CM_DEVICE_MOD 0x0700
|
||||
#define AM33XX_CM_RTC_MOD 0x0800
|
||||
#define AM33XX_CM_GFX_MOD 0x0900
|
||||
#define AM33XX_CM_CEFUSE_MOD 0x0A00
|
||||
|
||||
/* CM */
|
||||
|
||||
/* CM.PER_CM register offsets */
|
||||
#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
|
||||
#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004
|
||||
#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
|
||||
#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008
|
||||
#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
|
||||
#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c
|
||||
#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
|
||||
#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014
|
||||
#define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
|
||||
#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018
|
||||
#define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
|
||||
#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c
|
||||
#define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
|
||||
#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020
|
||||
#define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
|
||||
#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024
|
||||
#define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
|
||||
#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028
|
||||
#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
|
||||
#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c
|
||||
#define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
|
||||
#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030
|
||||
#define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
|
||||
#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034
|
||||
#define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
|
||||
#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038
|
||||
#define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
|
||||
#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c
|
||||
#define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
|
||||
#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040
|
||||
#define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
|
||||
#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044
|
||||
#define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
|
||||
#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048
|
||||
#define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
|
||||
#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c
|
||||
#define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
|
||||
#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050
|
||||
#define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
|
||||
#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054
|
||||
#define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
|
||||
#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058
|
||||
#define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
|
||||
#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060
|
||||
#define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
|
||||
#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064
|
||||
#define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
|
||||
#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068
|
||||
#define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
|
||||
#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c
|
||||
#define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
|
||||
#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070
|
||||
#define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
|
||||
#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074
|
||||
#define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
|
||||
#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078
|
||||
#define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
|
||||
#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c
|
||||
#define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
|
||||
#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080
|
||||
#define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
|
||||
#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084
|
||||
#define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
|
||||
#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088
|
||||
#define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
|
||||
#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c
|
||||
#define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
|
||||
#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090
|
||||
#define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
|
||||
#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094
|
||||
#define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
|
||||
#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098
|
||||
#define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
|
||||
#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c
|
||||
#define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
|
||||
#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0
|
||||
#define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
|
||||
#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4
|
||||
#define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
|
||||
#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8
|
||||
#define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
|
||||
#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac
|
||||
#define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
|
||||
#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0
|
||||
#define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
|
||||
#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4
|
||||
#define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
|
||||
#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8
|
||||
#define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
|
||||
#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc
|
||||
#define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
|
||||
#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0
|
||||
#define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
|
||||
#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4
|
||||
#define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
|
||||
#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc
|
||||
#define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
|
||||
#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0
|
||||
#define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
|
||||
#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4
|
||||
#define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
|
||||
#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8
|
||||
#define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
|
||||
#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc
|
||||
#define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
|
||||
#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0
|
||||
#define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
|
||||
#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4
|
||||
#define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
|
||||
#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8
|
||||
#define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
|
||||
#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec
|
||||
#define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
|
||||
#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0
|
||||
#define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
|
||||
#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4
|
||||
#define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
|
||||
#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8
|
||||
#define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
|
||||
#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc
|
||||
#define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
|
||||
#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100
|
||||
#define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
|
||||
#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104
|
||||
#define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
|
||||
#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c
|
||||
#define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
|
||||
#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110
|
||||
#define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
|
||||
#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c
|
||||
#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
|
||||
#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120
|
||||
#define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
|
||||
#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124
|
||||
#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
|
||||
#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128
|
||||
#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
|
||||
#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c
|
||||
#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
|
||||
#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130
|
||||
#define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
|
||||
#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134
|
||||
#define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
|
||||
#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140
|
||||
#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
|
||||
#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144
|
||||
#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
|
||||
#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148
|
||||
#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
|
||||
#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c
|
||||
#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
|
||||
#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150
|
||||
#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
|
||||
|
||||
/* CM.WKUP_CM register offsets */
|
||||
#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
|
||||
#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004
|
||||
#define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
|
||||
#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008
|
||||
#define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
|
||||
#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c
|
||||
#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
|
||||
#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010
|
||||
#define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
|
||||
#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014
|
||||
#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
|
||||
#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018
|
||||
#define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
|
||||
#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020
|
||||
#define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
|
||||
#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c
|
||||
#define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
|
||||
#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034
|
||||
#define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
|
||||
#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040
|
||||
#define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
|
||||
#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048
|
||||
#define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
|
||||
#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054
|
||||
#define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
|
||||
#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c
|
||||
#define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
|
||||
#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068
|
||||
#define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c
|
||||
#define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
|
||||
#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070
|
||||
#define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074
|
||||
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078
|
||||
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
|
||||
#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c
|
||||
#define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
|
||||
#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080
|
||||
#define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
|
||||
#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084
|
||||
#define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
|
||||
#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088
|
||||
#define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
|
||||
#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c
|
||||
#define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
|
||||
#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090
|
||||
#define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
|
||||
#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094
|
||||
#define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
|
||||
#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098
|
||||
#define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
|
||||
#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c
|
||||
#define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
|
||||
#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0
|
||||
#define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
|
||||
#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4
|
||||
#define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
|
||||
#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8
|
||||
#define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
|
||||
#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac
|
||||
#define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
|
||||
#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0
|
||||
#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
|
||||
#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4
|
||||
#define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
|
||||
#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8
|
||||
#define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
|
||||
#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc
|
||||
#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
|
||||
#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0
|
||||
#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
|
||||
#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4
|
||||
#define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
|
||||
#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8
|
||||
#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
|
||||
#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc
|
||||
#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
|
||||
#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0
|
||||
#define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
|
||||
#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4
|
||||
#define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
|
||||
#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8
|
||||
#define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
|
||||
|
||||
/* CM.DPLL_CM register offsets */
|
||||
#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004
|
||||
#define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
|
||||
#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008
|
||||
#define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
|
||||
#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c
|
||||
#define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
|
||||
#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010
|
||||
#define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
|
||||
#define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014
|
||||
#define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
|
||||
#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018
|
||||
#define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
|
||||
#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c
|
||||
#define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
|
||||
#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020
|
||||
#define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
|
||||
#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028
|
||||
#define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c
|
||||
#define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
|
||||
#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030
|
||||
#define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
|
||||
#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034
|
||||
#define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
|
||||
#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038
|
||||
#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
|
||||
#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c
|
||||
#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
|
||||
|
||||
/* CM.MPU_CM register offsets */
|
||||
#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
|
||||
#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004
|
||||
#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
|
||||
|
||||
/* CM.DEVICE_CM register offsets */
|
||||
#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000
|
||||
#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
|
||||
|
||||
/* CM.RTC_CM register offsets */
|
||||
#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000
|
||||
#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
|
||||
#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004
|
||||
#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
|
||||
|
||||
/* CM.GFX_CM register offsets */
|
||||
#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
|
||||
#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004
|
||||
#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
|
||||
#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008
|
||||
#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
|
||||
#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c
|
||||
#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
|
||||
#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010
|
||||
#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
|
||||
#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014
|
||||
#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
|
||||
|
||||
/* CM.CEFUSE_CM register offsets */
|
||||
#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
|
||||
#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
|
||||
#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
|
||||
|
||||
|
||||
extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
|
||||
extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
|
||||
extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
|
||||
extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
|
||||
extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
|
||||
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs);
|
||||
extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs);
|
||||
extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs);
|
||||
extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs);
|
||||
#else
|
||||
static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs)
|
||||
{
|
||||
}
|
||||
static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs)
|
||||
{
|
||||
}
|
||||
static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -120,6 +120,7 @@ extern void omap2_init_common_infrastructure(void);
|
||||
extern struct sys_timer omap2_timer;
|
||||
extern struct sys_timer omap3_timer;
|
||||
extern struct sys_timer omap3_secure_timer;
|
||||
extern struct sys_timer omap3_am33xx_timer;
|
||||
extern struct sys_timer omap4_timer;
|
||||
|
||||
void omap2420_init_early(void);
|
||||
@ -128,8 +129,10 @@ void omap3430_init_early(void);
|
||||
void omap35xx_init_early(void);
|
||||
void omap3630_init_early(void);
|
||||
void omap3_init_early(void); /* Do not use this one */
|
||||
void am33xx_init_early(void);
|
||||
void am35xx_init_early(void);
|
||||
void ti81xx_init_early(void);
|
||||
void am33xx_init_early(void);
|
||||
void omap4430_init_early(void);
|
||||
void omap3_init_late(void); /* Do not use this one */
|
||||
void omap4430_init_late(void);
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
#include <mach/ctrl_module_pad_core_44xx.h>
|
||||
#include <mach/ctrl_module_pad_wkup_44xx.h>
|
||||
|
||||
#include <plat/am33xx.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define OMAP242X_CTRL_REGADDR(reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
|
||||
@ -28,6 +30,8 @@
|
||||
OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
|
||||
#define OMAP343X_CTRL_REGADDR(reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
|
||||
#define AM33XX_CTRL_REGADDR(reg) \
|
||||
AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
|
||||
#else
|
||||
#define OMAP242X_CTRL_REGADDR(reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
|
||||
@ -35,6 +39,8 @@
|
||||
OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
|
||||
#define OMAP343X_CTRL_REGADDR(reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
|
||||
#define AM33XX_CTRL_REGADDR(reg) \
|
||||
AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
@ -312,15 +318,15 @@
|
||||
OMAP343X_SCRATCHPAD + reg)
|
||||
|
||||
/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
|
||||
#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
|
||||
#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
|
||||
#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
|
||||
#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
|
||||
#define AM35XX_USBOTG_FCLK_SHIFT 8
|
||||
#define AM35XX_CPGMAC_FCLK_SHIFT 9
|
||||
#define AM35XX_VPFE_FCLK_SHIFT 10
|
||||
#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
|
||||
#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
|
||||
#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
|
||||
#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
|
||||
#define AM35XX_USBOTG_FCLK_SHIFT 8
|
||||
#define AM35XX_CPGMAC_FCLK_SHIFT 9
|
||||
#define AM35XX_VPFE_FCLK_SHIFT 10
|
||||
|
||||
/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
|
||||
/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
|
||||
#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
|
||||
#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
|
||||
#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
|
||||
@ -330,21 +336,22 @@
|
||||
#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
|
||||
#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
|
||||
|
||||
/*AM35XX CONTROL_IP_SW_RESET bits*/
|
||||
/* AM35XX CONTROL_IP_SW_RESET bits */
|
||||
#define AM35XX_USBOTGSS_SW_RST BIT(0)
|
||||
#define AM35XX_CPGMACSS_SW_RST BIT(1)
|
||||
#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
|
||||
#define AM35XX_HECC_SW_RST BIT(3)
|
||||
#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
|
||||
|
||||
/*
|
||||
* CONTROL AM33XX STATUS register
|
||||
*/
|
||||
/* AM33XX CONTROL_STATUS register */
|
||||
#define AM33XX_CONTROL_STATUS 0x040
|
||||
#define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
|
||||
|
||||
/*
|
||||
* CONTROL OMAP STATUS register to identify OMAP3 features
|
||||
*/
|
||||
/* AM33XX CONTROL_STATUS bitfields (partial) */
|
||||
#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
|
||||
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
|
||||
|
||||
/* CONTROL OMAP STATUS register to identify OMAP3 features */
|
||||
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
|
||||
|
||||
#define OMAP3_SGX_SHIFT 13
|
||||
|
||||
@ -72,6 +72,8 @@ omap_uart_lsr: .word 0
|
||||
beq 82f @ configure UART2
|
||||
cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
|
||||
beq 83f @ configure UART3
|
||||
cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different
|
||||
beq 84f @ configure UART1
|
||||
cmp \rp, #ZOOM_UART @ only on zoom2/3
|
||||
beq 95f @ configure ZOOM_UART
|
||||
|
||||
@ -100,7 +102,9 @@ omap_uart_lsr: .word 0
|
||||
b 98f
|
||||
83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
|
||||
b 98f
|
||||
|
||||
84: ldr \rp, =AM33XX_UART1_BASE
|
||||
and \rp, \rp, #0x00ffffff
|
||||
b 97f
|
||||
95: ldr \rp, =ZOOM_UART_BASE
|
||||
str \rp, [\tmp, #0] @ omap_uart_phys
|
||||
ldr \rp, =ZOOM_UART_VIRT
|
||||
@ -109,6 +113,17 @@ omap_uart_lsr: .word 0
|
||||
str \rp, [\tmp, #8] @ omap_uart_lsr
|
||||
b 10b
|
||||
|
||||
/* AM33XX: Store both phys and virt address for the uart */
|
||||
97: add \rp, \rp, #0x44000000 @ phys base
|
||||
str \rp, [\tmp, #0] @ omap_uart_phys
|
||||
sub \rp, \rp, #0x44000000 @ phys base
|
||||
add \rp, \rp, #0xf9000000 @ virt base
|
||||
str \rp, [\tmp, #4] @ omap_uart_virt
|
||||
mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
|
||||
str \rp, [\tmp, #8] @ omap_uart_lsr
|
||||
|
||||
b 10b
|
||||
|
||||
/* Store both phys and virt address for the uart */
|
||||
98: add \rp, \rp, #0x48000000 @ phys base
|
||||
str \rp, [\tmp, #0] @ omap_uart_phys
|
||||
|
||||
@ -477,6 +477,19 @@ void __init ti81xx_init_late(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
void __init am33xx_init_early(void)
|
||||
{
|
||||
omap2_set_globals_am33xx();
|
||||
omap3xxx_check_revision();
|
||||
ti81xx_check_features();
|
||||
omap_common_init_early();
|
||||
am33xx_voltagedomains_init();
|
||||
am33xx_powerdomains_init();
|
||||
am33xx_clockdomains_init();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
void __init omap4430_init_early(void)
|
||||
{
|
||||
|
||||
@ -279,7 +279,7 @@ int __init omap_intc_of_init(struct device_node *node,
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
|
||||
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
|
||||
|
||||
void omap_intc_save_context(void)
|
||||
|
||||
@ -67,9 +67,9 @@
|
||||
|
||||
/*
|
||||
* Maximum number of clockdomains that can be associated with a powerdomain.
|
||||
* CORE powerdomain on OMAP4 is the worst case
|
||||
* PER powerdomain on AM33XX is the worst case
|
||||
*/
|
||||
#define PWRDM_MAX_CLKDMS 9
|
||||
#define PWRDM_MAX_CLKDMS 11
|
||||
|
||||
/* XXX A completely arbitrary number. What is reasonable here? */
|
||||
#define PWRDM_TRANSITION_BAILOUT 100000
|
||||
@ -92,6 +92,15 @@ struct powerdomain;
|
||||
* @pwrdm_clkdms: Clockdomains in this powerdomain
|
||||
* @node: list_head linking all powerdomains
|
||||
* @voltdm_node: list_head linking all powerdomains in a voltagedomain
|
||||
* @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
|
||||
* @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
|
||||
* @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
|
||||
* in @pwrstctrl_offs
|
||||
* @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
|
||||
* @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
|
||||
* @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
|
||||
* @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
|
||||
* in @pwrstctrl_offs
|
||||
* @state:
|
||||
* @state_counter:
|
||||
* @timer:
|
||||
@ -121,6 +130,14 @@ struct powerdomain {
|
||||
unsigned ret_logic_off_counter;
|
||||
unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
|
||||
|
||||
const u8 pwrstctrl_offs;
|
||||
const u8 pwrstst_offs;
|
||||
const u32 logicretstate_mask;
|
||||
const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
|
||||
const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
|
||||
const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
|
||||
const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
|
||||
|
||||
#ifdef CONFIG_PM_DEBUG
|
||||
s64 timer;
|
||||
s64 state_timer[PWRDM_MAX_PWRSTS];
|
||||
@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
|
||||
extern void omap242x_powerdomains_init(void);
|
||||
extern void omap243x_powerdomains_init(void);
|
||||
extern void omap3xxx_powerdomains_init(void);
|
||||
extern void am33xx_powerdomains_init(void);
|
||||
extern void omap44xx_powerdomains_init(void);
|
||||
|
||||
extern struct pwrdm_ops omap2_pwrdm_operations;
|
||||
extern struct pwrdm_ops omap3_pwrdm_operations;
|
||||
extern struct pwrdm_ops am33xx_pwrdm_operations;
|
||||
extern struct pwrdm_ops omap4_pwrdm_operations;
|
||||
|
||||
/* Common Internal functions used across OMAP rev's */
|
||||
|
||||
229
arch/arm/mach-omap2/powerdomain33xx.c
Normal file
229
arch/arm/mach-omap2/powerdomain33xx.c
Normal file
@ -0,0 +1,229 @@
|
||||
/*
|
||||
* AM33XX Powerdomain control
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
|
||||
* <rnayak@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <plat/prcm.h>
|
||||
|
||||
#include "powerdomain.h"
|
||||
#include "prm33xx.h"
|
||||
#include "prm-regbits-33xx.h"
|
||||
|
||||
|
||||
static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
||||
{
|
||||
am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
|
||||
(pwrst << OMAP_POWERSTATE_SHIFT),
|
||||
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
|
||||
v &= OMAP_POWERSTATE_MASK;
|
||||
v >>= OMAP_POWERSTATE_SHIFT;
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
|
||||
v &= OMAP_POWERSTATEST_MASK;
|
||||
v >>= OMAP_POWERSTATEST_SHIFT;
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
|
||||
v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
|
||||
v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
|
||||
{
|
||||
am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
|
||||
(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
|
||||
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
|
||||
AM33XX_LASTPOWERSTATEENTERED_MASK,
|
||||
pwrdm->prcm_offs, pwrdm->pwrstst_offs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
|
||||
{
|
||||
u32 m;
|
||||
|
||||
m = pwrdm->logicretstate_mask;
|
||||
if (!m)
|
||||
return -EINVAL;
|
||||
|
||||
am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
|
||||
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
|
||||
v &= AM33XX_LOGICSTATEST_MASK;
|
||||
v >>= AM33XX_LOGICSTATEST_SHIFT;
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
|
||||
{
|
||||
u32 v, m;
|
||||
|
||||
m = pwrdm->logicretstate_mask;
|
||||
if (!m)
|
||||
return -EINVAL;
|
||||
|
||||
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
|
||||
v &= m;
|
||||
v >>= __ffs(m);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
|
||||
u8 pwrst)
|
||||
{
|
||||
u32 m;
|
||||
|
||||
m = pwrdm->mem_on_mask[bank];
|
||||
if (!m)
|
||||
return -EINVAL;
|
||||
|
||||
am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
|
||||
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
|
||||
u8 pwrst)
|
||||
{
|
||||
u32 m;
|
||||
|
||||
m = pwrdm->mem_ret_mask[bank];
|
||||
if (!m)
|
||||
return -EINVAL;
|
||||
|
||||
am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
|
||||
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
|
||||
{
|
||||
u32 m, v;
|
||||
|
||||
m = pwrdm->mem_pwrst_mask[bank];
|
||||
if (!m)
|
||||
return -EINVAL;
|
||||
|
||||
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
|
||||
v &= m;
|
||||
v >>= __ffs(m);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
|
||||
{
|
||||
u32 m, v;
|
||||
|
||||
m = pwrdm->mem_retst_mask[bank];
|
||||
if (!m)
|
||||
return -EINVAL;
|
||||
|
||||
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
|
||||
v &= m;
|
||||
v >>= __ffs(m);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
|
||||
{
|
||||
u32 c = 0;
|
||||
|
||||
/*
|
||||
* REVISIT: pwrdm_wait_transition() may be better implemented
|
||||
* via a callback and a periodic timer check -- how long do we expect
|
||||
* powerdomain transitions to take?
|
||||
*/
|
||||
|
||||
/* XXX Is this udelay() value meaningful? */
|
||||
while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
|
||||
& OMAP_INTRANSITION_MASK) &&
|
||||
(c++ < PWRDM_TRANSITION_BAILOUT))
|
||||
udelay(1);
|
||||
|
||||
if (c > PWRDM_TRANSITION_BAILOUT) {
|
||||
pr_err("powerdomain: %s: waited too long to complete transition\n",
|
||||
pwrdm->name);
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
pr_debug("powerdomain: completed transition in %d loops\n", c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct pwrdm_ops am33xx_pwrdm_operations = {
|
||||
.pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
|
||||
.pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
|
||||
.pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
|
||||
.pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
|
||||
.pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
|
||||
.pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
|
||||
.pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
|
||||
.pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
|
||||
.pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
|
||||
.pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
|
||||
.pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
|
||||
.pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
|
||||
.pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
|
||||
.pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
|
||||
};
|
||||
185
arch/arm/mach-omap2/powerdomains33xx_data.c
Normal file
185
arch/arm/mach-omap2/powerdomains33xx_data.c
Normal file
@ -0,0 +1,185 @@
|
||||
/*
|
||||
* AM33XX Power domain data
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include "powerdomain.h"
|
||||
#include "prcm-common.h"
|
||||
#include "prm-regbits-33xx.h"
|
||||
#include "prm33xx.h"
|
||||
|
||||
static struct powerdomain gfx_33xx_pwrdm = {
|
||||
.name = "gfx_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = AM33XX_PRM_GFX_MOD,
|
||||
.pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
|
||||
.pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.banks = 1,
|
||||
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
|
||||
.mem_on_mask = {
|
||||
[0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */
|
||||
},
|
||||
.mem_ret_mask = {
|
||||
[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
|
||||
},
|
||||
.mem_pwrst_mask = {
|
||||
[0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */
|
||||
},
|
||||
.mem_retst_mask = {
|
||||
[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
|
||||
},
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* gfx_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* gfx_mem */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain rtc_33xx_pwrdm = {
|
||||
.name = "rtc_pwrdm",
|
||||
.voltdm = { .name = "rtc" },
|
||||
.prcm_offs = AM33XX_PRM_RTC_MOD,
|
||||
.pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
|
||||
.pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
|
||||
};
|
||||
|
||||
static struct powerdomain wkup_33xx_pwrdm = {
|
||||
.name = "wkup_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = AM33XX_PRM_WKUP_MOD,
|
||||
.pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
|
||||
.pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
|
||||
};
|
||||
|
||||
static struct powerdomain per_33xx_pwrdm = {
|
||||
.name = "per_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = AM33XX_PRM_PER_MOD,
|
||||
.pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
|
||||
.pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.banks = 3,
|
||||
.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
|
||||
.mem_on_mask = {
|
||||
[0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
|
||||
[1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */
|
||||
[2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */
|
||||
},
|
||||
.mem_ret_mask = {
|
||||
[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
|
||||
[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
|
||||
[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
|
||||
},
|
||||
.mem_pwrst_mask = {
|
||||
[0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
|
||||
[1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */
|
||||
[2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */
|
||||
},
|
||||
.mem_retst_mask = {
|
||||
[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
|
||||
[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
|
||||
[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
|
||||
},
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* pruss_mem */
|
||||
[1] = PWRSTS_OFF_RET, /* per_mem */
|
||||
[2] = PWRSTS_OFF_RET, /* ram_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* pruss_mem */
|
||||
[1] = PWRSTS_ON, /* per_mem */
|
||||
[2] = PWRSTS_ON, /* ram_mem */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain mpu_33xx_pwrdm = {
|
||||
.name = "mpu_pwrdm",
|
||||
.voltdm = { .name = "mpu" },
|
||||
.prcm_offs = AM33XX_PRM_MPU_MOD,
|
||||
.pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
|
||||
.pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.banks = 3,
|
||||
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
|
||||
.mem_on_mask = {
|
||||
[0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */
|
||||
[1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */
|
||||
[2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */
|
||||
},
|
||||
.mem_ret_mask = {
|
||||
[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
|
||||
[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
|
||||
[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
|
||||
},
|
||||
.mem_pwrst_mask = {
|
||||
[0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */
|
||||
[1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */
|
||||
[2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */
|
||||
},
|
||||
.mem_retst_mask = {
|
||||
[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
|
||||
[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
|
||||
[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
|
||||
},
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* mpu_l1 */
|
||||
[1] = PWRSTS_OFF_RET, /* mpu_l2 */
|
||||
[2] = PWRSTS_OFF_RET, /* mpu_ram */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* mpu_l1 */
|
||||
[1] = PWRSTS_ON, /* mpu_l2 */
|
||||
[2] = PWRSTS_ON, /* mpu_ram */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain cefuse_33xx_pwrdm = {
|
||||
.name = "cefuse_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = AM33XX_PRM_CEFUSE_MOD,
|
||||
.pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
|
||||
.pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct powerdomain *powerdomains_am33xx[] __initdata = {
|
||||
&gfx_33xx_pwrdm,
|
||||
&rtc_33xx_pwrdm,
|
||||
&wkup_33xx_pwrdm,
|
||||
&per_33xx_pwrdm,
|
||||
&mpu_33xx_pwrdm,
|
||||
&cefuse_33xx_pwrdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init am33xx_powerdomains_init(void)
|
||||
{
|
||||
pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
|
||||
pwrdm_register_pwrdms(powerdomains_am33xx);
|
||||
pwrdm_complete_init();
|
||||
}
|
||||
357
arch/arm/mach-omap2/prm-regbits-33xx.h
Normal file
357
arch/arm/mach-omap2/prm-regbits-33xx.h
Normal file
@ -0,0 +1,357 @@
|
||||
/*
|
||||
* AM33XX PRM_XXX register bits
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
|
||||
|
||||
#include "prm.h"
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
|
||||
#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
|
||||
#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_AIPOFF_SHIFT 8
|
||||
#define AM33XX_AIPOFF_MASK (1 << 8)
|
||||
|
||||
/* Used by PM_WKUP_PWRSTST */
|
||||
#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
|
||||
#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
|
||||
#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
|
||||
#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
|
||||
#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
|
||||
#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
|
||||
#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
|
||||
#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
|
||||
#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
|
||||
#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
|
||||
#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
|
||||
#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
|
||||
#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
|
||||
|
||||
/* Used by RM_WKUP_RSTST */
|
||||
#define AM33XX_EMULATION_M3_RST_SHIFT 6
|
||||
#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
|
||||
|
||||
/* Used by RM_MPU_RSTST */
|
||||
#define AM33XX_EMULATION_MPU_RST_SHIFT 5
|
||||
#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
|
||||
#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
|
||||
#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ENFUNC4_SHIFT 6
|
||||
#define AM33XX_ENFUNC4_MASK (1 << 6)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ENFUNC5_SHIFT 7
|
||||
#define AM33XX_ENFUNC5_MASK (1 << 7)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
|
||||
#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_FORCEWKUP_EN_SHIFT 10
|
||||
#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_FORCEWKUP_ST_SHIFT 10
|
||||
#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
|
||||
|
||||
/* Used by PM_GFX_PWRSTCTRL */
|
||||
#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
|
||||
#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
|
||||
|
||||
/* Used by PM_GFX_PWRSTCTRL */
|
||||
#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
|
||||
#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
|
||||
|
||||
/* Used by PM_GFX_PWRSTST */
|
||||
#define AM33XX_GFX_MEM_STATEST_SHIFT 4
|
||||
#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
|
||||
|
||||
/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
|
||||
#define AM33XX_GFX_RST_SHIFT 0
|
||||
#define AM33XX_GFX_RST_MASK (1 << 0)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
|
||||
#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
|
||||
#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
|
||||
|
||||
/* Used by RM_WKUP_RSTST */
|
||||
#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
|
||||
#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
|
||||
|
||||
/* Used by RM_MPU_RSTST */
|
||||
#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
|
||||
#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_ICEPICK_RST_SHIFT 9
|
||||
#define AM33XX_ICEPICK_RST_MASK (1 << 9)
|
||||
|
||||
/* Used by RM_PER_RSTCTRL */
|
||||
#define AM33XX_PRUSS_LRST_SHIFT 1
|
||||
#define AM33XX_PRUSS_LRST_MASK (1 << 1)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
|
||||
#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
|
||||
#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
|
||||
|
||||
/* Used by PM_PER_PWRSTST */
|
||||
#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
|
||||
#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
|
||||
|
||||
/*
|
||||
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
|
||||
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
|
||||
*/
|
||||
#define AM33XX_INTRANSITION_SHIFT 20
|
||||
#define AM33XX_INTRANSITION_MASK (1 << 20)
|
||||
|
||||
/* Used by PM_CEFUSE_PWRSTST */
|
||||
#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
|
||||
#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
|
||||
|
||||
/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
|
||||
#define AM33XX_LOGICRETSTATE_SHIFT 2
|
||||
#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
|
||||
|
||||
/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
|
||||
#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
|
||||
#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
|
||||
|
||||
/*
|
||||
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
|
||||
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
|
||||
*/
|
||||
#define AM33XX_LOGICSTATEST_SHIFT 2
|
||||
#define AM33XX_LOGICSTATEST_MASK (1 << 2)
|
||||
|
||||
/*
|
||||
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
|
||||
* PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
|
||||
*/
|
||||
#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
|
||||
#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
|
||||
#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
|
||||
#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
|
||||
|
||||
/* Used by PM_MPU_PWRSTST */
|
||||
#define AM33XX_MPU_L1_STATEST_SHIFT 6
|
||||
#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
|
||||
#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
|
||||
#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
|
||||
|
||||
/* Used by PM_MPU_PWRSTST */
|
||||
#define AM33XX_MPU_L2_STATEST_SHIFT 8
|
||||
#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
|
||||
#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
|
||||
#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
|
||||
|
||||
/* Used by PM_MPU_PWRSTST */
|
||||
#define AM33XX_MPU_RAM_STATEST_SHIFT 4
|
||||
#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
|
||||
#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
|
||||
|
||||
/* Used by PRM_SRAM_COUNT */
|
||||
#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
|
||||
#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
|
||||
|
||||
/* Used by RM_PER_RSTCTRL */
|
||||
#define AM33XX_PCI_LRST_SHIFT 0
|
||||
#define AM33XX_PCI_LRST_MASK (1 << 0)
|
||||
|
||||
/* Renamed from PCI_LRST Used by RM_PER_RSTST */
|
||||
#define AM33XX_PCI_LRST_5_5_SHIFT 5
|
||||
#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
|
||||
#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
|
||||
#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
|
||||
|
||||
/* Used by PM_PER_PWRSTST */
|
||||
#define AM33XX_PER_MEM_STATEST_SHIFT 17
|
||||
#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
|
||||
|
||||
/*
|
||||
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
|
||||
* PM_MPU_PWRSTCTRL
|
||||
*/
|
||||
#define AM33XX_POWERSTATE_SHIFT 0
|
||||
#define AM33XX_POWERSTATE_MASK (0x3 << 0)
|
||||
|
||||
/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
|
||||
#define AM33XX_POWERSTATEST_SHIFT 0
|
||||
#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
|
||||
#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
|
||||
#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
|
||||
|
||||
/* Used by PM_PER_PWRSTST */
|
||||
#define AM33XX_RAM_MEM_STATEST_SHIFT 21
|
||||
#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
|
||||
#define AM33XX_RETMODE_ENABLE_SHIFT 0
|
||||
#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
|
||||
|
||||
/* Used by REVISION_PRM */
|
||||
#define AM33XX_REV_SHIFT 0
|
||||
#define AM33XX_REV_MASK (0xff << 0)
|
||||
|
||||
/* Used by PRM_RSTTIME */
|
||||
#define AM33XX_RSTTIME1_SHIFT 0
|
||||
#define AM33XX_RSTTIME1_MASK (0xff << 0)
|
||||
|
||||
/* Used by PRM_RSTTIME */
|
||||
#define AM33XX_RSTTIME2_SHIFT 8
|
||||
#define AM33XX_RSTTIME2_MASK (0x1f << 8)
|
||||
|
||||
/* Used by PRM_RSTCTRL */
|
||||
#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
|
||||
#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
|
||||
|
||||
/* Used by PRM_RSTCTRL */
|
||||
#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
|
||||
#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
|
||||
|
||||
/* Used by PRM_SRAM_COUNT */
|
||||
#define AM33XX_SLPCNT_VALUE_SHIFT 16
|
||||
#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
|
||||
#define AM33XX_SRAMLDO_STATUS_SHIFT 8
|
||||
#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
|
||||
#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
|
||||
#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
|
||||
|
||||
/* Used by PRM_SRAM_COUNT */
|
||||
#define AM33XX_STARTUP_COUNT_SHIFT 24
|
||||
#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_TRANSITION_EN_SHIFT 8
|
||||
#define AM33XX_TRANSITION_EN_MASK (1 << 8)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_TRANSITION_ST_SHIFT 8
|
||||
#define AM33XX_TRANSITION_ST_MASK (1 << 8)
|
||||
|
||||
/* Used by PRM_SRAM_COUNT */
|
||||
#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
|
||||
#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_WDT0_RST_SHIFT 3
|
||||
#define AM33XX_WDT0_RST_MASK (1 << 3)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_WDT1_RST_SHIFT 4
|
||||
#define AM33XX_WDT1_RST_MASK (1 << 4)
|
||||
|
||||
/* Used by RM_WKUP_RSTCTRL */
|
||||
#define AM33XX_WKUP_M3_LRST_SHIFT 3
|
||||
#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
|
||||
|
||||
/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
|
||||
#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
|
||||
#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
|
||||
|
||||
#endif
|
||||
135
arch/arm/mach-omap2/prm33xx.c
Normal file
135
arch/arm/mach-omap2/prm33xx.c
Normal file
@ -0,0 +1,135 @@
|
||||
/*
|
||||
* AM33XX PRM functions
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <plat/common.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "prm33xx.h"
|
||||
#include "prm-regbits-33xx.h"
|
||||
|
||||
/* Read a register in a PRM instance */
|
||||
u32 am33xx_prm_read_reg(s16 inst, u16 idx)
|
||||
{
|
||||
return __raw_readl(prm_base + inst + idx);
|
||||
}
|
||||
|
||||
/* Write into a register in a PRM instance */
|
||||
void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
|
||||
{
|
||||
__raw_writel(val, prm_base + inst + idx);
|
||||
}
|
||||
|
||||
/* Read-modify-write a register in PRM. Caller must lock */
|
||||
u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_prm_read_reg(inst, idx);
|
||||
v &= ~mask;
|
||||
v |= bits;
|
||||
am33xx_prm_write_reg(v, inst, idx);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_prm_is_hardreset_asserted - read the HW reset line state of
|
||||
* submodules contained in the hwmod module
|
||||
* @shift: register bit shift corresponding to the reset line to check
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @rstctrl_offs: RM_RSTCTRL register address offset for this module
|
||||
*
|
||||
* Returns 1 if the (sub)module hardreset line is currently asserted,
|
||||
* 0 if the (sub)module hardreset line is not currently asserted, or
|
||||
* -EINVAL upon parameter error.
|
||||
*/
|
||||
int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = am33xx_prm_read_reg(inst, rstctrl_offs);
|
||||
v &= 1 << shift;
|
||||
v >>= shift;
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
|
||||
* @shift: register bit shift corresponding to the reset line to assert
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @rstctrl_reg: RM_RSTCTRL register address for this module
|
||||
*
|
||||
* Some IPs like dsp, ipu or iva contain processors that require an HW
|
||||
* reset line to be asserted / deasserted in order to fully enable the
|
||||
* IP. These modules may have multiple hard-reset lines that reset
|
||||
* different 'submodules' inside the IP block. This function will
|
||||
* place the submodule into reset. Returns 0 upon success or -EINVAL
|
||||
* upon an argument error.
|
||||
*/
|
||||
int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
|
||||
{
|
||||
u32 mask = 1 << shift;
|
||||
|
||||
am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
|
||||
* wait
|
||||
* @shift: register bit shift corresponding to the reset line to deassert
|
||||
* @inst: CM instance register offset (*_INST macro)
|
||||
* @rstctrl_reg: RM_RSTCTRL register address for this module
|
||||
* @rstst_reg: RM_RSTST register address for this module
|
||||
*
|
||||
* Some IPs like dsp, ipu or iva contain processors that require an HW
|
||||
* reset line to be asserted / deasserted in order to fully enable the
|
||||
* IP. These modules may have multiple hard-reset lines that reset
|
||||
* different 'submodules' inside the IP block. This function will
|
||||
* take the submodule out of reset and wait until the PRCM indicates
|
||||
* that the reset has completed before returning. Returns 0 upon success or
|
||||
* -EINVAL upon an argument error, -EEXIST if the submodule was already out
|
||||
* of reset, or -EBUSY if the submodule did not exit reset promptly.
|
||||
*/
|
||||
int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
|
||||
u16 rstctrl_offs, u16 rstst_offs)
|
||||
{
|
||||
int c;
|
||||
u32 mask = 1 << shift;
|
||||
|
||||
/* Check the current status to avoid de-asserting the line twice */
|
||||
if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
|
||||
return -EEXIST;
|
||||
|
||||
/* Clear the reset status by writing 1 to the status bit */
|
||||
am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
|
||||
/* de-assert the reset control line */
|
||||
am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
|
||||
/* wait the status to be set */
|
||||
|
||||
omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
|
||||
rstst_offs),
|
||||
MAX_MODULE_HARDRESET_WAIT, c);
|
||||
|
||||
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
|
||||
}
|
||||
129
arch/arm/mach-omap2/prm33xx.h
Normal file
129
arch/arm/mach-omap2/prm33xx.h
Normal file
@ -0,0 +1,129 @@
|
||||
/*
|
||||
* AM33XX PRM instance offset macros
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
|
||||
|
||||
#include "prcm-common.h"
|
||||
#include "prm.h"
|
||||
|
||||
#define AM33XX_PRM_BASE 0x44E00000
|
||||
|
||||
#define AM33XX_PRM_REGADDR(inst, reg) \
|
||||
AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
|
||||
|
||||
|
||||
/* PRM instances */
|
||||
#define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
|
||||
#define AM33XX_PRM_PER_MOD 0x0C00
|
||||
#define AM33XX_PRM_WKUP_MOD 0x0D00
|
||||
#define AM33XX_PRM_MPU_MOD 0x0E00
|
||||
#define AM33XX_PRM_DEVICE_MOD 0x0F00
|
||||
#define AM33XX_PRM_RTC_MOD 0x1000
|
||||
#define AM33XX_PRM_GFX_MOD 0x1100
|
||||
#define AM33XX_PRM_CEFUSE_MOD 0x1200
|
||||
|
||||
/* PRM */
|
||||
|
||||
/* PRM.OCP_SOCKET_PRM register offsets */
|
||||
#define AM33XX_REVISION_PRM_OFFSET 0x0000
|
||||
#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
|
||||
#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
|
||||
#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
|
||||
#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
|
||||
#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
|
||||
#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c
|
||||
#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
|
||||
#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010
|
||||
#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
|
||||
|
||||
/* PRM.PER_PRM register offsets */
|
||||
#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
|
||||
#define AM33XX_RM_PER_RSTST_OFFSET 0x0004
|
||||
#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
|
||||
#define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
|
||||
#define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
|
||||
#define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c
|
||||
#define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
|
||||
|
||||
/* PRM.WKUP_PRM register offsets */
|
||||
#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
|
||||
#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004
|
||||
#define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
|
||||
#define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008
|
||||
#define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
|
||||
#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c
|
||||
#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
|
||||
|
||||
/* PRM.MPU_PRM register offsets */
|
||||
#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
|
||||
#define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004
|
||||
#define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
|
||||
#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008
|
||||
#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
|
||||
|
||||
/* PRM.DEVICE_PRM register offsets */
|
||||
#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
|
||||
#define AM33XX_PRM_RSTTIME_OFFSET 0x0004
|
||||
#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
|
||||
#define AM33XX_PRM_RSTST_OFFSET 0x0008
|
||||
#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
|
||||
#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c
|
||||
#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
|
||||
#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010
|
||||
#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
|
||||
#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014
|
||||
#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
|
||||
#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018
|
||||
#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
|
||||
#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c
|
||||
#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
|
||||
|
||||
/* PRM.RTC_PRM register offsets */
|
||||
#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
|
||||
#define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004
|
||||
#define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
|
||||
|
||||
/* PRM.GFX_PRM register offsets */
|
||||
#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
|
||||
#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004
|
||||
#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
|
||||
#define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010
|
||||
#define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
|
||||
#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014
|
||||
#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
|
||||
|
||||
/* PRM.CEFUSE_PRM register offsets */
|
||||
#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
|
||||
#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
|
||||
#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
|
||||
|
||||
extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
|
||||
extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
|
||||
extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
|
||||
extern void am33xx_prm_global_warm_sw_reset(void);
|
||||
extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
|
||||
u16 rstctrl_offs);
|
||||
extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
|
||||
extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
|
||||
u16 rstctrl_offs, u16 rstst_offs);
|
||||
#endif
|
||||
@ -368,6 +368,11 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
|
||||
OMAP_SYS_TIMER(3_secure)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
|
||||
OMAP_SYS_TIMER(3_am33xx)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
|
||||
|
||||
@ -156,6 +156,7 @@ int omap_voltage_late_init(void);
|
||||
|
||||
extern void omap2xxx_voltagedomains_init(void);
|
||||
extern void omap3xxx_voltagedomains_init(void);
|
||||
extern void am33xx_voltagedomains_init(void);
|
||||
extern void omap44xx_voltagedomains_init(void);
|
||||
|
||||
struct voltagedomain *voltdm_lookup(const char *name);
|
||||
|
||||
43
arch/arm/mach-omap2/voltagedomains33xx_data.c
Normal file
43
arch/arm/mach-omap2/voltagedomains33xx_data.c
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* AM33XX voltage domain data
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include "voltage.h"
|
||||
|
||||
static struct voltagedomain am33xx_voltdm_mpu = {
|
||||
.name = "mpu",
|
||||
};
|
||||
|
||||
static struct voltagedomain am33xx_voltdm_core = {
|
||||
.name = "core",
|
||||
};
|
||||
|
||||
static struct voltagedomain am33xx_voltdm_rtc = {
|
||||
.name = "rtc",
|
||||
};
|
||||
|
||||
static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
|
||||
&am33xx_voltdm_mpu,
|
||||
&am33xx_voltdm_core,
|
||||
&am33xx_voltdm_rtc,
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init am33xx_voltagedomains_init(void)
|
||||
{
|
||||
voltdm_init(voltagedomains_am33xx);
|
||||
}
|
||||
@ -60,6 +60,9 @@
|
||||
/* AM3505/3517 UART4 */
|
||||
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
|
||||
|
||||
/* AM33XX serial port */
|
||||
#define AM33XX_UART1_BASE 0x44E09000
|
||||
|
||||
/* External port on Zoom2/3 */
|
||||
#define ZOOM_UART_BASE 0x10000000
|
||||
#define ZOOM_UART_VIRT 0xfa400000
|
||||
@ -93,6 +96,7 @@
|
||||
#define TI81XXUART1 81
|
||||
#define TI81XXUART2 82
|
||||
#define TI81XXUART3 83
|
||||
#define AM33XXUART1 84
|
||||
#define ZOOM_UART 95 /* Only on zoom2/3 */
|
||||
|
||||
/* This is only used by 8250.c for omap1510 */
|
||||
|
||||
@ -103,6 +103,10 @@ static inline void flush(void)
|
||||
_DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
|
||||
TI81XXUART##p)
|
||||
|
||||
#define DEBUG_LL_AM33XX(p, mach) \
|
||||
_DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
|
||||
AM33XXUART##p)
|
||||
|
||||
static inline void __arch_decomp_setup(unsigned long arch_id)
|
||||
{
|
||||
int port = 0;
|
||||
@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
|
||||
/* TI8148 base boards using UART1 */
|
||||
DEBUG_LL_TI81XX(1, ti8148evm);
|
||||
|
||||
/* AM33XX base boards using UART1 */
|
||||
DEBUG_LL_AM33XX(1, am335xevm);
|
||||
} while (0);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user