forked from Minki/linux
iwlwifi: Partially clean-up, add comments to iwl-*-hw.h
Partially clean-up, add comments to iwl-XXXX-hw.h Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Ben Cahill
David S. Miller
parent
f7d09d7c45
commit
1fea8e8838
@ -64,10 +64,11 @@
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#ifndef __iwl_3945_hw__
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#define __iwl_3945_hw__
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/* uCode queue management definitions */
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/*
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* uCode queue management definitions ...
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* Queue #4 is the command queue for 3945 and 4965.
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*/
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#define IWL_CMD_QUEUE_NUM 4
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#define IWL_CMD_FIFO_NUM 4
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#define IWL_BACK_QUEUE_FIRST_ID 7
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/* Tx rates */
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#define IWL_CCK_RATES 4
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@ -314,7 +315,6 @@ struct iwl3945_eeprom {
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u8 reserved9[194];
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/*
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* 3945 Txpower calibration data.
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*/
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@ -355,7 +355,18 @@ struct iwl3945_eeprom {
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#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
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#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
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#define CSR_GP_CNTRL (CSR_BASE+0x024)
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/*
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* Hardware revision info
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* Bit fields:
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* 31-8: Reserved
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* 7-4: Type of device: 0x0 = 4965, 0xd = 3945
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* 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
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* 1-0: "Dash" value, as in A-1, etc.
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*/
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#define CSR_HW_REV (CSR_BASE+0x028)
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/* EEPROM reads */
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#define CSR_EEPROM_REG (CSR_BASE+0x02c)
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#define CSR_EEPROM_GP (CSR_BASE+0x030)
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#define CSR_GP_UCODE (CSR_BASE+0x044)
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@ -363,13 +374,13 @@ struct iwl3945_eeprom {
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#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
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#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
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#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
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#define CSR_LED_REG (CSR_BASE+0x094)
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#define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0)
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#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
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#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
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#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
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/* HW I/F configuration */
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/* Analog phase-lock-loop configuration (3945 only)
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* Set bit 24. */
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#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
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/* Bits for CSR_HW_IF_CONFIG_REG */
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#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
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#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
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#define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
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@ -468,31 +479,46 @@ struct iwl3945_eeprom {
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/* CSR_ANA_PLL_CFG */
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#define CSR_ANA_PLL_CFG_SH (0x00880300)
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#define CSR_LED_REG_TRUN_ON (0x00000078)
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#define CSR_LED_REG_TRUN_OFF (0x00000038)
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#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
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/* DRAM_INT_TBL_CTRL */
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#define CSR_DRAM_INT_TBL_CTRL_EN (1<<31)
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#define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27)
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/*=== HBUS (Host-side Bus) ===*/
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#define HBUS_BASE (0x400)
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/*
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* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
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* structures, error log, event log, verifying uCode load).
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* First write to address register, then read from or write to data register
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* to complete the job. Once the address register is set up, accesses to
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* data registers auto-increment the address by one dword.
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* Bit usage for address registers (read or write):
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* 0-31: memory address within device
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*/
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#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
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#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
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#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
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#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
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/*
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* Registers for accessing device's internal peripheral registers
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* (e.g. SCD, BSM, etc.). First write to address register,
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* then read from or write to data register to complete the job.
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* Bit usage for address registers (read or write):
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* 0-15: register address (offset) within device
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* 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
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*/
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#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
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#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
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#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
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#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
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/*
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* Per-Tx-queue write pointer (index, really!) (3945 and 4965).
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* Indicates index to next TFD that driver will fill (1 past latest filled).
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* Bit usage:
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* 0-7: queue write index
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* 11-8: queue selector
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*/
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#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
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#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
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/* SCD (Scheduler) */
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/* SCD (3945 Tx Frame Scheduler) */
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#define SCD_BASE (CSR_BASE + 0x2E00)
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#define SCD_MODE_REG (SCD_BASE + 0x000)
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@ -64,7 +64,12 @@
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#ifndef __iwl_4965_hw_h__
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#define __iwl_4965_hw_h__
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/* uCode queue management definitions */
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/*
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* uCode queue management definitions ...
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* Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4.
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* The first queue used for block-ack aggregation is #7 (4965 only).
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* All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
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*/
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#define IWL_CMD_QUEUE_NUM 4
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#define IWL_CMD_FIFO_NUM 4
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#define IWL_BACK_QUEUE_FIRST_ID 7
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@ -444,7 +449,20 @@ struct iwl4965_eeprom {
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#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
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#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
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#define CSR_GP_CNTRL (CSR_BASE+0x024)
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/*
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* Hardware revision info
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* Bit fields:
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* 31-8: Reserved
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* 7-4: Type of device: 0x0 = 4965, 0xd = 3945
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* 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
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* 1-0: "Dash" value, as in A-1, etc.
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*
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* NOTE: Revision step affects calculation of CCK txpower for 4965.
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*/
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#define CSR_HW_REV (CSR_BASE+0x028)
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/* EEPROM reads */
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#define CSR_EEPROM_REG (CSR_BASE+0x02c)
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#define CSR_EEPROM_GP (CSR_BASE+0x030)
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#define CSR_GP_UCODE (CSR_BASE+0x044)
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@ -452,10 +470,13 @@ struct iwl4965_eeprom {
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#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
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#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
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#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
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#define CSR_LED_REG (CSR_BASE+0x094)
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#define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0)
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#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
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#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
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/*
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* Indicates hardware rev, to determine CCK backoff for txpower calculation.
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* Bit fields:
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* 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
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*/
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#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
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/* HW I/F configuration */
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@ -554,44 +575,47 @@ struct iwl4965_eeprom {
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
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/* CSR_ANA_PLL_CFG */
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#define CSR_ANA_PLL_CFG_SH (0x00880300)
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#define CSR_LED_REG_TRUN_ON (0x00000078)
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#define CSR_LED_REG_TRUN_OFF (0x00000038)
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#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
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/* DRAM_INT_TBL_CTRL */
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#define CSR_DRAM_INT_TBL_CTRL_EN (1<<31)
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#define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27)
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/*=== HBUS (Host-side Bus) ===*/
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#define HBUS_BASE (0x400)
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/*
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* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
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* structures, error log, event log, verifying uCode load).
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* First write to address register, then read from or write to data register
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* to complete the job. Once the address register is set up, accesses to
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* data registers auto-increment the address by one dword.
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* Bit usage for address registers (read or write):
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* 0-31: memory address within device
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*/
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#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
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#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
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#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
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#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
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/*
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* Registers for accessing device's internal peripheral registers
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* (e.g. SCD, BSM, etc.). First write to address register,
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* then read from or write to data register to complete the job.
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* Bit usage for address registers (read or write):
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* 0-15: register address (offset) within device
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* 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
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*/
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#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
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#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
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#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
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#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
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/*
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* Per-Tx-queue write pointer (index, really!) (3945 and 4965).
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* Indicates index to next TFD that driver will fill (1 past latest filled).
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* Bit usage:
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* 0-7: queue write index (0-255)
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* 11-8: queue selector (0-15)
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*/
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#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
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#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
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/* SCD (Scheduler) */
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#define SCD_BASE (CSR_BASE + 0x2E00)
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#define SCD_MODE_REG (SCD_BASE + 0x000)
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#define SCD_ARASTAT_REG (SCD_BASE + 0x004)
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#define SCD_TXFACT_REG (SCD_BASE + 0x010)
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#define SCD_TXF4MF_REG (SCD_BASE + 0x014)
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#define SCD_TXF5MF_REG (SCD_BASE + 0x020)
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#define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
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#define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
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/*=== FH (data Flow Handler) ===*/
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#define FH_BASE (0x800)
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