Merge branch 'irqchip/keystone' into irqchip/core
This commit is contained in:
Jason Cooper
commit
1fc9d96ec6
@ -0,0 +1,36 @@
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Keystone 2 IRQ controller IP
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On Keystone SOCs, DSP cores can send interrupts to ARM
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host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
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The IRQ handler running on HOST OS can identify DSP signal source by
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analyzing SRCCx bits in IPCARx registers. This is one of the component
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used by the IPC mechanism used on Keystone SOCs.
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Required Properties:
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- compatible: should be "ti,keystone-irq"
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- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
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access device control registers and the offset inside
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device control registers range.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode interrupt
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source should be 1.
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- interrupts: interrupt reference to primary interrupt controller
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Please refer to interrupts.txt in this directory for details of the common
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Interrupt Controllers bindings used by client devices.
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Example:
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kirq0: keystone_irq0@026202a0 {
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compatible = "ti,keystone-irq";
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ti,syscon-dev = <&devctrl 0x2a0>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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dsp0: dsp0 {
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compatible = "linux,rproc-user";
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...
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interrupt-parent = <&kirq0>;
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interrupts = <10 2>;
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};
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@ -113,3 +113,10 @@ config IRQ_CROSSBAR
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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config KEYSTONE_IRQ
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tristate "Keystone 2 IRQ controller IP"
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depends on ARCH_KEYSTONE
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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@ -34,3 +34,4 @@ obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
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obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
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obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
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obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
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obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
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232
drivers/irqchip/irq-keystone.c
Normal file
232
drivers/irqchip/irq-keystone.c
Normal file
@ -0,0 +1,232 @@
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/*
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* Texas Instruments Keystone IRQ controller IP driver
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*
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* Copyright (C) 2014 Texas Instruments, Inc.
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* Author: Sajesh Kumar Saran <sajesh@ti.com>
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* Grygorii Strashko <grygorii.strashko@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "irqchip.h"
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/* The source ID bits start from 4 to 31 (total 28 bits)*/
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#define BIT_OFS 4
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#define KEYSTONE_N_IRQ (32 - BIT_OFS)
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struct keystone_irq_device {
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struct device *dev;
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struct irq_chip chip;
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u32 mask;
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int irq;
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struct irq_domain *irqd;
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struct regmap *devctrl_regs;
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u32 devctrl_offset;
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};
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static inline u32 keystone_irq_readl(struct keystone_irq_device *kirq)
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{
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int ret;
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u32 val = 0;
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ret = regmap_read(kirq->devctrl_regs, kirq->devctrl_offset, &val);
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if (ret < 0)
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dev_dbg(kirq->dev, "irq read failed ret(%d)\n", ret);
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return val;
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}
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static inline void
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keystone_irq_writel(struct keystone_irq_device *kirq, u32 value)
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{
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int ret;
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ret = regmap_write(kirq->devctrl_regs, kirq->devctrl_offset, value);
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if (ret < 0)
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dev_dbg(kirq->dev, "irq write failed ret(%d)\n", ret);
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}
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static void keystone_irq_setmask(struct irq_data *d)
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{
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struct keystone_irq_device *kirq = irq_data_get_irq_chip_data(d);
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kirq->mask |= BIT(d->hwirq);
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dev_dbg(kirq->dev, "mask %lu [%x]\n", d->hwirq, kirq->mask);
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}
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static void keystone_irq_unmask(struct irq_data *d)
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{
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struct keystone_irq_device *kirq = irq_data_get_irq_chip_data(d);
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kirq->mask &= ~BIT(d->hwirq);
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dev_dbg(kirq->dev, "unmask %lu [%x]\n", d->hwirq, kirq->mask);
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}
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static void keystone_irq_ack(struct irq_data *d)
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{
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/* nothing to do here */
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}
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static void keystone_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct keystone_irq_device *kirq = irq_desc_get_handler_data(desc);
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unsigned long pending;
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int src, virq;
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dev_dbg(kirq->dev, "start irq %d\n", irq);
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chained_irq_enter(irq_desc_get_chip(desc), desc);
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pending = keystone_irq_readl(kirq);
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keystone_irq_writel(kirq, pending);
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dev_dbg(kirq->dev, "pending 0x%lx, mask 0x%x\n", pending, kirq->mask);
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pending = (pending >> BIT_OFS) & ~kirq->mask;
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dev_dbg(kirq->dev, "pending after mask 0x%lx\n", pending);
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for (src = 0; src < KEYSTONE_N_IRQ; src++) {
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if (BIT(src) & pending) {
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virq = irq_find_mapping(kirq->irqd, src);
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dev_dbg(kirq->dev, "dispatch bit %d, virq %d\n",
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src, virq);
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if (!virq)
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dev_warn(kirq->dev, "sporious irq detected hwirq %d, virq %d\n",
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src, virq);
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generic_handle_irq(virq);
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}
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}
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chained_irq_exit(irq_desc_get_chip(desc), desc);
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dev_dbg(kirq->dev, "end irq %d\n", irq);
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}
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static int keystone_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct keystone_irq_device *kirq = h->host_data;
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irq_set_chip_data(virq, kirq);
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irq_set_chip_and_handler(virq, &kirq->chip, handle_level_irq);
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops keystone_irq_ops = {
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.map = keystone_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int keystone_irq_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct keystone_irq_device *kirq;
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int ret;
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if (np == NULL)
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return -EINVAL;
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kirq = devm_kzalloc(dev, sizeof(*kirq), GFP_KERNEL);
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if (!kirq)
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return -ENOMEM;
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kirq->devctrl_regs =
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syscon_regmap_lookup_by_phandle(np, "ti,syscon-dev");
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if (IS_ERR(kirq->devctrl_regs))
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return PTR_ERR(kirq->devctrl_regs);
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ret = of_property_read_u32_index(np, "ti,syscon-dev", 1,
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&kirq->devctrl_offset);
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if (ret) {
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dev_err(dev, "couldn't read the devctrl_offset offset!\n");
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return ret;
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}
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kirq->irq = platform_get_irq(pdev, 0);
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if (kirq->irq < 0) {
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dev_err(dev, "no irq resource %d\n", kirq->irq);
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return kirq->irq;
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}
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kirq->dev = dev;
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kirq->mask = ~0x0;
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kirq->chip.name = "keystone-irq";
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kirq->chip.irq_ack = keystone_irq_ack;
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kirq->chip.irq_mask = keystone_irq_setmask;
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kirq->chip.irq_unmask = keystone_irq_unmask;
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kirq->irqd = irq_domain_add_linear(np, KEYSTONE_N_IRQ,
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&keystone_irq_ops, kirq);
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if (!kirq->irqd) {
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dev_err(dev, "IRQ domain registration failed\n");
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return -ENODEV;
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}
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platform_set_drvdata(pdev, kirq);
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irq_set_chained_handler(kirq->irq, keystone_irq_handler);
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irq_set_handler_data(kirq->irq, kirq);
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/* clear all source bits */
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keystone_irq_writel(kirq, ~0x0);
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dev_info(dev, "irqchip registered, nr_irqs %u\n", KEYSTONE_N_IRQ);
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return 0;
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}
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static int keystone_irq_remove(struct platform_device *pdev)
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{
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struct keystone_irq_device *kirq = platform_get_drvdata(pdev);
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int hwirq;
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for (hwirq = 0; hwirq < KEYSTONE_N_IRQ; hwirq++)
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irq_dispose_mapping(irq_find_mapping(kirq->irqd, hwirq));
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irq_domain_remove(kirq->irqd);
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return 0;
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}
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static const struct of_device_id keystone_irq_dt_ids[] = {
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{ .compatible = "ti,keystone-irq", },
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{},
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};
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MODULE_DEVICE_TABLE(of, keystone_irq_dt_ids);
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static struct platform_driver keystone_irq_device_driver = {
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.probe = keystone_irq_probe,
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.remove = keystone_irq_remove,
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.driver = {
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.name = "keystone_irq",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(keystone_irq_dt_ids),
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}
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};
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module_platform_driver(keystone_irq_device_driver);
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MODULE_AUTHOR("Texas Instruments");
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MODULE_AUTHOR("Sajesh Kumar Saran");
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MODULE_AUTHOR("Grygorii Strashko");
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MODULE_DESCRIPTION("Keystone IRQ chip");
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MODULE_LICENSE("GPL v2");
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