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[ARM] mv78xx0: wire up ethernet error interrupt

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Wire up the ethernet port's error interrupt so that the
mv643xx_eth driver can sleep for SMI event completion instead of
having to busy-wait for it.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Lennert Buytenhek 2008-08-26 16:04:05 +02:00 committed by Nicolas Pitre
parent 144f814a43
commit 1f8081f539
5 changed files with 28 additions and 7 deletions
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7
arch/arm/mach-mv78xx0/common.c
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@ -285,6 +285,11 @@ static struct resource mv78xx0_ge00_shared_resources[] = {
.start = GE00_PHYS_BASE + 0x2000, .start = GE00_PHYS_BASE + 0x2000,
.end = GE00_PHYS_BASE + 0x3fff, .end = GE00_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, {
.name = "ge err irq",
.start = IRQ_MV78XX0_GE_ERR,
.end = IRQ_MV78XX0_GE_ERR,
.flags = IORESOURCE_IRQ,
}, },
}; };
@ -294,7 +299,7 @@ static struct platform_device mv78xx0_ge00_shared = {
.dev = { .dev = {
.platform_data = &mv78xx0_ge00_shared_data, .platform_data = &mv78xx0_ge00_shared_data,
}, },
.num_resources = 1, .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
.resource = mv78xx0_ge00_shared_resources, .resource = mv78xx0_ge00_shared_resources,
}; };

18
arch/arm/mach-mv78xx0/include/mach/entry-macro.S
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@ -26,14 +26,22 @@
ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
mov \irqnr, #31 mov \irqnr, #31
ands \irqstat, \irqstat, \tmp ands \irqstat, \irqstat, \tmp
bne 1001f
@ if no low interrupts set, check high interrupts @ if no low interrupts set, check high interrupts
ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
moveq \irqnr, #63 mov \irqnr, #63
andeqs \irqstat, \irqstat, \tmp ands \irqstat, \irqstat, \tmp
bne 1001f
@ if no high interrupts set, check error interrupts
ldr \irqstat, [\base, #IRQ_CAUSE_ERR_OFF]
ldr \tmp, [\base, #IRQ_MASK_ERR_OFF]
mov \irqnr, #95
ands \irqstat, \irqstat, \tmp
@ find first active interrupt source @ find first active interrupt source
clzne \irqstat, \irqstat 1001: clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat subne \irqnr, \irqnr, \irqstat
.endm .endm

7
arch/arm/mach-mv78xx0/include/mach/irqs.h
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@ -79,10 +79,15 @@
#define IRQ_MV78XX0_DB_IN 60 #define IRQ_MV78XX0_DB_IN 60
#define IRQ_MV78XX0_DB_OUT 61 #define IRQ_MV78XX0_DB_OUT 61
/*
* MV78xx0 Error Interrupt Controller
*/
#define IRQ_MV78XX0_GE_ERR 70
/* /*
* MV78XX0 General Purpose Pins * MV78XX0 General Purpose Pins
*/ */
#define IRQ_MV78XX0_GPIO_START 64 #define IRQ_MV78XX0_GPIO_START 96
#define NR_GPIO_IRQS GPIO_MAX #define NR_GPIO_IRQS GPIO_MAX
#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) #define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)

2
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
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@ -71,8 +71,10 @@
#define BRIDGE_INT_TIMER1 0x0004 #define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004) #define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_ERR_OFF 0x0000
#define IRQ_CAUSE_LOW_OFF 0x0004 #define IRQ_CAUSE_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0008 #define IRQ_CAUSE_HIGH_OFF 0x0008
#define IRQ_MASK_ERR_OFF 0x000c
#define IRQ_MASK_LOW_OFF 0x0010 #define IRQ_MASK_LOW_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014 #define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)

1
arch/arm/mach-mv78xx0/irq.c
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@ -19,4 +19,5 @@ void __init mv78xx0_init_irq(void)
{ {
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
} }