forked from Minki/linux
Watchdog: sp5100_tco: Refactor MMIO base address initialization
Combine MMIO base address and alternate base address detection. Combine based on layout type. This will simplify the function by eliminating a switch case. Move existing request/release code into functions. This currently only supports port I/O request/release. The move into a separate function will make it ready for adding MMIO region support. Co-developed-by: Robert Richter <rrichter@amd.com> Signed-off-by: Robert Richter <rrichter@amd.com> Signed-off-by: Terry Bowman <terry.bowman@amd.com> Tested-by: Jean Delvare <jdelvare@suse.de> Reviewed-by: Jean Delvare <jdelvare@suse.de> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220202153525.1693378-3-terry.bowman@amd.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Terry Bowman
Wim Van Sebroeck
parent
abd71a948f
commit
1f182aca23
@ -223,6 +223,55 @@ static u32 sp5100_tco_read_pm_reg32(u8 index)
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return val;
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}
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static u32 sp5100_tco_request_region(struct device *dev,
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u32 mmio_addr,
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const char *dev_name)
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{
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if (!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
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dev_name)) {
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dev_dbg(dev, "MMIO address 0x%08x already in use\n", mmio_addr);
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return 0;
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}
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return mmio_addr;
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}
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static u32 sp5100_tco_prepare_base(struct sp5100_tco *tco,
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u32 mmio_addr,
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u32 alt_mmio_addr,
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const char *dev_name)
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{
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struct device *dev = tco->wdd.parent;
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dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n", mmio_addr);
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if (!mmio_addr && !alt_mmio_addr)
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return -ENODEV;
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/* Check for MMIO address and alternate MMIO address conflicts */
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if (mmio_addr)
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mmio_addr = sp5100_tco_request_region(dev, mmio_addr, dev_name);
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if (!mmio_addr && alt_mmio_addr)
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mmio_addr = sp5100_tco_request_region(dev, alt_mmio_addr, dev_name);
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if (!mmio_addr) {
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dev_err(dev, "Failed to reserve MMIO or alternate MMIO region\n");
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return -EBUSY;
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}
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tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
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if (!tco->tcobase) {
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dev_err(dev, "MMIO address 0x%08x failed mapping\n", mmio_addr);
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devm_release_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
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return -ENOMEM;
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}
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dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
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return 0;
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}
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static int sp5100_tco_timer_init(struct sp5100_tco *tco)
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{
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struct watchdog_device *wdd = &tco->wdd;
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@ -264,6 +313,7 @@ static int sp5100_tco_setupdevice(struct device *dev,
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struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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const char *dev_name;
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u32 mmio_addr = 0, val;
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u32 alt_mmio_addr = 0;
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int ret;
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/* Request the IO ports used by this driver */
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@ -282,11 +332,32 @@ static int sp5100_tco_setupdevice(struct device *dev,
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dev_name = SP5100_DEVNAME;
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mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
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0xfffffff8;
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/*
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* Secondly, find the watchdog timer MMIO address
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* from SBResource_MMIO register.
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*/
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/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
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pci_read_config_dword(sp5100_tco_pci,
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SP5100_SB_RESOURCE_MMIO_BASE,
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&val);
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/* Verify MMIO is enabled and using bar0 */
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if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
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alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
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break;
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case sb800:
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dev_name = SB800_DEVNAME;
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mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
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0xfffffff8;
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/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
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val = sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
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/* Verify MMIO is enabled and using bar0 */
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if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
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alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
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break;
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case efch:
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dev_name = SB800_DEVNAME;
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@ -305,87 +376,23 @@ static int sp5100_tco_setupdevice(struct device *dev,
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val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
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if (val & EFCH_PM_DECODEEN_WDT_TMREN)
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mmio_addr = EFCH_PM_WDT_ADDR;
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val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
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if (val & EFCH_PM_ISACONTROL_MMIOEN)
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alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
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EFCH_PM_ACPI_MMIO_WDT_OFFSET;
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break;
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default:
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return -ENODEV;
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}
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/* Check MMIO address conflict */
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if (!mmio_addr ||
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!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
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dev_name)) {
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if (mmio_addr)
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dev_dbg(dev, "MMIO address 0x%08x already in use\n",
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mmio_addr);
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switch (tco->tco_reg_layout) {
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case sp5100:
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/*
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* Secondly, Find the watchdog timer MMIO address
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* from SBResource_MMIO register.
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*/
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/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
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pci_read_config_dword(sp5100_tco_pci,
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SP5100_SB_RESOURCE_MMIO_BASE,
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&mmio_addr);
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if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
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SB800_ACPI_MMIO_SEL)) !=
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SB800_ACPI_MMIO_DECODE_EN) {
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr &= ~0xFFF;
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mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
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break;
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case sb800:
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/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
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mmio_addr =
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sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
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if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
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SB800_ACPI_MMIO_SEL)) !=
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SB800_ACPI_MMIO_DECODE_EN) {
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr &= ~0xFFF;
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mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
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break;
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case efch:
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val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
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if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
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EFCH_PM_ACPI_MMIO_WDT_OFFSET;
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break;
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}
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dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
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mmio_addr);
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if (!devm_request_mem_region(dev, mmio_addr,
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SP5100_WDT_MEM_MAP_SIZE,
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dev_name)) {
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dev_dbg(dev, "MMIO address 0x%08x already in use\n",
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mmio_addr);
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ret = -EBUSY;
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goto unreg_region;
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}
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ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
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if (!ret) {
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/* Setup the watchdog timer */
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tco_timer_enable(tco);
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ret = sp5100_tco_timer_init(tco);
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}
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tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
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if (!tco->tcobase) {
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dev_err(dev, "failed to get tcobase address\n");
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ret = -ENOMEM;
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goto unreg_region;
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}
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dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
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/* Setup the watchdog timer */
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tco_timer_enable(tco);
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ret = sp5100_tco_timer_init(tco);
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unreg_region:
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release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
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return ret;
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}
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@ -58,6 +58,7 @@
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#define SB800_PM_WATCHDOG_SECOND_RES GENMASK(1, 0)
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#define SB800_ACPI_MMIO_DECODE_EN BIT(0)
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#define SB800_ACPI_MMIO_SEL BIT(1)
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#define SB800_ACPI_MMIO_MASK GENMASK(1, 0)
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#define SB800_PM_WDT_MMIO_OFFSET 0xB00
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