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[MIPS] MIPS R2 optimized endianess swapping.

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From Franck Bui-Huu <vagabon.xyz@gmail.com> with modifications by me.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2006-02-01 15:29:21 +00:00
parent 7e5b24ac75
commit 1e32ceeca2
1 changed files with 29 additions and 0 deletions
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29
include/asm-mips/byteorder.h
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@ -8,10 +8,39 @@
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
#include <linux/config.h>
#include <linux/compiler.h>
#include <asm/types.h>
#ifdef __GNUC__
#ifdef CONFIG_CPU_MIPSR2
static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
{
__asm__(
" wsbh %0, %1 \n"
: "=r" (x)
: "r" (x));
return x;
}
#define __arch__swab16(x) ___arch__swab16(x)
static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
{
__asm__(
" wsbh %0, %1 \n"
" rotr %0, %0, 16 \n"
: "=r" (x)
: "r" (x));
return x;
}
#define __arch__swab32(x) ___arch__swab32(x)
#endif /* CONFIG_CPU_MIPSR2 */
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__