clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:
one fractional part and one divider. On SAMA7G5 the CPU PLL could be
changed at run-time to implement DVFS. The hardware clock tree on
SAMA7G5 for CPU PLL is as follows:
+---- div1 ----------------> cpuck
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FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0
The div1 block is not implemented in Linux; on prescaler block it has
been discovered a bug on some scenarios and will be removed from Linux
in next commits. Thus, the final clock tree that will be used in Linux
will be as follows:
+-----------> cpuck
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FRAC PLL ---> DIV PLL -+-> div0 ---> mck0
It has been proposed in [1] to not introduce a new CPUFreq driver but
to overload the proper clock drivers with proper operation such that
cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement
clock notifiers which applies safe dividers before FRAC PLL is changed.
The current commit treats only the DIV PLL by adding a notifier that
sets a safe divider on PRE_RATE_CHANGE events. The safe divider is
provided by initialization clock code (sama7g5.c). The div0 is treated
in next commits (to keep the changes as clean as possible).
[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Claudiu Beznea
Stephen Boyd
parent
0ef99f8202
commit
1e229c21a4
@ -5,6 +5,7 @@
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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@ -47,12 +48,15 @@ struct sam9x60_div {
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struct sam9x60_pll_core core;
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struct at91_clk_pms pms;
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u8 div;
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u8 safe_div;
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};
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#define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
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#define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core)
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#define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core)
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static struct sam9x60_div *notifier_div;
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static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
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{
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unsigned int status;
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@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac_pll_ops_chg = {
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.restore_context = sam9x60_frac_pll_restore_context,
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};
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/* This function should be called with spinlock acquired. */
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static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
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bool enable)
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{
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struct regmap *regmap = core->regmap;
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u32 ena_msk = enable ? core->layout->endiv_mask : 0;
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u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0;
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regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
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core->layout->div_mask | ena_msk,
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(div << core->layout->div_shift) | ena_val);
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regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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AT91_PMC_PLL_UPDT_UPDATE | core->id);
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while (!sam9x60_pll_ready(regmap, core->id))
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cpu_relax();
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}
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static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
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{
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struct sam9x60_div *div = to_sam9x60_div(core);
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@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
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if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
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goto unlock;
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regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
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core->layout->div_mask | core->layout->endiv_mask,
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(div->div << core->layout->div_shift) |
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(1 << core->layout->endiv_shift));
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regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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AT91_PMC_PLL_UPDT_UPDATE | core->id);
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while (!sam9x60_pll_ready(regmap, core->id))
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cpu_relax();
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sam9x60_div_pll_set_div(core, div->div, 1);
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unlock:
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spin_unlock_irqrestore(core->lock, flags);
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@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
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if (cdiv == div->div)
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goto unlock;
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regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
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core->layout->div_mask,
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(div->div << core->layout->div_shift));
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regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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AT91_PMC_PLL_UPDT_UPDATE | core->id);
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while (!sam9x60_pll_ready(regmap, core->id))
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cpu_relax();
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sam9x60_div_pll_set_div(core, div->div, 0);
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unlock:
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spin_unlock_irqrestore(core->lock, irqflags);
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@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_context(struct clk_hw *hw)
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sam9x60_div_pll_set(core);
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}
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static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,
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unsigned long code, void *data)
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{
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struct sam9x60_div *div = notifier_div;
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struct sam9x60_pll_core core = div->core;
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struct regmap *regmap = core.regmap;
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unsigned long irqflags;
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u32 val, cdiv;
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int ret = NOTIFY_DONE;
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if (code != PRE_RATE_CHANGE)
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return ret;
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/*
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* We switch to safe divider to avoid overclocking of other domains
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* feed by us while the frac PLL (our parent) is changed.
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*/
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div->div = div->safe_div;
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spin_lock_irqsave(core.lock, irqflags);
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regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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core.id);
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regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
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cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
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/* Stop if nothing changed. */
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if (cdiv == div->safe_div)
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goto unlock;
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sam9x60_div_pll_set_div(&core, div->div, 0);
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ret = NOTIFY_OK;
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unlock:
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spin_unlock_irqrestore(core.lock, irqflags);
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return ret;
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}
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static struct notifier_block sam9x60_div_pll_notifier = {
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.notifier_call = sam9x60_div_pll_notifier_fn,
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};
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static const struct clk_ops sam9x60_div_pll_ops = {
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.prepare = sam9x60_div_pll_prepare,
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.unprepare = sam9x60_div_pll_unprepare,
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@ -647,7 +694,8 @@ struct clk_hw * __init
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sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name, u8 id,
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const struct clk_pll_characteristics *characteristics,
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const struct clk_pll_layout *layout, u32 flags)
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const struct clk_pll_layout *layout, u32 flags,
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u32 safe_div)
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{
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struct sam9x60_div *div;
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struct clk_hw *hw;
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@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
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unsigned int val;
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int ret;
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if (id > PLL_MAX_ID || !lock)
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/* We only support one changeable PLL. */
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if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div))
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return ERR_PTR(-EINVAL);
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if (safe_div >= PLL_DIV_MAX)
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safe_div = PLL_DIV_MAX - 1;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
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div->core.layout = layout;
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div->core.regmap = regmap;
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div->core.lock = lock;
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div->safe_div = safe_div;
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spin_lock_irqsave(div->core.lock, irqflags);
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@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
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if (ret) {
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kfree(div);
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hw = ERR_PTR(ret);
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} else if (div->safe_div) {
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notifier_div = div;
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clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier);
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}
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return hw;
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@ -214,7 +214,8 @@ struct clk_hw * __init
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sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name, u8 id,
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const struct clk_pll_characteristics *characteristics,
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const struct clk_pll_layout *layout, u32 flags);
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const struct clk_pll_layout *layout, u32 flags,
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u32 safe_div);
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struct clk_hw * __init
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sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
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@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
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* This feeds CPU. It should not
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* be disabled.
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*/
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CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
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CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0);
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if (IS_ERR(hw))
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goto err_free;
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@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
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&pll_div_layout,
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CLK_SET_RATE_GATE |
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CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT);
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CLK_SET_RATE_PARENT, 0);
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if (IS_ERR(hw))
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goto err_free;
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@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
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hw = at91_clk_register_master_div(regmap, "masterck_div",
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"masterck_pres", &sam9x60_master_layout,
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&mck_characteristics, &mck_lock,
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CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE, 0);
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if (IS_ERR(hw))
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goto err_free;
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@ -127,6 +127,8 @@ static const struct clk_pll_characteristics pll_characteristics = {
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* @t: clock type
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* @f: clock flags
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* @eid: export index in sama7g5->chws[] array
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* @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE
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* notification
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*/
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static const struct {
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const char *n;
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@ -136,6 +138,7 @@ static const struct {
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unsigned long f;
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u8 t;
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u8 eid;
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u8 safe_div;
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} sama7g5_plls[][PLL_ID_MAX] = {
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[PLL_ID_CPU] = {
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{ .n = "cpupll_fracck",
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@ -156,7 +159,12 @@ static const struct {
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.t = PLL_TYPE_DIV,
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/* This feeds CPU. It should not be disabled. */
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.f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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.eid = PMC_CPUPLL, },
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.eid = PMC_CPUPLL,
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/*
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* Safe div=15 should be safe even for switching b/w 1GHz and
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* 90MHz (frac pll might go up to 1.2GHz).
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*/
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.safe_div = 15, },
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},
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[PLL_ID_SYS] = {
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@ -967,7 +975,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
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sama7g5_plls[i][j].p, i,
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sama7g5_plls[i][j].c,
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sama7g5_plls[i][j].l,
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sama7g5_plls[i][j].f);
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sama7g5_plls[i][j].f,
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sama7g5_plls[i][j].safe_div);
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break;
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default:
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