drm/amd/display: [FW Promotion] Release 0.0.72
- Updated SCR definition for FW boot options for Separate DCN init for DMUB FW loaded in VBL Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher
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9f95e77800
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1e0958bb9c
@@ -47,10 +47,10 @@
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/* Firmware versioning. */
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#ifdef DMUB_EXPOSE_VERSION
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#define DMUB_FW_VERSION_GIT_HASH 0xf3da2b656
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#define DMUB_FW_VERSION_GIT_HASH 0x2fe298ec9
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#define DMUB_FW_VERSION_MAJOR 0
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#define DMUB_FW_VERSION_MINOR 0
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#define DMUB_FW_VERSION_REVISION 71
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#define DMUB_FW_VERSION_REVISION 72
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#define DMUB_FW_VERSION_TEST 0
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#define DMUB_FW_VERSION_VBIOS 0
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#define DMUB_FW_VERSION_HOTFIX 0
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@@ -334,6 +334,7 @@ enum dmub_fw_boot_status_bit {
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DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
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DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
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DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
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DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
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};
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/* Register bit definition for SCRATCH5 */
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@@ -352,7 +353,7 @@ enum dmub_lvtma_status_bit {
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};
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/**
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* union dmub_fw_boot_options - Boot option definitions for SCRATCH15
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* union dmub_fw_boot_options - Boot option definitions for SCRATCH14
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*/
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union dmub_fw_boot_options {
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struct {
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@@ -363,7 +364,9 @@ union dmub_fw_boot_options {
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uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
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uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
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uint32_t z10_disable: 1; /**< 1 to disable z10 */
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uint32_t reserved : 25; /**< reserved */
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uint32_t reserved2: 1; /**< reserved for an unreleased feature */
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uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
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uint32_t reserved : 23; /**< reserved */
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} bits; /**< boot bits */
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uint32_t all; /**< 32-bit access to bits */
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};
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