diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl index 1692c4dd5487..4a0c599b6a6d 100644 --- a/Documentation/DocBook/gpu.tmpl +++ b/Documentation/DocBook/gpu.tmpl @@ -1615,6 +1615,11 @@ void intel_crt_init(struct drm_device *dev) !Pdrivers/gpu/drm/drm_fb_helper.c fbdev helpers !Edrivers/gpu/drm/drm_fb_helper.c !Iinclude/drm/drm_fb_helper.h + + + Framebuffer CMA Helper Functions Reference +!Pdrivers/gpu/drm/drm_fb_cma_helper.c framebuffer cma helper functions +!Edrivers/gpu/drm/drm_fb_cma_helper.c Display Port Helper Functions Reference @@ -1671,17 +1676,23 @@ void intel_crt_init(struct drm_device *dev) !Pdrivers/gpu/drm/drm_crtc.c Tile group - Bridges + Bridges - Overview + Overview !Pdrivers/gpu/drm/drm_bridge.c overview - Default bridge callback sequence + Default bridge callback sequence !Pdrivers/gpu/drm/drm_bridge.c bridge callbacks !Edrivers/gpu/drm/drm_bridge.c + + Panel Helper Reference +!Iinclude/drm/drm_panel.h +!Edrivers/gpu/drm/drm_panel.c +!Pdrivers/gpu/drm/drm_panel.c drm panel + @@ -1817,7 +1828,7 @@ void intel_crt_init(struct drm_device *dev) DRM - Generic + Generic “rotation” BITMASK { 0, "rotate-0" }, @@ -1832,6 +1843,13 @@ void intel_crt_init(struct drm_device *dev) image along the specified axis prior to rotation + “scaling mode” + ENUM + { "None", "Full", "Center", "Full aspect" } + Connector + Supported by: amdgpu, gma500, i915, nouveau and radeon. + + Connector “EDID” BLOB | IMMUTABLE @@ -2068,21 +2086,12 @@ void intel_crt_init(struct drm_device *dev) property to suggest an Y offset for a connector - Optional - “scaling mode” - ENUM - { "None", "Full", "Center", "Full aspect" } - Connector - TBD - - + Optional "aspect ratio" ENUM { "None", "4:3", "16:9" } Connector - DRM property to set aspect ratio from user space app. - This enum is made generic to allow addition of custom aspect - ratios. + TDB “dirty” @@ -2153,7 +2162,11 @@ void intel_crt_init(struct drm_device *dev) ENUM { "Automatic", "Full", "Limited 16:235" } Connector - TBD + When this property is set to Limited 16:235 + and CTM is set, the hardware will be programmed with the + result of the multiplication of CTM by the limited range + matrix to ensure the pixels normaly in the range 0..1.0 are + remapped to the range 16/255..235/255. “audio” @@ -3334,7 +3347,7 @@ int num_ioctls; Video BIOS Table (VBT) !Pdrivers/gpu/drm/i915/intel_bios.c Video BIOS Table (VBT) !Idrivers/gpu/drm/i915/intel_bios.c -!Idrivers/gpu/drm/i915/intel_bios.h +!Idrivers/gpu/drm/i915/intel_vbt_defs.h diff --git a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt index 9f97df4d5152..a5ea451e67fc 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt +++ b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt @@ -35,12 +35,22 @@ Optional properties for HDMI: as an interrupt/status bit in the HDMI controller itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt +Required properties for DPI: +- compatible: Should be "brcm,bcm2835-dpi" +- reg: Physical base address and length of the registers +- clocks: a) core: The core clock the unit runs on + b) pixel: The pixel clock that feeds the pixelvalve +- port: Port node with a single endpoint connecting to the panel + device, as defined in [1] + Required properties for V3D: - compatible: Should be "brcm,bcm2835-v3d" - reg: Physical base address and length of the V3D's registers - interrupts: The interrupt number See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +[1] Documentation/devicetree/bindings/media/video-interfaces.txt + Example: pixelvalve@7e807000 { compatible = "brcm,bcm2835-pixelvalve2"; @@ -66,6 +76,22 @@ hdmi: hdmi@7e902000 { clock-names = "pixel", "hdmi"; }; +dpi: dpi@7e208000 { + compatible = "brcm,bcm2835-dpi"; + reg = <0x7e208000 0x8c>; + clocks = <&clocks BCM2835_CLOCK_VPU>, + <&clocks BCM2835_CLOCK_DPI>; + clock-names = "core", "pixel"; + #address-cells = <1>; + #size-cells = <0>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&panel_in>; + }; + }; +}; + v3d: v3d@7ec00000 { compatible = "brcm,bcm2835-v3d"; reg = <0x7ec00000 0x1000>; @@ -75,3 +101,13 @@ v3d: v3d@7ec00000 { vc4: gpu { compatible = "brcm,bcm2835-vc4"; }; + +panel: panel { + compatible = "ontat,yx700wv03", "simple-panel"; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt new file mode 100644 index 000000000000..4f2ba8c13d92 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt @@ -0,0 +1,52 @@ +Analogix Display Port bridge bindings + +Required properties for dp-controller: + -compatible: + platform specific such as: + * "samsung,exynos5-dp" + * "rockchip,rk3288-dp" + -reg: + physical base address of the controller and length + of memory mapped region. + -interrupts: + interrupt combiner values. + -clocks: + from common clock binding: handle to dp clock. + -clock-names: + from common clock binding: Shall be "dp". + -interrupt-parent: + phandle to Interrupt combiner node. + -phys: + from general PHY binding: the phandle for the PHY device. + -phy-names: + from general PHY binding: Should be "dp". + +Optional properties for dp-controller: + -force-hpd: + Indicate driver need force hpd when hpd detect failed, this + is used for some eDP screen which don't have hpd signal. + -hpd-gpios: + Hotplug detect GPIO. + Indicates which GPIO should be used for hotplug detection + -port@[X]: SoC specific port nodes with endpoint definitions as defined + in Documentation/devicetree/bindings/media/video-interfaces.txt, + please refer to the SoC specific binding document: + * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt + * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt + +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt +------------------------------------------------------------------------------- + +Example: + + dp-controller { + compatible = "samsung,exynos5-dp"; + reg = <0x145b0000 0x10000>; + interrupts = <10 3>; + interrupt-parent = <&combiner>; + clocks = <&clock 342>; + clock-names = "dp"; + + phys = <&dp_phy>; + phy-names = "dp"; + }; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt b/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt index 377afbf5122a..c9fd7b3807e7 100644 --- a/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt +++ b/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt @@ -5,7 +5,8 @@ Exynos series of SoCs which transfers the image data from a video memory buffer to an external LCD interface. Required properties: -- compatible: value should be "samsung,exynos5433-decon"; +- compatible: value should be one of: + "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv"; - reg: physical base address and length of the DECON registers set. - interrupts: should contain a list of all DECON IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier format @@ -16,7 +17,7 @@ Required properties: - clocks: must include clock specifiers corresponding to entries in the clock-names property. - clock-names: list of clock names sorted in the same order as the clocks - property. Must contain "aclk_decon", "aclk_smmu_decon0x", + property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk", "sclk_decon_eclk" - ports: contains a port which is connected to mic node. address-cells and diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt index fe4a7a2dea9c..ade5d8eebf85 100644 --- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt @@ -1,20 +1,3 @@ -Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP) - -DisplayPort is industry standard to accommodate the growing board adoption -of digital display technology within the PC and CE industries. -It consolidates the internal and external connection methods to reduce device -complexity and cost. It also supports necessary features for important cross -industry applications and provides performance scalability to enable the next -generation of displays that feature higher color depths, refresh rates, and -display resolutions. - -eDP (embedded display port) device is compliant with Embedded DisplayPort -standard as follows, -- DisplayPort standard 1.1a for Exynos5250 and Exynos5260. -- DisplayPort standard 1.3 for Exynos5422s and Exynos5800. - -eDP resides between FIMD and panel or FIMD and bridge such as LVDS. - The Exynos display port interface should be configured based on the type of panel connected to it. @@ -48,26 +31,6 @@ Required properties for dp-controller: from general PHY binding: the phandle for the PHY device. -phy-names: from general PHY binding: Should be "dp". - -samsung,color-space: - input video data format. - COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 - -samsung,dynamic-range: - dynamic range for input video data. - VESA = 0, CEA = 1 - -samsung,ycbcr-coeff: - YCbCr co-efficients for input video. - COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1 - -samsung,color-depth: - number of bits per colour component. - COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3 - -samsung,link-rate: - link rate supported by the panel. - LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A - -samsung,lane-count: - number of lanes supported by the panel. - LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4 - - display-timings: timings for the connected panel as described by - Documentation/devicetree/bindings/display/display-timing.txt Optional properties for dp-controller: -interlaced: @@ -83,17 +46,31 @@ Optional properties for dp-controller: Hotplug detect GPIO. Indicates which GPIO should be used for hotplug detection -Video interfaces: - Device node can contain video interface port nodes according to [1]. - The following are properties specific to those nodes: + -video interfaces: Device node can contain video interface port + nodes according to [1]. + - display-timings: timings for the connected panel as described by + Documentation/devicetree/bindings/display/panel/display-timing.txt - endpoint node connected to bridge or panel node: - - remote-endpoint: specifies the endpoint in panel or bridge node. - This node is required in all kinds of exynos dp - to represent the connection between dp and bridge - or dp and panel. +For the below properties, please refer to Analogix DP binding document: + * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt + -phys (required) + -phy-names (required) + -hpd-gpios (optional) + force-hpd (optional) -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt +Deprecated properties for DisplayPort: +-interlaced: deprecated prop that can parsed from drm_display_mode. +-vsync-active-high: deprecated prop that can parsed from drm_display_mode. +-hsync-active-high: deprecated prop that can parsed from drm_display_mode. +-samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode. +-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode. +-samsung,color-space: deprecated prop that can parsed from drm_display_info. +-samsung,color-depth: deprecated prop that can parsed from drm_display_info. +-samsung,link-rate: deprecated prop that can reading from monitor by dpcd method. +-samsung,lane-count: deprecated prop that can reading from monitor by dpcd method. +-samsung,hpd-gpio: deprecated name for hpd-gpios. + +------------------------------------------------------------------------------- Example: @@ -112,13 +89,6 @@ SOC specific portion: Board Specific portion: dp-controller { - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - display-timings { native-mode = <&lcd_timing>; lcd_timing: 1366x768 { @@ -135,18 +105,9 @@ Board Specific portion: }; ports { - port { + port@0 { dp_out: endpoint { - remote-endpoint = <&dp_in>; - }; - }; - }; - - panel { - ... - port { - dp_in: endpoint { - remote-endpoint = <&dp_out>; + remote-endpoint = <&bridge_in>; }; }; }; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt b/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt index d474f59be6d6..a2ec4c1c9382 100644 --- a/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt @@ -5,6 +5,7 @@ Required properties: 1) "samsung,exynos4210-hdmi" 2) "samsung,exynos4212-hdmi" 3) "samsung,exynos5420-hdmi" + 4) "samsung,exynos5433-hdmi" - reg: physical base address of the hdmi and length of memory mapped region. - interrupts: interrupt number to the cpu. @@ -12,6 +13,11 @@ Required properties: a) phandle of the gpio controller node. b) pin number within the gpio controller. c) optional flags and pull up/down. +- ddc: phandle to the hdmi ddc node +- phy: phandle to the hdmi phy node +- samsung,syscon-phandle: phandle for system controller node for PMU. + +Required properties for Exynos 4210, 4212, 5420 and 5433: - clocks: list of clock IDs from SoC clock driver. a) hdmi: Gate of HDMI IP bus clock. b) sclk_hdmi: Gate of HDMI special clock. @@ -25,9 +31,24 @@ Required properties: sclk_pixel. - clock-names: aliases as per driver requirements for above clock IDs: "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi". -- ddc: phandle to the hdmi ddc node -- phy: phandle to the hdmi phy node -- samsung,syscon-phandle: phandle for system controller node for PMU. + +Required properties for Exynos 5433: +- clocks: list of clock specifiers according to common clock bindings. + a) hdmi_pclk: Gate of HDMI IP APB bus. + b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus. + d) i_tmds_clk: Gate of HDMI TMDS clock. + e) i_pixel_clk: Gate of HDMI pixel clock. + f) i_spdif_clk: Gate of HDMI SPDIF clock. + g) oscclk: Oscillator clock, used as parent of following *_user clocks + in case HDMI-PHY is not operational. + h) tmds_clko: TMDS clock generated by HDMI-PHY. + i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko, + respectively if HDMI-PHY is off and operational. + j) pixel_clko: Pixel clock generated by HDMI-PHY. + k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko, + respectively if HDMI-PHY is off and operational. +- clock-names: aliases for above clock specfiers. +- samsung,sysreg: handle to syscon used to control the system registers. Example: diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt index ebf1be9ae393..ae55cde1b69e 100644 --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt @@ -6,17 +6,24 @@ Required properties: * "fsl,vf610-dcu". - reg: Address and length of the register set for dcu. -- clocks: From common clock binding: handle to dcu clock. -- clock-names: From common clock binding: Shall be "dcu". +- clocks: Handle to "dcu" and "pix" clock (in the order below) + This can be the same clock (e.g. LS1021a) + See ../clocks/clock-bindings.txt for details. +- clock-names: Should be "dcu" and "pix" + See ../clocks/clock-bindings.txt for details. - big-endian Boolean property, LS1021A DCU registers are big-endian. - fsl,panel: The phandle to panel node. +Optional properties: +- fsl,tcon: The phandle to the timing controller node. + Examples: dcu: dcu@2ce0000 { compatible = "fsl,ls1021a-dcu"; reg = <0x0 0x2ce0000 0x0 0x10000>; - clocks = <&platform_clk 0>; - clock-names = "dcu"; + clocks = <&platform_clk 0>, <&platform_clk 0>; + clock-names = "dcu", "pix"; big-endian; fsl,panel = <&panel>; + fsl,tcon = <&tcon>; }; diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt new file mode 100644 index 000000000000..6fa4ab668db5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/fsl,tcon.txt @@ -0,0 +1,18 @@ +Device Tree bindings for Freescale TCON Driver + +Required properties: +- compatible: Should be one of + * "fsl,vf610-tcon". + +- reg: Address and length of the register set for tcon. +- clocks: From common clock binding: handle to tcon ipg clock. +- clock-names: From common clock binding: Shall be "ipg". + +Examples: +timing-controller@4003d000 { + compatible = "fsl,vf610-tcon"; + reg = <0x4003d000 0x1000>; + clocks = <&clks VF610_CLK_TCON0>; + clock-names = "ipg"; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt new file mode 100644 index 000000000000..d270bfe4e4e0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt @@ -0,0 +1,72 @@ +Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver + +A DSI Host Controller resides in the middle of display controller and external +HDMI converter or panel. + +Required properties: +- compatible: value should be "hisilicon,hi6220-dsi". +- reg: physical base address and length of dsi controller's registers. +- clocks: contains APB clock phandle + clock-specifier pair. +- clock-names: should be "pclk". +- ports: contains DSI controller input and output sub port. + The input port connects to ADE output port with the reg value "0". + The output port with the reg value "1", it could connect to panel or + any other bridge endpoints. + See Documentation/devicetree/bindings/graph.txt for more device graph info. + +A example of HiKey board hi6220 SoC and board specific DT entry: +Example: + +SoC specific: + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; + }; + }; + }; + }; + + +Board specific: + &dsi { + status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + reg = <1>; + + dsi_out0: endpoint@0 { + remote-endpoint = <&adv7533_in>; + }; + }; + }; + }; + + &i2c2 { + ... + + adv7533: adv7533@39 { + ... + + port { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt new file mode 100644 index 000000000000..38dc9d60eef8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt @@ -0,0 +1,64 @@ +Device-Tree bindings for hisilicon ADE display controller driver + +ADE (Advanced Display Engine) is the display controller which grab image +data from memory, do composition, do post image processing, generate RGB +timing stream and transfer to DSI. + +Required properties: +- compatible: value should be "hisilicon,hi6220-ade". +- reg: physical base address and length of the ADE controller's registers. +- hisilicon,noc-syscon: ADE NOC QoS syscon. +- resets: The ADE reset controller node. +- interrupt: the ldi vblank interrupt number used. +- clocks: a list of phandle + clock-specifier pairs, one for each entry + in clock-names. +- clock-names: should contain: + "clk_ade_core" for the ADE core clock. + "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with + jpeg codec. + "clk_ade_pix" for the ADE pixel clok. +- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks' + phandle + clock-specifier pairs. +- assigned-clock-rates: clock rates, one for each entry in assigned-clocks. + The rate of "clk_ade_core" could be "360000000" or "180000000"; + The rate of "clk_codec_jpeg" could be or less than "1440000000". + These rate values could be configured according to performance and power + consumption. +- port: the output port. This contains one endpoint subnode, with its + remote-endpoint set to the phandle of the connected DSI input endpoint. + See Documentation/devicetree/bindings/graph.txt for more device graph info. + +Optional properties: +- dma-coherent: Present if dma operations are coherent. + + +A example of HiKey board hi6220 SoC specific DT entry: +Example: + + ade: ade@f4100000 { + compatible = "hisilicon,hi6220-ade"; + reg = <0x0 0xf4100000 0x0 0x7800>; + reg-names = "ade_base"; + hisilicon,noc-syscon = <&medianoc_ade>; + resets = <&media_ctrl MEDIA_ADE>; + interrupts = <0 115 4>; /* ldi interrupt */ + + clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>, + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ + clock-names = "clk_ade_core", + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt new file mode 100644 index 000000000000..db6e77edbea8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -0,0 +1,203 @@ +Mediatek display subsystem +========================== + +The Mediatek display subsystem consists of various DISP function blocks in the +MMSYS register space. The connections between them can be configured by output +and input selectors in the MMSYS_CONFIG register space. Pixel clock and start +of frame signal are distributed to the other function blocks by a DISP_MUTEX +function block. + +All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. +For a description of the MMSYS_CONFIG binding, see +Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt. + +DISP function blocks +==================== + +A display stream starts at a source function block that reads pixel data from +memory and ends with a sink function block that drives pixels on a display +interface, or writes pixels back to memory. All DISP function blocks have +their own register space, interrupt, and clock gate. The blocks that can +access memory additionally have to list the IOMMU and local arbiter they are +connected to. + +For a description of the display interface sink function blocks, see +Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and +Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt. + +Required properties (all function blocks): +- compatible: "mediatek,-disp-", one of + "mediatek,-disp-ovl" - overlay (4 layers, blending, csc) + "mediatek,-disp-rdma" - read DMA / line buffer + "mediatek,-disp-wdma" - write DMA + "mediatek,-disp-color" - color processor + "mediatek,-disp-aal" - adaptive ambient light controller + "mediatek,-disp-gamma" - gamma correction + "mediatek,-disp-merge" - merge streams from two RDMA sources + "mediatek,-disp-split" - split stream to two encoders + "mediatek,-disp-ufoe" - data compression engine + "mediatek,-dsi" - DSI controller, see mediatek,dsi.txt + "mediatek,-dpi" - DPI controller, see mediatek,dpi.txt + "mediatek,-disp-mutex" - display mutex + "mediatek,-disp-od" - overdrive +- reg: Physical base address and length of the function block register space +- interrupts: The interrupt signal from the function block (required, except for + merge and split function blocks). +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. + For most function blocks this is just a single clock input. Only the DSI and + DPI controller nodes have multiple clock inputs. These are documented in + mediatek,dsi.txt and mediatek,dpi.txt, respectively. + +Required properties (DMA function blocks): +- compatible: Should be one of + "mediatek,-disp-ovl" + "mediatek,-disp-rdma" + "mediatek,-disp-wdma" +- larb: Should contain a phandle pointing to the local arbiter device as defined + in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt +- iommus: Should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. + +Examples: + +mmsys: clock-controller@14000000 { + compatible = "mediatek,mt8173-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + #clock-cells = <1>; +}; + +ovl0: ovl@1400c000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,larb = <&larb0>; +}; + +ovl1: ovl@1400d000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL1>; + iommus = <&iommu M4U_PORT_DISP_OVL1>; + mediatek,larb = <&larb4>; +}; + +rdma0: rdma@1400e000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,larb = <&larb0>; +}; + +rdma1: rdma@1400f000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb4>; +}; + +rdma2: rdma@14010000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA2>; + iommus = <&iommu M4U_PORT_DISP_RDMA2>; + mediatek,larb = <&larb4>; +}; + +wdma0: wdma@14011000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA0>; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + mediatek,larb = <&larb0>; +}; + +wdma1: wdma@14012000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA1>; + iommus = <&iommu M4U_PORT_DISP_WDMA1>; + mediatek,larb = <&larb4>; +}; + +color0: color@14013000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14013000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; +}; + +color1: color@14014000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR1>; +}; + +aal@14015000 { + compatible = "mediatek,mt8173-disp-aal"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_AAL>; +}; + +gamma@14016000 { + compatible = "mediatek,mt8173-disp-gamma"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; +}; + +ufoe@1401a000 { + compatible = "mediatek,mt8173-disp-ufoe"; + reg = <0 0x1401a000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_UFOE>; +}; + +dsi0: dsi@1401b000 { + /* See mediatek,dsi.txt for details */ +}; + +dpi0: dpi@1401d000 { + /* See mediatek,dpi.txt for details */ +}; + +mutex: mutex@14020000 { + compatible = "mediatek,mt8173-disp-mutex"; + reg = <0 0x14020000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MUTEX_32K>; +}; + +od@14023000 { + compatible = "mediatek,mt8173-disp-od"; + reg = <0 0x14023000 0 0x1000>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OD>; +}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt new file mode 100644 index 000000000000..b6a7e7397b8b --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -0,0 +1,35 @@ +Mediatek DPI Device +=================== + +The Mediatek DPI function block is a sink of the display subsystem and +provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel +output bus. + +Required properties: +- compatible: "mediatek,-dpi" +- reg: Physical base address and length of the controller's registers +- interrupts: The interrupt signal from the function block. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "pixel", "engine", and "pll" +- port: Output port node with endpoint definitions as described in + Documentation/devicetree/bindings/graph.txt. This port should be connected + to the input port of an attached HDMI or LVDS encoder chip. + +Example: + +dpi0: dpi@1401d000 { + compatible = "mediatek,mt8173-dpi"; + reg = <0 0x1401d000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI_PIXEL>, + <&mmsys CLK_MM_DPI_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + + port { + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt new file mode 100644 index 000000000000..2b1585a34b85 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -0,0 +1,60 @@ +Mediatek DSI Device +=================== + +The Mediatek DSI function block is a sink of the display subsystem and can +drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- +channel output. + +Required properties: +- compatible: "mediatek,-dsi" +- reg: Physical base address and length of the controller's registers +- interrupts: The interrupt signal from the function block. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "engine", "digital", and "hs" +- phys: phandle link to the MIPI D-PHY controller. +- phy-names: must contain "dphy" +- port: Output port node with endpoint definitions as described in + Documentation/devicetree/bindings/graph.txt. This port should be connected + to the input port of an attached DSI panel or DSI-to-eDP encoder chip. + +MIPI TX Configuration Module +============================ + +The MIPI TX configuration module controls the MIPI D-PHY. + +Required properties: +- compatible: "mediatek,-mipi-tx" +- reg: Physical base address and length of the controller's registers +- clocks: PLL reference clock +- clock-output-names: name of the output clock line to the DSI encoder +- #clock-cells: must be <0>; +- #phy-cells: must be <0>. + +Example: + +mipi_tx0: mipi-dphy@10215000 { + compatible = "mediatek,mt8173-mipi-tx"; + reg = <0 0x10215000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; +}; + +dsi0: dsi@1401b000 { + compatible = "mediatek,mt8173-dsi"; + reg = <0 0x1401b000 0 0x1000>; + interrupts = ; + clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + + port { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt b/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt new file mode 100644 index 000000000000..3e10cd782491 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt @@ -0,0 +1,7 @@ +Innolux AT070TN92 7.0" WQVGA TFT LCD panel + +Required properties: +- compatible: should be "innolux,at070tn92" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt new file mode 100644 index 000000000000..74540a090669 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt @@ -0,0 +1,7 @@ +Olimex 4.3" TFT LCD panel + +Required properties: +- compatible: should be "olimex,lcd-olinuxino-43-ts" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt b/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt new file mode 100644 index 000000000000..3d8a5e029242 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt @@ -0,0 +1,7 @@ +On Tat Industrial Company 7" DPI TFT panel. + +Required properties: +- compatible: should be "ontat,yx700wv03" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt b/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt new file mode 100644 index 000000000000..a2613b9675df --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt @@ -0,0 +1,8 @@ +TPK U.S.A. LLC Fusion 7" integrated projected capacitive touch display with, +800 x 480 (WVGA) LCD panel. + +Required properties: +- compatible: should be "tpk,f07a-0102" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt b/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt new file mode 100644 index 000000000000..b9d051196ba9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt @@ -0,0 +1,8 @@ +TPK U.S.A. LLC Fusion 10.1" integrated projected capacitive touch display with, +1024 x 600 (WSVGA) LCD panel. + +Required properties: +- compatible: should be "tpk,f10a-0102" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt new file mode 100644 index 000000000000..e832ff98fd61 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt @@ -0,0 +1,92 @@ +Rockchip RK3288 specific extensions to the Analogix Display Port +================================ + +Required properties: +- compatible: "rockchip,rk3288-edp"; + +- reg: physical base address of the controller and length + +- clocks: from common clock binding: handle to dp clock. + of memory mapped region. + +- clock-names: from common clock binding: + Required elements: "dp" "pclk" + +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + +- pinctrl-names: Names corresponding to the chip hotplug pinctrl states. +- pinctrl-0: pin-control mode. should be <&edp_hpd> + +- reset-names: Must include the name "dp" + +- rockchip,grf: this soc should set GRF regs, so need get grf here. + +- ports: there are 2 port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + Port 0: contained 2 endpoints, connecting to the output of vop. + Port 1: contained 1 endpoint, connecting to the input of panel. + +For the below properties, please refer to Analogix DP binding document: + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt +- phys (required) +- phy-names (required) +- hpd-gpios (optional) +- force-hpd (optional) +------------------------------------------------------------------------------- + +Example: + dp-controller: dp@ff970000 { + compatible = "rockchip,rk3288-dp"; + reg = <0xff970000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + phys = <&dp_phy>; + phy-names = "dp"; + + rockchip,grf = <&grf>; + resets = <&cru 111>; + reset-names = "dp"; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + edp_out_panel: endpoint { + reg = <0>; + remote-endpoint = <&panel_in_edp> + }; + }; + }; + }; + + pinctrl { + edp { + edp_hpd: edp-hpd { + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/snps,arcpgu.txt b/Documentation/devicetree/bindings/display/snps,arcpgu.txt new file mode 100644 index 000000000000..c5c7dfd37df2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/snps,arcpgu.txt @@ -0,0 +1,35 @@ +ARC PGU + +This is a display controller found on several development boards produced +by Synopsys. The ARC PGU is an RGB streamer that reads the data from a +framebuffer and sends it to a single digital encoder (usually HDMI). + +Required properties: + - compatible: "snps,arcpgu" + - reg: Physical base address and length of the controller's registers. + - clocks: A list of phandle + clock-specifier pairs, one for each + entry in 'clock-names'. + - clock-names: A list of clock names. For ARC PGU it should contain: + - "pxlclk" for the clock feeding the output PLL of the controller. + +Required sub-nodes: + - port: The PGU connection to an encoder chip. + +Example: + +/ { + ... + + pgu@XXXXXXXX { + compatible = "snps,arcpgu"; + reg = <0xXXXXXXXX 0x400>; + clocks = <&clock_node>; + clock-names = "pxlclk"; + + port { + pgu_output: endpoint { + remote-endpoint = <&hdmi_enc_input>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt new file mode 100644 index 000000000000..df8f4aeefe4c --- /dev/null +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -0,0 +1,258 @@ +Allwinner A10 Display Pipeline +============================== + +The Allwinner A10 Display pipeline is composed of several components +that are going to be documented below: + +TV Encoder +---------- + +The TV Encoder supports the composite and VGA output. It is one end of +the pipeline. + +Required properties: + - compatible: value should be "allwinner,sun4i-a10-tv-encoder". + - reg: base address and size of memory-mapped region + - clocks: the clocks driving the TV encoder + - resets: phandle to the reset controller driving the encoder + +- ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoint. + +TCON +---- + +The TCON acts as a timing controller for RGB, LVDS and TV interfaces. + +Required properties: + - compatible: value should be "allwinner,sun5i-a13-tcon". + - reg: base address and size of memory-mapped region + - interrupts: interrupt associated to this IP + - clocks: phandles to the clocks feeding the TCON. Three are needed: + - 'ahb': the interface clocks + - 'tcon-ch0': The clock driving the TCON channel 0 + - 'tcon-ch1': The clock driving the TCON channel 1 + - resets: phandles to the reset controllers driving the encoder + - "lcd": the reset line for the TCON channel 0 + + - clock-names: the clock names mentioned above + - reset-names: the reset names mentioned above + - clock-output-names: Name of the pixel clock created + +- ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoint, the second one the output + + The output should have two endpoints. The first is the block + connected to the TCON channel 0 (usually a panel or a bridge), the + second the block connected to the TCON channel 1 (usually the TV + encoder) + + +Display Engine Backend +---------------------- + +The display engine backend exposes layers and sprites to the +system. + +Required properties: + - compatible: value must be one of: + * allwinner,sun5i-a13-display-backend + - reg: base address and size of the memory-mapped region. + - clocks: phandles to the clocks feeding the frontend and backend + * ahb: the backend interface clock + * mod: the backend module clock + * ram: the backend DRAM clock + - clock-names: the clock names mentioned above + - resets: phandles to the reset controllers driving the backend + +- ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoints, the second one the output + +Display Engine Frontend +----------------------- + +The display engine frontend does formats conversion, scaling, +deinterlacing and color space conversion. + +Required properties: + - compatible: value must be one of: + * allwinner,sun5i-a13-display-frontend + - reg: base address and size of the memory-mapped region. + - interrupts: interrupt associated to this IP + - clocks: phandles to the clocks feeding the frontend and backend + * ahb: the backend interface clock + * mod: the backend module clock + * ram: the backend DRAM clock + - clock-names: the clock names mentioned above + - resets: phandles to the reset controllers driving the backend + +- ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoints, the second one the outputs + + +Display Engine Pipeline +----------------------- + +The display engine pipeline (and its entry point, since it can be +either directly the backend or the frontend) is represented as an +extra node. + +Required properties: + - compatible: value must be one of: + * allwinner,sun5i-a13-display-engine + + - allwinner,pipelines: list of phandle to the display engine + frontends available. + +Example: + +panel: panel { + compatible = "olimex,lcd-olinuxino-43-ts"; + #address-cells = <1>; + #size-cells = <0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint { + remote-endpoint = <&tcon0_out_panel>; + }; + }; +}; + +tve0: tv-encoder@01c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ahb_gates 34>; + resets = <&tcon_ch0_clk 0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_tve0>; + }; + }; +}; + +tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun5i-a13-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&tcon_ch0_clk 1>; + reset-names = "lcd"; + clocks = <&ahb_gates 36>, + <&tcon_ch0_clk>, + <&tcon_ch1_clk>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + + tcon0_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon0>; + }; + }; + }; +}; + +fe0: display-frontend@1e00000 { + compatible = "allwinner,sun5i-a13-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ahb_gates 46>, <&de_fe_clk>, + <&dram_gates 25>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_fe_clk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint { + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; +}; + +be0: display-backend@1e60000 { + compatible = "allwinner,sun5i-a13-display-backend"; + reg = <0x01e60000 0x10000>; + clocks = <&ahb_gates 44>, <&de_be_clk>, + <&dram_gates 26>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_be_clk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + }; + }; +}; + +display-engine { + compatible = "allwinner,sun5i-a13-display-engine"; + allwinner,pipelines = <&fe0>; +}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4454483cc53f..a7440bcd67ff 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -23,6 +23,7 @@ amlogic Amlogic, Inc. ampire Ampire Co., Ltd. ams AMS AG amstaos AMS-Taos Inc. +analogix Analogix Semiconductor, Inc. apm Applied Micro Circuits Corporation (APM) aptina Aptina Imaging arasan Arasan Chip Systems @@ -185,6 +186,7 @@ okaya Okaya Electric America, Inc. olimex OLIMEX Ltd. onion Onion Corporation onnn ON Semiconductor Corp. +ontat On Tat Industrial Company opencores OpenCores.org option Option NV ortustech Ortus Technology Co., Ltd. @@ -261,6 +263,7 @@ toradex Toradex AG toshiba Toshiba Corporation toumaz Toumaz tplink TP-LINK Technologies Co., Ltd. +tpk TPK U.S.A. LLC tronfy Tronfy tronsmart Tronsmart truly Truly Semiconductors Limited diff --git a/Documentation/devicetree/bindings/video/bridge/anx7814.txt b/Documentation/devicetree/bindings/video/bridge/anx7814.txt new file mode 100644 index 000000000000..b2a22c28c9b3 --- /dev/null +++ b/Documentation/devicetree/bindings/video/bridge/anx7814.txt @@ -0,0 +1,40 @@ +Analogix ANX7814 SlimPort (Full-HD Transmitter) +----------------------------------------------- + +The ANX7814 is an ultra-low power Full-HD (1080p60) SlimPort transmitter +designed for portable devices. + +Required properties: + + - compatible : "analogix,anx7814" + - reg : I2C address of the device + - interrupt-parent : Should be the phandle of the interrupt controller + that services interrupts for this device + - interrupts : Should contain the INTP interrupt + - hpd-gpios : Which GPIO to use for hpd + - pd-gpios : Which GPIO to use for power down + - reset-gpios : Which GPIO to use for reset + +Optional properties: + + - dvdd10-supply : Regulator for 1.0V digital core power. + - Video port for HDMI input, using the DT bindings defined in [1]. + +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + + anx7814: anx7814@38 { + compatible = "analogix,anx7814"; + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <99 IRQ_TYPE_LEVEL_LOW>; /* INTP */ + hpd-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; + pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>; + port { + anx7814_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5f83015ff016..ee7fb1668c15 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -856,6 +856,12 @@ S: Maintained F: drivers/net/arcnet/ F: include/uapi/linux/if_arcnet.h +ARC PGU DRM DRIVER +M: Alexey Brodkin +S: Supported +F: drivers/gpu/drm/arc/ +F: Documentation/devicetree/bindings/display/snps,arcpgu.txt + ARM HDLCD DRM DRIVER M: Liviu Dudau S: Supported @@ -3837,9 +3843,25 @@ T: git git://people.freedesktop.org/~airlied/linux S: Maintained F: drivers/gpu/drm/ F: drivers/gpu/vga/ +F: Documentation/DocBook/gpu.* F: include/drm/ F: include/uapi/drm/ +DRM DRIVER FOR AST SERVER GRAPHICS CHIPS +M: Dave Airlie +S: Odd Fixes +F: drivers/gpu/drm/ast/ + +DRM DRIVER FOR BOCHS VIRTUAL GPU +M: Gerd Hoffmann +S: Odd Fixes +F: drivers/gpu/drm/bochs/ + +DRM DRIVER FOR QEMU'S CIRRUS DEVICE +M: Dave Airlie +S: Odd Fixes +F: drivers/gpu/drm/cirrus/ + RADEON and AMDGPU DRM DRIVERS M: Alex Deucher M: Christian König @@ -3847,9 +3869,9 @@ L: dri-devel@lists.freedesktop.org T: git git://people.freedesktop.org/~agd5f/linux S: Supported F: drivers/gpu/drm/radeon/ -F: include/uapi/drm/radeon* +F: include/uapi/drm/radeon_drm.h F: drivers/gpu/drm/amd/ -F: include/uapi/drm/amdgpu* +F: include/uapi/drm/amdgpu_drm.h DRM PANEL DRIVERS M: Thierry Reding @@ -3872,7 +3894,7 @@ T: git git://anongit.freedesktop.org/drm-intel S: Supported F: drivers/gpu/drm/i915/ F: include/drm/i915* -F: include/uapi/drm/i915* +F: include/uapi/drm/i915_drm.h DRM DRIVERS FOR ATMEL HLCDC M: Boris Brezillon @@ -3881,6 +3903,13 @@ S: Supported F: drivers/gpu/drm/atmel-hlcdc/ F: Documentation/devicetree/bindings/drm/atmel/ +DRM DRIVERS FOR ALLWINNER A10 +M: Maxime Ripard +L: dri-devel@lists.freedesktop.org +S: Supported +F: drivers/gpu/drm/sun4i/ +F: Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt + DRM DRIVERS FOR EXYNOS M: Inki Dae M: Joonyoung Shim @@ -3890,8 +3919,8 @@ L: dri-devel@lists.freedesktop.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git S: Supported F: drivers/gpu/drm/exynos/ -F: include/drm/exynos* -F: include/uapi/drm/exynos* +F: include/uapi/drm/exynos_drm.h +F: Documentation/devicetree/bindings/display/exynos/ DRM DRIVERS FOR FREESCALE DCU M: Stefan Agner @@ -3900,6 +3929,7 @@ L: dri-devel@lists.freedesktop.org S: Supported F: drivers/gpu/drm/fsl-dcu/ F: Documentation/devicetree/bindings/display/fsl,dcu.txt +F: Documentation/devicetree/bindings/display/fsl,tcon.txt F: Documentation/devicetree/bindings/display/panel/nec,nl4827hc19_05b.txt DRM DRIVERS FOR FREESCALE IMX @@ -3915,12 +3945,45 @@ M: Patrik Jakobsson L: dri-devel@lists.freedesktop.org T: git git://github.com/patjak/drm-gma500 S: Maintained -F: drivers/gpu/drm/gma500 -F: include/drm/gma500* +F: drivers/gpu/drm/gma500/ + +DRM DRIVERS FOR HISILICON +M: Xinliang Liu +R: Xinwei Kong +R: Chen Feng +L: dri-devel@lists.freedesktop.org +T: git git://github.com/xin3liang/linux.git +S: Maintained +F: drivers/gpu/drm/hisilicon/ +F: Documentation/devicetree/bindings/display/hisilicon/ + +DRM DRIVER FOR INTEL I810 VIDEO CARDS +S: Orphan / Obsolete +F: drivers/gpu/drm/i810/ +F: include/uapi/drm/i810_drm.h + +DRM DRIVER FOR MSM ADRENO GPU +M: Rob Clark +L: linux-arm-msm@vger.kernel.org +L: dri-devel@lists.freedesktop.org +L: freedreno@lists.freedesktop.org +T: git git://people.freedesktop.org/~robclark/linux +S: Maintained +F: drivers/gpu/drm/msm/ +F: include/uapi/drm/msm_drm.h +F: Documentation/devicetree/bindings/display/msm/ + +DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS +M: Ben Skeggs +L: dri-devel@lists.freedesktop.org +L: nouveau@lists.freedesktop.org +T: git git://github.com/skeggsb/linux +S: Supported +F: drivers/gpu/drm/nouveau/ +F: include/uapi/drm/nouveau_drm.h DRM DRIVERS FOR NVIDIA TEGRA M: Thierry Reding -M: Terje Bergström L: dri-devel@lists.freedesktop.org L: linux-tegra@vger.kernel.org T: git git://anongit.freedesktop.org/tegra/linux.git @@ -3931,22 +3994,54 @@ F: include/linux/host1x.h F: include/uapi/drm/tegra_drm.h F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +DRM DRIVER FOR MATROX G200/G400 GRAPHICS CARDS +S: Orphan / Obsolete +F: drivers/gpu/drm/mga/ +F: include/uapi/drm/mga_drm.h + +DRM DRIVER FOR MGA G200 SERVER GRAPHICS CHIPS +M: Dave Airlie +S: Odd Fixes +F: drivers/gpu/drm/mgag200/ + +DRM DRIVER FOR RAGE 128 VIDEO CARDS +S: Orphan / Obsolete +F: drivers/gpu/drm/r128/ +F: include/uapi/drm/r128_drm.h + DRM DRIVERS FOR RENESAS M: Laurent Pinchart L: dri-devel@lists.freedesktop.org L: linux-renesas-soc@vger.kernel.org -T: git git://people.freedesktop.org/~airlied/linux +T: git git://linuxtv.org/pinchartl/fbdev S: Supported F: drivers/gpu/drm/rcar-du/ F: drivers/gpu/drm/shmobile/ F: include/linux/platform_data/shmob_drm.h +F: Documentation/devicetree/bindings/display/renesas,du.txt + +DRM DRIVER FOR QXL VIRTUAL GPU +M: Dave Airlie +S: Odd Fixes +F: drivers/gpu/drm/qxl/ +F: include/uapi/drm/qxl_drm.h DRM DRIVERS FOR ROCKCHIP M: Mark Yao L: dri-devel@lists.freedesktop.org S: Maintained F: drivers/gpu/drm/rockchip/ -F: Documentation/devicetree/bindings/display/rockchip* +F: Documentation/devicetree/bindings/display/rockchip/ + +DRM DRIVER FOR SAVAGE VIDEO CARDS +S: Orphan / Obsolete +F: drivers/gpu/drm/savage/ +F: include/uapi/drm/savage_drm.h + +DRM DRIVER FOR SIS VIDEO CARDS +S: Orphan / Obsolete +F: drivers/gpu/drm/sis/ +F: include/uapi/drm/sis_drm.h DRM DRIVERS FOR STI M: Benjamin Gaignard @@ -3957,14 +4052,43 @@ S: Maintained F: drivers/gpu/drm/sti F: Documentation/devicetree/bindings/display/st,stih4xx.txt +DRM DRIVER FOR TDFX VIDEO CARDS +S: Orphan / Obsolete +F: drivers/gpu/drm/tdfx/ + +DRM DRIVER FOR USB DISPLAYLINK VIDEO ADAPTERS +M: Dave Airlie +S: Odd Fixes +F: drivers/gpu/drm/udl/ + DRM DRIVERS FOR VIVANTE GPU IP M: Lucas Stach R: Russell King R: Christian Gmeiner L: dri-devel@lists.freedesktop.org S: Maintained -F: drivers/gpu/drm/etnaviv -F: Documentation/devicetree/bindings/display/etnaviv +F: drivers/gpu/drm/etnaviv/ +F: include/uapi/drm/etnaviv_drm.h +F: Documentation/devicetree/bindings/display/etnaviv/ + +DRM DRIVER FOR VMWARE VIRTUAL GPU +M: "VMware Graphics" +M: Sinclair Yeh +M: Thomas Hellstrom +L: dri-devel@lists.freedesktop.org +T: git git://people.freedesktop.org/~syeh/repos_linux +T: git git://people.freedesktop.org/~thomash/linux +S: Supported +F: drivers/gpu/drm/vmwgfx/ +F: include/uapi/drm/vmwgfx_drm.h + +DRM DRIVERS FOR VC4 +M: Eric Anholt +T: git git://github.com/anholt/linux +S: Supported +F: drivers/gpu/drm/vc4/ +F: include/uapi/drm/vc4_drm.h +F: Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt DSBR100 USB FM RADIO DRIVER M: Alexey Klimov @@ -7005,6 +7129,8 @@ MARVELL ARMADA DRM SUPPORT M: Russell King S: Maintained F: drivers/gpu/drm/armada/ +F: include/uapi/drm/armada_drm.h +F: Documentation/devicetree/bindings/display/armada/ MARVELL 88E6352 DSA support M: Guenter Roeck diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi index 40bcecfc3687..3e02f152edcb 100644 --- a/arch/arc/boot/dts/axc001.dtsi +++ b/arch/arc/boot/dts/axc001.dtsi @@ -101,8 +101,26 @@ memory { #address-cells = <1>; #size-cells = <1>; - ranges = <0x00000000 0x80000000 0x40000000>; + ranges = <0x00000000 0x80000000 0x20000000>; device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512MiB */ + reg = <0x80000000 0x1b000000>; /* (512 - 32) MiB */ + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* + * We just move frame buffer area to the very end of + * available DDR. And even though in case of ARC770 there's + * no strict requirement for a frame-buffer to be in any + * particular location it allows us to use the same + * base board's DT node for ARC PGU as for ARc HS38. + */ + frame_buffer: frame_buffer@9e000000 { + compatible = "shared-dma-pool"; + reg = <0x9e000000 0x2000000>; + no-map; + }; }; }; diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi index cabe0deeb2d8..378e455a94c4 100644 --- a/arch/arc/boot/dts/axc003.dtsi +++ b/arch/arc/boot/dts/axc003.dtsi @@ -108,4 +108,18 @@ device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512MiB */ }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* + * Move frame buffer out of IOC aperture (0x8z-0xAz). + */ + frame_buffer: frame_buffer@be000000 { + compatible = "shared-dma-pool"; + reg = <0xbe000000 0x2000000>; + no-map; + }; + }; }; diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi index ed1674b16e82..64c94b2860ab 100644 --- a/arch/arc/boot/dts/axc003_idu.dtsi +++ b/arch/arc/boot/dts/axc003_idu.dtsi @@ -131,4 +131,18 @@ device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512MiB */ }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* + * Move frame buffer out of IOC aperture (0x8z-0xAz). + */ + frame_buffer: frame_buffer@be000000 { + compatible = "shared-dma-pool"; + reg = <0xbe000000 0x2000000>; + no-map; + }; + }; }; diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi index 68c84a2fc1e4..d6c1bbc98ac3 100644 --- a/arch/arc/boot/dts/axs10x_mb.dtsi +++ b/arch/arc/boot/dts/axs10x_mb.dtsi @@ -47,6 +47,12 @@ clock-frequency = <50000000>; #clock-cells = <0>; }; + + pguclk: pguclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <74440000>; + }; }; ethernet@0x18000 { @@ -160,6 +166,37 @@ clocks = <&i2cclk>; interrupts = <16>; + adv7511:adv7511@39{ + compatible="adi,adv7511"; + reg = <0x39>; + interrupts = <23>; + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,clock-delay = <0x03>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* RGB/YUV input */ + port@0 { + reg = <0>; + adv7511_input:endpoint { + remote-endpoint = <&pgu_output>; + }; + }; + + /* HDMI output */ + port@1 { + reg = <1>; + adv7511_output: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + eeprom@0x54{ compatible = "24c01"; reg = <0x54>; @@ -173,6 +210,16 @@ }; }; + hdmi0: connector { + compatible = "hdmi-connector"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7511_output>; + }; + }; + }; + gpio0:gpio@13000 { compatible = "snps,dw-apb-gpio"; reg = <0x13000 0x1000>; @@ -234,5 +281,19 @@ reg = <2>; }; }; + + pgu@17000 { + compatible = "snps,arcpgu"; + reg = <0x17000 0x400>; + encoder-slave = <&adv7511>; + clocks = <&pguclk>; + clock-names = "pxlclk"; + memory-region = <&frame_buffer>; + port { + pgu_output: endpoint { + remote-endpoint = <&adv7511_input>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 1e25152dc0f6..85dad29c08dc 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -124,8 +124,6 @@ &dp { status = "okay"; samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <4>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 0e2eb3f6b590..b7992b13c9de 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -80,8 +80,6 @@ &dp { samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <4>; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index c9889b1f530a..ddfe1f558c10 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -236,12 +236,10 @@ pinctrl-names = "default"; pinctrl-0 = <&dp_hpd>; samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; ports { port0 { diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 273d66282ebc..ac291f540812 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -74,12 +74,10 @@ pinctrl-names = "default"; pinctrl-0 = <&dp_hpd_gpio>; samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <1>; - samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>; }; &ehci { diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 8811e170c2af..f9d2e4f1a0e0 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -157,12 +157,10 @@ pinctrl-names = "default"; pinctrl-0 = <&dp_hpd_gpio>; samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; samsung,link-rate = <0x06>; samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; ports { port0 { diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 9b77940c9201..2e748d19322f 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -102,8 +102,6 @@ pinctrl-names = "default"; pinctrl-0 = <&dp_hpd>; samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <4>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index f95992520a77..62ceb89e073f 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -157,8 +157,6 @@ pinctrl-names = "default"; pinctrl-0 = <&dp_hpd_gpio>; samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <2>; diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 227e356403d9..10c986018a08 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -61,7 +61,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793), FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1), - FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "tvdpll_445p5m", 1, 3), FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2), FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3), @@ -558,7 +557,11 @@ static const struct mtk_composite top_muxes[] __initconst = { MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23), MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7), + /* + * The dpi0_sel clock should not propagate rate changes to its parent + * clock so the dpi driver can have full control over PLL and divider. + */ + MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0), MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15), MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23), MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31), @@ -1091,6 +1094,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node) clk_data->clks[cku->id] = clk; } + clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0, + base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO, + NULL); + clk_data->clks[CLK_APMIXED_HDMI_REF] = clk; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 32d2e455eb3f..9f24fcfa304f 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -83,7 +83,11 @@ struct mtk_composite { signed char num_parents; }; -#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \ +/* + * In case the rate change propagation to parent clocks is undesirable, + * this macro allows to specify the clock flags manually. + */ +#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \ .id = _id, \ .name = _name, \ .mux_reg = _reg, \ @@ -94,9 +98,16 @@ struct mtk_composite { .divider_shift = -1, \ .parent_names = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_SET_RATE_PARENT, \ + .flags = _flags, \ } +/* + * Unless necessary, all MUX_GATE clocks propagate rate changes to their + * parent clock by default. + */ +#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ + MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT) + #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ .id = _id, \ .name = _name, \ diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index f2a74d0b68ae..fc357319de35 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -52,6 +52,7 @@ config DRM_KMS_FB_HELPER select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT + select FB_DEFERRED_IO help FBDEV helpers for KMS drivers. @@ -252,6 +253,8 @@ source "drivers/gpu/drm/rcar-du/Kconfig" source "drivers/gpu/drm/shmobile/Kconfig" +source "drivers/gpu/drm/sun4i/Kconfig" + source "drivers/gpu/drm/omapdrm/Kconfig" source "drivers/gpu/drm/tilcdc/Kconfig" @@ -281,3 +284,9 @@ source "drivers/gpu/drm/imx/Kconfig" source "drivers/gpu/drm/vc4/Kconfig" source "drivers/gpu/drm/etnaviv/Kconfig" + +source "drivers/gpu/drm/arc/Kconfig" + +source "drivers/gpu/drm/hisilicon/Kconfig" + +source "drivers/gpu/drm/mediatek/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 6eb94fc561dc..2bd3e5aa43c6 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -1,4 +1,4 @@ -# + # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. @@ -65,6 +65,7 @@ obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/ obj-y += omapdrm/ +obj-$(CONFIG_DRM_SUN4I) += sun4i/ obj-y += tilcdc/ obj-$(CONFIG_DRM_QXL) += qxl/ obj-$(CONFIG_DRM_BOCHS) += bochs/ @@ -73,8 +74,11 @@ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STI) += sti/ obj-$(CONFIG_DRM_IMX) += imx/ +obj-$(CONFIG_DRM_MEDIATEK) += mediatek/ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/ obj-$(CONFIG_DRM_ETNAVIV) += etnaviv/ +obj-$(CONFIG_DRM_ARCPGU)+= arc/ +obj-y += hisilicon/ diff --git a/drivers/gpu/drm/amd/acp/acp_hw.c b/drivers/gpu/drm/amd/acp/acp_hw.c index 7af83f142b4b..c7d7205c9b11 100644 --- a/drivers/gpu/drm/amd/acp/acp_hw.c +++ b/drivers/gpu/drm/amd/acp/acp_hw.c @@ -34,7 +34,7 @@ #define mmACP_AZALIA_I2S_SELECT 0x51d4 -int amd_acp_hw_init(void *cgs_device, +int amd_acp_hw_init(struct cgs_device *cgs_device, unsigned acp_version_major, unsigned acp_version_minor) { unsigned int acp_mode = ACP_MODE_I2S; diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h index bccf47b63899..a72ddb2f69ac 100644 --- a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h +++ b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h @@ -28,7 +28,7 @@ #include "cgs_linux.h" #include "cgs_common.h" -int amd_acp_hw_init(void *cgs_device, +int amd_acp_hw_init(struct cgs_device *cgs_device, unsigned acp_version_major, unsigned acp_version_minor); #endif /* _ACP_GFX_IF_H */ diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index b30fcfa4b1f2..7335c0420c70 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -15,3 +15,13 @@ config DRM_AMDGPU_USERPTR help This option selects CONFIG_MMU_NOTIFIER if it isn't already selected to enabled full userptr support. + +config DRM_AMDGPU_GART_DEBUGFS + bool "Allow GART access through debugfs" + depends on DRM_AMDGPU + depends on DEBUG_FS + default n + help + Selecting this option creates a debugfs file to inspect the mapped + pages. Uses more memory for housekeeping, enable only for debugging. + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1bcbade479dc..2a009c398dcb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -283,7 +283,8 @@ struct amdgpu_ring_funcs { int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); /* command emit functions */ void (*emit_ib)(struct amdgpu_ring *ring, - struct amdgpu_ib *ib); + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch); void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq, unsigned flags); void (*emit_pipeline_sync)(struct amdgpu_ring *ring); @@ -302,6 +303,8 @@ struct amdgpu_ring_funcs { void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); /* pad the indirect buffer to the necessary number of dw */ void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); + unsigned (*init_cond_exec)(struct amdgpu_ring *ring); + void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); }; /* @@ -365,13 +368,6 @@ struct amdgpu_fence_driver { #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) #define AMDGPU_FENCE_FLAG_INT (1 << 1) -struct amdgpu_user_fence { - /* write-back bo */ - struct amdgpu_bo *bo; - /* write-back address offset to bo start */ - uint32_t offset; -}; - int amdgpu_fence_driver_init(struct amdgpu_device *adev); void amdgpu_fence_driver_fini(struct amdgpu_device *adev); void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); @@ -391,6 +387,14 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); /* * TTM. */ + +#define AMDGPU_TTM_LRU_SIZE 20 + +struct amdgpu_mman_lru { + struct list_head *lru[TTM_NUM_MEM_TYPES]; + struct list_head *swap_lru; +}; + struct amdgpu_mman { struct ttm_bo_global_ref bo_global_ref; struct drm_global_reference mem_global_ref; @@ -408,6 +412,9 @@ struct amdgpu_mman { struct amdgpu_ring *buffer_funcs_ring; /* Scheduler entity for buffer moves */ struct amd_sched_entity entity; + + /* custom LRU management */ + struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE]; }; int amdgpu_copy_buffer(struct amdgpu_ring *ring, @@ -494,9 +501,10 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv); unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); -struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, - struct dma_buf_attachment *attach, - struct sg_table *sg); +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg); struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, struct drm_gem_object *gobj, int flags); @@ -586,6 +594,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, struct reservation_object *resv, void *owner); +bool amdgpu_sync_is_idle(struct amdgpu_sync *sync); +int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src, + struct fence *fence); struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); int amdgpu_sync_wait(struct amdgpu_sync *sync); void amdgpu_sync_free(struct amdgpu_sync *sync); @@ -609,8 +620,9 @@ struct amdgpu_gart { unsigned num_gpu_pages; unsigned num_cpu_pages; unsigned table_size; +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS struct page **pages; - dma_addr_t *pages_addr; +#endif bool ready; const struct amdgpu_gart_funcs *gart_funcs; }; @@ -709,6 +721,7 @@ struct amdgpu_flip_work { unsigned shared_count; struct fence **shared; struct fence_cb cb; + bool async; }; @@ -721,17 +734,7 @@ struct amdgpu_ib { uint32_t length_dw; uint64_t gpu_addr; uint32_t *ptr; - struct amdgpu_user_fence *user; - struct amdgpu_vm *vm; - unsigned vm_id; - uint64_t vm_pd_addr; - struct amdgpu_ctx *ctx; - uint32_t gds_base, gds_size; - uint32_t gws_base, gws_size; - uint32_t oa_base, oa_size; uint32_t flags; - /* resulting sequence number */ - uint64_t sequence; }; enum amdgpu_ring_type { @@ -742,22 +745,25 @@ enum amdgpu_ring_type { AMDGPU_RING_TYPE_VCE }; -extern struct amd_sched_backend_ops amdgpu_sched_ops; +extern const struct amd_sched_backend_ops amdgpu_sched_ops; int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, - struct amdgpu_job **job); + struct amdgpu_job **job, struct amdgpu_vm *vm); int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, struct amdgpu_job **job); + void amdgpu_job_free(struct amdgpu_job *job); +void amdgpu_job_free_func(struct kref *refcount); int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, struct amd_sched_entity *entity, void *owner, struct fence **f); +void amdgpu_job_timeout_func(struct work_struct *work); struct amdgpu_ring { struct amdgpu_device *adev; const struct amdgpu_ring_funcs *funcs; struct amdgpu_fence_driver fence_drv; - struct amd_gpu_scheduler sched; + struct amd_gpu_scheduler sched; spinlock_t fence_lock; struct amdgpu_bo *ring_obj; @@ -785,9 +791,12 @@ struct amdgpu_ring { unsigned wptr_offs; unsigned next_rptr_offs; unsigned fence_offs; - struct amdgpu_ctx *current_ctx; + uint64_t current_ctx; enum amdgpu_ring_type type; char name[16]; + unsigned cond_exe_offs; + u64 cond_exe_gpu_addr; + volatile u32 *cond_exe_cpu_addr; }; /* @@ -830,13 +839,6 @@ struct amdgpu_vm_pt { uint64_t addr; }; -struct amdgpu_vm_id { - struct amdgpu_vm_manager_id *mgr_id; - uint64_t pd_gpu_addr; - /* last flushed PD/PT update */ - struct fence *flushed_updates; -}; - struct amdgpu_vm { /* tree of virtual addresses mapped */ struct rb_root va; @@ -862,19 +864,29 @@ struct amdgpu_vm { struct amdgpu_vm_pt *page_tables; /* for id and flush management per ring */ - struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; + struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; /* protecting freed */ spinlock_t freed_lock; /* Scheduler entity for page table updates */ struct amd_sched_entity entity; + + /* client id */ + u64 client_id; }; -struct amdgpu_vm_manager_id { +struct amdgpu_vm_id { struct list_head list; - struct fence *active; - atomic_long_t owner; + struct fence *first; + struct amdgpu_sync active; + struct fence *last_flush; + struct amdgpu_ring *last_user; + atomic64_t owner; + + uint64_t pd_gpu_addr; + /* last flushed PD/PT update */ + struct fence *flushed_updates; uint32_t gds_base; uint32_t gds_size; @@ -889,7 +901,7 @@ struct amdgpu_vm_manager { struct mutex lock; unsigned num_ids; struct list_head ids_lru; - struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM]; + struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; uint32_t max_pfn; /* vram base address for page table entry */ @@ -901,6 +913,8 @@ struct amdgpu_vm_manager { struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; unsigned vm_pte_num_rings; atomic_t vm_pte_next_ring; + /* client id counter */ + atomic64_t client_counter; }; void amdgpu_vm_manager_init(struct amdgpu_device *adev); @@ -916,11 +930,11 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync, struct fence *fence, unsigned *vm_id, uint64_t *vm_pd_addr); -void amdgpu_vm_flush(struct amdgpu_ring *ring, - unsigned vm_id, uint64_t pd_addr, - uint32_t gds_base, uint32_t gds_size, - uint32_t gws_base, uint32_t gws_size, - uint32_t oa_base, uint32_t oa_size); +int amdgpu_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size); void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, @@ -1026,6 +1040,11 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list); */ #include "clearstate_defs.h" +struct amdgpu_rlc_funcs { + void (*enter_safe_mode)(struct amdgpu_device *adev); + void (*exit_safe_mode)(struct amdgpu_device *adev); +}; + struct amdgpu_rlc { /* for power gating */ struct amdgpu_bo *save_restore_obj; @@ -1044,6 +1063,24 @@ struct amdgpu_rlc { uint64_t cp_table_gpu_addr; volatile uint32_t *cp_table_ptr; u32 cp_table_size; + + /* safe mode for updating CG/PG state */ + bool in_safe_mode; + const struct amdgpu_rlc_funcs *funcs; + + /* for firmware data */ + u32 save_and_restore_offset; + u32 clear_state_descriptor_offset; + u32 avail_scratch_ram_locations; + u32 reg_restore_list_size; + u32 reg_list_format_start; + u32 reg_list_format_separate_start; + u32 starting_offsets_start; + u32 reg_list_format_size_bytes; + u32 reg_list_size_bytes; + + u32 *register_list_format; + u32 *register_restore; }; struct amdgpu_mec { @@ -1097,6 +1134,12 @@ struct amdgpu_gca_config { uint32_t macrotile_mode_array[16]; }; +struct amdgpu_cu_info { + uint32_t number; /* total active CU number */ + uint32_t ao_cu_mask; + uint32_t bitmap[4][4]; +}; + struct amdgpu_gfx { struct mutex gpu_clock_mutex; struct amdgpu_gca_config config; @@ -1129,17 +1172,19 @@ struct amdgpu_gfx { struct amdgpu_irq_src priv_reg_irq; struct amdgpu_irq_src priv_inst_irq; /* gfx status */ - uint32_t gfx_current_status; + uint32_t gfx_current_status; /* ce ram size*/ - unsigned ce_ram_size; + unsigned ce_ram_size; + struct amdgpu_cu_info cu_info; }; int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned size, struct amdgpu_ib *ib); -void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f); +void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, + struct fence *f); int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, struct amdgpu_ib *ib, struct fence *last_vm_update, - struct fence **f); + struct amdgpu_job *job, struct fence **f); int amdgpu_ib_pool_init(struct amdgpu_device *adev); void amdgpu_ib_pool_fini(struct amdgpu_device *adev); int amdgpu_ib_ring_tests(struct amdgpu_device *adev); @@ -1164,7 +1209,7 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring); struct amdgpu_cs_chunk { uint32_t chunk_id; uint32_t length_dw; - uint32_t *kdata; + void *kdata; }; struct amdgpu_cs_parser { @@ -1195,13 +1240,25 @@ struct amdgpu_cs_parser { struct amdgpu_job { struct amd_sched_job base; struct amdgpu_device *adev; + struct amdgpu_vm *vm; struct amdgpu_ring *ring; struct amdgpu_sync sync; struct amdgpu_ib *ibs; struct fence *fence; /* the hw fence */ uint32_t num_ibs; void *owner; - struct amdgpu_user_fence uf; + uint64_t ctx; + unsigned vm_id; + uint64_t vm_pd_addr; + uint32_t gds_base, gds_size; + uint32_t gws_base, gws_size; + uint32_t oa_base, oa_size; + + /* user fence handling */ + struct amdgpu_bo *uf_bo; + uint32_t uf_offset; + uint64_t uf_sequence; + }; #define to_amdgpu_job(sched_job) \ container_of((sched_job), struct amdgpu_job, base) @@ -1582,10 +1639,12 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev); /* * UVD */ -#define AMDGPU_MAX_UVD_HANDLES 10 -#define AMDGPU_UVD_STACK_SIZE (1024*1024) -#define AMDGPU_UVD_HEAP_SIZE (1024*1024) -#define AMDGPU_UVD_FIRMWARE_OFFSET 256 +#define AMDGPU_DEFAULT_UVD_HANDLES 10 +#define AMDGPU_MAX_UVD_HANDLES 40 +#define AMDGPU_UVD_STACK_SIZE (200*1024) +#define AMDGPU_UVD_HEAP_SIZE (256*1024) +#define AMDGPU_UVD_SESSION_SIZE (50*1024) +#define AMDGPU_UVD_FIRMWARE_OFFSET 256 struct amdgpu_uvd { struct amdgpu_bo *vcpu_bo; @@ -1593,6 +1652,7 @@ struct amdgpu_uvd { uint64_t gpu_addr; unsigned fw_version; void *saved_bo; + unsigned max_handles; atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; struct delayed_work idle_work; @@ -1645,7 +1705,7 @@ struct amdgpu_sdma { struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; struct amdgpu_irq_src trap_irq; struct amdgpu_irq_src illegal_inst_irq; - int num_instances; + int num_instances; }; /* @@ -1691,12 +1751,12 @@ static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} * Debugfs */ struct amdgpu_debugfs { - struct drm_info_list *files; + const struct drm_info_list *files; unsigned num_files; }; int amdgpu_debugfs_add_files(struct amdgpu_device *adev, - struct drm_info_list *files, + const struct drm_info_list *files, unsigned nfiles); int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); @@ -1738,13 +1798,6 @@ struct amdgpu_allowed_register_entry { bool grbm_indexed; }; -struct amdgpu_cu_info { - uint32_t number; /* total active CU number */ - uint32_t ao_cu_mask; - uint32_t bitmap[4][4]; -}; - - /* * ASIC specific functions. */ @@ -1762,7 +1815,6 @@ struct amdgpu_asic_funcs { u32 (*get_xclk)(struct amdgpu_device *adev); /* get the gpu clock counter */ uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); - int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); /* MM block clocks */ int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); @@ -1855,15 +1907,8 @@ struct amdgpu_atcs { /* * CGS */ -void *amdgpu_cgs_create_device(struct amdgpu_device *adev); -void amdgpu_cgs_destroy_device(void *cgs_device); - - -/* - * CGS - */ -void *amdgpu_cgs_create_device(struct amdgpu_device *adev); -void amdgpu_cgs_destroy_device(void *cgs_device); +struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); +void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); /* GPU virtualization */ @@ -1904,16 +1949,15 @@ struct amdgpu_device { int usec_timeout; const struct amdgpu_asic_funcs *asic_funcs; bool shutdown; - bool suspend; bool need_dma32; bool accel_working; - struct work_struct reset_work; + struct work_struct reset_work; struct notifier_block acpi_nb; struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; - unsigned debugfs_count; + unsigned debugfs_count; #if defined(CONFIG_DEBUG_FS) - struct dentry *debugfs_regs; + struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; #endif struct amdgpu_atif atif; struct amdgpu_atcs atcs; @@ -1926,7 +1970,6 @@ struct amdgpu_device { /* BIOS */ uint8_t *bios; bool is_atom_bios; - uint16_t bios_header_start; struct amdgpu_bo *stollen_vga_memory; uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; @@ -2163,7 +2206,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) -#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) @@ -2175,7 +2217,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) -#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) +#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) @@ -2183,6 +2225,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) +#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) +#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) @@ -2196,7 +2240,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) -#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) +#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) @@ -2339,7 +2383,7 @@ static inline void amdgpu_unregister_atpx_handler(void) {} * KMS */ extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; -extern int amdgpu_max_kms_ioctl; +extern const int amdgpu_max_kms_ioctl; int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); int amdgpu_driver_unload_kms(struct drm_device *dev); @@ -2398,5 +2442,4 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, uint64_t addr, struct amdgpu_bo **bo); #include "amdgpu_object.h" - #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index b7b583c42ea8..252edba16e36 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -467,13 +467,6 @@ static int acp_soft_reset(void *handle) return 0; } -static void acp_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "ACP STATUS\n"); -} - static int acp_set_clockgating_state(void *handle, enum amd_clockgating_state state) { @@ -487,6 +480,7 @@ static int acp_set_powergating_state(void *handle, } const struct amd_ip_funcs acp_ip_funcs = { + .name = "acp_ip", .early_init = acp_early_init, .late_init = NULL, .sw_init = acp_sw_init, @@ -498,7 +492,6 @@ const struct amd_ip_funcs acp_ip_funcs = { .is_idle = acp_is_idle, .wait_for_idle = acp_wait_for_idle, .soft_reset = acp_soft_reset, - .print_status = acp_print_status, .set_clockgating_state = acp_set_clockgating_state, .set_powergating_state = acp_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h index f6e32a639107..8a396313c86f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h @@ -30,7 +30,7 @@ struct amdgpu_acp { struct device *parent; - void *cgs_device; + struct cgs_device *cgs_device; struct amd_acp_private *private; struct mfd_cell *acp_cell; struct resource *acp_res; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 84b0ce39ee14..9df1bcb35bf0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -234,16 +234,6 @@ amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, return hpd; } -static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev, - uint32_t supported_device, - int *connector_type, - struct amdgpu_i2c_bus_rec *i2c_bus, - uint16_t *line_mux, - struct amdgpu_hpd *hpd) -{ - return true; -} - static const int object_connector_convert[] = { DRM_MODE_CONNECTOR_Unknown, DRM_MODE_CONNECTOR_DVII, @@ -514,11 +504,6 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * conn_id = le16_to_cpu(path->usConnObjectId); - if (!amdgpu_atombios_apply_quirks - (adev, le16_to_cpu(path->usDeviceTag), &connector_type, - &ddc_bus, &conn_id, &hpd)) - continue; - amdgpu_display_add_connector(adev, conn_id, le16_to_cpu(path->usDeviceTag), @@ -699,6 +684,36 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) return ret; } +union gfx_info { + ATOM_GFX_INFO_V2_1 info; +}; + +int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index = GetIndexIntoMasterTable(DATA, GFX_Info); + uint8_t frev, crev; + uint16_t data_offset; + int ret = -EINVAL; + + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) { + union gfx_info *gfx_info = (union gfx_info *) + (mode_info->atom_context->bios + data_offset); + + adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines; + adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; + adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; + adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; + adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; + adev->gfx.config.max_texture_channel_caches = + gfx_info->info.max_texture_channel_caches; + + ret = 0; + } + return ret; +} + union igp_info { struct _ATOM_INTEGRATED_SYSTEM_INFO info; struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index 9e1442053fe4..8c2e69661799 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -144,6 +144,8 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev); +int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev); + bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, struct amdgpu_atom_ss *ss, int id, u32 clock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c index cd639c362df3..33e47a43ae32 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -141,7 +141,7 @@ out_cleanup: void amdgpu_benchmark(struct amdgpu_device *adev, int test_number) { int i; - int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = { + static const int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = { 640 * 480 * 4, 720 * 480 * 4, 800 * 600 * 4, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 80add22375ee..99ca75baa47d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -349,7 +349,7 @@ static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) bool amdgpu_get_bios(struct amdgpu_device *adev) { bool r; - uint16_t tmp; + uint16_t tmp, bios_header_start; r = amdgpu_atrm_get_bios(adev); if (r == false) @@ -383,11 +383,11 @@ bool amdgpu_get_bios(struct amdgpu_device *adev) goto free_bios; } - adev->bios_header_start = RBIOS16(0x48); - if (!adev->bios_header_start) { + bios_header_start = RBIOS16(0x48); + if (!bios_header_start) { goto free_bios; } - tmp = adev->bios_header_start + 4; + tmp = bios_header_start + 4; if (!memcmp(adev->bios + tmp, "ATOM", 4) || !memcmp(adev->bios + tmp, "MOTA", 4)) { adev->is_atom_bios = true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index eacd810fc09b..823bf5e0b0c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -106,7 +106,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, struct amdgpu_bo *bo; struct mm_struct *usermm; - gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle); + gobj = drm_gem_object_lookup(filp, info[i].bo_handle); if (!gobj) { r = -ENOENT; goto error_free; @@ -263,7 +263,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, for (i = 0; i < args->in.bo_number; ++i) { if (copy_from_user(&info[i], uptr, bytes)) goto error_free; - + uptr += args->in.bo_info_size; } } @@ -271,7 +271,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, switch (args->in.operation) { case AMDGPU_BO_LIST_OP_CREATE: r = amdgpu_bo_list_create(fpriv, &list, &handle); - if (r) + if (r) goto error_free; r = amdgpu_bo_list_set(adev, filp, list, info, @@ -281,7 +281,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, goto error_free; break; - + case AMDGPU_BO_LIST_OP_DESTROY: amdgpu_bo_list_destroy(fpriv, handle); handle = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index 6043dc7c3a94..199f76baf22c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -42,7 +42,7 @@ struct amdgpu_cgs_device { struct amdgpu_device *adev = \ ((struct amdgpu_cgs_device *)cgs_device)->adev -static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type, +static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, uint64_t *mc_start, uint64_t *mc_size, uint64_t *mem_size) { @@ -73,7 +73,7 @@ static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type, return 0; } -static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem, +static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem, uint64_t size, uint64_t min_offset, uint64_t max_offset, cgs_handle_t *kmem_handle, uint64_t *mcaddr) @@ -102,7 +102,7 @@ static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem, return ret; } -static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle) +static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle) { struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle; @@ -118,7 +118,7 @@ static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle) return 0; } -static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, +static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, uint64_t size, uint64_t align, uint64_t min_offset, uint64_t max_offset, @@ -208,7 +208,7 @@ static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, return ret; } -static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle) +static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle) { struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; @@ -225,7 +225,7 @@ static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle) return 0; } -static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle, +static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle, uint64_t *mcaddr) { int r; @@ -246,7 +246,7 @@ static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle, return r; } -static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) +static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle) { int r; struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; @@ -258,7 +258,7 @@ static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) return r; } -static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle, +static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle, void **map) { int r; @@ -271,7 +271,7 @@ static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle, return r; } -static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) +static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle) { int r; struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; @@ -283,20 +283,20 @@ static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) return r; } -static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset) +static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset) { CGS_FUNC_ADEV; return RREG32(offset); } -static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset, +static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset, uint32_t value) { CGS_FUNC_ADEV; WREG32(offset, value); } -static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device, +static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device, enum cgs_ind_reg space, unsigned index) { @@ -320,7 +320,7 @@ static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device, return 0; } -static void amdgpu_cgs_write_ind_register(void *cgs_device, +static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device, enum cgs_ind_reg space, unsigned index, uint32_t value) { @@ -343,7 +343,7 @@ static void amdgpu_cgs_write_ind_register(void *cgs_device, WARN(1, "Invalid indirect register space"); } -static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr) +static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr) { CGS_FUNC_ADEV; uint8_t val; @@ -353,7 +353,7 @@ static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr) return val; } -static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr) +static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr) { CGS_FUNC_ADEV; uint16_t val; @@ -363,7 +363,7 @@ static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr) return val; } -static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device, +static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device, unsigned addr) { CGS_FUNC_ADEV; @@ -374,7 +374,7 @@ static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device, return val; } -static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr, +static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr, uint8_t value) { CGS_FUNC_ADEV; @@ -382,7 +382,7 @@ static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr, WARN(ret, "pci_write_config_byte error"); } -static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr, +static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr, uint16_t value) { CGS_FUNC_ADEV; @@ -390,7 +390,7 @@ static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr, WARN(ret, "pci_write_config_word error"); } -static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, +static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr, uint32_t value) { CGS_FUNC_ADEV; @@ -399,7 +399,7 @@ static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, } -static int amdgpu_cgs_get_pci_resource(void *cgs_device, +static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device, enum cgs_resource_type resource_type, uint64_t size, uint64_t offset, @@ -433,7 +433,7 @@ static int amdgpu_cgs_get_pci_resource(void *cgs_device, } } -static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, +static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device, unsigned table, uint16_t *size, uint8_t *frev, uint8_t *crev) { @@ -449,7 +449,7 @@ static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, return NULL; } -static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table, +static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table, uint8_t *frev, uint8_t *crev) { CGS_FUNC_ADEV; @@ -462,7 +462,7 @@ static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table, return -EINVAL; } -static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table, +static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table, void *args) { CGS_FUNC_ADEV; @@ -471,33 +471,33 @@ static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table, adev->mode_info.atom_context, table, args); } -static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request) +static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request) { /* TODO */ return 0; } -static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request) +static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request) { /* TODO */ return 0; } -static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request, +static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request, int active) { /* TODO */ return 0; } -static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request, +static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request, enum cgs_clock clock, unsigned freq) { /* TODO */ return 0; } -static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request, +static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request, enum cgs_engine engine, int powered) { /* TODO */ @@ -506,7 +506,7 @@ static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request, -static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device, +static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device, enum cgs_clock clock, struct cgs_clock_limits *limits) { @@ -514,7 +514,7 @@ static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device, return 0; } -static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask, +static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask, const uint32_t *voltages) { DRM_ERROR("not implemented"); @@ -565,7 +565,7 @@ static const struct amdgpu_irq_src_funcs cgs_irq_funcs = { .process = cgs_process_irq, }; -static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id, +static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id, unsigned num_types, cgs_irq_source_set_func_t set, cgs_irq_handler_func_t handler, @@ -600,19 +600,19 @@ static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id, return ret; } -static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type) +static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type) { CGS_FUNC_ADEV; return amdgpu_irq_get(adev, adev->irq.sources[src_id], type); } -static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type) +static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type) { CGS_FUNC_ADEV; return amdgpu_irq_put(adev, adev->irq.sources[src_id], type); } -int amdgpu_cgs_set_clockgating_state(void *cgs_device, +int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, enum amd_ip_block_type block_type, enum amd_clockgating_state state) { @@ -633,7 +633,7 @@ int amdgpu_cgs_set_clockgating_state(void *cgs_device, return r; } -int amdgpu_cgs_set_powergating_state(void *cgs_device, +int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device, enum amd_ip_block_type block_type, enum amd_powergating_state state) { @@ -655,7 +655,7 @@ int amdgpu_cgs_set_powergating_state(void *cgs_device, } -static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type) +static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) { CGS_FUNC_ADEV; enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM; @@ -681,9 +681,10 @@ static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type) result = AMDGPU_UCODE_ID_CP_MEC1; break; case CGS_UCODE_ID_CP_MEC_JT2: - if (adev->asic_type == CHIP_TONGA) + if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11 + || adev->asic_type == CHIP_POLARIS10) result = AMDGPU_UCODE_ID_CP_MEC2; - else if (adev->asic_type == CHIP_CARRIZO) + else result = AMDGPU_UCODE_ID_CP_MEC1; break; case CGS_UCODE_ID_RLC_G: @@ -695,13 +696,13 @@ static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type) return result; } -static int amdgpu_cgs_get_firmware_info(void *cgs_device, +static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, enum cgs_ucode_id type, struct cgs_firmware_info *info) { CGS_FUNC_ADEV; - if (CGS_UCODE_ID_SMU != type) { + if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) { uint64_t gpu_addr; uint32_t data_size; const struct gfx_firmware_header_v1_0 *header; @@ -734,30 +735,44 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device, const uint8_t *src; const struct smc_firmware_header_v1_0 *hdr; - switch (adev->asic_type) { - case CHIP_TONGA: - strcpy(fw_name, "amdgpu/tonga_smc.bin"); - break; - case CHIP_FIJI: - strcpy(fw_name, "amdgpu/fiji_smc.bin"); - break; - default: - DRM_ERROR("SMC firmware not supported\n"); - return -EINVAL; - } + if (!adev->pm.fw) { + switch (adev->asic_type) { + case CHIP_TONGA: + strcpy(fw_name, "amdgpu/tonga_smc.bin"); + break; + case CHIP_FIJI: + strcpy(fw_name, "amdgpu/fiji_smc.bin"); + break; + case CHIP_POLARIS11: + if (type == CGS_UCODE_ID_SMU) + strcpy(fw_name, "amdgpu/polaris11_smc.bin"); + else if (type == CGS_UCODE_ID_SMU_SK) + strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin"); + break; + case CHIP_POLARIS10: + if (type == CGS_UCODE_ID_SMU) + strcpy(fw_name, "amdgpu/polaris10_smc.bin"); + else if (type == CGS_UCODE_ID_SMU_SK) + strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin"); + break; + default: + DRM_ERROR("SMC firmware not supported\n"); + return -EINVAL; + } - err = request_firmware(&adev->pm.fw, fw_name, adev->dev); - if (err) { - DRM_ERROR("Failed to request firmware\n"); - return err; - } + err = request_firmware(&adev->pm.fw, fw_name, adev->dev); + if (err) { + DRM_ERROR("Failed to request firmware\n"); + return err; + } - err = amdgpu_ucode_validate(adev->pm.fw); - if (err) { - DRM_ERROR("Failed to load firmware \"%s\"", fw_name); - release_firmware(adev->pm.fw); - adev->pm.fw = NULL; - return err; + err = amdgpu_ucode_validate(adev->pm.fw); + if (err) { + DRM_ERROR("Failed to load firmware \"%s\"", fw_name); + release_firmware(adev->pm.fw); + adev->pm.fw = NULL; + return err; + } } hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; @@ -774,7 +789,7 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device, return 0; } -static int amdgpu_cgs_query_system_info(void *cgs_device, +static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, struct cgs_system_info *sys_info) { CGS_FUNC_ADEV; @@ -801,6 +816,9 @@ static int amdgpu_cgs_query_system_info(void *cgs_device, case CGS_SYSTEM_INFO_PG_FLAGS: sys_info->value = adev->pg_flags; break; + case CGS_SYSTEM_INFO_GFX_CU_INFO: + sys_info->value = adev->gfx.cu_info.number; + break; default: return -ENODEV; } @@ -808,7 +826,7 @@ static int amdgpu_cgs_query_system_info(void *cgs_device, return 0; } -static int amdgpu_cgs_get_active_displays_info(void *cgs_device, +static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, struct cgs_display_info *info) { CGS_FUNC_ADEV; @@ -851,7 +869,7 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device, } -static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled) +static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled) { CGS_FUNC_ADEV; @@ -867,7 +885,7 @@ static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled) */ #if defined(CONFIG_ACPI) -static int amdgpu_cgs_acpi_eval_object(void *cgs_device, +static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device, struct cgs_acpi_method_info *info) { CGS_FUNC_ADEV; @@ -1030,14 +1048,14 @@ error: return result; } #else -static int amdgpu_cgs_acpi_eval_object(void *cgs_device, +static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device, struct cgs_acpi_method_info *info) { return -EIO; } #endif -int amdgpu_cgs_call_acpi_method(void *cgs_device, +int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device, uint32_t acpi_method, uint32_t acpi_function, void *pinput, void *poutput, @@ -1121,7 +1139,7 @@ static const struct cgs_os_ops amdgpu_cgs_os_ops = { amdgpu_cgs_irq_put }; -void *amdgpu_cgs_create_device(struct amdgpu_device *adev) +struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) { struct amdgpu_cgs_device *cgs_device = kmalloc(sizeof(*cgs_device), GFP_KERNEL); @@ -1135,10 +1153,10 @@ void *amdgpu_cgs_create_device(struct amdgpu_device *adev) cgs_device->base.os_ops = &amdgpu_cgs_os_ops; cgs_device->adev = adev; - return cgs_device; + return (struct cgs_device *)cgs_device; } -void amdgpu_cgs_destroy_device(void *cgs_device) +void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device) { kfree(cgs_device); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 119cdc2c43e7..60a0c9ac11b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -439,7 +439,7 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, struct drm_display_mode *mode = NULL; struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; int i; - struct mode_size { + static const struct mode_size { int w; int h; } common_modes[17] = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 9392e50a7ba4..9bc8f1d99733 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -24,7 +24,6 @@ * Authors: * Jerome Glisse */ -#include #include #include #include @@ -88,44 +87,41 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, } static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, - struct amdgpu_user_fence *uf, - struct drm_amdgpu_cs_chunk_fence *fence_data) + struct drm_amdgpu_cs_chunk_fence *data, + uint32_t *offset) { struct drm_gem_object *gobj; - uint32_t handle; - handle = fence_data->handle; - gobj = drm_gem_object_lookup(p->adev->ddev, p->filp, - fence_data->handle); + gobj = drm_gem_object_lookup(p->filp, data->handle); if (gobj == NULL) return -EINVAL; - uf->bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); - uf->offset = fence_data->offset; - - if (amdgpu_ttm_tt_get_usermm(uf->bo->tbo.ttm)) { - drm_gem_object_unreference_unlocked(gobj); - return -EINVAL; - } - - p->uf_entry.robj = amdgpu_bo_ref(uf->bo); + p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); p->uf_entry.priority = 0; p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; p->uf_entry.tv.shared = true; p->uf_entry.user_pages = NULL; + *offset = data->offset; drm_gem_object_unreference_unlocked(gobj); + + if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { + amdgpu_bo_unref(&p->uf_entry.robj); + return -EINVAL; + } + return 0; } int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) { struct amdgpu_fpriv *fpriv = p->filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; union drm_amdgpu_cs *cs = data; uint64_t *chunk_array_user; uint64_t *chunk_array; - struct amdgpu_user_fence uf = {}; unsigned size, num_ibs = 0; + uint32_t uf_offset = 0; int i; int ret; @@ -200,7 +196,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) goto free_partial_kdata; } - ret = amdgpu_cs_user_fence_chunk(p, &uf, (void *)p->chunks[i].kdata); + ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata, + &uf_offset); if (ret) goto free_partial_kdata; @@ -215,11 +212,14 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) } } - ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job); + ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm); if (ret) goto free_all_kdata; - p->job->uf = uf; + if (p->uf_entry.robj) { + p->job->uf_bo = amdgpu_bo_ref(p->uf_entry.robj); + p->job->uf_offset = uf_offset; + } kfree(chunk_array); return 0; @@ -377,7 +377,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, INIT_LIST_HEAD(&duplicates); amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); - if (p->job->uf.bo) + if (p->uf_entry.robj) list_add(&p->uf_entry.tv.head, &p->validated); if (need_mmap_lock) @@ -473,6 +473,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_validate; if (p->bo_list) { + struct amdgpu_bo *gds = p->bo_list->gds_obj; + struct amdgpu_bo *gws = p->bo_list->gws_obj; + struct amdgpu_bo *oa = p->bo_list->oa_obj; struct amdgpu_vm *vm = &fpriv->vm; unsigned i; @@ -481,6 +484,19 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo); } + + if (gds) { + p->job->gds_base = amdgpu_bo_gpu_offset(gds); + p->job->gds_size = amdgpu_bo_size(gds); + } + if (gws) { + p->job->gws_base = amdgpu_bo_gpu_offset(gws); + p->job->gws_size = amdgpu_bo_size(gws); + } + if (oa) { + p->job->oa_base = amdgpu_bo_gpu_offset(oa); + p->job->oa_size = amdgpu_bo_size(oa); + } } error_validate: @@ -527,16 +543,6 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) return 0; } -static int cmp_size_smaller_first(void *priv, struct list_head *a, - struct list_head *b) -{ - struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); - struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); - - /* Sort A before B if A is smaller. */ - return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; -} - /** * cs_parser_fini() - clean parser states * @parser: parser structure holding parsing context. @@ -553,18 +559,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo if (!error) { amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); - /* Sort the buffer list from the smallest to largest buffer, - * which affects the order of buffers in the LRU list. - * This assures that the smallest buffers are added first - * to the LRU list, so they are likely to be later evicted - * first, instead of large buffers whose eviction is more - * expensive. - * - * This slightly lowers the number of bytes moved by TTM - * per frame under memory pressure. - */ - list_sort(NULL, &parser->validated, cmp_size_smaller_first); - ttm_eu_fence_buffer_objects(&parser->ticket, &parser->validated, parser->fence); @@ -763,41 +757,14 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, ib->length_dw = chunk_ib->ib_bytes / 4; ib->flags = chunk_ib->flags; - ib->ctx = parser->ctx; j++; } - /* add GDS resources to first IB */ - if (parser->bo_list) { - struct amdgpu_bo *gds = parser->bo_list->gds_obj; - struct amdgpu_bo *gws = parser->bo_list->gws_obj; - struct amdgpu_bo *oa = parser->bo_list->oa_obj; - struct amdgpu_ib *ib = &parser->job->ibs[0]; - - if (gds) { - ib->gds_base = amdgpu_bo_gpu_offset(gds); - ib->gds_size = amdgpu_bo_size(gds); - } - if (gws) { - ib->gws_base = amdgpu_bo_gpu_offset(gws); - ib->gws_size = amdgpu_bo_size(gws); - } - if (oa) { - ib->oa_base = amdgpu_bo_gpu_offset(oa); - ib->oa_size = amdgpu_bo_size(oa); - } - } - /* wrap the last IB with user fence */ - if (parser->job->uf.bo) { - struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1]; - - /* UVD & VCE fw doesn't support user fences */ - if (parser->job->ring->type == AMDGPU_RING_TYPE_UVD || - parser->job->ring->type == AMDGPU_RING_TYPE_VCE) - return -EINVAL; - - ib->user = &parser->job->uf; - } + /* UVD & VCE fw doesn't support user fences */ + if (parser->job->uf_bo && ( + parser->job->ring->type == AMDGPU_RING_TYPE_UVD || + parser->job->ring->type == AMDGPU_RING_TYPE_VCE)) + return -EINVAL; return 0; } @@ -862,28 +829,28 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs) { struct amdgpu_ring *ring = p->job->ring; - struct amd_sched_fence *fence; + struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity; + struct fence *fence; struct amdgpu_job *job; + int r; job = p->job; p->job = NULL; - job->base.sched = &ring->sched; - job->base.s_entity = &p->ctx->rings[ring->idx].entity; - job->owner = p->filp; - - fence = amd_sched_fence_create(job->base.s_entity, p->filp); - if (!fence) { + r = amd_sched_job_init(&job->base, &ring->sched, + entity, amdgpu_job_timeout_func, + amdgpu_job_free_func, + p->filp, &fence); + if (r) { amdgpu_job_free(job); - return -ENOMEM; + return r; } - job->base.s_fence = fence; - p->fence = fence_get(&fence->base); - - cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, - &fence->base); - job->ibs[job->num_ibs - 1].sequence = cs->out.handle; + job->owner = p->filp; + job->ctx = entity->fence_context; + p->fence = fence_get(fence); + cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, fence); + job->uf_sequence = cs->out.handle; trace_amdgpu_cs_ioctl(job); amd_sched_entity_push_job(&job->base); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2139da773da6..bb8b149786d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -59,6 +59,8 @@ static const char *amdgpu_asic_name[] = { "FIJI", "CARRIZO", "STONEY", + "POLARIS10", + "POLARIS11", "LAST", }; @@ -346,7 +348,7 @@ static int amdgpu_doorbell_init(struct amdgpu_device *adev) adev->doorbell.base = pci_resource_start(adev->pdev, 2); adev->doorbell.size = pci_resource_len(adev->pdev, 2); - adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), + adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); if (adev->doorbell.num_doorbells == 0) return -EINVAL; @@ -936,15 +938,11 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) } if (amdgpu_gart_size != -1) { - /* gtt size must be power of two and greater or equal to 32M */ + /* gtt size must be greater or equal to 32M */ if (amdgpu_gart_size < 32) { dev_warn(adev->dev, "gart size (%d) too small\n", amdgpu_gart_size); amdgpu_gart_size = -1; - } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) { - dev_warn(adev->dev, "gart size (%d) must be a power of 2\n", - amdgpu_gart_size); - amdgpu_gart_size = -1; } } @@ -1144,6 +1142,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) case CHIP_TOPAZ: case CHIP_TONGA: case CHIP_FIJI: + case CHIP_POLARIS11: + case CHIP_POLARIS10: case CHIP_CARRIZO: case CHIP_STONEY: if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) @@ -1196,7 +1196,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev) if (r == -ENOENT) { adev->ip_block_status[i].valid = false; } else if (r) { - DRM_ERROR("early_init %d failed %d\n", i, r); + DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); return r; } else { adev->ip_block_status[i].valid = true; @@ -1219,7 +1219,7 @@ static int amdgpu_init(struct amdgpu_device *adev) continue; r = adev->ip_blocks[i].funcs->sw_init((void *)adev); if (r) { - DRM_ERROR("sw_init %d failed %d\n", i, r); + DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); return r; } adev->ip_block_status[i].sw = true; @@ -1252,7 +1252,7 @@ static int amdgpu_init(struct amdgpu_device *adev) continue; r = adev->ip_blocks[i].funcs->hw_init((void *)adev); if (r) { - DRM_ERROR("hw_init %d failed %d\n", i, r); + DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); return r; } adev->ip_block_status[i].hw = true; @@ -1272,13 +1272,13 @@ static int amdgpu_late_init(struct amdgpu_device *adev) r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, AMD_CG_STATE_GATE); if (r) { - DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r); + DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); return r; } if (adev->ip_blocks[i].funcs->late_init) { r = adev->ip_blocks[i].funcs->late_init((void *)adev); if (r) { - DRM_ERROR("late_init %d failed %d\n", i, r); + DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); return r; } } @@ -1302,13 +1302,13 @@ static int amdgpu_fini(struct amdgpu_device *adev) r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, AMD_CG_STATE_UNGATE); if (r) { - DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r); + DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); return r; } r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); /* XXX handle errors */ if (r) { - DRM_DEBUG("hw_fini %d failed %d\n", i, r); + DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); } adev->ip_block_status[i].hw = false; } @@ -1319,7 +1319,7 @@ static int amdgpu_fini(struct amdgpu_device *adev) r = adev->ip_blocks[i].funcs->sw_fini((void *)adev); /* XXX handle errors */ if (r) { - DRM_DEBUG("sw_fini %d failed %d\n", i, r); + DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); } adev->ip_block_status[i].sw = false; adev->ip_block_status[i].valid = false; @@ -1332,20 +1332,29 @@ static int amdgpu_suspend(struct amdgpu_device *adev) { int i, r; + /* ungate SMC block first */ + r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, + AMD_CG_STATE_UNGATE); + if (r) { + DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); + } + for (i = adev->num_ip_blocks - 1; i >= 0; i--) { if (!adev->ip_block_status[i].valid) continue; /* ungate blocks so that suspend can properly shut them down */ - r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, - AMD_CG_STATE_UNGATE); - if (r) { - DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r); + if (i != AMD_IP_BLOCK_TYPE_SMC) { + r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, + AMD_CG_STATE_UNGATE); + if (r) { + DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + } } /* XXX handle errors */ r = adev->ip_blocks[i].funcs->suspend(adev); /* XXX handle errors */ if (r) { - DRM_ERROR("suspend %d failed %d\n", i, r); + DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); } } @@ -1361,7 +1370,7 @@ static int amdgpu_resume(struct amdgpu_device *adev) continue; r = adev->ip_blocks[i].funcs->resume(adev); if (r) { - DRM_ERROR("resume %d failed %d\n", i, r); + DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); return r; } } @@ -2007,7 +2016,7 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev) * Debugfs */ int amdgpu_debugfs_add_files(struct amdgpu_device *adev, - struct drm_info_list *files, + const struct drm_info_list *files, unsigned nfiles) { unsigned i; @@ -2119,32 +2128,246 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, return result; } +static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + value = RREG32_PCIE(*pos >> 2); + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + WREG32_PCIE(*pos >> 2, value); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + value = RREG32_DIDT(*pos >> 2); + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + WREG32_DIDT(*pos >> 2, value); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + value = RREG32_SMC(*pos >> 2); + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + WREG32_SMC(*pos >> 2, value); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + static const struct file_operations amdgpu_debugfs_regs_fops = { .owner = THIS_MODULE, .read = amdgpu_debugfs_regs_read, .write = amdgpu_debugfs_regs_write, .llseek = default_llseek }; +static const struct file_operations amdgpu_debugfs_regs_didt_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_didt_read, + .write = amdgpu_debugfs_regs_didt_write, + .llseek = default_llseek +}; +static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_pcie_read, + .write = amdgpu_debugfs_regs_pcie_write, + .llseek = default_llseek +}; +static const struct file_operations amdgpu_debugfs_regs_smc_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_smc_read, + .write = amdgpu_debugfs_regs_smc_write, + .llseek = default_llseek +}; + +static const struct file_operations *debugfs_regs[] = { + &amdgpu_debugfs_regs_fops, + &amdgpu_debugfs_regs_didt_fops, + &amdgpu_debugfs_regs_pcie_fops, + &amdgpu_debugfs_regs_smc_fops, +}; + +static const char *debugfs_regs_names[] = { + "amdgpu_regs", + "amdgpu_regs_didt", + "amdgpu_regs_pcie", + "amdgpu_regs_smc", +}; static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) { struct drm_minor *minor = adev->ddev->primary; struct dentry *ent, *root = minor->debugfs_root; + unsigned i, j; - ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root, - adev, &amdgpu_debugfs_regs_fops); - if (IS_ERR(ent)) - return PTR_ERR(ent); - i_size_write(ent->d_inode, adev->rmmio_size); - adev->debugfs_regs = ent; + for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { + ent = debugfs_create_file(debugfs_regs_names[i], + S_IFREG | S_IRUGO, root, + adev, debugfs_regs[i]); + if (IS_ERR(ent)) { + for (j = 0; j < i; j++) { + debugfs_remove(adev->debugfs_regs[i]); + adev->debugfs_regs[i] = NULL; + } + return PTR_ERR(ent); + } + + if (!i) + i_size_write(ent->d_inode, adev->rmmio_size); + adev->debugfs_regs[i] = ent; + } return 0; } static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { - debugfs_remove(adev->debugfs_regs); - adev->debugfs_regs = NULL; + unsigned i; + + for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { + if (adev->debugfs_regs[i]) { + debugfs_remove(adev->debugfs_regs[i]); + adev->debugfs_regs[i] = NULL; + } + } } int amdgpu_debugfs_init(struct drm_minor *minor) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 3fb405b3a614..b0832da2ef7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -131,12 +131,17 @@ static void amdgpu_flip_work_func(struct work_struct *__work) vblank->framedur_ns / 1000, vblank->linedur_ns / 1000, stat, vpos, hpos); - /* set the flip status */ + /* Do the flip (mmio) */ + adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); + + /* Set the flip status */ amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - /* Do the flip (mmio) */ - adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); + + DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", + amdgpuCrtc->crtc_id, amdgpuCrtc, work); + } /* @@ -192,6 +197,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, work->event = event; work->adev = adev; work->crtc_id = amdgpu_crtc->crtc_id; + work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; /* schedule unpin of the old buffer */ old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); @@ -252,6 +258,9 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; amdgpu_crtc->pflip_works = work; + + DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", + amdgpu_crtc->crtc_id, amdgpu_crtc, work); /* update crtc fb */ crtc->primary->fb = fb; spin_unlock_irqrestore(&crtc->dev->event_lock, flags); @@ -554,7 +563,7 @@ amdgpu_user_framebuffer_create(struct drm_device *dev, struct amdgpu_framebuffer *amdgpu_fb; int ret; - obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); + obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); if (obj == NULL) { dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " "can't create framebuffer\n", mode_cmd->handles[0]); @@ -588,20 +597,20 @@ const struct drm_mode_config_funcs amdgpu_mode_funcs = { .output_poll_changed = amdgpu_output_poll_changed }; -static struct drm_prop_enum_list amdgpu_underscan_enum_list[] = +static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = { { UNDERSCAN_OFF, "off" }, { UNDERSCAN_ON, "on" }, { UNDERSCAN_AUTO, "auto" }, }; -static struct drm_prop_enum_list amdgpu_audio_enum_list[] = +static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = { { AMDGPU_AUDIO_DISABLE, "off" }, { AMDGPU_AUDIO_ENABLE, "on" }, { AMDGPU_AUDIO_AUTO, "auto" }, }; /* XXX support different dither options? spatial, temporal, both, etc. */ -static struct drm_prop_enum_list amdgpu_dither_enum_list[] = +static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = { { AMDGPU_FMT_DITHER_DISABLE, "off" }, { AMDGPU_FMT_DITHER_ENABLE, "on" }, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 7b7f4aba60c0..fe36caf1b7d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -150,7 +150,7 @@ u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { amdgpu_crtc = to_amdgpu_crtc(crtc); if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { - vrefresh = amdgpu_crtc->hw_mode.vrefresh; + vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); break; } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f1e17d60055a..1dab5f2b725b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -166,7 +166,7 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); -static struct pci_device_id pciidlist[] = { +static const struct pci_device_id pciidlist[] = { #ifdef CONFIG_DRM_AMDGPU_CIK /* Kaveri */ {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, @@ -277,6 +277,16 @@ static struct pci_device_id pciidlist[] = { {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, /* stoney */ {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, + /* Polaris11 */ + {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + /* Polaris10 */ + {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, + {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0, 0, 0} }; @@ -514,7 +524,7 @@ static struct drm_driver kms_driver = { .irq_uninstall = amdgpu_irq_uninstall, .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, - .gem_free_object = amdgpu_gem_object_free, + .gem_free_object_unlocked = amdgpu_gem_object_free, .gem_open_object = amdgpu_gem_object_open, .gem_close_object = amdgpu_gem_object_close, .dumb_create = amdgpu_mode_dumb_create, @@ -556,12 +566,10 @@ static struct pci_driver amdgpu_kms_pci_driver = { static int __init amdgpu_init(void) { amdgpu_sync_init(); -#ifdef CONFIG_VGA_CONSOLE if (vgacon_text_force()) { DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); return -EINVAL; } -#endif DRM_INFO("amdgpu kernel modesetting enabled.\n"); driver = &kms_driver; pdriver = &amdgpu_kms_pci_driver; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d81f1f4883a6..ba9c04283d01 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -198,7 +198,7 @@ void amdgpu_fence_process(struct amdgpu_ring *ring) /* There is always exactly one thread signaling this fence slot */ fence = rcu_dereference_protected(*ptr, 1); - rcu_assign_pointer(*ptr, NULL); + RCU_INIT_POINTER(*ptr, NULL); BUG_ON(!fence); @@ -352,9 +352,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, (unsigned long)ring); - ring->fence_drv.num_fences_mask = num_hw_submission - 1; + ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; spin_lock_init(&ring->fence_drv.lock); - ring->fence_drv.fences = kcalloc(num_hw_submission, sizeof(void *), + ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), GFP_KERNEL); if (!ring->fence_drv.fences) return -ENOMEM; @@ -639,7 +639,7 @@ static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) return 0; } -static struct drm_info_list amdgpu_debugfs_fence_list[] = { +static const struct drm_info_list amdgpu_debugfs_fence_list[] = { {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 7312d729d300..921bce2df0b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -238,18 +238,17 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, t = offset / AMDGPU_GPU_PAGE_SIZE; p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); for (i = 0; i < pages; i++, p++) { - if (adev->gart.pages[p]) { - adev->gart.pages[p] = NULL; - adev->gart.pages_addr[p] = adev->dummy_page.addr; - page_base = adev->gart.pages_addr[p]; - if (!adev->gart.ptr) - continue; +#ifdef CONFIG_AMDGPU_GART_DEBUGFS + adev->gart.pages[p] = NULL; +#endif + page_base = adev->dummy_page.addr; + if (!adev->gart.ptr) + continue; - for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { - amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, - t, page_base, flags); - page_base += AMDGPU_GPU_PAGE_SIZE; - } + for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { + amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, + t, page_base, flags); + page_base += AMDGPU_GPU_PAGE_SIZE; } } mb(); @@ -287,10 +286,11 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); for (i = 0; i < pages; i++, p++) { - adev->gart.pages_addr[p] = dma_addr[i]; +#ifdef CONFIG_AMDGPU_GART_DEBUGFS adev->gart.pages[p] = pagelist[i]; +#endif if (adev->gart.ptr) { - page_base = adev->gart.pages_addr[p]; + page_base = dma_addr[i]; for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags); page_base += AMDGPU_GPU_PAGE_SIZE; @@ -312,11 +312,11 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, */ int amdgpu_gart_init(struct amdgpu_device *adev) { - int r, i; + int r; - if (adev->gart.pages) { + if (adev->dummy_page.page) return 0; - } + /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { DRM_ERROR("Page size is smaller than GPU page size!\n"); @@ -330,22 +330,16 @@ int amdgpu_gart_init(struct amdgpu_device *adev) adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE; DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); + +#ifdef CONFIG_AMDGPU_GART_DEBUGFS /* Allocate pages table */ adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages); if (adev->gart.pages == NULL) { amdgpu_gart_fini(adev); return -ENOMEM; } - adev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) * - adev->gart.num_cpu_pages); - if (adev->gart.pages_addr == NULL) { - amdgpu_gart_fini(adev); - return -ENOMEM; - } - /* set GART entry to point to the dummy page by default */ - for (i = 0; i < adev->gart.num_cpu_pages; i++) { - adev->gart.pages_addr[i] = adev->dummy_page.addr; - } +#endif + return 0; } @@ -358,15 +352,14 @@ int amdgpu_gart_init(struct amdgpu_device *adev) */ void amdgpu_gart_fini(struct amdgpu_device *adev) { - if (adev->gart.pages && adev->gart.pages_addr && adev->gart.ready) { + if (adev->gart.ready) { /* unbind pages */ amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages); } adev->gart.ready = false; +#ifdef CONFIG_AMDGPU_GART_DEBUGFS vfree(adev->gart.pages); - vfree(adev->gart.pages_addr); adev->gart.pages = NULL; - adev->gart.pages_addr = NULL; - +#endif amdgpu_dummy_page_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h index c3f4e85594ff..503d54098128 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h @@ -43,7 +43,7 @@ struct amdgpu_ring; struct amdgpu_bo; struct amdgpu_gds_asic_info { - uint32_t total_size; + uint32_t total_size; uint32_t gfx_partition_size; uint32_t cs_partition_size; }; @@ -52,8 +52,8 @@ struct amdgpu_gds { struct amdgpu_gds_asic_info mem; struct amdgpu_gds_asic_info gws; struct amdgpu_gds_asic_info oa; - /* At present, GDS, GWS and OA resources for gfx (graphics) - * is always pre-allocated and available for graphics operation. + /* At present, GDS, GWS and OA resources for gfx (graphics) + * is always pre-allocated and available for graphics operation. * Such resource is shared between all gfx clients. * TODO: move this operation to user space * */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index fa6a27bff298..8fab6486064f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -93,7 +93,7 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev) struct drm_device *ddev = adev->ddev; struct drm_file *file; - mutex_lock(&ddev->struct_mutex); + mutex_lock(&ddev->filelist_mutex); list_for_each_entry(file, &ddev->filelist, lhead) { struct drm_gem_object *gobj; @@ -103,13 +103,13 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev) spin_lock(&file->table_lock); idr_for_each_entry(&file->object_idr, gobj, handle) { WARN_ONCE(1, "And also active allocations!\n"); - drm_gem_object_unreference(gobj); + drm_gem_object_unreference_unlocked(gobj); } idr_destroy(&file->object_idr); spin_unlock(&file->table_lock); } - mutex_unlock(&ddev->struct_mutex); + mutex_unlock(&ddev->filelist_mutex); } /* @@ -338,7 +338,7 @@ int amdgpu_mode_dumb_mmap(struct drm_file *filp, struct drm_gem_object *gobj; struct amdgpu_bo *robj; - gobj = drm_gem_object_lookup(dev, filp, handle); + gobj = drm_gem_object_lookup(filp, handle); if (gobj == NULL) { return -ENOENT; } @@ -402,7 +402,7 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, int r = 0; long ret; - gobj = drm_gem_object_lookup(dev, filp, handle); + gobj = drm_gem_object_lookup(filp, handle); if (gobj == NULL) { return -ENOENT; } @@ -436,7 +436,7 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, int r = -1; DRM_DEBUG("%d \n", args->handle); - gobj = drm_gem_object_lookup(dev, filp, args->handle); + gobj = drm_gem_object_lookup(filp, args->handle); if (gobj == NULL) return -ENOENT; robj = gem_to_amdgpu_bo(gobj); @@ -584,7 +584,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, return -EINVAL; } - gobj = drm_gem_object_lookup(dev, filp, args->handle); + gobj = drm_gem_object_lookup(filp, args->handle); if (gobj == NULL) return -ENOENT; rbo = gem_to_amdgpu_bo(gobj); @@ -646,7 +646,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, struct amdgpu_bo *robj; int r; - gobj = drm_gem_object_lookup(dev, filp, args->handle); + gobj = drm_gem_object_lookup(filp, args->handle); if (gobj == NULL) { return -ENOENT; } @@ -769,7 +769,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) struct drm_file *file; int r; - r = mutex_lock_interruptible(&dev->struct_mutex); + r = mutex_lock_interruptible(&dev->filelist_mutex); if (r) return r; @@ -793,11 +793,11 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) spin_unlock(&file->table_lock); } - mutex_unlock(&dev->struct_mutex); + mutex_unlock(&dev->filelist_mutex); return 0; } -static struct drm_info_list amdgpu_debugfs_gem_list[] = { +static const struct drm_info_list amdgpu_debugfs_gem_list[] = { {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, }; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 8443cea6821a..34e35423b78e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -74,9 +74,6 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); } - ib->vm = vm; - ib->vm_id = 0; - return 0; } @@ -89,7 +86,8 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, * * Free an IB (all asics). */ -void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f) +void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, + struct fence *f) { amdgpu_sa_bo_free(adev, &ib->sa_bo, f); } @@ -117,28 +115,37 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fen */ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, struct amdgpu_ib *ibs, struct fence *last_vm_update, - struct fence **f) + struct amdgpu_job *job, struct fence **f) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib *ib = &ibs[0]; - struct amdgpu_ctx *ctx, *old_ctx; + bool skip_preamble, need_ctx_switch; + unsigned patch_offset = ~0; struct amdgpu_vm *vm; struct fence *hwf; + uint64_t ctx; + unsigned i; int r = 0; if (num_ibs == 0) return -EINVAL; - ctx = ibs->ctx; - vm = ibs->vm; + /* ring tests don't use a job */ + if (job) { + vm = job->vm; + ctx = job->ctx; + } else { + vm = NULL; + ctx = 0; + } if (!ring->ready) { dev_err(adev->dev, "couldn't schedule ib\n"); return -EINVAL; } - if (vm && !ibs->vm_id) { + if (vm && !job->vm_id) { dev_err(adev->dev, "VM IB without ID\n"); return -EINVAL; } @@ -149,58 +156,68 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, return r; } - if (vm) { - /* do context switch */ - amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr, - ib->gds_base, ib->gds_size, - ib->gws_base, ib->gws_size, - ib->oa_base, ib->oa_size); + if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec) + patch_offset = amdgpu_ring_init_cond_exec(ring); - if (ring->funcs->emit_hdp_flush) - amdgpu_ring_emit_hdp_flush(ring); + if (vm) { + r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr, + job->gds_base, job->gds_size, + job->gws_base, job->gws_size, + job->oa_base, job->oa_size); + if (r) { + amdgpu_ring_undo(ring); + return r; + } } - old_ctx = ring->current_ctx; + if (ring->funcs->emit_hdp_flush) + amdgpu_ring_emit_hdp_flush(ring); + + /* always set cond_exec_polling to CONTINUE */ + *ring->cond_exe_cpu_addr = 1; + + skip_preamble = ring->current_ctx == ctx; + need_ctx_switch = ring->current_ctx != ctx; for (i = 0; i < num_ibs; ++i) { ib = &ibs[i]; - if (ib->ctx != ctx || ib->vm != vm) { - ring->current_ctx = old_ctx; - if (ib->vm_id) - amdgpu_vm_reset_id(adev, ib->vm_id); - amdgpu_ring_undo(ring); - return -EINVAL; - } - amdgpu_ring_emit_ib(ring, ib); - ring->current_ctx = ctx; + /* drop preamble IBs if we don't have a context switch */ + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble) + continue; + + amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, + need_ctx_switch); + need_ctx_switch = false; } - if (vm) { - if (ring->funcs->emit_hdp_invalidate) - amdgpu_ring_emit_hdp_invalidate(ring); - } + if (ring->funcs->emit_hdp_invalidate) + amdgpu_ring_emit_hdp_invalidate(ring); r = amdgpu_fence_emit(ring, &hwf); if (r) { dev_err(adev->dev, "failed to emit fence (%d)\n", r); - ring->current_ctx = old_ctx; - if (ib->vm_id) - amdgpu_vm_reset_id(adev, ib->vm_id); + if (job && job->vm_id) + amdgpu_vm_reset_id(adev, job->vm_id); amdgpu_ring_undo(ring); return r; } /* wrap the last IB with fence */ - if (ib->user) { - uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); - addr += ib->user->offset; - amdgpu_ring_emit_fence(ring, addr, ib->sequence, + if (job && job->uf_bo) { + uint64_t addr = amdgpu_bo_gpu_offset(job->uf_bo); + + addr += job->uf_offset; + amdgpu_ring_emit_fence(ring, addr, job->uf_sequence, AMDGPU_FENCE_FLAG_64BIT); } if (f) *f = fence_get(hwf); + if (patch_offset != ~0 && ring->funcs->patch_cond_exec) + amdgpu_ring_patch_cond_exec(ring, patch_offset); + + ring->current_ctx = ctx; amdgpu_ring_commit(ring); return 0; } @@ -315,7 +332,7 @@ static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) } -static struct drm_info_list amdgpu_debugfs_sa_list[] = { +static const struct drm_info_list amdgpu_debugfs_sa_list[] = { {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 762cfdb85147..835a3fa8d8df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -219,7 +219,6 @@ int amdgpu_irq_init(struct amdgpu_device *adev) if (r) { return r; } - adev->ddev->vblank_disable_allowed = true; /* enable msi */ adev->irq.msi_enabled = false; @@ -498,7 +497,7 @@ static int amdgpu_irqdomain_map(struct irq_domain *d, return 0; } -static struct irq_domain_ops amdgpu_hw_irqdomain_ops = { +static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { .map = amdgpu_irqdomain_map, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 9c9b19e2f353..f0dafa514fe4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -28,8 +28,25 @@ #include "amdgpu.h" #include "amdgpu_trace.h" +static void amdgpu_job_free_handler(struct work_struct *ws) +{ + struct amdgpu_job *job = container_of(ws, struct amdgpu_job, base.work_free_job); + amd_sched_job_put(&job->base); +} + +void amdgpu_job_timeout_func(struct work_struct *work) +{ + struct amdgpu_job *job = container_of(work, struct amdgpu_job, base.work_tdr.work); + DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n", + job->base.sched->name, + (uint32_t)atomic_read(&job->ring->fence_drv.last_seq), + job->ring->fence_drv.sync_seq); + + amd_sched_job_put(&job->base); +} + int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, - struct amdgpu_job **job) + struct amdgpu_job **job, struct amdgpu_vm *vm) { size_t size = sizeof(struct amdgpu_job); @@ -43,8 +60,10 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, return -ENOMEM; (*job)->adev = adev; + (*job)->vm = vm; (*job)->ibs = (void *)&(*job)[1]; (*job)->num_ibs = num_ibs; + INIT_WORK(&(*job)->base.work_free_job, amdgpu_job_free_handler); amdgpu_sync_create(&(*job)->sync); @@ -56,7 +75,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, { int r; - r = amdgpu_job_alloc(adev, 1, job); + r = amdgpu_job_alloc(adev, 1, job, NULL); if (r) return r; @@ -78,8 +97,16 @@ void amdgpu_job_free(struct amdgpu_job *job) amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, f); fence_put(job->fence); - amdgpu_bo_unref(&job->uf.bo); + amdgpu_bo_unref(&job->uf_bo); amdgpu_sync_free(&job->sync); + + if (!job->base.use_sched) + kfree(job); +} + +void amdgpu_job_free_func(struct kref *refcount) +{ + struct amdgpu_job *job = container_of(refcount, struct amdgpu_job, base.refcount); kfree(job); } @@ -87,16 +114,22 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, struct amd_sched_entity *entity, void *owner, struct fence **f) { + struct fence *fence; + int r; job->ring = ring; - job->base.sched = &ring->sched; - job->base.s_entity = entity; - job->base.s_fence = amd_sched_fence_create(job->base.s_entity, owner); - if (!job->base.s_fence) - return -ENOMEM; - *f = fence_get(&job->base.s_fence->base); + if (!f) + return -EINVAL; + + r = amd_sched_job_init(&job->base, &ring->sched, + entity, amdgpu_job_timeout_func, + amdgpu_job_free_func, owner, &fence); + if (r) + return r; job->owner = owner; + job->ctx = entity->fence_context; + *f = fence_get(fence); amd_sched_entity_push_job(&job->base); return 0; @@ -105,27 +138,19 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) { struct amdgpu_job *job = to_amdgpu_job(sched_job); - struct amdgpu_vm *vm = job->ibs->vm; + struct amdgpu_vm *vm = job->vm; struct fence *fence = amdgpu_sync_get_fence(&job->sync); - if (fence == NULL && vm && !job->ibs->vm_id) { + if (fence == NULL && vm && !job->vm_id) { struct amdgpu_ring *ring = job->ring; - unsigned i, vm_id; - uint64_t vm_pd_addr; int r; r = amdgpu_vm_grab_id(vm, ring, &job->sync, &job->base.s_fence->base, - &vm_id, &vm_pd_addr); + &job->vm_id, &job->vm_pd_addr); if (r) DRM_ERROR("Error getting VM ID (%d)\n", r); - else { - for (i = 0; i < job->num_ibs; ++i) { - job->ibs[i].vm_id = vm_id; - job->ibs[i].vm_pd_addr = vm_pd_addr; - } - } fence = amdgpu_sync_get_fence(&job->sync); } @@ -153,7 +178,7 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job) trace_amdgpu_sched_run_job(job); r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, - job->sync.last_vm_update, &fence); + job->sync.last_vm_update, job, &fence); if (r) { DRM_ERROR("Error scheduling IBs (%d)\n", r); goto err; @@ -165,7 +190,9 @@ err: return fence; } -struct amd_sched_backend_ops amdgpu_sched_ops = { +const struct amd_sched_backend_ops amdgpu_sched_ops = { .dependency = amdgpu_job_dependency, .run_job = amdgpu_job_run, + .begin_job = amd_sched_job_begin, + .finish_job = amd_sched_job_finish, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index b04337de65d1..40a23704a981 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -427,7 +427,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file } case AMDGPU_INFO_DEV_INFO: { struct drm_amdgpu_info_device dev_info = {}; - struct amdgpu_cu_info cu_info; dev_info.device_id = dev->pdev->device; dev_info.chip_rev = adev->rev_id; @@ -461,11 +460,11 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file AMDGPU_GPU_PAGE_SIZE; dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; - amdgpu_asic_get_cu_info(adev, &cu_info); - dev_info.cu_active_number = cu_info.number; - dev_info.cu_ao_mask = cu_info.ao_cu_mask; + dev_info.cu_active_number = adev->gfx.cu_info.number; + dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; dev_info.ce_ram_size = adev->gfx.ce_ram_size; - memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap)); + memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], + sizeof(adev->gfx.cu_info.bitmap)); dev_info.vram_type = adev->mc.vram_type; dev_info.vram_bit_width = adev->mc.vram_width; dev_info.vce_harvest_config = adev->vce.harvest_config; @@ -755,4 +754,4 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), }; -int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); +const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 81bd964d3dfc..6b1d7d306564 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -283,7 +283,7 @@ struct amdgpu_display_funcs { u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); /* pageflipping */ void (*page_flip)(struct amdgpu_device *adev, - int crtc_id, u64 crtc_base); + int crtc_id, u64 crtc_base, bool async); int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, u32 *vbl, u32 *position); /* display topology setup */ @@ -530,7 +530,7 @@ struct amdgpu_framebuffer { ((em) == ATOM_ENCODER_MODE_DP_MST)) /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */ -#define USE_REAL_VBLANKSTART (1 << 30) +#define USE_REAL_VBLANKSTART (1 << 30) #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) void amdgpu_link_encoder_connector(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index acc08018c6cc..bdb01d932548 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -71,7 +71,7 @@ static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) { int r; - r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); + r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) dev_err(bo->adev->dev, "%p reserve failed\n", bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index ff9597ce268c..589b36e8c5cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -362,16 +362,23 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; int ret; long level; + uint32_t i, mask = 0; + char sub_str[2]; - ret = kstrtol(buf, 0, &level); + for (i = 0; i < strlen(buf) - 1; i++) { + sub_str[0] = *(buf + i); + sub_str[1] = '\0'; + ret = kstrtol(sub_str, 0, &level); - if (ret) { - count = -EINVAL; - goto fail; + if (ret) { + count = -EINVAL; + goto fail; + } + mask |= 1 << level; } if (adev->pp_enabled) - amdgpu_dpm_force_clock_level(adev, PP_SCLK, level); + amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); fail: return count; } @@ -399,16 +406,23 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; int ret; long level; + uint32_t i, mask = 0; + char sub_str[2]; - ret = kstrtol(buf, 0, &level); + for (i = 0; i < strlen(buf) - 1; i++) { + sub_str[0] = *(buf + i); + sub_str[1] = '\0'; + ret = kstrtol(sub_str, 0, &level); - if (ret) { - count = -EINVAL; - goto fail; + if (ret) { + count = -EINVAL; + goto fail; + } + mask |= 1 << level; } if (adev->pp_enabled) - amdgpu_dpm_force_clock_level(adev, PP_MCLK, level); + amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); fail: return count; } @@ -436,16 +450,23 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; int ret; long level; + uint32_t i, mask = 0; + char sub_str[2]; - ret = kstrtol(buf, 0, &level); + for (i = 0; i < strlen(buf) - 1; i++) { + sub_str[0] = *(buf + i); + sub_str[1] = '\0'; + ret = kstrtol(sub_str, 0, &level); - if (ret) { - count = -EINVAL; - goto fail; + if (ret) { + count = -EINVAL; + goto fail; + } + mask |= 1 << level; } if (adev->pp_enabled) - amdgpu_dpm_force_clock_level(adev, PP_PCIE, level); + amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); fail: return count; } @@ -1212,7 +1233,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) return 0; } -static struct drm_info_list amdgpu_pm_info_list[] = { +static const struct drm_info_list amdgpu_pm_info_list[] = { {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL}, }; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index e9c6ae6ed2f7..6bd961fb43dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -99,6 +99,10 @@ static int amdgpu_pp_early_init(void *handle) #ifdef CONFIG_DRM_AMD_POWERPLAY switch (adev->asic_type) { + case CHIP_POLARIS11: + case CHIP_POLARIS10: + adev->pp_enabled = true; + break; case CHIP_TONGA: case CHIP_FIJI: adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true; @@ -299,16 +303,8 @@ static int amdgpu_pp_soft_reset(void *handle) return ret; } -static void amdgpu_pp_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - if (adev->powerplay.ip_funcs->print_status) - adev->powerplay.ip_funcs->print_status( - adev->powerplay.pp_handle); -} - const struct amd_ip_funcs amdgpu_pp_ip_funcs = { + .name = "amdgpu_powerplay", .early_init = amdgpu_pp_early_init, .late_init = amdgpu_pp_late_init, .sw_init = amdgpu_pp_sw_init, @@ -320,7 +316,6 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = { .is_idle = amdgpu_pp_is_idle, .wait_for_idle = amdgpu_pp_wait_for_idle, .soft_reset = amdgpu_pp_soft_reset, - .print_status = amdgpu_pp_print_status, .set_clockgating_state = amdgpu_pp_set_clockgating_state, .set_powergating_state = amdgpu_pp_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c index be6388f73ba2..7700dc22f243 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c @@ -57,9 +57,10 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) ttm_bo_kunmap(&bo->dma_buf_vmap); } -struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, - struct dma_buf_attachment *attach, - struct sg_table *sg) +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg) { struct reservation_object *resv = attach->dmabuf->resv; struct amdgpu_device *adev = dev->dev_private; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 972eed2ef787..3b02272db678 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -46,7 +46,8 @@ * wptr. The GPU then starts fetching commands and executes * them until the pointers are equal again. */ -static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring); +static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, + struct amdgpu_ring *ring); /** * amdgpu_ring_alloc - allocate space on the ring buffer @@ -215,18 +216,17 @@ int amdgpu_ring_restore(struct amdgpu_ring *ring, * * @adev: amdgpu_device pointer * @ring: amdgpu_ring structure holding ring information - * @ring_size: size of the ring + * @max_ndw: maximum number of dw for ring alloc * @nop: nop packet for this ring * * Initialize the driver information for the selected ring (all asics). * Returns 0 on success, error on failure. */ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned ring_size, u32 nop, u32 align_mask, + unsigned max_dw, u32 nop, u32 align_mask, struct amdgpu_irq_src *irq_src, unsigned irq_type, enum amdgpu_ring_type ring_type) { - u32 rb_bufsz; int r; if (ring->adev == NULL) { @@ -265,8 +265,17 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r); return r; } - ring->next_rptr_gpu_addr = adev->wb.gpu_addr + (ring->next_rptr_offs * 4); + ring->next_rptr_gpu_addr = adev->wb.gpu_addr + ring->next_rptr_offs * 4; ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs]; + + r = amdgpu_wb_get(adev, &ring->cond_exe_offs); + if (r) { + dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); + return r; + } + ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4); + ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs]; + spin_lock_init(&ring->fence_lock); r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); if (r) { @@ -274,10 +283,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, return r; } - /* Align ring size */ - rb_bufsz = order_base_2(ring_size / 8); - ring_size = (1 << (rb_bufsz + 1)) * 4; - ring->ring_size = ring_size; + ring->ring_size = roundup_pow_of_two(max_dw * 4 * + amdgpu_sched_hw_submission); ring->align_mask = align_mask; ring->nop = nop; ring->type = ring_type; @@ -310,8 +317,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, } } ring->ptr_mask = (ring->ring_size / 4) - 1; - ring->max_dw = DIV_ROUND_UP(ring->ring_size / 4, - amdgpu_sched_hw_submission); + ring->max_dw = max_dw; if (amdgpu_debugfs_ring_init(adev, ring)) { DRM_ERROR("Failed to register debugfs file for rings !\n"); @@ -363,9 +369,8 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data) struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; struct amdgpu_device *adev = dev->dev_private; - int roffset = *(int*)node->info_ent->data; + int roffset = (unsigned long)node->info_ent->data; struct amdgpu_ring *ring = (void *)(((uint8_t*)adev) + roffset); - uint32_t rptr, wptr, rptr_next; unsigned i; @@ -408,46 +413,37 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data) return 0; } -/* TODO: clean this up !*/ -static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]); -static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]); -static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]); -static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma.instance[0].ring); -static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma.instance[1].ring); -static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring); -static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]); -static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]); - -static struct drm_info_list amdgpu_debugfs_ring_info_list[] = { - {"amdgpu_ring_gfx", amdgpu_debugfs_ring_info, 0, &amdgpu_gfx_index}, - {"amdgpu_ring_cp1", amdgpu_debugfs_ring_info, 0, &cayman_cp1_index}, - {"amdgpu_ring_cp2", amdgpu_debugfs_ring_info, 0, &cayman_cp2_index}, - {"amdgpu_ring_dma1", amdgpu_debugfs_ring_info, 0, &amdgpu_dma1_index}, - {"amdgpu_ring_dma2", amdgpu_debugfs_ring_info, 0, &amdgpu_dma2_index}, - {"amdgpu_ring_uvd", amdgpu_debugfs_ring_info, 0, &r600_uvd_index}, - {"amdgpu_ring_vce1", amdgpu_debugfs_ring_info, 0, &si_vce1_index}, - {"amdgpu_ring_vce2", amdgpu_debugfs_ring_info, 0, &si_vce2_index}, -}; +static struct drm_info_list amdgpu_debugfs_ring_info_list[AMDGPU_MAX_RINGS]; +static char amdgpu_debugfs_ring_names[AMDGPU_MAX_RINGS][32]; #endif -static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) +static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, + struct amdgpu_ring *ring) { #if defined(CONFIG_DEBUG_FS) + unsigned offset = (uint8_t*)ring - (uint8_t*)adev; unsigned i; + struct drm_info_list *info; + char *name; + for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) { - struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i]; - int roffset = *(int*)amdgpu_debugfs_ring_info_list[i].data; - struct amdgpu_ring *other = (void *)(((uint8_t*)adev) + roffset); - unsigned r; - - if (other != ring) - continue; - - r = amdgpu_debugfs_add_files(adev, info, 1); - if (r) - return r; + info = &amdgpu_debugfs_ring_info_list[i]; + if (!info->data) + break; } + + if (i == ARRAY_SIZE(amdgpu_debugfs_ring_info_list)) + return -ENOSPC; + + name = &amdgpu_debugfs_ring_names[i][0]; + sprintf(name, "amdgpu_ring_%s", ring->name); + info->name = name; + info->show = amdgpu_debugfs_ring_info; + info->driver_features = 0; + info->data = (void*)(uintptr_t)offset; + + return amdgpu_debugfs_add_files(adev, info, 1); #endif return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index c48b4fce5e57..34a92808bbd4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -108,6 +108,29 @@ static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence) *keep = fence_get(fence); } +/** + * amdgpu_sync_add_later - add the fence to the hash + * + * @sync: sync object to add the fence to + * @f: fence to add + * + * Tries to add the fence to an existing hash entry. Returns true when an entry + * was found, false otherwise. + */ +static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct fence *f) +{ + struct amdgpu_sync_entry *e; + + hash_for_each_possible(sync->fences, e, node, f->context) { + if (unlikely(e->fence->context != f->context)) + continue; + + amdgpu_sync_keep_later(&e->fence, f); + return true; + } + return false; +} + /** * amdgpu_sync_fence - remember to sync to this fence * @@ -127,13 +150,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM) amdgpu_sync_keep_later(&sync->last_vm_update, f); - hash_for_each_possible(sync->fences, e, node, f->context) { - if (unlikely(e->fence->context != f->context)) - continue; - - amdgpu_sync_keep_later(&e->fence, f); + if (amdgpu_sync_add_later(sync, f)) return 0; - } e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL); if (!e) @@ -204,6 +222,81 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, return r; } +/** + * amdgpu_sync_is_idle - test if all fences are signaled + * + * @sync: the sync object + * + * Returns true if all fences in the sync object are signaled. + */ +bool amdgpu_sync_is_idle(struct amdgpu_sync *sync) +{ + struct amdgpu_sync_entry *e; + struct hlist_node *tmp; + int i; + + hash_for_each_safe(sync->fences, i, tmp, e, node) { + struct fence *f = e->fence; + + if (fence_is_signaled(f)) { + hash_del(&e->node); + fence_put(f); + kmem_cache_free(amdgpu_sync_slab, e); + continue; + } + + return false; + } + + return true; +} + +/** + * amdgpu_sync_cycle_fences - move fences from one sync object into another + * + * @dst: the destination sync object + * @src: the source sync object + * @fence: fence to add to source + * + * Remove all fences from source and put them into destination and add + * fence as new one into source. + */ +int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src, + struct fence *fence) +{ + struct amdgpu_sync_entry *e, *newone; + struct hlist_node *tmp; + int i; + + /* Allocate the new entry before moving the old ones */ + newone = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL); + if (!newone) + return -ENOMEM; + + hash_for_each_safe(src->fences, i, tmp, e, node) { + struct fence *f = e->fence; + + hash_del(&e->node); + if (fence_is_signaled(f)) { + fence_put(f); + kmem_cache_free(amdgpu_sync_slab, e); + continue; + } + + if (amdgpu_sync_add_later(dst, f)) { + kmem_cache_free(amdgpu_sync_slab, e); + continue; + } + + hash_add(dst->fences, &e->node, f->context); + } + + hash_add(src->fences, &newone->node, fence->context); + newone->fence = fence_get(fence); + + return 0; +} + struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) { struct amdgpu_sync_entry *e; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 11af4492b4be..3b9053af4762 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -911,6 +911,52 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, return flags; } +static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo) +{ + struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev); + unsigned i, j; + + for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) { + struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i]; + + for (j = 0; j < TTM_NUM_MEM_TYPES; ++j) + if (&tbo->lru == lru->lru[j]) + lru->lru[j] = tbo->lru.prev; + + if (&tbo->swap == lru->swap_lru) + lru->swap_lru = tbo->swap.prev; + } +} + +static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo) +{ + struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev); + unsigned log2_size = min(ilog2(tbo->num_pages), + AMDGPU_TTM_LRU_SIZE - 1); + + return &adev->mman.log2_size[log2_size]; +} + +static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo) +{ + struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo); + struct list_head *res = lru->lru[tbo->mem.mem_type]; + + lru->lru[tbo->mem.mem_type] = &tbo->lru; + + return res; +} + +static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo) +{ + struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo); + struct list_head *res = lru->swap_lru; + + lru->swap_lru = &tbo->swap; + + return res; +} + static struct ttm_bo_driver amdgpu_bo_driver = { .ttm_tt_create = &amdgpu_ttm_tt_create, .ttm_tt_populate = &amdgpu_ttm_tt_populate, @@ -924,10 +970,14 @@ static struct ttm_bo_driver amdgpu_bo_driver = { .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, .io_mem_free = &amdgpu_ttm_io_mem_free, + .lru_removal = &amdgpu_ttm_lru_removal, + .lru_tail = &amdgpu_ttm_lru_tail, + .swap_lru_tail = &amdgpu_ttm_swap_lru_tail, }; int amdgpu_ttm_init(struct amdgpu_device *adev) { + unsigned i, j; int r; r = amdgpu_ttm_global_init(adev); @@ -945,6 +995,15 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_ERROR("failed initializing buffer object driver(%d).\n", r); return r; } + + for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) { + struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i]; + + for (j = 0; j < TTM_NUM_MEM_TYPES; ++j) + lru->lru[j] = &adev->mman.bdev.man[j].lru; + lru->swap_lru = &adev->mman.bdev.glob->swap_lru; + } + adev->mman.initialized = true; r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, adev->mc.real_vram_size >> PAGE_SHIFT); @@ -1167,7 +1226,7 @@ static int amdgpu_mm_dump_table(struct seq_file *m, void *data) static int ttm_pl_vram = TTM_PL_VRAM; static int ttm_pl_tt = TTM_PL_TT; -static struct drm_info_list amdgpu_ttm_debugfs_list[] = { +static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram}, {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt}, {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, @@ -1218,6 +1277,8 @@ static const struct file_operations amdgpu_ttm_vram_fops = { .llseek = default_llseek }; +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS + static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { @@ -1265,6 +1326,8 @@ static const struct file_operations amdgpu_ttm_gtt_fops = { #endif +#endif + static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) @@ -1280,6 +1343,7 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) i_size_write(ent->d_inode, adev->mc.mc_vram_size); adev->mman.vram = ent; +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, adev, &amdgpu_ttm_gtt_fops); if (IS_ERR(ent)) @@ -1287,6 +1351,7 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) i_size_write(ent->d_inode, adev->mc.gtt_size); adev->mman.gtt = ent; +#endif count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); #ifdef CONFIG_SWIOTLB @@ -1308,7 +1373,10 @@ static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) debugfs_remove(adev->mman.vram); adev->mman.vram = NULL; +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS debugfs_remove(adev->mman.gtt); adev->mman.gtt = NULL; #endif + +#endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 871018c634e0..01abfc21b4a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -41,19 +41,23 @@ /* 1 second timeout */ #define UVD_IDLE_TIMEOUT_MS 1000 +/* Polaris10/11 firmware version */ +#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) /* Firmware Names */ #ifdef CONFIG_DRM_AMDGPU_CIK #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" -#define FIRMWARE_KABINI "radeon/kabini_uvd.bin" -#define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" -#define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" +#define FIRMWARE_KABINI "radeon/kabini_uvd.bin" +#define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" +#define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" #endif #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" +#define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" +#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" /** * amdgpu_uvd_cs_ctx - Command submission parser context @@ -85,6 +89,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); MODULE_FIRMWARE(FIRMWARE_STONEY); +MODULE_FIRMWARE(FIRMWARE_POLARIS10); +MODULE_FIRMWARE(FIRMWARE_POLARIS11); static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); static void amdgpu_uvd_idle_work_handler(struct work_struct *work); @@ -131,6 +137,12 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break; + case CHIP_POLARIS10: + fw_name = FIRMWARE_POLARIS10; + break; + case CHIP_POLARIS11: + fw_name = FIRMWARE_POLARIS11; + break; default: return -EINVAL; } @@ -151,6 +163,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) return r; } + /* Set the default UVD handles that the firmware can handle */ + adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; + hdr = (const struct common_firmware_header *)adev->uvd.fw->data; family_id = le32_to_cpu(hdr->ucode_version) & 0xff; version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; @@ -158,11 +173,28 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", version_major, version_minor, family_id); + /* + * Limit the number of UVD handles depending on microcode major + * and minor versions. The firmware version which has 40 UVD + * instances support is 1.80. So all subsequent versions should + * also have the same support. + */ + if ((version_major > 0x01) || + ((version_major == 0x01) && (version_minor >= 0x50))) + adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; + adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | (family_id << 8)); + if ((adev->asic_type == CHIP_POLARIS10 || + adev->asic_type == CHIP_POLARIS11) && + (adev->uvd.fw_version < FW_1_66_16)) + DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", + version_major, version_minor); + bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) - + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; + + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE + + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, @@ -205,7 +237,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) return r; } - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + for (i = 0; i < adev->uvd.max_handles; ++i) { atomic_set(&adev->uvd.handles[i], 0); adev->uvd.filp[i] = NULL; } @@ -251,7 +283,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) if (adev->uvd.vcpu_bo == NULL) return 0; - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + for (i = 0; i < adev->uvd.max_handles; ++i) if (atomic_read(&adev->uvd.handles[i])) break; @@ -308,7 +340,7 @@ void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) struct amdgpu_ring *ring = &adev->uvd.ring; int i, r; - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + for (i = 0; i < adev->uvd.max_handles; ++i) { uint32_t handle = atomic_read(&adev->uvd.handles[i]); if (handle != 0 && adev->uvd.filp[i] == filp) { struct fence *fence; @@ -390,7 +422,8 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) * * Peek into the decode message and calculate the necessary buffer sizes. */ -static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) +static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, + unsigned buf_sizes[]) { unsigned stream_type = msg[4]; unsigned width = msg[6]; @@ -412,7 +445,6 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) switch (stream_type) { case 0: /* H264 */ - case 7: /* H264 Perf */ switch(level) { case 30: num_dpb_buffer = 8100 / fs_in_mb; @@ -490,6 +522,54 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); break; + case 7: /* H264 Perf */ + switch(level) { + case 30: + num_dpb_buffer = 8100 / fs_in_mb; + break; + case 31: + num_dpb_buffer = 18000 / fs_in_mb; + break; + case 32: + num_dpb_buffer = 20480 / fs_in_mb; + break; + case 41: + num_dpb_buffer = 32768 / fs_in_mb; + break; + case 42: + num_dpb_buffer = 34816 / fs_in_mb; + break; + case 50: + num_dpb_buffer = 110400 / fs_in_mb; + break; + case 51: + num_dpb_buffer = 184320 / fs_in_mb; + break; + default: + num_dpb_buffer = 184320 / fs_in_mb; + break; + } + num_dpb_buffer++; + if (num_dpb_buffer > 17) + num_dpb_buffer = 17; + + /* reference picture buffer */ + min_dpb_size = image_size * num_dpb_buffer; + + if (adev->asic_type < CHIP_POLARIS10){ + /* macroblock context buffer */ + min_dpb_size += + width_in_mb * height_in_mb * num_dpb_buffer * 192; + + /* IT surface buffer */ + min_dpb_size += width_in_mb * height_in_mb * 32; + } else { + /* macroblock context buffer */ + min_ctx_size = + width_in_mb * height_in_mb * num_dpb_buffer * 192; + } + break; + case 16: /* H265 */ image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; image_size = ALIGN(image_size, 256); @@ -568,7 +648,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, amdgpu_bo_kunmap(bo); /* try to alloc a new handle */ - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + for (i = 0; i < adev->uvd.max_handles; ++i) { if (atomic_read(&adev->uvd.handles[i]) == handle) { DRM_ERROR("Handle 0x%x already in use!\n", handle); return -EINVAL; @@ -585,13 +665,13 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, case 1: /* it's a decode msg, calc buffer sizes */ - r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); + r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); amdgpu_bo_kunmap(bo); if (r) return r; /* validate the handle */ - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + for (i = 0; i < adev->uvd.max_handles; ++i) { if (atomic_read(&adev->uvd.handles[i]) == handle) { if (adev->uvd.filp[i] != ctx->parser->filp) { DRM_ERROR("UVD handle collision detected!\n"); @@ -606,7 +686,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, case 2: /* it's a destroy msg, free the handle */ - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + for (i = 0; i < adev->uvd.max_handles; ++i) atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); amdgpu_bo_kunmap(bo); return 0; @@ -886,7 +966,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, ib->length_dw = 16; if (direct) { - r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); job->fence = f; if (r) goto err_free; @@ -1018,7 +1098,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) fences = amdgpu_fence_count_emitted(&adev->uvd.ring); - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + for (i = 0; i < adev->uvd.max_handles; ++i) if (atomic_read(&adev->uvd.handles[i])) ++handles; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 481a64fa9b47..875626a2eccb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -41,15 +41,17 @@ /* Firmware Names */ #ifdef CONFIG_DRM_AMDGPU_CIK #define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin" -#define FIRMWARE_KABINI "radeon/kabini_vce.bin" -#define FIRMWARE_KAVERI "radeon/kaveri_vce.bin" -#define FIRMWARE_HAWAII "radeon/hawaii_vce.bin" +#define FIRMWARE_KABINI "radeon/kabini_vce.bin" +#define FIRMWARE_KAVERI "radeon/kaveri_vce.bin" +#define FIRMWARE_HAWAII "radeon/hawaii_vce.bin" #define FIRMWARE_MULLINS "radeon/mullins_vce.bin" #endif #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin" #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin" #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin" +#define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin" +#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin" #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); @@ -62,6 +64,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); MODULE_FIRMWARE(FIRMWARE_STONEY); +MODULE_FIRMWARE(FIRMWARE_POLARIS10); +MODULE_FIRMWARE(FIRMWARE_POLARIS11); static void amdgpu_vce_idle_work_handler(struct work_struct *work); @@ -113,6 +117,12 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break; + case CHIP_POLARIS10: + fw_name = FIRMWARE_POLARIS10; + break; + case CHIP_POLARIS11: + fw_name = FIRMWARE_POLARIS11; + break; default: return -EINVAL; @@ -426,7 +436,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, for (i = ib->length_dw; i < ib_size_dw; ++i) ib->ptr[i] = 0x0; - r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); job->fence = f; if (r) goto err; @@ -488,7 +498,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, ib->ptr[i] = 0x0; if (direct) { - r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); job->fence = f; if (r) goto err; @@ -752,7 +762,8 @@ out: * @ib: the IB to execute * */ -void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) +void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { amdgpu_ring_write(ring, VCE_CMD_IB); amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index ef99d2370182..f40cf761c66f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -34,7 +34,8 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, bool direct, struct fence **fence); void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); -void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); +void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch); void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags); int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index b6c011b83641..ea708cb94862 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -166,74 +166,109 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, { uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); struct amdgpu_device *adev = ring->adev; - struct amdgpu_vm_id *id = &vm->ids[ring->idx]; struct fence *updates = sync->last_vm_update; + struct amdgpu_vm_id *id; + unsigned i = ring->idx; int r; mutex_lock(&adev->vm_manager.lock); - /* check if the id is still valid */ - if (id->mgr_id) { - struct fence *flushed = id->flushed_updates; - bool is_later; - long owner; + /* Check if we can use a VMID already assigned to this VM */ + do { + struct fence *flushed; - if (!flushed) - is_later = true; - else if (!updates) - is_later = false; - else - is_later = fence_is_later(updates, flushed); + id = vm->ids[i++]; + if (i == AMDGPU_MAX_RINGS) + i = 0; - owner = atomic_long_read(&id->mgr_id->owner); - if (!is_later && owner == (long)id && - pd_addr == id->pd_gpu_addr) { + /* Check all the prerequisites to using this VMID */ + if (!id) + continue; + if (atomic64_read(&id->owner) != vm->client_id) + continue; + + if (pd_addr != id->pd_gpu_addr) + continue; + + if (id->last_user != ring && + (!id->last_flush || !fence_is_signaled(id->last_flush))) + continue; + + flushed = id->flushed_updates; + if (updates && (!flushed || fence_is_later(updates, flushed))) + continue; + + /* Good we can use this VMID */ + if (id->last_user == ring) { r = amdgpu_sync_fence(ring->adev, sync, - id->mgr_id->active); - if (r) { - mutex_unlock(&adev->vm_manager.lock); - return r; - } - - fence_put(id->mgr_id->active); - id->mgr_id->active = fence_get(fence); - - list_move_tail(&id->mgr_id->list, - &adev->vm_manager.ids_lru); - - *vm_id = id->mgr_id - adev->vm_manager.ids; - *vm_pd_addr = AMDGPU_VM_NO_FLUSH; - trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, - *vm_pd_addr); - - mutex_unlock(&adev->vm_manager.lock); - return 0; + id->first); + if (r) + goto error; } - } - id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru, - struct amdgpu_vm_manager_id, - list); + /* And remember this submission as user of the VMID */ + r = amdgpu_sync_fence(ring->adev, &id->active, fence); + if (r) + goto error; - r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active); - if (!r) { - fence_put(id->mgr_id->active); - id->mgr_id->active = fence_get(fence); + list_move_tail(&id->list, &adev->vm_manager.ids_lru); + vm->ids[ring->idx] = id; - fence_put(id->flushed_updates); - id->flushed_updates = fence_get(updates); - - id->pd_gpu_addr = pd_addr; - - list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru); - atomic_long_set(&id->mgr_id->owner, (long)id); - - *vm_id = id->mgr_id - adev->vm_manager.ids; - *vm_pd_addr = pd_addr; + *vm_id = id - adev->vm_manager.ids; + *vm_pd_addr = AMDGPU_VM_NO_FLUSH; trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); + + mutex_unlock(&adev->vm_manager.lock); + return 0; + + } while (i != ring->idx); + + id = list_first_entry(&adev->vm_manager.ids_lru, + struct amdgpu_vm_id, + list); + + if (!amdgpu_sync_is_idle(&id->active)) { + struct list_head *head = &adev->vm_manager.ids_lru; + struct amdgpu_vm_id *tmp; + + list_for_each_entry_safe(id, tmp, &adev->vm_manager.ids_lru, + list) { + if (amdgpu_sync_is_idle(&id->active)) { + list_move(&id->list, head); + head = &id->list; + } + } + id = list_first_entry(&adev->vm_manager.ids_lru, + struct amdgpu_vm_id, + list); } + r = amdgpu_sync_cycle_fences(sync, &id->active, fence); + if (r) + goto error; + + fence_put(id->first); + id->first = fence_get(fence); + + fence_put(id->last_flush); + id->last_flush = NULL; + + fence_put(id->flushed_updates); + id->flushed_updates = fence_get(updates); + + id->pd_gpu_addr = pd_addr; + + list_move_tail(&id->list, &adev->vm_manager.ids_lru); + id->last_user = ring; + atomic64_set(&id->owner, vm->client_id); + vm->ids[ring->idx] = id; + + *vm_id = id - adev->vm_manager.ids; + *vm_pd_addr = pd_addr; + trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); + +error: mutex_unlock(&adev->vm_manager.lock); return r; } @@ -247,43 +282,62 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, * * Emit a VM flush when it is necessary. */ -void amdgpu_vm_flush(struct amdgpu_ring *ring, - unsigned vm_id, uint64_t pd_addr, - uint32_t gds_base, uint32_t gds_size, - uint32_t gws_base, uint32_t gws_size, - uint32_t oa_base, uint32_t oa_size) +int amdgpu_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size) { struct amdgpu_device *adev = ring->adev; - struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; + struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; bool gds_switch_needed = ring->funcs->emit_gds_switch && ( - mgr_id->gds_base != gds_base || - mgr_id->gds_size != gds_size || - mgr_id->gws_base != gws_base || - mgr_id->gws_size != gws_size || - mgr_id->oa_base != oa_base || - mgr_id->oa_size != oa_size); + id->gds_base != gds_base || + id->gds_size != gds_size || + id->gws_base != gws_base || + id->gws_size != gws_size || + id->oa_base != oa_base || + id->oa_size != oa_size); + int r; if (ring->funcs->emit_pipeline_sync && ( - pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed)) + pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || + ring->type == AMDGPU_RING_TYPE_COMPUTE)) amdgpu_ring_emit_pipeline_sync(ring); - if (pd_addr != AMDGPU_VM_NO_FLUSH) { + if (ring->funcs->emit_vm_flush && + pd_addr != AMDGPU_VM_NO_FLUSH) { + struct fence *fence; + trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); + + mutex_lock(&adev->vm_manager.lock); + if ((id->pd_gpu_addr == pd_addr) && (id->last_user == ring)) { + r = amdgpu_fence_emit(ring, &fence); + if (r) { + mutex_unlock(&adev->vm_manager.lock); + return r; + } + fence_put(id->last_flush); + id->last_flush = fence; + } + mutex_unlock(&adev->vm_manager.lock); } if (gds_switch_needed) { - mgr_id->gds_base = gds_base; - mgr_id->gds_size = gds_size; - mgr_id->gws_base = gws_base; - mgr_id->gws_size = gws_size; - mgr_id->oa_base = oa_base; - mgr_id->oa_size = oa_size; + id->gds_base = gds_base; + id->gds_size = gds_size; + id->gws_base = gws_base; + id->gws_size = gws_size; + id->oa_base = oa_base; + id->oa_size = oa_size; amdgpu_ring_emit_gds_switch(ring, vm_id, gds_base, gds_size, gws_base, gws_size, oa_base, oa_size); } + + return 0; } /** @@ -296,14 +350,14 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring, */ void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) { - struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; + struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; - mgr_id->gds_base = 0; - mgr_id->gds_size = 0; - mgr_id->gws_base = 0; - mgr_id->gws_size = 0; - mgr_id->oa_base = 0; - mgr_id->oa_size = 0; + id->gds_base = 0; + id->gds_size = 0; + id->gws_base = 0; + id->gws_size = 0; + id->oa_base = 0; + id->oa_size = 0; } /** @@ -335,8 +389,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, * amdgpu_vm_update_pages - helper to call the right asic function * * @adev: amdgpu_device pointer - * @gtt: GART instance to use for mapping - * @gtt_flags: GTT hw access flags + * @src: address where to copy page table entries from + * @pages_addr: DMA addresses to use for mapping * @ib: indirect buffer to fill with commands * @pe: addr of the page entry * @addr: dst addr to write into pe @@ -348,8 +402,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, * to setup the page table using the DMA. */ static void amdgpu_vm_update_pages(struct amdgpu_device *adev, - struct amdgpu_gart *gtt, - uint32_t gtt_flags, + uint64_t src, + dma_addr_t *pages_addr, struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, @@ -357,12 +411,11 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev, { trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); - if ((gtt == &adev->gart) && (flags == gtt_flags)) { - uint64_t src = gtt->table_addr + (addr >> 12) * 8; + if (src) { + src += (addr >> 12) * 8; amdgpu_vm_copy_pte(adev, ib, pe, src, count); - } else if (gtt) { - dma_addr_t *pages_addr = gtt->pages_addr; + } else if (pages_addr) { amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, count, incr, flags); @@ -412,7 +465,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, if (r) goto error; - amdgpu_vm_update_pages(adev, NULL, 0, &job->ibs[0], addr, 0, entries, + amdgpu_vm_update_pages(adev, 0, NULL, &job->ibs[0], addr, 0, entries, 0, 0); amdgpu_ring_pad_ib(ring, &job->ibs[0]); @@ -522,7 +575,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, ((last_pt + incr * count) != pt)) { if (count) { - amdgpu_vm_update_pages(adev, NULL, 0, ib, + amdgpu_vm_update_pages(adev, 0, NULL, ib, last_pde, last_pt, count, incr, AMDGPU_PTE_VALID); @@ -537,7 +590,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, } if (count) - amdgpu_vm_update_pages(adev, NULL, 0, ib, last_pde, last_pt, + amdgpu_vm_update_pages(adev, 0, NULL, ib, last_pde, last_pt, count, incr, AMDGPU_PTE_VALID); if (ib->length_dw != 0) { @@ -570,8 +623,8 @@ error_free: * amdgpu_vm_frag_ptes - add fragment information to PTEs * * @adev: amdgpu_device pointer - * @gtt: GART instance to use for mapping - * @gtt_flags: GTT hw mapping flags + * @src: address where to copy page table entries from + * @pages_addr: DMA addresses to use for mapping * @ib: IB for the update * @pe_start: first PTE to handle * @pe_end: last PTE to handle @@ -579,8 +632,8 @@ error_free: * @flags: hw mapping flags */ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, - struct amdgpu_gart *gtt, - uint32_t gtt_flags, + uint64_t src, + dma_addr_t *pages_addr, struct amdgpu_ib *ib, uint64_t pe_start, uint64_t pe_end, uint64_t addr, uint32_t flags) @@ -618,10 +671,11 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, return; /* system pages are non continuously */ - if (gtt || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) { + if (src || pages_addr || !(flags & AMDGPU_PTE_VALID) || + (frag_start >= frag_end)) { count = (pe_end - pe_start) / 8; - amdgpu_vm_update_pages(adev, gtt, gtt_flags, ib, pe_start, + amdgpu_vm_update_pages(adev, src, pages_addr, ib, pe_start, addr, count, AMDGPU_GPU_PAGE_SIZE, flags); return; @@ -630,21 +684,21 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, /* handle the 4K area at the beginning */ if (pe_start != frag_start) { count = (frag_start - pe_start) / 8; - amdgpu_vm_update_pages(adev, NULL, 0, ib, pe_start, addr, + amdgpu_vm_update_pages(adev, 0, NULL, ib, pe_start, addr, count, AMDGPU_GPU_PAGE_SIZE, flags); addr += AMDGPU_GPU_PAGE_SIZE * count; } /* handle the area in the middle */ count = (frag_end - frag_start) / 8; - amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_start, addr, count, + amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_start, addr, count, AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); /* handle the 4K area at the end */ if (frag_end != pe_end) { addr += AMDGPU_GPU_PAGE_SIZE * count; count = (pe_end - frag_end) / 8; - amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_end, addr, + amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_end, addr, count, AMDGPU_GPU_PAGE_SIZE, flags); } } @@ -653,8 +707,8 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, * amdgpu_vm_update_ptes - make sure that page tables are valid * * @adev: amdgpu_device pointer - * @gtt: GART instance to use for mapping - * @gtt_flags: GTT hw mapping flags + * @src: address where to copy page table entries from + * @pages_addr: DMA addresses to use for mapping * @vm: requested vm * @start: start of GPU address range * @end: end of GPU address range @@ -664,8 +718,8 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, * Update the page tables in the range @start - @end. */ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, - struct amdgpu_gart *gtt, - uint32_t gtt_flags, + uint64_t src, + dma_addr_t *pages_addr, struct amdgpu_vm *vm, struct amdgpu_ib *ib, uint64_t start, uint64_t end, @@ -693,7 +747,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, if (last_pe_end != pe_start) { - amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, + amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start, last_pe_end, last_dst, flags); @@ -708,17 +762,16 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, dst += nptes * AMDGPU_GPU_PAGE_SIZE; } - amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, - last_pe_start, last_pe_end, - last_dst, flags); + amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start, + last_pe_end, last_dst, flags); } /** * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table * * @adev: amdgpu_device pointer - * @gtt: GART instance to use for mapping - * @gtt_flags: flags as they are used for GTT + * @src: address where to copy page table entries from + * @pages_addr: DMA addresses to use for mapping * @vm: requested vm * @start: start of mapped range * @last: last mapped entry @@ -730,8 +783,8 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, * Returns 0 for success, -EINVAL for failure. */ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, - struct amdgpu_gart *gtt, - uint32_t gtt_flags, + uint64_t src, + dma_addr_t *pages_addr, struct amdgpu_vm *vm, uint64_t start, uint64_t last, uint32_t flags, uint64_t addr, @@ -762,11 +815,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, /* padding, etc. */ ndw = 64; - if ((gtt == &adev->gart) && (flags == gtt_flags)) { + if (src) { /* only copy commands needed */ ndw += ncmds * 7; - } else if (gtt) { + } else if (pages_addr) { /* header for write data commands */ ndw += ncmds * 4; @@ -796,8 +849,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, if (r) goto error_free; - amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, last + 1, - addr, flags); + amdgpu_vm_update_ptes(adev, src, pages_addr, vm, ib, start, + last + 1, addr, flags); amdgpu_ring_pad_ib(ring, ib); WARN_ON(ib->length_dw > ndw); @@ -823,11 +876,12 @@ error_free: * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks * * @adev: amdgpu_device pointer - * @gtt: GART instance to use for mapping + * @gtt_flags: flags as they are used for GTT + * @pages_addr: DMA addresses to use for mapping * @vm: requested vm * @mapping: mapped range and flags to use for the update * @addr: addr to set the area to - * @gtt_flags: flags as they are used for GTT + * @flags: HW flags for the mapping * @fence: optional resulting fence * * Split the mapping into smaller chunks so that each update fits @@ -835,16 +889,16 @@ error_free: * Returns 0 for success, -EINVAL for failure. */ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, - struct amdgpu_gart *gtt, uint32_t gtt_flags, + dma_addr_t *pages_addr, struct amdgpu_vm *vm, struct amdgpu_bo_va_mapping *mapping, - uint64_t addr, struct fence **fence) + uint32_t flags, uint64_t addr, + struct fence **fence) { const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; - uint64_t start = mapping->it.start; - uint32_t flags = gtt_flags; + uint64_t src = 0, start = mapping->it.start; int r; /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here @@ -857,10 +911,15 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, trace_amdgpu_vm_bo_update(mapping); + if (pages_addr) { + if (flags == gtt_flags) + src = adev->gart.table_addr + (addr >> 12) * 8; + addr = 0; + } addr += mapping->offset; - if (!gtt || ((gtt == &adev->gart) && (flags == gtt_flags))) - return amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, + if (!pages_addr || src) + return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, start, mapping->it.last, flags, addr, fence); @@ -868,7 +927,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, uint64_t last; last = min((uint64_t)mapping->it.last, start + max_size - 1); - r = amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, + r = amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, start, last, flags, addr, fence); if (r) @@ -899,16 +958,20 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, { struct amdgpu_vm *vm = bo_va->vm; struct amdgpu_bo_va_mapping *mapping; - struct amdgpu_gart *gtt = NULL; - uint32_t flags; + dma_addr_t *pages_addr = NULL; + uint32_t gtt_flags, flags; uint64_t addr; int r; if (mem) { + struct ttm_dma_tt *ttm; + addr = (u64)mem->start << PAGE_SHIFT; switch (mem->mem_type) { case TTM_PL_TT: - gtt = &bo_va->bo->adev->gart; + ttm = container_of(bo_va->bo->tbo.ttm, struct + ttm_dma_tt, ttm); + pages_addr = ttm->dma_address; break; case TTM_PL_VRAM: @@ -923,6 +986,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, } flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); + gtt_flags = (adev == bo_va->bo->adev) ? flags : 0; spin_lock(&vm->status_lock); if (!list_empty(&bo_va->vm_status)) @@ -930,7 +994,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, spin_unlock(&vm->status_lock); list_for_each_entry(mapping, &bo_va->invalids, list) { - r = amdgpu_vm_bo_split_mapping(adev, gtt, flags, vm, mapping, addr, + r = amdgpu_vm_bo_split_mapping(adev, gtt_flags, pages_addr, vm, + mapping, flags, addr, &bo_va->last_pt_update); if (r) return r; @@ -976,8 +1041,8 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping, list); list_del(&mapping->list); - r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping, - 0, NULL); + r = amdgpu_vm_bo_split_mapping(adev, 0, NULL, vm, mapping, + 0, 0, NULL); kfree(mapping); if (r) return r; @@ -1320,11 +1385,10 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) struct amd_sched_rq *rq; int i, r; - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - vm->ids[i].mgr_id = NULL; - vm->ids[i].flushed_updates = NULL; - } + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) + vm->ids[i] = NULL; vm->va = RB_ROOT; + vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); spin_lock_init(&vm->status_lock); INIT_LIST_HEAD(&vm->invalidated); INIT_LIST_HEAD(&vm->cleared); @@ -1416,15 +1480,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) amdgpu_bo_unref(&vm->page_directory); fence_put(vm->page_directory_fence); - - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - struct amdgpu_vm_id *id = &vm->ids[i]; - - if (id->mgr_id) - atomic_long_cmpxchg(&id->mgr_id->owner, - (long)id, 0); - fence_put(id->flushed_updates); - } } /** @@ -1443,11 +1498,13 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) /* skip over VMID 0, since it is the system VM */ for (i = 1; i < adev->vm_manager.num_ids; ++i) { amdgpu_vm_reset_id(adev, i); + amdgpu_sync_create(&adev->vm_manager.ids[i].active); list_add_tail(&adev->vm_manager.ids[i].list, &adev->vm_manager.ids_lru); } atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); + atomic64_set(&adev->vm_manager.client_counter, 0); } /** @@ -1461,6 +1518,11 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) { unsigned i; - for (i = 0; i < AMDGPU_NUM_VM; ++i) - fence_put(adev->vm_manager.ids[i].active); + for (i = 0; i < AMDGPU_NUM_VM; ++i) { + struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; + + fence_put(adev->vm_manager.ids[i].first); + amdgpu_sync_free(&adev->vm_manager.ids[i].active); + fence_put(id->flushed_updates); + } } diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index fece8f45dc7a..49daf6d723e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -92,7 +92,7 @@ #define ATOM_WS_AND_MASK 0x45 #define ATOM_WS_FB_WINDOW 0x46 #define ATOM_WS_ATTRIBUTES 0x47 -#define ATOM_WS_REGPTR 0x48 +#define ATOM_WS_REGPTR 0x48 #define ATOM_IIO_NOP 0 #define ATOM_IIO_START 1 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c index 49aa35016653..49a39b1a0a96 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c @@ -461,13 +461,14 @@ union set_pixel_clock { PIXEL_CLOCK_PARAMETERS_V3 v3; PIXEL_CLOCK_PARAMETERS_V5 v5; PIXEL_CLOCK_PARAMETERS_V6 v6; + PIXEL_CLOCK_PARAMETERS_V7 v7; }; /* on DCE5, make sure the voltage is high enough to support the * required disp clk. */ void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, - u32 dispclk) + u32 dispclk) { u8 frev, crev; int index; @@ -510,6 +511,49 @@ void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); } +union set_dce_clock { + SET_DCE_CLOCK_PS_ALLOCATION_V1_1 v1_1; + SET_DCE_CLOCK_PS_ALLOCATION_V2_1 v2_1; +}; + +u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev, + u32 freq, u8 clk_type, u8 clk_src) +{ + u8 frev, crev; + int index; + union set_dce_clock args; + u32 ret_freq = 0; + + memset(&args, 0, sizeof(args)); + + index = GetIndexIntoMasterTable(COMMAND, SetDCEClock); + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, + &crev)) + return 0; + + switch (frev) { + case 2: + switch (crev) { + case 1: + args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */ + args.v2_1.asParam.ucDCEClkType = clk_type; + args.v2_1.asParam.ucDCEClkSrc = clk_src; + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10; + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return 0; + } + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return 0; + } + + return ret_freq; +} + static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id) { if (ENCODER_MODE_IS_DP(encoder_mode)) { @@ -523,18 +567,18 @@ static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id) } void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, - u32 crtc_id, - int pll_id, - u32 encoder_mode, - u32 encoder_id, - u32 clock, - u32 ref_div, - u32 fb_div, - u32 frac_fb_div, - u32 post_div, - int bpc, - bool ss_enabled, - struct amdgpu_atom_ss *ss) + u32 crtc_id, + int pll_id, + u32 encoder_mode, + u32 encoder_id, + u32 clock, + u32 ref_div, + u32 fb_div, + u32 frac_fb_div, + u32 post_div, + int bpc, + bool ss_enabled, + struct amdgpu_atom_ss *ss) { struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = dev->dev_private; @@ -652,6 +696,34 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, args.v6.ucEncoderMode = encoder_mode; args.v6.ucPpll = pll_id; break; + case 7: + args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */ + args.v7.ucMiscInfo = 0; + if ((encoder_mode == ATOM_ENCODER_MODE_DVI) && + (clock > 165000)) + args.v7.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN; + args.v7.ucCRTC = crtc_id; + if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { + switch (bpc) { + case 8: + default: + args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS; + break; + case 10: + args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4; + break; + case 12: + args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2; + break; + case 16: + args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1; + break; + } + } + args.v7.ucTransmitterID = encoder_id; + args.v7.ucEncoderMode = encoder_mode; + args.v7.ucPpll = pll_id; + break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return; diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h index c67083335b13..0eeda8e3bf5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h @@ -37,6 +37,8 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, struct drm_display_mode *mode); void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, u32 dispclk); +u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev, + u32 freq, u8 clk_type, u8 clk_src); void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 1cd6de575305..48b6bd671cda 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -567,6 +567,7 @@ union dig_encoder_control { DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; + DIG_ENCODER_CONTROL_PARAMETERS_V5 v5; }; void @@ -694,6 +695,47 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder, else args.v4.ucHPD_ID = hpd_id + 1; break; + case 5: + switch (action) { + case ATOM_ENCODER_CMD_SETUP_PANEL_MODE: + args.v5.asDPPanelModeParam.ucAction = action; + args.v5.asDPPanelModeParam.ucPanelMode = panel_mode; + args.v5.asDPPanelModeParam.ucDigId = dig->dig_encoder; + break; + case ATOM_ENCODER_CMD_STREAM_SETUP: + args.v5.asStreamParam.ucAction = action; + args.v5.asStreamParam.ucDigId = dig->dig_encoder; + args.v5.asStreamParam.ucDigMode = + amdgpu_atombios_encoder_get_encoder_mode(encoder); + if (ENCODER_MODE_IS_DP(args.v5.asStreamParam.ucDigMode)) + args.v5.asStreamParam.ucLaneNum = dp_lane_count; + else if (amdgpu_dig_monitor_is_duallink(encoder, + amdgpu_encoder->pixel_clock)) + args.v5.asStreamParam.ucLaneNum = 8; + else + args.v5.asStreamParam.ucLaneNum = 4; + args.v5.asStreamParam.ulPixelClock = + cpu_to_le32(amdgpu_encoder->pixel_clock / 10); + args.v5.asStreamParam.ucBitPerColor = + amdgpu_atombios_encoder_get_bpc(encoder); + args.v5.asStreamParam.ucLinkRateIn270Mhz = dp_clock / 27000; + break; + case ATOM_ENCODER_CMD_DP_LINK_TRAINING_START: + case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1: + case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2: + case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3: + case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4: + case ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE: + case ATOM_ENCODER_CMD_DP_VIDEO_OFF: + case ATOM_ENCODER_CMD_DP_VIDEO_ON: + args.v5.asCmdParam.ucAction = action; + args.v5.asCmdParam.ucDigId = dig->dig_encoder; + break; + default: + DRM_ERROR("Unsupported action 0x%x\n", action); + break; + } + break; default: DRM_ERROR("Unknown table version %d, %d\n", frev, crev); break; @@ -714,11 +756,12 @@ union dig_transmitter_control { DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 v6; }; void amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int action, - uint8_t lane_num, uint8_t lane_set) + uint8_t lane_num, uint8_t lane_set) { struct drm_device *dev = encoder->dev; struct amdgpu_device *adev = dev->dev_private; @@ -1070,6 +1113,54 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a args.v5.ucDigEncoderSel = 1 << dig_encoder; args.v5.ucDPLaneSet = lane_set; break; + case 6: + args.v6.ucAction = action; + if (is_dp) + args.v6.ulSymClock = cpu_to_le32(dp_clock / 10); + else + args.v6.ulSymClock = cpu_to_le32(amdgpu_encoder->pixel_clock / 10); + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + if (dig->linkb) + args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYB; + else + args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYA; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + if (dig->linkb) + args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYD; + else + args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYC; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + if (dig->linkb) + args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYF; + else + args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYE; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYG; + break; + } + if (is_dp) + args.v6.ucLaneNum = dp_lane_count; + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v6.ucLaneNum = 8; + else + args.v6.ucLaneNum = 4; + args.v6.ucConnObjId = connector_object_id; + if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) + args.v6.ucDPLaneSet = lane_set; + else + args.v6.ucDigMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + + if (hpd_id == AMDGPU_HPD_NONE) + args.v6.ucHPDSel = 0; + else + args.v6.ucHPDSel = hpd_id + 1; + args.v6.ucDigEncoderSel = 1 << dig_encoder; + break; default: DRM_ERROR("Unknown table version %d, %d\n", frev, crev); break; diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 1f9109d3348b..ea407db1fbcf 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -2549,19 +2549,17 @@ static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev, return 0; } -static u8 ci_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, - u32 sclk, u32 min_sclk_in_sr) +static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr) { u32 i; u32 tmp; - u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? - min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; + u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK); if (sclk < min) return 0; for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { - tmp = sclk / (1 << i); + tmp = sclk >> i; if (tmp >= min || i == 0) break; } @@ -3358,8 +3356,7 @@ static int ci_populate_single_graphic_level(struct amdgpu_device *adev, graphic_level->PowerThrottle = 0; if (pi->caps_sclk_ds) - graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(adev, - engine_clock, + graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock, CISLAND_MINIMUM_ENGINE_CLOCK); graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; @@ -6309,215 +6306,6 @@ static int ci_dpm_wait_for_idle(void *handle) return 0; } -static void ci_dpm_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "CIK DPM registers\n"); - dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n", - RREG32(mmBIOS_SCRATCH_4)); - dev_info(adev->dev, " MC_ARB_DRAM_TIMING=0x%08X\n", - RREG32(mmMC_ARB_DRAM_TIMING)); - dev_info(adev->dev, " MC_ARB_DRAM_TIMING2=0x%08X\n", - RREG32(mmMC_ARB_DRAM_TIMING2)); - dev_info(adev->dev, " MC_ARB_BURST_TIME=0x%08X\n", - RREG32(mmMC_ARB_BURST_TIME)); - dev_info(adev->dev, " MC_ARB_DRAM_TIMING_1=0x%08X\n", - RREG32(mmMC_ARB_DRAM_TIMING_1)); - dev_info(adev->dev, " MC_ARB_DRAM_TIMING2_1=0x%08X\n", - RREG32(mmMC_ARB_DRAM_TIMING2_1)); - dev_info(adev->dev, " MC_CG_CONFIG=0x%08X\n", - RREG32(mmMC_CG_CONFIG)); - dev_info(adev->dev, " MC_ARB_CG=0x%08X\n", - RREG32(mmMC_ARB_CG)); - dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", - RREG32_DIDT(ixDIDT_SQ_CTRL0)); - dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n", - RREG32_DIDT(ixDIDT_DB_CTRL0)); - dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n", - RREG32_DIDT(ixDIDT_TD_CTRL0)); - dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n", - RREG32_DIDT(ixDIDT_TCP_CTRL0)); - dev_info(adev->dev, " CG_THERMAL_INT=0x%08X\n", - RREG32_SMC(ixCG_THERMAL_INT)); - dev_info(adev->dev, " CG_THERMAL_CTRL=0x%08X\n", - RREG32_SMC(ixCG_THERMAL_CTRL)); - dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n", - RREG32_SMC(ixGENERAL_PWRMGT)); - dev_info(adev->dev, " MC_SEQ_CNTL_3=0x%08X\n", - RREG32(mmMC_SEQ_CNTL_3)); - dev_info(adev->dev, " LCAC_MC0_CNTL=0x%08X\n", - RREG32_SMC(ixLCAC_MC0_CNTL)); - dev_info(adev->dev, " LCAC_MC1_CNTL=0x%08X\n", - RREG32_SMC(ixLCAC_MC1_CNTL)); - dev_info(adev->dev, " LCAC_CPL_CNTL=0x%08X\n", - RREG32_SMC(ixLCAC_CPL_CNTL)); - dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", - RREG32_SMC(ixSCLK_PWRMGT_CNTL)); - dev_info(adev->dev, " BIF_LNCNT_RESET=0x%08X\n", - RREG32(mmBIF_LNCNT_RESET)); - dev_info(adev->dev, " FIRMWARE_FLAGS=0x%08X\n", - RREG32_SMC(ixFIRMWARE_FLAGS)); - dev_info(adev->dev, " CG_SPLL_FUNC_CNTL=0x%08X\n", - RREG32_SMC(ixCG_SPLL_FUNC_CNTL)); - dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n", - RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2)); - dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_3=0x%08X\n", - RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3)); - dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_4=0x%08X\n", - RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4)); - dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM=0x%08X\n", - RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM)); - dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n", - RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2)); - dev_info(adev->dev, " DLL_CNTL=0x%08X\n", - RREG32(mmDLL_CNTL)); - dev_info(adev->dev, " MCLK_PWRMGT_CNTL=0x%08X\n", - RREG32(mmMCLK_PWRMGT_CNTL)); - dev_info(adev->dev, " MPLL_AD_FUNC_CNTL=0x%08X\n", - RREG32(mmMPLL_AD_FUNC_CNTL)); - dev_info(adev->dev, " MPLL_DQ_FUNC_CNTL=0x%08X\n", - RREG32(mmMPLL_DQ_FUNC_CNTL)); - dev_info(adev->dev, " MPLL_FUNC_CNTL=0x%08X\n", - RREG32(mmMPLL_FUNC_CNTL)); - dev_info(adev->dev, " MPLL_FUNC_CNTL_1=0x%08X\n", - RREG32(mmMPLL_FUNC_CNTL_1)); - dev_info(adev->dev, " MPLL_FUNC_CNTL_2=0x%08X\n", - RREG32(mmMPLL_FUNC_CNTL_2)); - dev_info(adev->dev, " MPLL_SS1=0x%08X\n", - RREG32(mmMPLL_SS1)); - dev_info(adev->dev, " MPLL_SS2=0x%08X\n", - RREG32(mmMPLL_SS2)); - dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL=0x%08X\n", - RREG32_SMC(ixCG_DISPLAY_GAP_CNTL)); - dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL2=0x%08X\n", - RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2)); - dev_info(adev->dev, " CG_STATIC_SCREEN_PARAMETER=0x%08X\n", - RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_1=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_2=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_3=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_4=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_5=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_6=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_7=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7)); - dev_info(adev->dev, " RCU_UC_EVENTS=0x%08X\n", - RREG32_SMC(ixRCU_UC_EVENTS)); - dev_info(adev->dev, " DPM_TABLE_475=0x%08X\n", - RREG32_SMC(ixDPM_TABLE_475)); - dev_info(adev->dev, " MC_SEQ_RAS_TIMING_LP=0x%08X\n", - RREG32(mmMC_SEQ_RAS_TIMING_LP)); - dev_info(adev->dev, " MC_SEQ_RAS_TIMING=0x%08X\n", - RREG32(mmMC_SEQ_RAS_TIMING)); - dev_info(adev->dev, " MC_SEQ_CAS_TIMING_LP=0x%08X\n", - RREG32(mmMC_SEQ_CAS_TIMING_LP)); - dev_info(adev->dev, " MC_SEQ_CAS_TIMING=0x%08X\n", - RREG32(mmMC_SEQ_CAS_TIMING)); - dev_info(adev->dev, " MC_SEQ_DLL_STBY_LP=0x%08X\n", - RREG32(mmMC_SEQ_DLL_STBY_LP)); - dev_info(adev->dev, " MC_SEQ_DLL_STBY=0x%08X\n", - RREG32(mmMC_SEQ_DLL_STBY)); - dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0_LP=0x%08X\n", - RREG32(mmMC_SEQ_G5PDX_CMD0_LP)); - dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0=0x%08X\n", - RREG32(mmMC_SEQ_G5PDX_CMD0)); - dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1_LP=0x%08X\n", - RREG32(mmMC_SEQ_G5PDX_CMD1_LP)); - dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1=0x%08X\n", - RREG32(mmMC_SEQ_G5PDX_CMD1)); - dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL_LP=0x%08X\n", - RREG32(mmMC_SEQ_G5PDX_CTRL_LP)); - dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL=0x%08X\n", - RREG32(mmMC_SEQ_G5PDX_CTRL)); - dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n", - RREG32(mmMC_SEQ_PMG_DVS_CMD_LP)); - dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD=0x%08X\n", - RREG32(mmMC_SEQ_PMG_DVS_CMD)); - dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n", - RREG32(mmMC_SEQ_PMG_DVS_CTL_LP)); - dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL=0x%08X\n", - RREG32(mmMC_SEQ_PMG_DVS_CTL)); - dev_info(adev->dev, " MC_SEQ_MISC_TIMING_LP=0x%08X\n", - RREG32(mmMC_SEQ_MISC_TIMING_LP)); - dev_info(adev->dev, " MC_SEQ_MISC_TIMING=0x%08X\n", - RREG32(mmMC_SEQ_MISC_TIMING)); - dev_info(adev->dev, " MC_SEQ_MISC_TIMING2_LP=0x%08X\n", - RREG32(mmMC_SEQ_MISC_TIMING2_LP)); - dev_info(adev->dev, " MC_SEQ_MISC_TIMING2=0x%08X\n", - RREG32(mmMC_SEQ_MISC_TIMING2)); - dev_info(adev->dev, " MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n", - RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP)); - dev_info(adev->dev, " MC_PMG_CMD_EMRS=0x%08X\n", - RREG32(mmMC_PMG_CMD_EMRS)); - dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n", - RREG32(mmMC_SEQ_PMG_CMD_MRS_LP)); - dev_info(adev->dev, " MC_PMG_CMD_MRS=0x%08X\n", - RREG32(mmMC_PMG_CMD_MRS)); - dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n", - RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP)); - dev_info(adev->dev, " MC_PMG_CMD_MRS1=0x%08X\n", - RREG32(mmMC_PMG_CMD_MRS1)); - dev_info(adev->dev, " MC_SEQ_WR_CTL_D0_LP=0x%08X\n", - RREG32(mmMC_SEQ_WR_CTL_D0_LP)); - dev_info(adev->dev, " MC_SEQ_WR_CTL_D0=0x%08X\n", - RREG32(mmMC_SEQ_WR_CTL_D0)); - dev_info(adev->dev, " MC_SEQ_WR_CTL_D1_LP=0x%08X\n", - RREG32(mmMC_SEQ_WR_CTL_D1_LP)); - dev_info(adev->dev, " MC_SEQ_WR_CTL_D1=0x%08X\n", - RREG32(mmMC_SEQ_WR_CTL_D1)); - dev_info(adev->dev, " MC_SEQ_RD_CTL_D0_LP=0x%08X\n", - RREG32(mmMC_SEQ_RD_CTL_D0_LP)); - dev_info(adev->dev, " MC_SEQ_RD_CTL_D0=0x%08X\n", - RREG32(mmMC_SEQ_RD_CTL_D0)); - dev_info(adev->dev, " MC_SEQ_RD_CTL_D1_LP=0x%08X\n", - RREG32(mmMC_SEQ_RD_CTL_D1_LP)); - dev_info(adev->dev, " MC_SEQ_RD_CTL_D1=0x%08X\n", - RREG32(mmMC_SEQ_RD_CTL_D1)); - dev_info(adev->dev, " MC_SEQ_PMG_TIMING_LP=0x%08X\n", - RREG32(mmMC_SEQ_PMG_TIMING_LP)); - dev_info(adev->dev, " MC_SEQ_PMG_TIMING=0x%08X\n", - RREG32(mmMC_SEQ_PMG_TIMING)); - dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n", - RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP)); - dev_info(adev->dev, " MC_PMG_CMD_MRS2=0x%08X\n", - RREG32(mmMC_PMG_CMD_MRS2)); - dev_info(adev->dev, " MC_SEQ_WR_CTL_2_LP=0x%08X\n", - RREG32(mmMC_SEQ_WR_CTL_2_LP)); - dev_info(adev->dev, " MC_SEQ_WR_CTL_2=0x%08X\n", - RREG32(mmMC_SEQ_WR_CTL_2)); - dev_info(adev->dev, " PCIE_LC_SPEED_CNTL=0x%08X\n", - RREG32_PCIE(ixPCIE_LC_SPEED_CNTL)); - dev_info(adev->dev, " PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n", - RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL)); - dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n", - RREG32(mmSMC_IND_INDEX_0)); - dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n", - RREG32(mmSMC_IND_DATA_0)); - dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n", - RREG32(mmSMC_IND_ACCESS_CNTL)); - dev_info(adev->dev, " SMC_RESP_0=0x%08X\n", - RREG32(mmSMC_RESP_0)); - dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n", - RREG32(mmSMC_MESSAGE_0)); - dev_info(adev->dev, " SMC_SYSCON_RESET_CNTL=0x%08X\n", - RREG32_SMC(ixSMC_SYSCON_RESET_CNTL)); - dev_info(adev->dev, " SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n", - RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0)); - dev_info(adev->dev, " SMC_SYSCON_MISC_CNTL=0x%08X\n", - RREG32_SMC(ixSMC_SYSCON_MISC_CNTL)); - dev_info(adev->dev, " SMC_PC_C=0x%08X\n", - RREG32_SMC(ixSMC_PC_C)); -} - static int ci_dpm_soft_reset(void *handle) { return 0; @@ -6572,7 +6360,7 @@ static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev, } static int ci_dpm_process_interrupt(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, + struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { bool queue_thermal = false; @@ -6614,6 +6402,7 @@ static int ci_dpm_set_powergating_state(void *handle, } const struct amd_ip_funcs ci_dpm_ip_funcs = { + .name = "ci_dpm", .early_init = ci_dpm_early_init, .late_init = ci_dpm_late_init, .sw_init = ci_dpm_sw_init, @@ -6625,7 +6414,6 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = { .is_idle = ci_dpm_is_idle, .wait_for_idle = ci_dpm_wait_for_idle, .soft_reset = ci_dpm_soft_reset, - .print_status = ci_dpm_print_status, .set_clockgating_state = ci_dpm_set_clockgating_state, .set_powergating_state = ci_dpm_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index bddc9ba11495..07bc795a4ca9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -962,7 +962,7 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, return true; } -static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { +static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { {mmGRBM_STATUS, false}, {mmGB_ADDR_CONFIG, false}, {mmMC_ARB_RAMCFG, false}, @@ -2007,7 +2007,6 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = .get_xclk = &cik_get_xclk, .set_uvd_clocks = &cik_set_uvd_clocks, .set_vce_clocks = &cik_set_vce_clocks, - .get_cu_info = &gfx_v7_0_get_cu_info, /* these should be moved to their own ip modules */ .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, @@ -2214,11 +2213,6 @@ static int cik_common_wait_for_idle(void *handle) return 0; } -static void cik_common_print_status(void *handle) -{ - -} - static int cik_common_soft_reset(void *handle) { /* XXX hard reset?? */ @@ -2238,6 +2232,7 @@ static int cik_common_set_powergating_state(void *handle, } const struct amd_ip_funcs cik_common_ip_funcs = { + .name = "cik_common", .early_init = cik_common_early_init, .late_init = NULL, .sw_init = cik_common_sw_init, @@ -2249,7 +2244,6 @@ const struct amd_ip_funcs cik_common_ip_funcs = { .is_idle = cik_common_is_idle, .wait_for_idle = cik_common_wait_for_idle, .soft_reset = cik_common_soft_reset, - .print_status = cik_common_print_status, .set_clockgating_state = cik_common_set_clockgating_state, .set_powergating_state = cik_common_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 30c9b3beeef9..845c21b1b2ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -243,7 +243,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev, /* wptr/rptr are in bytes! */ u32 ring_index = adev->irq.ih.rptr >> 2; uint32_t dw[4]; - + dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); @@ -372,35 +372,6 @@ static int cik_ih_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void cik_ih_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "CIK IH registers\n"); - dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", - RREG32(mmSRBM_STATUS)); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", - RREG32(mmINTERRUPT_CNTL)); - dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", - RREG32(mmINTERRUPT_CNTL2)); - dev_info(adev->dev, " IH_CNTL=0x%08X\n", - RREG32(mmIH_CNTL)); - dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", - RREG32(mmIH_RB_CNTL)); - dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", - RREG32(mmIH_RB_BASE)); - dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", - RREG32(mmIH_RB_WPTR_ADDR_LO)); - dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", - RREG32(mmIH_RB_WPTR_ADDR_HI)); - dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", - RREG32(mmIH_RB_RPTR)); - dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", - RREG32(mmIH_RB_WPTR)); -} - static int cik_ih_soft_reset(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -412,8 +383,6 @@ static int cik_ih_soft_reset(void *handle) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; if (srbm_soft_reset) { - cik_ih_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -428,8 +397,6 @@ static int cik_ih_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - - cik_ih_print_status((void *)adev); } return 0; @@ -448,6 +415,7 @@ static int cik_ih_set_powergating_state(void *handle, } const struct amd_ip_funcs cik_ih_ip_funcs = { + .name = "cik_ih", .early_init = cik_ih_early_init, .late_init = NULL, .sw_init = cik_ih_sw_init, @@ -459,7 +427,6 @@ const struct amd_ip_funcs cik_ih_ip_funcs = { .is_idle = cik_ih_is_idle, .wait_for_idle = cik_ih_wait_for_idle, .soft_reset = cik_ih_soft_reset, - .print_status = cik_ih_print_status, .set_clockgating_state = cik_ih_set_clockgating_state, .set_powergating_state = cik_ih_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index d3ac3298fba8..518dca43b133 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -210,9 +210,10 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) * Schedule an IB in the DMA ring (CIK). */ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { - u32 extra_bits = ib->vm_id & 0xf; + u32 extra_bits = vm_id & 0xf; u32 next_rptr = ring->wptr + 5; while ((next_rptr & 7) != 4) @@ -643,7 +644,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring) ib.ptr[3] = 1; ib.ptr[4] = 0xDEADBEEF; ib.length_dw = 5; - r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); if (r) goto err1; @@ -976,7 +977,7 @@ static int cik_sdma_sw_init(void *handle) ring = &adev->sdma.instance[i].ring; ring->ring_obj = NULL; sprintf(ring->name, "sdma%d", i); - r = amdgpu_ring_init(adev, ring, 256 * 1024, + r = amdgpu_ring_init(adev, ring, 1024, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, &adev->sdma.trap_irq, (i == 0) ? @@ -1064,57 +1065,6 @@ static int cik_sdma_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void cik_sdma_print_status(void *handle) -{ - int i, j; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "CIK SDMA registers\n"); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - for (i = 0; i < adev->sdma.num_instances; i++) { - dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", - i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", - i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); - mutex_lock(&adev->srbm_mutex); - for (j = 0; j < 16; j++) { - cik_srbm_select(adev, 0, 0, 0, j); - dev_info(adev->dev, " VM %d:\n", j); - dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n", - RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n", - RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); - } - cik_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - } -} - static int cik_sdma_soft_reset(void *handle) { u32 srbm_soft_reset = 0; @@ -1137,8 +1087,6 @@ static int cik_sdma_soft_reset(void *handle) } if (srbm_soft_reset) { - cik_sdma_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -1153,8 +1101,6 @@ static int cik_sdma_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - - cik_sdma_print_status((void *)adev); } return 0; @@ -1278,6 +1224,7 @@ static int cik_sdma_set_powergating_state(void *handle, } const struct amd_ip_funcs cik_sdma_ip_funcs = { + .name = "cik_sdma", .early_init = cik_sdma_early_init, .late_init = NULL, .sw_init = cik_sdma_sw_init, @@ -1289,7 +1236,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { .is_idle = cik_sdma_is_idle, .wait_for_idle = cik_sdma_wait_for_idle, .soft_reset = cik_sdma_soft_reset, - .print_status = cik_sdma_print_status, .set_clockgating_state = cik_sdma_set_clockgating_state, .set_powergating_state = cik_sdma_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h index 60d4493206dd..c4f6f00d62bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/cikd.h +++ b/drivers/gpu/drm/amd/amdgpu/cikd.h @@ -190,8 +190,8 @@ # define MACRO_TILE_ASPECT(x) ((x) << 4) # define NUM_BANKS(x) ((x) << 6) -#define MSG_ENTER_RLC_SAFE_MODE 1 -#define MSG_EXIT_RLC_SAFE_MODE 0 +#define MSG_ENTER_RLC_SAFE_MODE 1 +#define MSG_EXIT_RLC_SAFE_MODE 0 /* * PM4 diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index e7ef2261ff4a..fa4449e126e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -2230,6 +2230,7 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) } const struct amd_ip_funcs cz_dpm_ip_funcs = { + .name = "cz_dpm", .early_init = cz_dpm_early_init, .late_init = cz_dpm_late_init, .sw_init = cz_dpm_sw_init, @@ -2241,7 +2242,6 @@ const struct amd_ip_funcs cz_dpm_ip_funcs = { .is_idle = NULL, .wait_for_idle = NULL, .soft_reset = NULL, - .print_status = NULL, .set_clockgating_state = cz_dpm_set_clockgating_state, .set_powergating_state = cz_dpm_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index c79638f8e732..863cb16f6126 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -222,7 +222,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev, /* wptr/rptr are in bytes! */ u32 ring_index = adev->irq.ih.rptr >> 2; uint32_t dw[4]; - + dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); @@ -351,35 +351,6 @@ static int cz_ih_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void cz_ih_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "CZ IH registers\n"); - dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", - RREG32(mmSRBM_STATUS)); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", - RREG32(mmINTERRUPT_CNTL)); - dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", - RREG32(mmINTERRUPT_CNTL2)); - dev_info(adev->dev, " IH_CNTL=0x%08X\n", - RREG32(mmIH_CNTL)); - dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", - RREG32(mmIH_RB_CNTL)); - dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", - RREG32(mmIH_RB_BASE)); - dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", - RREG32(mmIH_RB_WPTR_ADDR_LO)); - dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", - RREG32(mmIH_RB_WPTR_ADDR_HI)); - dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", - RREG32(mmIH_RB_RPTR)); - dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", - RREG32(mmIH_RB_WPTR)); -} - static int cz_ih_soft_reset(void *handle) { u32 srbm_soft_reset = 0; @@ -391,8 +362,6 @@ static int cz_ih_soft_reset(void *handle) SOFT_RESET_IH, 1); if (srbm_soft_reset) { - cz_ih_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -407,8 +376,6 @@ static int cz_ih_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - - cz_ih_print_status((void *)adev); } return 0; @@ -429,6 +396,7 @@ static int cz_ih_set_powergating_state(void *handle, } const struct amd_ip_funcs cz_ih_ip_funcs = { + .name = "cz_ih", .early_init = cz_ih_early_init, .late_init = NULL, .sw_init = cz_ih_sw_init, @@ -440,7 +408,6 @@ const struct amd_ip_funcs cz_ih_ip_funcs = { .is_idle = cz_ih_is_idle, .wait_for_idle = cz_ih_wait_for_idle, .soft_reset = cz_ih_soft_reset, - .print_status = cz_ih_print_status, .set_clockgating_state = cz_ih_set_clockgating_state, .set_powergating_state = cz_ih_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h index 924d355b4e2c..026342fcf0f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h +++ b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h @@ -77,7 +77,7 @@ struct cz_smu_private_data { uint8_t driver_buffer_length; uint8_t scratch_buffer_length; uint16_t toc_entry_used_count; - uint16_t toc_entry_initialize_index; + uint16_t toc_entry_initialize_index; uint16_t toc_entry_power_profiling_index; uint16_t toc_entry_aram; uint16_t toc_entry_ih_register_restore_task_index; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 6de2ce535e37..8227344d2ff6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -284,10 +284,16 @@ static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) * surface base address. */ static void dce_v10_0_page_flip(struct amdgpu_device *adev, - int crtc_id, u64 crtc_base) + int crtc_id, u64 crtc_base, bool async) { struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + u32 tmp; + /* flip at hsync for async, default is vsync */ + tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update the primary scanout address */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -2211,6 +2217,14 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, dce_v10_0_vga_enable(crtc, false); + /* Make sure surface address is updated at vertical blank rather than + * horizontal blank + */ + tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(fb_location)); WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, @@ -2261,13 +2275,6 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, (viewport_w << 16) | viewport_h); - /* pageflip setup */ - /* make sure flip is at vb rather than hb */ - tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, - GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); - WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); - /* set pageflip to happen only at start of vblank interval (front porch) */ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); @@ -2587,7 +2594,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, return -EINVAL; } - obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); + obj = drm_gem_object_lookup(file_priv, handle); if (!obj) { DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); return -ENOENT; @@ -2992,6 +2999,8 @@ static int dce_v10_0_sw_init(void *handle) adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; + adev->ddev->mode_config.async_page_flip = true; + adev->ddev->mode_config.max_width = 16384; adev->ddev->mode_config.max_height = 16384; @@ -3130,14 +3139,6 @@ static int dce_v10_0_wait_for_idle(void *handle) return 0; } -static void dce_v10_0_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "DCE 10.x registers\n"); - /* XXX todo */ -} - static int dce_v10_0_soft_reset(void *handle) { u32 srbm_soft_reset = 0, tmp; @@ -3147,8 +3148,6 @@ static int dce_v10_0_soft_reset(void *handle) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; if (srbm_soft_reset) { - dce_v10_0_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -3163,7 +3162,6 @@ static int dce_v10_0_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - dce_v10_0_print_status((void *)adev); } return 0; } @@ -3370,7 +3368,7 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, /* wakeup usersapce */ if (works->event) - drm_send_vblank_event(adev->ddev, crtc_id, works->event); + drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); spin_unlock_irqrestore(&adev->ddev->event_lock, flags); @@ -3501,6 +3499,7 @@ static int dce_v10_0_set_powergating_state(void *handle, } const struct amd_ip_funcs dce_v10_0_ip_funcs = { + .name = "dce_v10_0", .early_init = dce_v10_0_early_init, .late_init = NULL, .sw_init = dce_v10_0_sw_init, @@ -3512,7 +3511,6 @@ const struct amd_ip_funcs dce_v10_0_ip_funcs = { .is_idle = dce_v10_0_is_idle, .wait_for_idle = dce_v10_0_wait_for_idle, .soft_reset = dce_v10_0_soft_reset, - .print_status = dce_v10_0_print_status, .set_clockgating_state = dce_v10_0_set_clockgating_state, .set_powergating_state = dce_v10_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index e9ccc6b787f3..c11b6007af80 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -132,6 +132,22 @@ static const u32 stoney_golden_settings_a11[] = mmFBC_MISC, 0x1f311fff, 0x14302000, }; +static const u32 polaris11_golden_settings_a11[] = +{ + mmDCI_CLK_CNTL, 0x00000080, 0x00000000, + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, + mmFBC_DEBUG1, 0xffffffff, 0x00000008, + mmFBC_MISC, 0x9f313fff, 0x14300008, + mmHDMI_CONTROL, 0x313f031f, 0x00000011, +}; + +static const u32 polaris10_golden_settings_a11[] = +{ + mmDCI_CLK_CNTL, 0x00000080, 0x00000000, + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, + mmFBC_MISC, 0x9f313fff, 0x14300008, + mmHDMI_CONTROL, 0x313f031f, 0x00000011, +}; static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) { @@ -149,6 +165,16 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) stoney_golden_settings_a11, (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); break; + case CHIP_POLARIS11: + amdgpu_program_register_sequence(adev, + polaris11_golden_settings_a11, + (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); + break; + case CHIP_POLARIS10: + amdgpu_program_register_sequence(adev, + polaris10_golden_settings_a11, + (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); + break; default: break; } @@ -276,10 +302,17 @@ static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) * surface base address. */ static void dce_v11_0_page_flip(struct amdgpu_device *adev, - int crtc_id, u64 crtc_base) + int crtc_id, u64 crtc_base, bool async) { struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + u32 tmp; + /* flip at hsync for async, default is vsync */ + /* use UPDATE_IMMEDIATE_EN instead for async? */ + tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -565,35 +598,14 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), CRTC_CONTROL, CRTC_MASTER_EN); if (crtc_enabled) { -#if 0 - u32 frame_count; - int j; - +#if 1 save->crtc_enabled[i] = true; tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { - amdgpu_display_vblank_wait(adev, i); - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + /*it is correct only for RGB ; black is 0*/ + WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); - } - /* wait for the next frame */ - frame_count = amdgpu_display_vblank_get_counter(adev, i); - for (j = 0; j < adev->usec_timeout; j++) { - if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) - break; - udelay(1); - } - tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); - if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { - tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); - WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); - } - tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); - if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { - tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); - WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); } #else /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ @@ -614,54 +626,20 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, struct amdgpu_mode_mc_save *save) { - u32 tmp, frame_count; - int i, j; + u32 tmp; + int i; /* update crtc base addresses */ for (i = 0; i < adev->mode_info.num_crtc; i++) { WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], upper_32_bits(adev->mc.vram_start)); - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], - upper_32_bits(adev->mc.vram_start)); WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], (u32)adev->mc.vram_start); - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], - (u32)adev->mc.vram_start); if (save->crtc_enabled[i]) { - tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); - if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { - tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); - WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); - } - tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); - if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { - tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); - WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); - } - tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); - if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { - tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); - WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); - } - for (j = 0; j < adev->usec_timeout; j++) { - tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); - if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) - break; - udelay(1); - } tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); - /* wait for the next frame */ - frame_count = amdgpu_display_vblank_get_counter(adev, i); - for (j = 0; j < adev->usec_timeout; j++) { - if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) - break; - udelay(1); - } } } @@ -1624,6 +1602,7 @@ static const u32 pin_offsets[] = AUD4_REGISTER_OFFSET, AUD5_REGISTER_OFFSET, AUD6_REGISTER_OFFSET, + AUD7_REGISTER_OFFSET, }; static int dce_v11_0_audio_init(struct amdgpu_device *adev) @@ -1635,7 +1614,20 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev) adev->mode_info.audio.enabled = true; - adev->mode_info.audio.num_pins = 7; + switch (adev->asic_type) { + case CHIP_CARRIZO: + case CHIP_STONEY: + adev->mode_info.audio.num_pins = 7; + break; + case CHIP_POLARIS10: + adev->mode_info.audio.num_pins = 8; + break; + case CHIP_POLARIS11: + adev->mode_info.audio.num_pins = 6; + break; + default: + return -EINVAL; + } for (i = 0; i < adev->mode_info.audio.num_pins; i++) { adev->mode_info.audio.pin[i].channels = -1; @@ -2201,6 +2193,14 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, dce_v11_0_vga_enable(crtc, false); + /* Make sure surface address is updated at vertical blank rather than + * horizontal blank + */ + tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(fb_location)); WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, @@ -2251,13 +2251,6 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, (viewport_w << 16) | viewport_h); - /* pageflip setup */ - /* make sure flip is at vb rather than hb */ - tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, - GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); - WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); - /* set pageflip to happen only at start of vblank interval (front porch) */ WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); @@ -2427,6 +2420,40 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) u32 pll_in_use; int pll; + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { + struct amdgpu_encoder *amdgpu_encoder = + to_amdgpu_encoder(amdgpu_crtc->encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) + return ATOM_DP_DTO; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + if (dig->linkb) + return ATOM_COMBOPHY_PLL1; + else + return ATOM_COMBOPHY_PLL0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + if (dig->linkb) + return ATOM_COMBOPHY_PLL3; + else + return ATOM_COMBOPHY_PLL2; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + if (dig->linkb) + return ATOM_COMBOPHY_PLL5; + else + return ATOM_COMBOPHY_PLL4; + break; + default: + DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); + return ATOM_PPLL_INVALID; + } + } + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { if (adev->clock.dp_extclk) /* skip PPLL programming if using ext clock */ @@ -2578,7 +2605,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, return -EINVAL; } - obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); + obj = drm_gem_object_lookup(file_priv, handle); if (!obj) { DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); return -ENOENT; @@ -2782,7 +2809,17 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) case ATOM_PPLL2: /* disable the ppll */ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, - 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + break; + case ATOM_COMBOPHY_PLL0: + case ATOM_COMBOPHY_PLL1: + case ATOM_COMBOPHY_PLL2: + case ATOM_COMBOPHY_PLL3: + case ATOM_COMBOPHY_PLL4: + case ATOM_COMBOPHY_PLL5: + /* disable the ppll */ + amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, + 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; default: break; @@ -2800,11 +2837,28 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; if (!amdgpu_crtc->adjusted_clock) return -EINVAL; - amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { + struct amdgpu_encoder *amdgpu_encoder = + to_amdgpu_encoder(amdgpu_crtc->encoder); + int encoder_mode = + amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); + + /* SetPixelClock calculates the plls and ss values now */ + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, + amdgpu_crtc->pll_id, + encoder_mode, amdgpu_encoder->encoder_id, + adjusted_mode->clock, 0, 0, 0, 0, + amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); + } else { + amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); + } amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); @@ -2955,6 +3009,16 @@ static int dce_v11_0_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; break; + case CHIP_POLARIS10: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; + break; + case CHIP_POLARIS11: + adev->mode_info.num_crtc = 5; + adev->mode_info.num_hpd = 5; + adev->mode_info.num_dig = 5; + break; default: /* FIXME: not supported yet */ return -EINVAL; @@ -2987,6 +3051,8 @@ static int dce_v11_0_sw_init(void *handle) adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; + adev->ddev->mode_config.async_page_flip = true; + adev->ddev->mode_config.max_width = 16384; adev->ddev->mode_config.max_height = 16384; @@ -3057,7 +3123,15 @@ static int dce_v11_0_hw_init(void *handle) /* init dig PHYs, disp eng pll */ amdgpu_atombios_crtc_powergate_init(adev); amdgpu_atombios_encoder_init_dig(adev); - amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { + amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, + DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); + amdgpu_atombios_crtc_set_dce_clock(adev, 0, + DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); + } else { + amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); + } /* initialize hpd */ dce_v11_0_hpd_init(adev); @@ -3126,14 +3200,6 @@ static int dce_v11_0_wait_for_idle(void *handle) return 0; } -static void dce_v11_0_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "DCE 10.x registers\n"); - /* XXX todo */ -} - static int dce_v11_0_soft_reset(void *handle) { u32 srbm_soft_reset = 0, tmp; @@ -3143,8 +3209,6 @@ static int dce_v11_0_soft_reset(void *handle) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; if (srbm_soft_reset) { - dce_v11_0_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -3159,7 +3223,6 @@ static int dce_v11_0_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - dce_v11_0_print_status((void *)adev); } return 0; } @@ -3366,7 +3429,7 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, /* wakeup usersapce */ if(works->event) - drm_send_vblank_event(adev->ddev, crtc_id, works->event); + drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); spin_unlock_irqrestore(&adev->ddev->event_lock, flags); @@ -3497,6 +3560,7 @@ static int dce_v11_0_set_powergating_state(void *handle, } const struct amd_ip_funcs dce_v11_0_ip_funcs = { + .name = "dce_v11_0", .early_init = dce_v11_0_early_init, .late_init = NULL, .sw_init = dce_v11_0_sw_init, @@ -3508,7 +3572,6 @@ const struct amd_ip_funcs dce_v11_0_ip_funcs = { .is_idle = dce_v11_0_is_idle, .wait_for_idle = dce_v11_0_wait_for_idle, .soft_reset = dce_v11_0_soft_reset, - .print_status = dce_v11_0_print_status, .set_clockgating_state = dce_v11_0_set_clockgating_state, .set_powergating_state = dce_v11_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index e56b55d8c280..3fb65e41a6ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -233,10 +233,13 @@ static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev) * surface base address. */ static void dce_v8_0_page_flip(struct amdgpu_device *adev, - int crtc_id, u64 crtc_base) + int crtc_id, u64 crtc_base, bool async) { struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + /* flip at hsync for async, default is vsync */ + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? + GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); /* update the primary scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1999,7 +2002,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, uint32_t fb_format, fb_pitch_pixels; u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); u32 pipe_config; - u32 tmp, viewport_w, viewport_h; + u32 viewport_w, viewport_h; int r; bool bypass_lut = false; @@ -2135,6 +2138,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, dce_v8_0_vga_enable(crtc, false); + /* Make sure surface address is updated at vertical blank rather than + * horizontal blank + */ + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(fb_location)); WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, @@ -2182,12 +2190,6 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, (viewport_w << 16) | viewport_h); - /* pageflip setup */ - /* make sure flip is at vb rather than hb */ - tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); - tmp &= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK; - WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); - /* set pageflip to happen only at start of vblank interval (front porch) */ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); @@ -2499,7 +2501,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, return -EINVAL; } - obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); + obj = drm_gem_object_lookup(file_priv, handle); if (!obj) { DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); return -ENOENT; @@ -2902,6 +2904,8 @@ static int dce_v8_0_sw_init(void *handle) adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; + adev->ddev->mode_config.async_page_flip = true; + adev->ddev->mode_config.max_width = 16384; adev->ddev->mode_config.max_height = 16384; @@ -3038,14 +3042,6 @@ static int dce_v8_0_wait_for_idle(void *handle) return 0; } -static void dce_v8_0_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "DCE 8.x registers\n"); - /* XXX todo */ -} - static int dce_v8_0_soft_reset(void *handle) { u32 srbm_soft_reset = 0, tmp; @@ -3055,8 +3051,6 @@ static int dce_v8_0_soft_reset(void *handle) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; if (srbm_soft_reset) { - dce_v8_0_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -3071,7 +3065,6 @@ static int dce_v8_0_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - dce_v8_0_print_status((void *)adev); } return 0; } @@ -3379,7 +3372,7 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, /* wakeup usersapce */ if (works->event) - drm_send_vblank_event(adev->ddev, crtc_id, works->event); + drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); spin_unlock_irqrestore(&adev->ddev->event_lock, flags); @@ -3431,6 +3424,7 @@ static int dce_v8_0_set_powergating_state(void *handle, } const struct amd_ip_funcs dce_v8_0_ip_funcs = { + .name = "dce_v8_0", .early_init = dce_v8_0_early_init, .late_init = NULL, .sw_init = dce_v8_0_sw_init, @@ -3442,7 +3436,6 @@ const struct amd_ip_funcs dce_v8_0_ip_funcs = { .is_idle = dce_v8_0_is_idle, .wait_for_idle = dce_v8_0_wait_for_idle, .soft_reset = dce_v8_0_soft_reset, - .print_status = dce_v8_0_print_status, .set_clockgating_state = dce_v8_0_set_clockgating_state, .set_powergating_state = dce_v8_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c index 4b0e45a27129..245cabf06575 100644 --- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c @@ -143,6 +143,7 @@ static int fiji_dpm_set_powergating_state(void *handle, } const struct amd_ip_funcs fiji_dpm_ip_funcs = { + .name = "fiji_dpm", .early_init = fiji_dpm_early_init, .late_init = NULL, .sw_init = fiji_dpm_sw_init, @@ -154,7 +155,6 @@ const struct amd_ip_funcs fiji_dpm_ip_funcs = { .is_idle = NULL, .wait_for_idle = NULL, .soft_reset = NULL, - .print_status = NULL, .set_clockgating_state = fiji_dpm_set_clockgating_state, .set_powergating_state = fiji_dpm_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index bb8709066fd8..7f18a53ab53a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -53,7 +53,6 @@ static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); -int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *); MODULE_FIRMWARE("radeon/bonaire_pfp.bin"); MODULE_FIRMWARE("radeon/bonaire_me.bin"); @@ -882,6 +881,7 @@ static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev); static void gfx_v7_0_init_pg(struct amdgpu_device *adev); +static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); /* * Core functions @@ -1718,6 +1718,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) gfx_v7_0_tiling_mode_table_init(adev); gfx_v7_0_setup_rb(adev); + gfx_v7_0_get_cu_info(adev); /* set HW defaults for 3D engine */ WREG32(mmCP_MEQ_THRESHOLDS, @@ -2029,17 +2030,13 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, * on the gfx ring for execution by the GPU. */ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { - bool need_ctx_switch = ring->current_ctx != ib->ctx; u32 header, control = 0; u32 next_rptr = ring->wptr + 5; - /* drop the CE preamble IB for the same context */ - if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch) - return; - - if (need_ctx_switch) + if (ctx_switch) next_rptr += 2; next_rptr += 4; @@ -2050,7 +2047,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, amdgpu_ring_write(ring, next_rptr); /* insert SWITCH_BUFFER packet before first IB in the ring frame */ - if (need_ctx_switch) { + if (ctx_switch) { amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); amdgpu_ring_write(ring, 0); } @@ -2060,7 +2057,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, else header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); - control |= ib->length_dw | (ib->vm_id << 24); + control |= ib->length_dw | (vm_id << 24); amdgpu_ring_write(ring, header); amdgpu_ring_write(ring, @@ -2073,7 +2070,8 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, } static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { u32 header, control = 0; u32 next_rptr = ring->wptr + 5; @@ -2088,7 +2086,7 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); - control |= ib->length_dw | (ib->vm_id << 24); + control |= ib->length_dw | (vm_id << 24); amdgpu_ring_write(ring, header); amdgpu_ring_write(ring, @@ -2136,7 +2134,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring) ib.ptr[2] = 0xDEADBEEF; ib.length_dw = 3; - r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); if (r) goto err2; @@ -3053,6 +3051,19 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + uint32_t seq = ring->fence_drv.sync_seq; + uint64_t addr = ring->fence_drv.gpu_addr; + + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ + WAIT_REG_MEM_FUNCTION(3) | /* equal */ + WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, 0xffffffff); + amdgpu_ring_write(ring, 4); /* poll interval */ + if (usepfp) { /* synce CE with ME to prevent CE fetch CEIB before context switch done */ amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); @@ -3080,18 +3091,6 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; - uint64_t addr = ring->fence_drv.gpu_addr; - - amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); - amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ - WAIT_REG_MEM_FUNCTION(3) | /* equal */ - WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ - amdgpu_ring_write(ring, addr & 0xfffffffc); - amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); - amdgpu_ring_write(ring, seq); - amdgpu_ring_write(ring, 0xffffffff); - amdgpu_ring_write(ring, 4); /* poll interval */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | @@ -3869,18 +3868,13 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) { - uint32_t tmp, active_cu_number; - struct amdgpu_cu_info cu_info; + u32 tmp; - gfx_v7_0_get_cu_info(adev, &cu_info); - tmp = cu_info.ao_cu_mask; - active_cu_number = cu_info.number; - - WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp); + WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); tmp = RREG32(mmRLC_MAX_PG_CU); tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; - tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); + tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); WREG32(mmRLC_MAX_PG_CU, tmp); } @@ -4414,7 +4408,7 @@ static int gfx_v7_0_sw_init(void *handle) ring = &adev->gfx.gfx_ring[i]; ring->ring_obj = NULL; sprintf(ring->name, "gfx"); - r = amdgpu_ring_init(adev, ring, 1024 * 1024, + r = amdgpu_ring_init(adev, ring, 1024, PACKET3(PACKET3_NOP, 0x3FFF), 0xf, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, AMDGPU_RING_TYPE_GFX); @@ -4438,10 +4432,10 @@ static int gfx_v7_0_sw_init(void *handle) ring->me = 1; /* first MEC */ ring->pipe = i / 8; ring->queue = i % 8; - sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); + sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; /* type-2 packets are deprecated on MEC, use type-3 instead */ - r = amdgpu_ring_init(adev, ring, 1024 * 1024, + r = amdgpu_ring_init(adev, ring, 1024, PACKET3(PACKET3_NOP, 0x3FFF), 0xf, &adev->gfx.eop_irq, irq_type, AMDGPU_RING_TYPE_COMPUTE); @@ -4572,256 +4566,6 @@ static int gfx_v7_0_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void gfx_v7_0_print_status(void *handle) -{ - int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "GFX 7.x registers\n"); - dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", - RREG32(mmGRBM_STATUS)); - dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", - RREG32(mmGRBM_STATUS2)); - dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", - RREG32(mmGRBM_STATUS_SE0)); - dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", - RREG32(mmGRBM_STATUS_SE1)); - dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", - RREG32(mmGRBM_STATUS_SE2)); - dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", - RREG32(mmGRBM_STATUS_SE3)); - dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); - dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", - RREG32(mmCP_STALLED_STAT1)); - dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", - RREG32(mmCP_STALLED_STAT2)); - dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", - RREG32(mmCP_STALLED_STAT3)); - dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", - RREG32(mmCP_CPF_BUSY_STAT)); - dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", - RREG32(mmCP_CPF_STALLED_STAT1)); - dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); - dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); - dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", - RREG32(mmCP_CPC_STALLED_STAT1)); - dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); - - for (i = 0; i < 32; i++) { - dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", - i, RREG32(mmGB_TILE_MODE0 + (i * 4))); - } - for (i = 0; i < 16; i++) { - dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", - i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); - } - for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { - dev_info(adev->dev, " se: %d\n", i); - gfx_v7_0_select_se_sh(adev, i, 0xffffffff); - dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", - RREG32(mmPA_SC_RASTER_CONFIG)); - dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", - RREG32(mmPA_SC_RASTER_CONFIG_1)); - } - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); - - dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", - RREG32(mmGB_ADDR_CONFIG)); - dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", - RREG32(mmHDP_ADDR_CONFIG)); - dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", - RREG32(mmDMIF_ADDR_CALC)); - - dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", - RREG32(mmCP_MEQ_THRESHOLDS)); - dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", - RREG32(mmSX_DEBUG_1)); - dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", - RREG32(mmTA_CNTL_AUX)); - dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", - RREG32(mmSPI_CONFIG_CNTL)); - dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", - RREG32(mmSQ_CONFIG)); - dev_info(adev->dev, " DB_DEBUG=0x%08X\n", - RREG32(mmDB_DEBUG)); - dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", - RREG32(mmDB_DEBUG2)); - dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", - RREG32(mmDB_DEBUG3)); - dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", - RREG32(mmCB_HW_CONTROL)); - dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", - RREG32(mmSPI_CONFIG_CNTL_1)); - dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", - RREG32(mmPA_SC_FIFO_SIZE)); - dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", - RREG32(mmVGT_NUM_INSTANCES)); - dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", - RREG32(mmCP_PERFMON_CNTL)); - dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", - RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); - dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", - RREG32(mmVGT_CACHE_INVALIDATION)); - dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", - RREG32(mmVGT_GS_VERTEX_REUSE)); - dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", - RREG32(mmPA_SC_LINE_STIPPLE_STATE)); - dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", - RREG32(mmPA_CL_ENHANCE)); - dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", - RREG32(mmPA_SC_ENHANCE)); - - dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", - RREG32(mmCP_ME_CNTL)); - dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", - RREG32(mmCP_MAX_CONTEXT)); - dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", - RREG32(mmCP_ENDIAN_SWAP)); - dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", - RREG32(mmCP_DEVICE_ID)); - - dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", - RREG32(mmCP_SEM_WAIT_TIMER)); - if (adev->asic_type != CHIP_HAWAII) - dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", - RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL)); - - dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", - RREG32(mmCP_RB_WPTR_DELAY)); - dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", - RREG32(mmCP_RB_VMID)); - dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", - RREG32(mmCP_RB0_CNTL)); - dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", - RREG32(mmCP_RB0_WPTR)); - dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", - RREG32(mmCP_RB0_RPTR_ADDR)); - dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", - RREG32(mmCP_RB0_RPTR_ADDR_HI)); - dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", - RREG32(mmCP_RB0_CNTL)); - dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", - RREG32(mmCP_RB0_BASE)); - dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", - RREG32(mmCP_RB0_BASE_HI)); - dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", - RREG32(mmCP_MEC_CNTL)); - dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", - RREG32(mmCP_CPF_DEBUG)); - - dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", - RREG32(mmSCRATCH_ADDR)); - dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", - RREG32(mmSCRATCH_UMSK)); - - /* init the pipes */ - mutex_lock(&adev->srbm_mutex); - for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { - int me = (i < 4) ? 1 : 2; - int pipe = (i < 4) ? i : (i - 4); - int queue; - - dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe); - cik_srbm_select(adev, me, pipe, 0, 0); - dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n", - RREG32(mmCP_HPD_EOP_BASE_ADDR)); - dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n", - RREG32(mmCP_HPD_EOP_BASE_ADDR_HI)); - dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n", - RREG32(mmCP_HPD_EOP_VMID)); - dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n", - RREG32(mmCP_HPD_EOP_CONTROL)); - - for (queue = 0; queue < 8; queue++) { - cik_srbm_select(adev, me, pipe, queue, 0); - dev_info(adev->dev, " queue: %d\n", queue); - dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n", - RREG32(mmCP_PQ_WPTR_POLL_CNTL)); - dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", - RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); - dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n", - RREG32(mmCP_HQD_ACTIVE)); - dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n", - RREG32(mmCP_HQD_DEQUEUE_REQUEST)); - dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n", - RREG32(mmCP_HQD_PQ_RPTR)); - dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", - RREG32(mmCP_HQD_PQ_WPTR)); - dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n", - RREG32(mmCP_HQD_PQ_BASE)); - dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n", - RREG32(mmCP_HQD_PQ_BASE_HI)); - dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n", - RREG32(mmCP_HQD_PQ_CONTROL)); - dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n", - RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR)); - dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n", - RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)); - dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n", - RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR)); - dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n", - RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)); - dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", - RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); - dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", - RREG32(mmCP_HQD_PQ_WPTR)); - dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n", - RREG32(mmCP_HQD_VMID)); - dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n", - RREG32(mmCP_MQD_BASE_ADDR)); - dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n", - RREG32(mmCP_MQD_BASE_ADDR_HI)); - dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n", - RREG32(mmCP_MQD_CONTROL)); - } - } - cik_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - - dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", - RREG32(mmCP_INT_CNTL_RING0)); - dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", - RREG32(mmRLC_LB_CNTL)); - dev_info(adev->dev, " RLC_CNTL=0x%08X\n", - RREG32(mmRLC_CNTL)); - dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", - RREG32(mmRLC_CGCG_CGLS_CTRL)); - dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", - RREG32(mmRLC_LB_CNTR_INIT)); - dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", - RREG32(mmRLC_LB_CNTR_MAX)); - dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", - RREG32(mmRLC_LB_INIT_CU_MASK)); - dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", - RREG32(mmRLC_LB_PARAMS)); - dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", - RREG32(mmRLC_LB_CNTL)); - dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", - RREG32(mmRLC_MC_CNTL)); - dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", - RREG32(mmRLC_UCODE_CNTL)); - - if (adev->asic_type == CHIP_BONAIRE) - dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n", - RREG32(mmRLC_DRIVER_CPDMA_STATUS)); - - mutex_lock(&adev->srbm_mutex); - for (i = 0; i < 16; i++) { - cik_srbm_select(adev, 0, 0, 0, i); - dev_info(adev->dev, " VM %d:\n", i); - dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", - RREG32(mmSH_MEM_CONFIG)); - dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", - RREG32(mmSH_MEM_APE1_BASE)); - dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", - RREG32(mmSH_MEM_APE1_LIMIT)); - dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", - RREG32(mmSH_MEM_BASES)); - } - cik_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); -} - static int gfx_v7_0_soft_reset(void *handle) { u32 grbm_soft_reset = 0, srbm_soft_reset = 0; @@ -4855,7 +4599,6 @@ static int gfx_v7_0_soft_reset(void *handle) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; if (grbm_soft_reset || srbm_soft_reset) { - gfx_v7_0_print_status((void *)adev); /* disable CG/PG */ gfx_v7_0_fini_pg(adev); gfx_v7_0_update_cg(adev, false); @@ -4898,7 +4641,6 @@ static int gfx_v7_0_soft_reset(void *handle) } /* Wait a little for things to settle down */ udelay(50); - gfx_v7_0_print_status((void *)adev); } return 0; } @@ -5150,6 +4892,7 @@ static int gfx_v7_0_set_powergating_state(void *handle, } const struct amd_ip_funcs gfx_v7_0_ip_funcs = { + .name = "gfx_v7_0", .early_init = gfx_v7_0_early_init, .late_init = gfx_v7_0_late_init, .sw_init = gfx_v7_0_sw_init, @@ -5161,7 +4904,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { .is_idle = gfx_v7_0_is_idle, .wait_for_idle = gfx_v7_0_wait_for_idle, .soft_reset = gfx_v7_0_soft_reset, - .print_status = gfx_v7_0_print_status, .set_clockgating_state = gfx_v7_0_set_clockgating_state, .set_powergating_state = gfx_v7_0_set_powergating_state, }; @@ -5268,14 +5010,11 @@ static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) } -int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, - struct amdgpu_cu_info *cu_info) +static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) { int i, j, k, counter, active_cu_number = 0; u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; - - if (!adev || !cu_info) - return -EINVAL; + struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; memset(cu_info, 0, sizeof(*cu_info)); @@ -5306,6 +5045,4 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, cu_info->number = active_cu_number; cu_info->ao_cu_mask = ao_cu_mask; - - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h index c04bfbabfc88..e747aa935c88 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h @@ -32,6 +32,5 @@ void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev); void gfx_v7_0_rlc_stop(struct amdgpu_device *adev); uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev); void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num); -int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index f0c7b3596480..92647fbf5b8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -27,6 +27,7 @@ #include "vi.h" #include "vid.h" #include "amdgpu_ucode.h" +#include "amdgpu_atombios.h" #include "clearstate_vi.h" #include "gmc/gmc_8_2_d.h" @@ -51,6 +52,7 @@ #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 +#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) @@ -84,6 +86,8 @@ enum { BPM_REG_FGCG_MAX }; +#define RLC_FormatDirectRegListLength 14 + MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); @@ -117,6 +121,20 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); + static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = { {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, @@ -247,6 +265,64 @@ static const u32 tonga_mgcg_cgcg_init[] = mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, }; +static const u32 golden_settings_polaris11_a11[] = +{ + mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, + mmDB_DEBUG2, 0xf00fffff, 0x00000400, + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, + mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, + mmSQ_CONFIG, 0x07f80000, 0x07180000, + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, + mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, + mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, + mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, +}; + +static const u32 polaris11_golden_common_all[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, + mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002, + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, +}; + +static const u32 golden_settings_polaris10_a11[] = +{ + mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, + mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, + mmDB_DEBUG2, 0xf00fffff, 0x00000400, + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012, + mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a, + mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, + mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, + mmSQ_CONFIG, 0x07f80000, 0x07180000, + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, + mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, + mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, +}; + +static const u32 polaris10_golden_common_all[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, + mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, +}; + static const u32 fiji_golden_common_all[] = { mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, @@ -527,7 +603,7 @@ static const u32 stoney_golden_settings_a11[] = mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, - mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCC_CTRL, 0x00100000, 0xf31fff7f, mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010, @@ -558,6 +634,9 @@ static const u32 stoney_mgcg_cgcg_init[] = static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); +static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev); +static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev); +static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev); static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) { @@ -596,6 +675,22 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) tonga_golden_common_all, (const u32)ARRAY_SIZE(tonga_golden_common_all)); break; + case CHIP_POLARIS11: + amdgpu_program_register_sequence(adev, + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + amdgpu_program_register_sequence(adev, + polaris11_golden_common_all, + (const u32)ARRAY_SIZE(polaris11_golden_common_all)); + break; + case CHIP_POLARIS10: + amdgpu_program_register_sequence(adev, + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + amdgpu_program_register_sequence(adev, + polaris10_golden_common_all, + (const u32)ARRAY_SIZE(polaris10_golden_common_all)); + break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, @@ -706,7 +801,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring) ib.ptr[2] = 0xDEADBEEF; ib.length_dw = 3; - r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); if (r) goto err2; @@ -747,6 +842,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; const struct gfx_firmware_header_v1_0 *cp_hdr; + const struct rlc_firmware_header_v2_0 *rlc_hdr; + unsigned int *tmp = NULL, i; DRM_DEBUG("\n"); @@ -763,6 +860,12 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; + case CHIP_POLARIS11: + chip_name = "polaris11"; + break; + case CHIP_POLARIS10: + chip_name = "polaris10"; + break; case CHIP_STONEY: chip_name = "stoney"; break; @@ -808,9 +911,49 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (err) goto out; err = amdgpu_ucode_validate(adev->gfx.rlc_fw); - cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; - adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); - adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); + rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; + adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); + adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); + + adev->gfx.rlc.save_and_restore_offset = + le32_to_cpu(rlc_hdr->save_and_restore_offset); + adev->gfx.rlc.clear_state_descriptor_offset = + le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); + adev->gfx.rlc.avail_scratch_ram_locations = + le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); + adev->gfx.rlc.reg_restore_list_size = + le32_to_cpu(rlc_hdr->reg_restore_list_size); + adev->gfx.rlc.reg_list_format_start = + le32_to_cpu(rlc_hdr->reg_list_format_start); + adev->gfx.rlc.reg_list_format_separate_start = + le32_to_cpu(rlc_hdr->reg_list_format_separate_start); + adev->gfx.rlc.starting_offsets_start = + le32_to_cpu(rlc_hdr->starting_offsets_start); + adev->gfx.rlc.reg_list_format_size_bytes = + le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); + adev->gfx.rlc.reg_list_size_bytes = + le32_to_cpu(rlc_hdr->reg_list_size_bytes); + + adev->gfx.rlc.register_list_format = + kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + + adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); + + if (!adev->gfx.rlc.register_list_format) { + err = -ENOMEM; + goto out; + } + + tmp = (unsigned int *)((uintptr_t)rlc_hdr + + le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); + for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) + adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); + + adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; + + tmp = (unsigned int *)((uintptr_t)rlc_hdr + + le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); + for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) + adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); @@ -911,6 +1054,153 @@ out: return err; } +static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, + volatile u32 *buffer) +{ + u32 count = 0, i; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + if (adev->gfx.rlc.cs_data == NULL) + return; + if (buffer == NULL) + return; + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); + buffer[count++] = cpu_to_le32(0x80000000); + buffer[count++] = cpu_to_le32(0x80000000); + + for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) { + buffer[count++] = + cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); + buffer[count++] = cpu_to_le32(ext->reg_index - + PACKET3_SET_CONTEXT_REG_START); + for (i = 0; i < ext->reg_count; i++) + buffer[count++] = cpu_to_le32(ext->extent[i]); + } else { + return; + } + } + } + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - + PACKET3_SET_CONTEXT_REG_START); + switch (adev->asic_type) { + case CHIP_TONGA: + case CHIP_POLARIS10: + buffer[count++] = cpu_to_le32(0x16000012); + buffer[count++] = cpu_to_le32(0x0000002A); + break; + case CHIP_POLARIS11: + buffer[count++] = cpu_to_le32(0x16000012); + buffer[count++] = cpu_to_le32(0x00000000); + break; + case CHIP_FIJI: + buffer[count++] = cpu_to_le32(0x3a00161a); + buffer[count++] = cpu_to_le32(0x0000002e); + break; + case CHIP_TOPAZ: + case CHIP_CARRIZO: + buffer[count++] = cpu_to_le32(0x00000002); + buffer[count++] = cpu_to_le32(0x00000000); + break; + case CHIP_STONEY: + buffer[count++] = cpu_to_le32(0x00000000); + buffer[count++] = cpu_to_le32(0x00000000); + break; + default: + buffer[count++] = cpu_to_le32(0x00000000); + buffer[count++] = cpu_to_le32(0x00000000); + break; + } + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); + buffer[count++] = cpu_to_le32(0); +} + +static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev) +{ + int r; + + /* clear state block */ + if (adev->gfx.rlc.clear_state_obj) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); + amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + + amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); + adev->gfx.rlc.clear_state_obj = NULL; + } +} + +static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) +{ + volatile u32 *dst_ptr; + u32 dws; + const struct cs_section_def *cs_data; + int r; + + adev->gfx.rlc.cs_data = vi_cs_data; + + cs_data = adev->gfx.rlc.cs_data; + + if (cs_data) { + /* clear state block */ + adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev); + + if (adev->gfx.rlc.clear_state_obj == NULL) { + r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + NULL, NULL, + &adev->gfx.rlc.clear_state_obj); + if (r) { + dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); + gfx_v8_0_rlc_fini(adev); + return r; + } + } + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (unlikely(r != 0)) { + gfx_v8_0_rlc_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.clear_state_gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); + gfx_v8_0_rlc_fini(adev); + return r; + } + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); + if (r) { + dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); + gfx_v8_0_rlc_fini(adev); + return r; + } + /* set up the cs buffer */ + dst_ptr = adev->gfx.rlc.cs_ptr; + gfx_v8_0_get_csb_buffer(adev, dst_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + } + + return 0; +} + static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) { int r; @@ -1262,7 +1552,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); /* shedule the ib on the ring */ - r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); if (r) { DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); goto fail; @@ -1296,12 +1586,13 @@ fail: return r; } -static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) +static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) { u32 gb_addr_config; u32 mc_shared_chmap, mc_arb_ramcfg; u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; u32 tmp; + int ret; switch (adev->asic_type) { case CHIP_TOPAZ: @@ -1332,6 +1623,34 @@ static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.max_gs_threads = 32; adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_POLARIS11: + ret = amdgpu_atombios_get_gfx_info(adev); + if (ret) + return ret; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_POLARIS10: + ret = amdgpu_atombios_get_gfx_info(adev); + if (ret) + return ret; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; adev->gfx.config.sc_prim_fifo_size_backend = 0x100; adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; @@ -1520,6 +1839,8 @@ static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) break; } adev->gfx.config.gb_addr_config = gb_addr_config; + + return 0; } static int gfx_v8_0_sw_init(void *handle) @@ -1553,6 +1874,12 @@ static int gfx_v8_0_sw_init(void *handle) return r; } + r = gfx_v8_0_rlc_init(adev); + if (r) { + DRM_ERROR("Failed to init rlc BOs!\n"); + return r; + } + r = gfx_v8_0_mec_init(adev); if (r) { DRM_ERROR("Failed to init MEC BOs!\n"); @@ -1570,7 +1897,7 @@ static int gfx_v8_0_sw_init(void *handle) ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; } - r = amdgpu_ring_init(adev, ring, 1024 * 1024, + r = amdgpu_ring_init(adev, ring, 1024, PACKET3(PACKET3_NOP, 0x3FFF), 0xf, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, AMDGPU_RING_TYPE_GFX); @@ -1594,10 +1921,10 @@ static int gfx_v8_0_sw_init(void *handle) ring->me = 1; /* first MEC */ ring->pipe = i / 8; ring->queue = i % 8; - sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); + sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; /* type-2 packets are deprecated on MEC, use type-3 instead */ - r = amdgpu_ring_init(adev, ring, 1024 * 1024, + r = amdgpu_ring_init(adev, ring, 1024, PACKET3(PACKET3_NOP, 0x3FFF), 0xf, &adev->gfx.eop_irq, irq_type, AMDGPU_RING_TYPE_COMPUTE); @@ -1629,7 +1956,9 @@ static int gfx_v8_0_sw_init(void *handle) adev->gfx.ce_ram_size = 0x8000; - gfx_v8_0_gpu_early_init(adev); + r = gfx_v8_0_gpu_early_init(adev); + if (r) + return r; return 0; } @@ -1650,6 +1979,10 @@ static int gfx_v8_0_sw_fini(void *handle) gfx_v8_0_mec_fini(adev); + gfx_v8_0_rlc_fini(adev); + + kfree(adev->gfx.rlc.register_list_format); + return 0; } @@ -2218,6 +2551,410 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) if (reg_offset != 7) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); + break; + case CHIP_POLARIS11: + modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P4_16x16)); + modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + + mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + + mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) + WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); + + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) + if (reg_offset != 7) + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); + + break; + case CHIP_POLARIS10: + modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); + modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + + mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + + mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK)); + + mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + + mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) + WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); + + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) + if (reg_offset != 7) + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); + break; case CHIP_STONEY: modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -2695,6 +3432,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) gfx_v8_0_tiling_mode_table_init(adev); gfx_v8_0_setup_rb(adev); + gfx_v8_0_get_cu_info(adev); /* XXX SH_MEM regs */ /* where to put LDS, scratch, GPUVM in FSA64 space */ @@ -2788,6 +3526,188 @@ static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32(mmCP_INT_CNTL_RING0, tmp); } +static void gfx_v8_0_init_csb(struct amdgpu_device *adev) +{ + /* csib */ + WREG32(mmRLC_CSIB_ADDR_HI, + adev->gfx.rlc.clear_state_gpu_addr >> 32); + WREG32(mmRLC_CSIB_ADDR_LO, + adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); + WREG32(mmRLC_CSIB_LENGTH, + adev->gfx.rlc.clear_state_size); +} + +static void gfx_v8_0_parse_ind_reg_list(int *register_list_format, + int ind_offset, + int list_size, + int *unique_indices, + int *indices_count, + int max_indices, + int *ind_start_offsets, + int *offset_count, + int max_offset) +{ + int indices; + bool new_entry = true; + + for (; ind_offset < list_size; ind_offset++) { + + if (new_entry) { + new_entry = false; + ind_start_offsets[*offset_count] = ind_offset; + *offset_count = *offset_count + 1; + BUG_ON(*offset_count >= max_offset); + } + + if (register_list_format[ind_offset] == 0xFFFFFFFF) { + new_entry = true; + continue; + } + + ind_offset += 2; + + /* look for the matching indice */ + for (indices = 0; + indices < *indices_count; + indices++) { + if (unique_indices[indices] == + register_list_format[ind_offset]) + break; + } + + if (indices >= *indices_count) { + unique_indices[*indices_count] = + register_list_format[ind_offset]; + indices = *indices_count; + *indices_count = *indices_count + 1; + BUG_ON(*indices_count >= max_indices); + } + + register_list_format[ind_offset] = indices; + } +} + +static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) +{ + int i, temp, data; + int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0}; + int indices_count = 0; + int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int offset_count = 0; + + int list_size; + unsigned int *register_list_format = + kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); + if (register_list_format == NULL) + return -ENOMEM; + memcpy(register_list_format, adev->gfx.rlc.register_list_format, + adev->gfx.rlc.reg_list_format_size_bytes); + + gfx_v8_0_parse_ind_reg_list(register_list_format, + RLC_FormatDirectRegListLength, + adev->gfx.rlc.reg_list_format_size_bytes >> 2, + unique_indices, + &indices_count, + sizeof(unique_indices) / sizeof(int), + indirect_start_offsets, + &offset_count, + sizeof(indirect_start_offsets)/sizeof(int)); + + /* save and restore list */ + temp = RREG32(mmRLC_SRM_CNTL); + temp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; + WREG32(mmRLC_SRM_CNTL, temp); + + WREG32(mmRLC_SRM_ARAM_ADDR, 0); + for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) + WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); + + /* indirect list */ + WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); + for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) + WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]); + + list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; + list_size = list_size >> 1; + WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); + WREG32(mmRLC_GPM_SCRATCH_DATA, list_size); + + /* starting offsets starts */ + WREG32(mmRLC_GPM_SCRATCH_ADDR, + adev->gfx.rlc.starting_offsets_start); + for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++) + WREG32(mmRLC_GPM_SCRATCH_DATA, + indirect_start_offsets[i]); + + /* unique indices */ + temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; + data = mmRLC_SRM_INDEX_CNTL_DATA_0; + for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) { + amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false); + amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false); + } + kfree(register_list_format); + + return 0; +} + +static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev) +{ + uint32_t data; + + data = RREG32(mmRLC_SRM_CNTL); + data |= RLC_SRM_CNTL__SRM_ENABLE_MASK; + WREG32(mmRLC_SRM_CNTL, data); +} + +static void polaris11_init_power_gating(struct amdgpu_device *adev) +{ + uint32_t data; + + if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_GFX_SMG | + AMD_PG_SUPPORT_GFX_DMG)) { + data = RREG32(mmCP_RB_WPTR_POLL_CNTL); + data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; + data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); + WREG32(mmCP_RB_WPTR_POLL_CNTL, data); + + data = 0; + data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); + data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); + data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); + data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); + WREG32(mmRLC_PG_DELAY, data); + + data = RREG32(mmRLC_PG_DELAY_2); + data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; + data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); + WREG32(mmRLC_PG_DELAY_2, data); + + data = RREG32(mmRLC_AUTO_PG_CTRL); + data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; + data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); + WREG32(mmRLC_AUTO_PG_CTRL, data); + } +} + +static void gfx_v8_0_init_pg(struct amdgpu_device *adev) +{ + if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_GFX_SMG | + AMD_PG_SUPPORT_GFX_DMG | + AMD_PG_SUPPORT_CP | + AMD_PG_SUPPORT_GDS | + AMD_PG_SUPPORT_RLC_SMU_HS)) { + gfx_v8_0_init_csb(adev); + gfx_v8_0_init_save_restore_list(adev); + gfx_v8_0_enable_save_restore_machine(adev); + + if (adev->asic_type == CHIP_POLARIS11) + polaris11_init_power_gating(adev); + } +} + void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) { u32 tmp = RREG32(mmRLC_CNTL); @@ -2858,12 +3778,17 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) /* disable CG */ WREG32(mmRLC_CGCG_CGLS_CTRL, 0); + if (adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10) + WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0); /* disable PG */ WREG32(mmRLC_PG_CNTL, 0); gfx_v8_0_rlc_reset(adev); + gfx_v8_0_init_pg(adev); + if (!adev->pp_enabled) { if (!adev->firmware.smu_load) { /* legacy rlc firmware loading */ @@ -3035,9 +3960,14 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TONGA: + case CHIP_POLARIS10: amdgpu_ring_write(ring, 0x16000012); amdgpu_ring_write(ring, 0x0000002A); break; + case CHIP_POLARIS11: + amdgpu_ring_write(ring, 0x16000012); + amdgpu_ring_write(ring, 0x00000000); + break; case CHIP_FIJI: amdgpu_ring_write(ring, 0x3a00161a); amdgpu_ring_write(ring, 0x0000002e); @@ -3121,6 +4051,8 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) if (ring->use_doorbell) { tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_OFFSET, ring->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_HIT, 0); tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 1); } else { @@ -3679,7 +4611,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) if (use_doorbell) { if ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_FIJI) || - (adev->asic_type == CHIP_STONEY)) { + (adev->asic_type == CHIP_STONEY) || + (adev->asic_type == CHIP_POLARIS11) || + (adev->asic_type == CHIP_POLARIS10)) { WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2); WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, @@ -3713,7 +4647,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); mqd->cp_hqd_persistent_state = tmp; - if (adev->asic_type == CHIP_STONEY) { + if (adev->asic_type == CHIP_STONEY || + adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10) { tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL); tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1); WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp); @@ -3845,6 +4781,9 @@ static int gfx_v8_0_hw_fini(void *handle) gfx_v8_0_rlc_stop(adev); gfx_v8_0_cp_compute_fini(adev); + amdgpu_set_powergating_state(adev, + AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE); + return 0; } @@ -3889,185 +4828,6 @@ static int gfx_v8_0_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void gfx_v8_0_print_status(void *handle) -{ - int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "GFX 8.x registers\n"); - dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", - RREG32(mmGRBM_STATUS)); - dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", - RREG32(mmGRBM_STATUS2)); - dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", - RREG32(mmGRBM_STATUS_SE0)); - dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", - RREG32(mmGRBM_STATUS_SE1)); - dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", - RREG32(mmGRBM_STATUS_SE2)); - dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", - RREG32(mmGRBM_STATUS_SE3)); - dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); - dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", - RREG32(mmCP_STALLED_STAT1)); - dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", - RREG32(mmCP_STALLED_STAT2)); - dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", - RREG32(mmCP_STALLED_STAT3)); - dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", - RREG32(mmCP_CPF_BUSY_STAT)); - dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", - RREG32(mmCP_CPF_STALLED_STAT1)); - dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); - dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); - dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", - RREG32(mmCP_CPC_STALLED_STAT1)); - dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); - - for (i = 0; i < 32; i++) { - dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", - i, RREG32(mmGB_TILE_MODE0 + (i * 4))); - } - for (i = 0; i < 16; i++) { - dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", - i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); - } - for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { - dev_info(adev->dev, " se: %d\n", i); - gfx_v8_0_select_se_sh(adev, i, 0xffffffff); - dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", - RREG32(mmPA_SC_RASTER_CONFIG)); - dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", - RREG32(mmPA_SC_RASTER_CONFIG_1)); - } - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); - - dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", - RREG32(mmGB_ADDR_CONFIG)); - dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", - RREG32(mmHDP_ADDR_CONFIG)); - dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", - RREG32(mmDMIF_ADDR_CALC)); - - dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", - RREG32(mmCP_MEQ_THRESHOLDS)); - dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", - RREG32(mmSX_DEBUG_1)); - dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", - RREG32(mmTA_CNTL_AUX)); - dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", - RREG32(mmSPI_CONFIG_CNTL)); - dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", - RREG32(mmSQ_CONFIG)); - dev_info(adev->dev, " DB_DEBUG=0x%08X\n", - RREG32(mmDB_DEBUG)); - dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", - RREG32(mmDB_DEBUG2)); - dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", - RREG32(mmDB_DEBUG3)); - dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", - RREG32(mmCB_HW_CONTROL)); - dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", - RREG32(mmSPI_CONFIG_CNTL_1)); - dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", - RREG32(mmPA_SC_FIFO_SIZE)); - dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", - RREG32(mmVGT_NUM_INSTANCES)); - dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", - RREG32(mmCP_PERFMON_CNTL)); - dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", - RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); - dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", - RREG32(mmVGT_CACHE_INVALIDATION)); - dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", - RREG32(mmVGT_GS_VERTEX_REUSE)); - dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", - RREG32(mmPA_SC_LINE_STIPPLE_STATE)); - dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", - RREG32(mmPA_CL_ENHANCE)); - dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", - RREG32(mmPA_SC_ENHANCE)); - - dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", - RREG32(mmCP_ME_CNTL)); - dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", - RREG32(mmCP_MAX_CONTEXT)); - dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", - RREG32(mmCP_ENDIAN_SWAP)); - dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", - RREG32(mmCP_DEVICE_ID)); - - dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", - RREG32(mmCP_SEM_WAIT_TIMER)); - - dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", - RREG32(mmCP_RB_WPTR_DELAY)); - dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", - RREG32(mmCP_RB_VMID)); - dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", - RREG32(mmCP_RB0_CNTL)); - dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", - RREG32(mmCP_RB0_WPTR)); - dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", - RREG32(mmCP_RB0_RPTR_ADDR)); - dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", - RREG32(mmCP_RB0_RPTR_ADDR_HI)); - dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", - RREG32(mmCP_RB0_CNTL)); - dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", - RREG32(mmCP_RB0_BASE)); - dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", - RREG32(mmCP_RB0_BASE_HI)); - dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", - RREG32(mmCP_MEC_CNTL)); - dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", - RREG32(mmCP_CPF_DEBUG)); - - dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", - RREG32(mmSCRATCH_ADDR)); - dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", - RREG32(mmSCRATCH_UMSK)); - - dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", - RREG32(mmCP_INT_CNTL_RING0)); - dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", - RREG32(mmRLC_LB_CNTL)); - dev_info(adev->dev, " RLC_CNTL=0x%08X\n", - RREG32(mmRLC_CNTL)); - dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", - RREG32(mmRLC_CGCG_CGLS_CTRL)); - dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", - RREG32(mmRLC_LB_CNTR_INIT)); - dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", - RREG32(mmRLC_LB_CNTR_MAX)); - dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", - RREG32(mmRLC_LB_INIT_CU_MASK)); - dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", - RREG32(mmRLC_LB_PARAMS)); - dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", - RREG32(mmRLC_LB_CNTL)); - dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", - RREG32(mmRLC_MC_CNTL)); - dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", - RREG32(mmRLC_UCODE_CNTL)); - - mutex_lock(&adev->srbm_mutex); - for (i = 0; i < 16; i++) { - vi_srbm_select(adev, 0, 0, 0, i); - dev_info(adev->dev, " VM %d:\n", i); - dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", - RREG32(mmSH_MEM_CONFIG)); - dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", - RREG32(mmSH_MEM_APE1_BASE)); - dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", - RREG32(mmSH_MEM_APE1_LIMIT)); - dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", - RREG32(mmSH_MEM_BASES)); - } - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); -} - static int gfx_v8_0_soft_reset(void *handle) { u32 grbm_soft_reset = 0, srbm_soft_reset = 0; @@ -4108,7 +4868,6 @@ static int gfx_v8_0_soft_reset(void *handle) SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); if (grbm_soft_reset || srbm_soft_reset) { - gfx_v8_0_print_status((void *)adev); /* stop the rlc */ gfx_v8_0_rlc_stop(adev); @@ -4168,7 +4927,6 @@ static int gfx_v8_0_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - gfx_v8_0_print_status((void *)adev); } return 0; } @@ -4250,6 +5008,7 @@ static int gfx_v8_0_early_init(void *handle) gfx_v8_0_set_ring_funcs(adev); gfx_v8_0_set_irq_funcs(adev); gfx_v8_0_set_gds_init(adev); + gfx_v8_0_set_rlc_funcs(adev); return 0; } @@ -4272,17 +5031,109 @@ static int gfx_v8_0_late_init(void *handle) if (r) return r; + amdgpu_set_powergating_state(adev, + AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE); + return 0; } +static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, temp; + + /* Send msg to SMU via Powerplay */ + amdgpu_set_powergating_state(adev, + AMD_IP_BLOCK_TYPE_SMC, + enable ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); + + if (enable) { + /* Enable static MGPG */ + temp = data = RREG32(mmRLC_PG_CNTL); + data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; + + if (temp != data) + WREG32(mmRLC_PG_CNTL, data); + } else { + temp = data = RREG32(mmRLC_PG_CNTL); + data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; + + if (temp != data) + WREG32(mmRLC_PG_CNTL, data); + } +} + +static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, temp; + + if (enable) { + /* Enable dynamic MGPG */ + temp = data = RREG32(mmRLC_PG_CNTL); + data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; + + if (temp != data) + WREG32(mmRLC_PG_CNTL, data); + } else { + temp = data = RREG32(mmRLC_PG_CNTL); + data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; + + if (temp != data) + WREG32(mmRLC_PG_CNTL, data); + } +} + +static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, temp; + + if (enable) { + /* Enable quick PG */ + temp = data = RREG32(mmRLC_PG_CNTL); + data |= 0x100000; + + if (temp != data) + WREG32(mmRLC_PG_CNTL, data); + } else { + temp = data = RREG32(mmRLC_PG_CNTL); + data &= ~0x100000; + + if (temp != data) + WREG32(mmRLC_PG_CNTL, data); + } +} + static int gfx_v8_0_set_powergating_state(void *handle, enum amd_powergating_state state) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) + return 0; + + switch (adev->asic_type) { + case CHIP_POLARIS11: + if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) + polaris11_enable_gfx_static_mg_power_gating(adev, + state == AMD_PG_STATE_GATE ? true : false); + else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) + polaris11_enable_gfx_dynamic_mg_power_gating(adev, + state == AMD_PG_STATE_GATE ? true : false); + else + polaris11_enable_gfx_quick_mg_power_gating(adev, + state == AMD_PG_STATE_GATE ? true : false); + break; + default: + break; + } + return 0; } -static void fiji_send_serdes_cmd(struct amdgpu_device *adev, - uint32_t reg_addr, uint32_t cmd) +static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev, + uint32_t reg_addr, uint32_t cmd) { uint32_t data; @@ -4292,7 +5143,8 @@ static void fiji_send_serdes_cmd(struct amdgpu_device *adev, WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); data = RREG32(mmRLC_SERDES_WR_CTRL); - data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | + if (adev->asic_type == CHIP_STONEY) + data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | RLC_SERDES_WR_CTRL__P1_SELECT_MASK | RLC_SERDES_WR_CTRL__P2_SELECT_MASK | @@ -4300,42 +5152,218 @@ static void fiji_send_serdes_cmd(struct amdgpu_device *adev, RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | RLC_SERDES_WR_CTRL__POWER_UP_MASK | RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | - RLC_SERDES_WR_CTRL__BPM_DATA_MASK | - RLC_SERDES_WR_CTRL__REG_ADDR_MASK | RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); + else + data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | + RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | + RLC_SERDES_WR_CTRL__P1_SELECT_MASK | + RLC_SERDES_WR_CTRL__P2_SELECT_MASK | + RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK | + RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | + RLC_SERDES_WR_CTRL__POWER_UP_MASK | + RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | + RLC_SERDES_WR_CTRL__BPM_DATA_MASK | + RLC_SERDES_WR_CTRL__REG_ADDR_MASK | + RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK | - (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) | - (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) | - (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT)); + (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) | + (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) | + (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT)); WREG32(mmRLC_SERDES_WR_CTRL, data); } -static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev, - bool enable) +#define MSG_ENTER_RLC_SAFE_MODE 1 +#define MSG_EXIT_RLC_SAFE_MODE 0 + +#define RLC_GPR_REG2__REQ_MASK 0x00000001 +#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001 +#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e + +static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev) +{ + u32 data = 0; + unsigned i; + + data = RREG32(mmRLC_CNTL); + if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0) + return; + + if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) || + (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG | + AMD_PG_SUPPORT_GFX_DMG))) { + data |= RLC_GPR_REG2__REQ_MASK; + data &= ~RLC_GPR_REG2__MESSAGE_MASK; + data |= (MSG_ENTER_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT); + WREG32(mmRLC_GPR_REG2, data); + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_GPM_STAT) & + (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | + RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) == + (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | + RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) + break; + udelay(1); + } + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0) + break; + udelay(1); + } + adev->gfx.rlc.in_safe_mode = true; + } +} + +static void cz_exit_rlc_safe_mode(struct amdgpu_device *adev) +{ + u32 data; + unsigned i; + + data = RREG32(mmRLC_CNTL); + if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0) + return; + + if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) || + (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG | + AMD_PG_SUPPORT_GFX_DMG))) { + data |= RLC_GPR_REG2__REQ_MASK; + data &= ~RLC_GPR_REG2__MESSAGE_MASK; + data |= (MSG_EXIT_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT); + WREG32(mmRLC_GPR_REG2, data); + adev->gfx.rlc.in_safe_mode = false; + } + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0) + break; + udelay(1); + } +} + +static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev) +{ + u32 data; + unsigned i; + + data = RREG32(mmRLC_CNTL); + if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK)) + return; + + if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { + data |= RLC_SAFE_MODE__CMD_MASK; + data &= ~RLC_SAFE_MODE__MESSAGE_MASK; + data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); + WREG32(mmRLC_SAFE_MODE, data); + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_GPM_STAT) & + (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | + RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) == + (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | + RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) + break; + udelay(1); + } + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0) + break; + udelay(1); + } + adev->gfx.rlc.in_safe_mode = true; + } +} + +static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev) +{ + u32 data = 0; + unsigned i; + + data = RREG32(mmRLC_CNTL); + if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK)) + return; + + if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { + if (adev->gfx.rlc.in_safe_mode) { + data |= RLC_SAFE_MODE__CMD_MASK; + data &= ~RLC_SAFE_MODE__MESSAGE_MASK; + WREG32(mmRLC_SAFE_MODE, data); + adev->gfx.rlc.in_safe_mode = false; + } + } + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0) + break; + udelay(1); + } +} + +static void gfx_v8_0_nop_enter_rlc_safe_mode(struct amdgpu_device *adev) +{ + adev->gfx.rlc.in_safe_mode = true; +} + +static void gfx_v8_0_nop_exit_rlc_safe_mode(struct amdgpu_device *adev) +{ + adev->gfx.rlc.in_safe_mode = false; +} + +static const struct amdgpu_rlc_funcs cz_rlc_funcs = { + .enter_safe_mode = cz_enter_rlc_safe_mode, + .exit_safe_mode = cz_exit_rlc_safe_mode +}; + +static const struct amdgpu_rlc_funcs iceland_rlc_funcs = { + .enter_safe_mode = iceland_enter_rlc_safe_mode, + .exit_safe_mode = iceland_exit_rlc_safe_mode +}; + +static const struct amdgpu_rlc_funcs gfx_v8_0_nop_rlc_funcs = { + .enter_safe_mode = gfx_v8_0_nop_enter_rlc_safe_mode, + .exit_safe_mode = gfx_v8_0_nop_exit_rlc_safe_mode +}; + +static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) { uint32_t temp, data; - /* It is disabled by HW by default */ - if (enable) { - /* 1 - RLC memory Light sleep */ - temp = data = RREG32(mmRLC_MEM_SLP_CNTL); - data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; - if (temp != data) - WREG32(mmRLC_MEM_SLP_CNTL, data); + adev->gfx.rlc.funcs->enter_safe_mode(adev); - /* 2 - CP memory Light sleep */ - temp = data = RREG32(mmCP_MEM_SLP_CNTL); - data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; - if (temp != data) - WREG32(mmCP_MEM_SLP_CNTL, data); + /* It is disabled by HW by default */ + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { + /* 1 - RLC memory Light sleep */ + temp = data = RREG32(mmRLC_MEM_SLP_CNTL); + data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; + if (temp != data) + WREG32(mmRLC_MEM_SLP_CNTL, data); + } + + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { + /* 2 - CP memory Light sleep */ + temp = data = RREG32(mmCP_MEM_SLP_CNTL); + data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; + if (temp != data) + WREG32(mmCP_MEM_SLP_CNTL, data); + } + } /* 3 - RLC_CGTT_MGCG_OVERRIDE */ temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); - data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | - RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | - RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK | - RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK); + if (adev->flags & AMD_IS_APU) + data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | + RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | + RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK); + else + data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | + RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | + RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK | + RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK); if (temp != data) WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); @@ -4344,19 +5372,23 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev, gfx_v8_0_wait_for_rlc_serdes(adev); /* 5 - clear mgcg override */ - fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD); + gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD); - /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */ - temp = data = RREG32(mmCGTS_SM_CTRL_REG); - data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK); - data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); - data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; - data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; - data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; - data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; - data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); - if (temp != data) - WREG32(mmCGTS_SM_CTRL_REG, data); + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { + /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */ + temp = data = RREG32(mmCGTS_SM_CTRL_REG); + data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK); + data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); + data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; + data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; + if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && + (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) + data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; + data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; + data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); + if (temp != data) + WREG32(mmCGTS_SM_CTRL_REG, data); + } udelay(50); /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ @@ -4396,23 +5428,27 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev, gfx_v8_0_wait_for_rlc_serdes(adev); /* 6 - set mgcg override */ - fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD); + gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD); udelay(50); /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ gfx_v8_0_wait_for_rlc_serdes(adev); } + + adev->gfx.rlc.funcs->exit_safe_mode(adev); } -static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev, - bool enable) +static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, + bool enable) { uint32_t temp, temp1, data, data1; temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL); - if (enable) { + adev->gfx.rlc.funcs->enter_safe_mode(adev); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { /* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/ * Cmp_busy/GFX_Idle interrupts */ @@ -4427,25 +5463,29 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev, gfx_v8_0_wait_for_rlc_serdes(adev); /* 3 - clear cgcg override */ - fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD); + gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD); /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ gfx_v8_0_wait_for_rlc_serdes(adev); /* 4 - write cmd to set CGLS */ - fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD); + gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD); /* 5 - enable cgcg */ data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; - /* enable cgls*/ - data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { + /* enable cgls*/ + data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; - temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); - data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK; + temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); + data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK; - if (temp1 != data1) - WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); + if (temp1 != data1) + WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); + } else { + data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; + } if (temp != data) WREG32(mmRLC_CGCG_CGLS_CTRL, data); @@ -4470,36 +5510,38 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev, gfx_v8_0_wait_for_rlc_serdes(adev); /* write cmd to Set CGCG Overrride */ - fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD); + gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD); /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ gfx_v8_0_wait_for_rlc_serdes(adev); /* write cmd to Clear CGLS */ - fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD); + gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD); /* disable cgcg, cgls should be disabled too. */ data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | - RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); + RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); if (temp != data) WREG32(mmRLC_CGCG_CGLS_CTRL, data); } + + adev->gfx.rlc.funcs->exit_safe_mode(adev); } -static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev, - bool enable) +static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev, + bool enable) { if (enable) { /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS) * === MGCG + MGLS + TS(CG/LS) === */ - fiji_update_medium_grain_clock_gating(adev, enable); - fiji_update_coarse_grain_clock_gating(adev, enable); + gfx_v8_0_update_medium_grain_clock_gating(adev, enable); + gfx_v8_0_update_coarse_grain_clock_gating(adev, enable); } else { /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS) * === CGCG + CGLS === */ - fiji_update_coarse_grain_clock_gating(adev, enable); - fiji_update_medium_grain_clock_gating(adev, enable); + gfx_v8_0_update_coarse_grain_clock_gating(adev, enable); + gfx_v8_0_update_medium_grain_clock_gating(adev, enable); } return 0; } @@ -4511,8 +5553,10 @@ static int gfx_v8_0_set_clockgating_state(void *handle, switch (adev->asic_type) { case CHIP_FIJI: - fiji_update_gfx_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + case CHIP_CARRIZO: + case CHIP_STONEY: + gfx_v8_0_update_gfx_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); break; default: break; @@ -4602,17 +5646,13 @@ static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) } static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { - bool need_ctx_switch = ring->current_ctx != ib->ctx; u32 header, control = 0; u32 next_rptr = ring->wptr + 5; - /* drop the CE preamble IB for the same context */ - if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch) - return; - - if (need_ctx_switch) + if (ctx_switch) next_rptr += 2; next_rptr += 4; @@ -4623,7 +5663,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, amdgpu_ring_write(ring, next_rptr); /* insert SWITCH_BUFFER packet before first IB in the ring frame */ - if (need_ctx_switch) { + if (ctx_switch) { amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); amdgpu_ring_write(ring, 0); } @@ -4633,7 +5673,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, else header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); - control |= ib->length_dw | (ib->vm_id << 24); + control |= ib->length_dw | (vm_id << 24); amdgpu_ring_write(ring, header); amdgpu_ring_write(ring, @@ -4646,7 +5686,8 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, } static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { u32 header, control = 0; u32 next_rptr = ring->wptr + 5; @@ -4662,7 +5703,7 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); - control |= ib->length_dw | (ib->vm_id << 24); + control |= ib->length_dw | (vm_id << 24); amdgpu_ring_write(ring, header); amdgpu_ring_write(ring, @@ -5022,6 +6063,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, } const struct amd_ip_funcs gfx_v8_0_ip_funcs = { + .name = "gfx_v8_0", .early_init = gfx_v8_0_early_init, .late_init = gfx_v8_0_late_init, .sw_init = gfx_v8_0_sw_init, @@ -5033,7 +6075,6 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = { .is_idle = gfx_v8_0_is_idle, .wait_for_idle = gfx_v8_0_wait_for_idle, .soft_reset = gfx_v8_0_soft_reset, - .print_status = gfx_v8_0_print_status, .set_clockgating_state = gfx_v8_0_set_clockgating_state, .set_powergating_state = gfx_v8_0_set_powergating_state, }; @@ -5112,6 +6153,22 @@ static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; } +static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_TOPAZ: + case CHIP_STONEY: + adev->gfx.rlc.funcs = &iceland_rlc_funcs; + break; + case CHIP_CARRIZO: + adev->gfx.rlc.funcs = &cz_rlc_funcs; + break; + default: + adev->gfx.rlc.funcs = &gfx_v8_0_nop_rlc_funcs; + break; + } +} + static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) { /* init asci gds info */ @@ -5155,14 +6212,11 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev) return (~data) & mask; } -int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, - struct amdgpu_cu_info *cu_info) +static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) { int i, j, k, counter, active_cu_number = 0; u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; - - if (!adev || !cu_info) - return -EINVAL; + struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; memset(cu_info, 0, sizeof(*cu_info)); @@ -5193,6 +6247,4 @@ int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, cu_info->number = active_cu_number; cu_info->ao_cu_mask = ao_cu_mask; - - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h index 021e05193cb9..16a49f53a2fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h @@ -28,6 +28,5 @@ extern const struct amd_ip_funcs gfx_v8_0_ip_funcs; uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev); void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num); -int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index a4a2e6cc61bb..1feb6439cb0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1117,114 +1117,6 @@ static int gmc_v7_0_wait_for_idle(void *handle) } -static void gmc_v7_0_print_status(void *handle) -{ - int i, j; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "GMC 8.x registers\n"); - dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", - RREG32(mmSRBM_STATUS)); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - - dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", - RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); - dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", - RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); - dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n", - RREG32(mmMC_VM_MX_L1_TLB_CNTL)); - dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n", - RREG32(mmVM_L2_CNTL)); - dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n", - RREG32(mmVM_L2_CNTL2)); - dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n", - RREG32(mmVM_L2_CNTL3)); - dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)); - dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)); - dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)); - dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n", - RREG32(mmVM_CONTEXT0_CNTL2)); - dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n", - RREG32(mmVM_CONTEXT0_CNTL)); - dev_info(adev->dev, " 0x15D4=0x%08X\n", - RREG32(0x575)); - dev_info(adev->dev, " 0x15D8=0x%08X\n", - RREG32(0x576)); - dev_info(adev->dev, " 0x15DC=0x%08X\n", - RREG32(0x577)); - dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)); - dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)); - dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)); - dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n", - RREG32(mmVM_CONTEXT1_CNTL2)); - dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n", - RREG32(mmVM_CONTEXT1_CNTL)); - for (i = 0; i < 16; i++) { - if (i < 8) - dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", - i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i)); - else - dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", - i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8)); - } - dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n", - RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)); - dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n", - RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)); - dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n", - RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)); - dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n", - RREG32(mmMC_VM_FB_LOCATION)); - dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n", - RREG32(mmMC_VM_AGP_BASE)); - dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n", - RREG32(mmMC_VM_AGP_TOP)); - dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n", - RREG32(mmMC_VM_AGP_BOT)); - - if (adev->asic_type == CHIP_KAVERI) { - dev_info(adev->dev, " CHUB_CONTROL=0x%08X\n", - RREG32(mmCHUB_CONTROL)); - } - - dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n", - RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL)); - dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n", - RREG32(mmHDP_NONSURFACE_BASE)); - dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n", - RREG32(mmHDP_NONSURFACE_INFO)); - dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n", - RREG32(mmHDP_NONSURFACE_SIZE)); - dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n", - RREG32(mmHDP_MISC_CNTL)); - dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n", - RREG32(mmHDP_HOST_PATH_CNTL)); - - for (i = 0, j = 0; i < 32; i++, j += 0x6) { - dev_info(adev->dev, " %d:\n", i); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb05 + j, RREG32(0xb05 + j)); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb06 + j, RREG32(0xb06 + j)); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb07 + j, RREG32(0xb07 + j)); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb08 + j, RREG32(0xb08 + j)); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb09 + j, RREG32(0xb09 + j)); - } - - dev_info(adev->dev, " BIF_FB_EN=0x%08X\n", - RREG32(mmBIF_FB_EN)); -} - static int gmc_v7_0_soft_reset(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1244,8 +1136,6 @@ static int gmc_v7_0_soft_reset(void *handle) } if (srbm_soft_reset) { - gmc_v7_0_print_status((void *)adev); - gmc_v7_0_mc_stop(adev, &save); if (gmc_v7_0_wait_for_idle(adev)) { dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); @@ -1269,8 +1159,6 @@ static int gmc_v7_0_soft_reset(void *handle) gmc_v7_0_mc_resume(adev, &save); udelay(50); - - gmc_v7_0_print_status((void *)adev); } return 0; @@ -1373,6 +1261,7 @@ static int gmc_v7_0_set_powergating_state(void *handle, } const struct amd_ip_funcs gmc_v7_0_ip_funcs = { + .name = "gmc_v7_0", .early_init = gmc_v7_0_early_init, .late_init = gmc_v7_0_late_init, .sw_init = gmc_v7_0_sw_init, @@ -1384,7 +1273,6 @@ const struct amd_ip_funcs gmc_v7_0_ip_funcs = { .is_idle = gmc_v7_0_is_idle, .wait_for_idle = gmc_v7_0_wait_for_idle, .soft_reset = gmc_v7_0_soft_reset, - .print_status = gmc_v7_0_print_status, .set_clockgating_state = gmc_v7_0_set_clockgating_state, .set_powergating_state = gmc_v7_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 7a9db2c72c89..9945d5bbf1fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -43,6 +43,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); static const u32 golden_settings_tonga_a11[] = { @@ -73,6 +75,23 @@ static const u32 fiji_mgcg_cgcg_init[] = mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 }; +static const u32 golden_settings_polaris11_a11[] = +{ + mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff +}; + +static const u32 golden_settings_polaris10_a11[] = +{ + mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, + mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff +}; + static const u32 cz_mgcg_cgcg_init[] = { mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 @@ -103,6 +122,16 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; + case CHIP_POLARIS11: + amdgpu_program_register_sequence(adev, + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + break; + case CHIP_POLARIS10: + amdgpu_program_register_sequence(adev, + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, @@ -209,6 +238,12 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_TONGA: chip_name = "tonga"; break; + case CHIP_POLARIS11: + chip_name = "polaris11"; + break; + case CHIP_POLARIS10: + chip_name = "polaris10"; + break; case CHIP_FIJI: case CHIP_CARRIZO: case CHIP_STONEY: @@ -1085,111 +1120,6 @@ static int gmc_v8_0_wait_for_idle(void *handle) } -static void gmc_v8_0_print_status(void *handle) -{ - int i, j; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "GMC 8.x registers\n"); - dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", - RREG32(mmSRBM_STATUS)); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - - dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", - RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); - dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", - RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); - dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n", - RREG32(mmMC_VM_MX_L1_TLB_CNTL)); - dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n", - RREG32(mmVM_L2_CNTL)); - dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n", - RREG32(mmVM_L2_CNTL2)); - dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n", - RREG32(mmVM_L2_CNTL3)); - dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n", - RREG32(mmVM_L2_CNTL4)); - dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)); - dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)); - dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)); - dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n", - RREG32(mmVM_CONTEXT0_CNTL2)); - dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n", - RREG32(mmVM_CONTEXT0_CNTL)); - dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n", - RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)); - dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n", - RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)); - dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n", - RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)); - dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)); - dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)); - dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", - RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)); - dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n", - RREG32(mmVM_CONTEXT1_CNTL2)); - dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n", - RREG32(mmVM_CONTEXT1_CNTL)); - for (i = 0; i < 16; i++) { - if (i < 8) - dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", - i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i)); - else - dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", - i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8)); - } - dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n", - RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)); - dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n", - RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)); - dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n", - RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)); - dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n", - RREG32(mmMC_VM_FB_LOCATION)); - dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n", - RREG32(mmMC_VM_AGP_BASE)); - dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n", - RREG32(mmMC_VM_AGP_TOP)); - dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n", - RREG32(mmMC_VM_AGP_BOT)); - - dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n", - RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL)); - dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n", - RREG32(mmHDP_NONSURFACE_BASE)); - dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n", - RREG32(mmHDP_NONSURFACE_INFO)); - dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n", - RREG32(mmHDP_NONSURFACE_SIZE)); - dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n", - RREG32(mmHDP_MISC_CNTL)); - dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n", - RREG32(mmHDP_HOST_PATH_CNTL)); - - for (i = 0, j = 0; i < 32; i++, j += 0x6) { - dev_info(adev->dev, " %d:\n", i); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb05 + j, RREG32(0xb05 + j)); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb06 + j, RREG32(0xb06 + j)); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb07 + j, RREG32(0xb07 + j)); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb08 + j, RREG32(0xb08 + j)); - dev_info(adev->dev, " 0x%04X=0x%08X\n", - 0xb09 + j, RREG32(0xb09 + j)); - } - - dev_info(adev->dev, " BIF_FB_EN=0x%08X\n", - RREG32(mmBIF_FB_EN)); -} - static int gmc_v8_0_soft_reset(void *handle) { struct amdgpu_mode_mc_save save; @@ -1209,8 +1139,6 @@ static int gmc_v8_0_soft_reset(void *handle) } if (srbm_soft_reset) { - gmc_v8_0_print_status((void *)adev); - gmc_v8_0_mc_stop(adev, &save); if (gmc_v8_0_wait_for_idle(adev)) { dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); @@ -1234,8 +1162,6 @@ static int gmc_v8_0_soft_reset(void *handle) gmc_v8_0_mc_resume(adev, &save); udelay(50); - - gmc_v8_0_print_status((void *)adev); } return 0; @@ -1313,11 +1239,11 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, } static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, - bool enable) + bool enable) { uint32_t data; - if (enable) { + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { data = RREG32(mmMC_HUB_MISC_HUB_CG); data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; WREG32(mmMC_HUB_MISC_HUB_CG, data); @@ -1393,11 +1319,11 @@ static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, } static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, - bool enable) + bool enable) { uint32_t data; - if (enable) { + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { data = RREG32(mmMC_HUB_MISC_HUB_CG); data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; WREG32(mmMC_HUB_MISC_HUB_CG, data); @@ -1497,6 +1423,7 @@ static int gmc_v8_0_set_powergating_state(void *handle, } const struct amd_ip_funcs gmc_v8_0_ip_funcs = { + .name = "gmc_v8_0", .early_init = gmc_v8_0_early_init, .late_init = gmc_v8_0_late_init, .sw_init = gmc_v8_0_sw_init, @@ -1508,7 +1435,6 @@ const struct amd_ip_funcs gmc_v8_0_ip_funcs = { .is_idle = gmc_v8_0_is_idle, .wait_for_idle = gmc_v8_0_wait_for_idle, .soft_reset = gmc_v8_0_soft_reset, - .print_status = gmc_v8_0_print_status, .set_clockgating_state = gmc_v8_0_set_clockgating_state, .set_powergating_state = gmc_v8_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c index 208d55f41c7f..460bc8ad37e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c @@ -157,6 +157,7 @@ static int iceland_dpm_set_powergating_state(void *handle, } const struct amd_ip_funcs iceland_dpm_ip_funcs = { + .name = "iceland_dpm", .early_init = iceland_dpm_early_init, .late_init = NULL, .sw_init = iceland_dpm_sw_init, @@ -168,7 +169,6 @@ const struct amd_ip_funcs iceland_dpm_ip_funcs = { .is_idle = NULL, .wait_for_idle = NULL, .soft_reset = NULL, - .print_status = NULL, .set_clockgating_state = iceland_dpm_set_clockgating_state, .set_powergating_state = iceland_dpm_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 679e7394a495..39bfc52d0b42 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -351,35 +351,6 @@ static int iceland_ih_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void iceland_ih_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "ICELAND IH registers\n"); - dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", - RREG32(mmSRBM_STATUS)); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", - RREG32(mmINTERRUPT_CNTL)); - dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", - RREG32(mmINTERRUPT_CNTL2)); - dev_info(adev->dev, " IH_CNTL=0x%08X\n", - RREG32(mmIH_CNTL)); - dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", - RREG32(mmIH_RB_CNTL)); - dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", - RREG32(mmIH_RB_BASE)); - dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", - RREG32(mmIH_RB_WPTR_ADDR_LO)); - dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", - RREG32(mmIH_RB_WPTR_ADDR_HI)); - dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", - RREG32(mmIH_RB_RPTR)); - dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", - RREG32(mmIH_RB_WPTR)); -} - static int iceland_ih_soft_reset(void *handle) { u32 srbm_soft_reset = 0; @@ -391,8 +362,6 @@ static int iceland_ih_soft_reset(void *handle) SOFT_RESET_IH, 1); if (srbm_soft_reset) { - iceland_ih_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -407,8 +376,6 @@ static int iceland_ih_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - - iceland_ih_print_status((void *)adev); } return 0; @@ -427,6 +394,7 @@ static int iceland_ih_set_powergating_state(void *handle, } const struct amd_ip_funcs iceland_ih_ip_funcs = { + .name = "iceland_ih", .early_init = iceland_ih_early_init, .late_init = NULL, .sw_init = iceland_ih_sw_init, @@ -438,7 +406,6 @@ const struct amd_ip_funcs iceland_ih_ip_funcs = { .is_idle = iceland_ih_is_idle, .wait_for_idle = iceland_ih_wait_for_idle, .soft_reset = iceland_ih_soft_reset, - .print_status = iceland_ih_print_status, .set_clockgating_state = iceland_ih_set_clockgating_state, .set_powergating_state = iceland_ih_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index 654d76723bc3..b45f54714574 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -135,11 +135,6 @@ static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable) #endif } -static u32 sumo_get_sleep_divider_from_id(u32 id) -{ - return 1 << id; -} - static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev, struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, ATOM_AVAILABLE_SCLK_LIST *table) @@ -2176,8 +2171,7 @@ static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, struct kv_power_info *pi = kv_get_pi(adev); u32 i; u32 temp; - u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ? - min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK; + u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK); if (sclk < min) return 0; @@ -2186,7 +2180,7 @@ static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, return 0; for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) { - temp = sclk / sumo_get_sleep_divider_from_id(i); + temp = sclk >> i; if (temp >= min) break; } @@ -3147,62 +3141,6 @@ static int kv_dpm_wait_for_idle(void *handle) return 0; } -static void kv_dpm_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "KV/KB DPM registers\n"); - dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", - RREG32_DIDT(ixDIDT_SQ_CTRL0)); - dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n", - RREG32_DIDT(ixDIDT_DB_CTRL0)); - dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n", - RREG32_DIDT(ixDIDT_TD_CTRL0)); - dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n", - RREG32_DIDT(ixDIDT_TCP_CTRL0)); - dev_info(adev->dev, " LCAC_SX0_OVR_SEL=0x%08X\n", - RREG32_SMC(ixLCAC_SX0_OVR_SEL)); - dev_info(adev->dev, " LCAC_SX0_OVR_VAL=0x%08X\n", - RREG32_SMC(ixLCAC_SX0_OVR_VAL)); - dev_info(adev->dev, " LCAC_MC0_OVR_SEL=0x%08X\n", - RREG32_SMC(ixLCAC_MC0_OVR_SEL)); - dev_info(adev->dev, " LCAC_MC0_OVR_VAL=0x%08X\n", - RREG32_SMC(ixLCAC_MC0_OVR_VAL)); - dev_info(adev->dev, " LCAC_MC1_OVR_SEL=0x%08X\n", - RREG32_SMC(ixLCAC_MC1_OVR_SEL)); - dev_info(adev->dev, " LCAC_MC1_OVR_VAL=0x%08X\n", - RREG32_SMC(ixLCAC_MC1_OVR_VAL)); - dev_info(adev->dev, " LCAC_MC2_OVR_SEL=0x%08X\n", - RREG32_SMC(ixLCAC_MC2_OVR_SEL)); - dev_info(adev->dev, " LCAC_MC2_OVR_VAL=0x%08X\n", - RREG32_SMC(ixLCAC_MC2_OVR_VAL)); - dev_info(adev->dev, " LCAC_MC3_OVR_SEL=0x%08X\n", - RREG32_SMC(ixLCAC_MC3_OVR_SEL)); - dev_info(adev->dev, " LCAC_MC3_OVR_VAL=0x%08X\n", - RREG32_SMC(ixLCAC_MC3_OVR_VAL)); - dev_info(adev->dev, " LCAC_CPL_OVR_SEL=0x%08X\n", - RREG32_SMC(ixLCAC_CPL_OVR_SEL)); - dev_info(adev->dev, " LCAC_CPL_OVR_VAL=0x%08X\n", - RREG32_SMC(ixLCAC_CPL_OVR_VAL)); - dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n", - RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0)); - dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n", - RREG32_SMC(ixGENERAL_PWRMGT)); - dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", - RREG32_SMC(ixSCLK_PWRMGT_CNTL)); - dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n", - RREG32(mmSMC_MESSAGE_0)); - dev_info(adev->dev, " SMC_RESP_0=0x%08X\n", - RREG32(mmSMC_RESP_0)); - dev_info(adev->dev, " SMC_MSG_ARG_0=0x%08X\n", - RREG32(mmSMC_MSG_ARG_0)); - dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n", - RREG32(mmSMC_IND_INDEX_0)); - dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n", - RREG32(mmSMC_IND_DATA_0)); - dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n", - RREG32(mmSMC_IND_ACCESS_CNTL)); -} static int kv_dpm_soft_reset(void *handle) { @@ -3300,6 +3238,7 @@ static int kv_dpm_set_powergating_state(void *handle, } const struct amd_ip_funcs kv_dpm_ip_funcs = { + .name = "kv_dpm", .early_init = kv_dpm_early_init, .late_init = kv_dpm_late_init, .sw_init = kv_dpm_sw_init, @@ -3311,7 +3250,6 @@ const struct amd_ip_funcs kv_dpm_ip_funcs = { .is_idle = kv_dpm_is_idle, .wait_for_idle = kv_dpm_wait_for_idle, .soft_reset = kv_dpm_soft_reset, - .print_status = kv_dpm_print_status, .set_clockgating_state = kv_dpm_set_clockgating_state, .set_powergating_state = kv_dpm_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 6e0a86a563f3..f4c3130d3fdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -242,9 +242,10 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) * Schedule an IB in the DMA ring (VI). */ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { - u32 vmid = ib->vm_id & 0xf; + u32 vmid = vm_id & 0xf; u32 next_rptr = ring->wptr + 5; while ((next_rptr & 7) != 2) @@ -701,7 +702,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring) ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); ib.length_dw = 8; - r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); if (r) goto err1; @@ -990,7 +991,7 @@ static int sdma_v2_4_sw_init(void *handle) ring->ring_obj = NULL; ring->use_doorbell = false; sprintf(ring->name, "sdma%d", i); - r = amdgpu_ring_init(adev, ring, 256 * 1024, + r = amdgpu_ring_init(adev, ring, 1024, SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, &adev->sdma.trap_irq, (i == 0) ? @@ -1080,55 +1081,6 @@ static int sdma_v2_4_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void sdma_v2_4_print_status(void *handle) -{ - int i, j; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "VI SDMA registers\n"); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - for (i = 0; i < adev->sdma.num_instances; i++) { - dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", - i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", - i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); - mutex_lock(&adev->srbm_mutex); - for (j = 0; j < 16; j++) { - vi_srbm_select(adev, 0, 0, 0, j); - dev_info(adev->dev, " VM %d:\n", j); - dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", - i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); - } - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - } -} - static int sdma_v2_4_soft_reset(void *handle) { u32 srbm_soft_reset = 0; @@ -1151,8 +1103,6 @@ static int sdma_v2_4_soft_reset(void *handle) } if (srbm_soft_reset) { - sdma_v2_4_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -1167,8 +1117,6 @@ static int sdma_v2_4_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - - sdma_v2_4_print_status((void *)adev); } return 0; @@ -1283,6 +1231,7 @@ static int sdma_v2_4_set_powergating_state(void *handle, } const struct amd_ip_funcs sdma_v2_4_ip_funcs = { + .name = "sdma_v2_4", .early_init = sdma_v2_4_early_init, .late_init = NULL, .sw_init = sdma_v2_4_sw_init, @@ -1294,7 +1243,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { .is_idle = sdma_v2_4_is_idle, .wait_for_idle = sdma_v2_4_wait_for_idle, .soft_reset = sdma_v2_4_soft_reset, - .print_status = sdma_v2_4_print_status, .set_clockgating_state = sdma_v2_4_set_clockgating_state, .set_powergating_state = sdma_v2_4_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 8c8ca98dd129..063f08a9957a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -56,6 +56,11 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); + static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { @@ -101,6 +106,32 @@ static const u32 fiji_mgcg_cgcg_init[] = mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; +static const u32 golden_settings_polaris11_a11[] = +{ + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + +static const u32 golden_settings_polaris10_a11[] = +{ + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + static const u32 cz_golden_settings_a11[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, @@ -172,6 +203,16 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; + case CHIP_POLARIS11: + amdgpu_program_register_sequence(adev, + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + break; + case CHIP_POLARIS10: + amdgpu_program_register_sequence(adev, + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, @@ -220,6 +261,12 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; + case CHIP_POLARIS11: + chip_name = "polaris11"; + break; + case CHIP_POLARIS10: + chip_name = "polaris10"; + break; case CHIP_CARRIZO: chip_name = "carrizo"; break; @@ -353,9 +400,10 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) * Schedule an IB in the DMA ring (VI). */ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { - u32 vmid = ib->vm_id & 0xf; + u32 vmid = vm_id & 0xf; u32 next_rptr = ring->wptr + 5; while ((next_rptr & 7) != 2) @@ -452,6 +500,31 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); } +unsigned init_cond_exec(struct amdgpu_ring *ring) +{ + unsigned ret; + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); + amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); + amdgpu_ring_write(ring, 1); + ret = ring->wptr;/* this is the offset we need patch later */ + amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ + return ret; +} + +void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) +{ + unsigned cur; + BUG_ON(ring->ring[offset] != 0x55aa55aa); + + cur = ring->wptr - 1; + if (likely(cur > offset)) + ring->ring[offset] = cur - offset; + else + ring->ring[offset] = (ring->ring_size>>2) - offset + cur; +} + + /** * sdma_v3_0_gfx_stop - stop the gfx async dma engines * @@ -853,7 +926,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); ib.length_dw = 8; - r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); if (r) goto err1; @@ -1151,7 +1224,7 @@ static int sdma_v3_0_sw_init(void *handle) AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; sprintf(ring->name, "sdma%d", i); - r = amdgpu_ring_init(adev, ring, 256 * 1024, + r = amdgpu_ring_init(adev, ring, 1024, SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, &adev->sdma.trap_irq, (i == 0) ? @@ -1242,57 +1315,6 @@ static int sdma_v3_0_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void sdma_v3_0_print_status(void *handle) -{ - int i, j; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "VI SDMA registers\n"); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - for (i = 0; i < adev->sdma.num_instances; i++) { - dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", - i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", - i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", - i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); - mutex_lock(&adev->srbm_mutex); - for (j = 0; j < 16; j++) { - vi_srbm_select(adev, 0, 0, 0, j); - dev_info(adev->dev, " VM %d:\n", j); - dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", - i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); - dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", - i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); - } - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - } -} - static int sdma_v3_0_soft_reset(void *handle) { u32 srbm_soft_reset = 0; @@ -1315,8 +1337,6 @@ static int sdma_v3_0_soft_reset(void *handle) } if (srbm_soft_reset) { - sdma_v3_0_print_status((void *)adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -1331,8 +1351,6 @@ static int sdma_v3_0_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - - sdma_v3_0_print_status((void *)adev); } return 0; @@ -1433,40 +1451,31 @@ static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, return 0; } -static void fiji_update_sdma_medium_grain_clock_gating( +static void sdma_v3_0_update_sdma_medium_grain_clock_gating( struct amdgpu_device *adev, bool enable) { uint32_t temp, data; + int i; - if (enable) { - temp = data = RREG32(mmSDMA0_CLK_CTRL); - data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); - if (data != temp) - WREG32(mmSDMA0_CLK_CTRL, data); - - temp = data = RREG32(mmSDMA1_CLK_CTRL); - data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); - - if (data != temp) - WREG32(mmSDMA1_CLK_CTRL, data); + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { + for (i = 0; i < adev->sdma.num_instances; i++) { + temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); + data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); + if (data != temp) + WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); + } } else { - temp = data = RREG32(mmSDMA0_CLK_CTRL); - data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | + for (i = 0; i < adev->sdma.num_instances; i++) { + temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); + data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | @@ -1475,54 +1484,35 @@ static void fiji_update_sdma_medium_grain_clock_gating( SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; - if (data != temp) - WREG32(mmSDMA0_CLK_CTRL, data); - - temp = data = RREG32(mmSDMA1_CLK_CTRL); - data |= SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | - SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK; - - if (data != temp) - WREG32(mmSDMA1_CLK_CTRL, data); + if (data != temp) + WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); + } } } -static void fiji_update_sdma_medium_grain_light_sleep( +static void sdma_v3_0_update_sdma_medium_grain_light_sleep( struct amdgpu_device *adev, bool enable) { uint32_t temp, data; + int i; - if (enable) { - temp = data = RREG32(mmSDMA0_POWER_CNTL); - data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { + for (i = 0; i < adev->sdma.num_instances; i++) { + temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); + data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; - if (temp != data) - WREG32(mmSDMA0_POWER_CNTL, data); - - temp = data = RREG32(mmSDMA1_POWER_CNTL); - data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; - - if (temp != data) - WREG32(mmSDMA1_POWER_CNTL, data); + if (temp != data) + WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); + } } else { - temp = data = RREG32(mmSDMA0_POWER_CNTL); - data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + for (i = 0; i < adev->sdma.num_instances; i++) { + temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); + data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; - if (temp != data) - WREG32(mmSDMA0_POWER_CNTL, data); - - temp = data = RREG32(mmSDMA1_POWER_CNTL); - data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; - - if (temp != data) - WREG32(mmSDMA1_POWER_CNTL, data); + if (temp != data) + WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); + } } } @@ -1533,9 +1523,11 @@ static int sdma_v3_0_set_clockgating_state(void *handle, switch (adev->asic_type) { case CHIP_FIJI: - fiji_update_sdma_medium_grain_clock_gating(adev, + case CHIP_CARRIZO: + case CHIP_STONEY: + sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); - fiji_update_sdma_medium_grain_light_sleep(adev, + sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE ? true : false); break; default: @@ -1551,6 +1543,7 @@ static int sdma_v3_0_set_powergating_state(void *handle, } const struct amd_ip_funcs sdma_v3_0_ip_funcs = { + .name = "sdma_v3_0", .early_init = sdma_v3_0_early_init, .late_init = NULL, .sw_init = sdma_v3_0_sw_init, @@ -1562,7 +1555,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { .is_idle = sdma_v3_0_is_idle, .wait_for_idle = sdma_v3_0_wait_for_idle, .soft_reset = sdma_v3_0_soft_reset, - .print_status = sdma_v3_0_print_status, .set_clockgating_state = sdma_v3_0_set_clockgating_state, .set_powergating_state = sdma_v3_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h index c24a81eebc7c..880152c0f775 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h +++ b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h @@ -44,6 +44,7 @@ #define UCODE_ID_IH_REG_RESTORE 11 #define UCODE_ID_VBIOS 12 #define UCODE_ID_MISC_METADATA 13 +#define UCODE_ID_SMU_SK 14 #define UCODE_ID_RLC_SCRATCH 32 #define UCODE_ID_RLC_SRM_ARAM 33 #define UCODE_ID_RLC_SRM_DRAM 34 diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c index 0497784b3652..b7615cefcac4 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c @@ -143,6 +143,7 @@ static int tonga_dpm_set_powergating_state(void *handle, } const struct amd_ip_funcs tonga_dpm_ip_funcs = { + .name = "tonga_dpm", .early_init = tonga_dpm_early_init, .late_init = NULL, .sw_init = tonga_dpm_sw_init, @@ -154,7 +155,6 @@ const struct amd_ip_funcs tonga_dpm_ip_funcs = { .is_idle = NULL, .wait_for_idle = NULL, .soft_reset = NULL, - .print_status = NULL, .set_clockgating_state = tonga_dpm_set_clockgating_state, .set_powergating_state = tonga_dpm_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 0f14199cf716..f036af937fbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -374,35 +374,6 @@ static int tonga_ih_wait_for_idle(void *handle) return -ETIMEDOUT; } -static void tonga_ih_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "TONGA IH registers\n"); - dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", - RREG32(mmSRBM_STATUS)); - dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", - RREG32(mmSRBM_STATUS2)); - dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", - RREG32(mmINTERRUPT_CNTL)); - dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", - RREG32(mmINTERRUPT_CNTL2)); - dev_info(adev->dev, " IH_CNTL=0x%08X\n", - RREG32(mmIH_CNTL)); - dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", - RREG32(mmIH_RB_CNTL)); - dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", - RREG32(mmIH_RB_BASE)); - dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", - RREG32(mmIH_RB_WPTR_ADDR_LO)); - dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", - RREG32(mmIH_RB_WPTR_ADDR_HI)); - dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", - RREG32(mmIH_RB_RPTR)); - dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", - RREG32(mmIH_RB_WPTR)); -} - static int tonga_ih_soft_reset(void *handle) { u32 srbm_soft_reset = 0; @@ -414,8 +385,6 @@ static int tonga_ih_soft_reset(void *handle) SOFT_RESET_IH, 1); if (srbm_soft_reset) { - tonga_ih_print_status(adev); - tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); @@ -430,8 +399,6 @@ static int tonga_ih_soft_reset(void *handle) /* Wait a little for things to settle down */ udelay(50); - - tonga_ih_print_status(adev); } return 0; @@ -450,6 +417,7 @@ static int tonga_ih_set_powergating_state(void *handle, } const struct amd_ip_funcs tonga_ih_ip_funcs = { + .name = "tonga_ih", .early_init = tonga_ih_early_init, .late_init = NULL, .sw_init = tonga_ih_sw_init, @@ -461,7 +429,6 @@ const struct amd_ip_funcs tonga_ih_ip_funcs = { .is_idle = tonga_ih_is_idle, .wait_for_idle = tonga_ih_wait_for_idle, .soft_reset = tonga_ih_soft_reset, - .print_status = tonga_ih_print_status, .set_clockgating_state = tonga_ih_set_clockgating_state, .set_powergating_state = tonga_ih_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index cb463753115b..f07551476a70 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -114,7 +114,7 @@ static int uvd_v4_2_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, + r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); return r; @@ -489,7 +489,8 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) * Write ring commands to execute the indirect buffer */ static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); amdgpu_ring_write(ring, ib->gpu_addr); @@ -559,12 +560,13 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_VCPU_CACHE_SIZE0, size); addr += size; - size = AMDGPU_UVD_STACK_SIZE >> 3; + size = AMDGPU_UVD_HEAP_SIZE >> 3; WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); WREG32(mmUVD_VCPU_CACHE_SIZE1, size); addr += size; - size = AMDGPU_UVD_HEAP_SIZE >> 3; + size = (AMDGPU_UVD_STACK_SIZE + + (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); WREG32(mmUVD_VCPU_CACHE_SIZE2, size); @@ -679,117 +681,6 @@ static int uvd_v4_2_soft_reset(void *handle) return uvd_v4_2_start(adev); } -static void uvd_v4_2_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - dev_info(adev->dev, "UVD 4.2 registers\n"); - dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", - RREG32(mmUVD_SEMA_ADDR_LOW)); - dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", - RREG32(mmUVD_SEMA_ADDR_HIGH)); - dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", - RREG32(mmUVD_SEMA_CMD)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_CMD)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_DATA0)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_DATA1)); - dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", - RREG32(mmUVD_ENGINE_CNTL)); - dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_CNTL)); - dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", - RREG32(mmUVD_LMI_EXT40_ADDR)); - dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", - RREG32(mmUVD_CTX_INDEX)); - dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", - RREG32(mmUVD_CTX_DATA)); - dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", - RREG32(mmUVD_CGC_GATE)); - dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", - RREG32(mmUVD_CGC_CTRL)); - dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", - RREG32(mmUVD_LMI_CTRL2)); - dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", - RREG32(mmUVD_MASTINT_EN)); - dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", - RREG32(mmUVD_LMI_ADDR_EXT)); - dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", - RREG32(mmUVD_LMI_CTRL)); - dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", - RREG32(mmUVD_LMI_SWAP_CNTL)); - dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", - RREG32(mmUVD_MP_SWAP_CNTL)); - dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXA0)); - dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXA1)); - dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXB0)); - dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXB1)); - dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUX)); - dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", - RREG32(mmUVD_MPC_SET_ALU)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET0)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE0)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET1)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE1)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET2)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE2)); - dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", - RREG32(mmUVD_VCPU_CNTL)); - dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", - RREG32(mmUVD_SOFT_RESET)); - dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n", - RREG32(mmUVD_RBC_IB_BASE)); - dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", - RREG32(mmUVD_RBC_IB_SIZE)); - dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n", - RREG32(mmUVD_RBC_RB_BASE)); - dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", - RREG32(mmUVD_RBC_RB_RPTR)); - dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", - RREG32(mmUVD_RBC_RB_WPTR)); - dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", - RREG32(mmUVD_RBC_RB_WPTR_CNTL)); - dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", - RREG32(mmUVD_RBC_RB_CNTL)); - dev_info(adev->dev, " UVD_STATUS=0x%08X\n", - RREG32(mmUVD_STATUS)); - dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", - RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); - dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", - RREG32(mmUVD_CONTEXT_ID)); - dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); - -} - static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, @@ -849,6 +740,7 @@ static int uvd_v4_2_set_powergating_state(void *handle, } const struct amd_ip_funcs uvd_v4_2_ip_funcs = { + .name = "uvd_v4_2", .early_init = uvd_v4_2_early_init, .late_init = NULL, .sw_init = uvd_v4_2_sw_init, @@ -860,7 +752,6 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { .is_idle = uvd_v4_2_is_idle, .wait_for_idle = uvd_v4_2_wait_for_idle, .soft_reset = uvd_v4_2_soft_reset, - .print_status = uvd_v4_2_print_status, .set_clockgating_state = uvd_v4_2_set_clockgating_state, .set_powergating_state = uvd_v4_2_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 16476d80f475..e0a76a883d46 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -31,6 +31,7 @@ #include "uvd/uvd_5_0_sh_mask.h" #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#include "vi.h" static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); @@ -110,7 +111,7 @@ static int uvd_v5_0_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, + r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); return r; @@ -271,12 +272,13 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_VCPU_CACHE_SIZE0, size); offset += size; - size = AMDGPU_UVD_STACK_SIZE; + size = AMDGPU_UVD_HEAP_SIZE; WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE1, size); offset += size; - size = AMDGPU_UVD_HEAP_SIZE; + size = AMDGPU_UVD_STACK_SIZE + + (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE2, size); @@ -537,7 +539,8 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) * Write ring commands to execute the indirect buffer */ static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); @@ -622,120 +625,6 @@ static int uvd_v5_0_soft_reset(void *handle) return uvd_v5_0_start(adev); } -static void uvd_v5_0_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - dev_info(adev->dev, "UVD 5.0 registers\n"); - dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", - RREG32(mmUVD_SEMA_ADDR_LOW)); - dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", - RREG32(mmUVD_SEMA_ADDR_HIGH)); - dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", - RREG32(mmUVD_SEMA_CMD)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_CMD)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_DATA0)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_DATA1)); - dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", - RREG32(mmUVD_ENGINE_CNTL)); - dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_CNTL)); - dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", - RREG32(mmUVD_LMI_EXT40_ADDR)); - dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", - RREG32(mmUVD_CTX_INDEX)); - dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", - RREG32(mmUVD_CTX_DATA)); - dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", - RREG32(mmUVD_CGC_GATE)); - dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", - RREG32(mmUVD_CGC_CTRL)); - dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", - RREG32(mmUVD_LMI_CTRL2)); - dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", - RREG32(mmUVD_MASTINT_EN)); - dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", - RREG32(mmUVD_LMI_ADDR_EXT)); - dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", - RREG32(mmUVD_LMI_CTRL)); - dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", - RREG32(mmUVD_LMI_SWAP_CNTL)); - dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", - RREG32(mmUVD_MP_SWAP_CNTL)); - dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXA0)); - dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXA1)); - dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXB0)); - dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXB1)); - dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUX)); - dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", - RREG32(mmUVD_MPC_SET_ALU)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET0)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE0)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET1)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE1)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET2)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE2)); - dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", - RREG32(mmUVD_VCPU_CNTL)); - dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", - RREG32(mmUVD_SOFT_RESET)); - dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n", - RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)); - dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n", - RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)); - dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", - RREG32(mmUVD_RBC_IB_SIZE)); - dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n", - RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)); - dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n", - RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)); - dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", - RREG32(mmUVD_RBC_RB_RPTR)); - dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", - RREG32(mmUVD_RBC_RB_WPTR)); - dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", - RREG32(mmUVD_RBC_RB_WPTR_CNTL)); - dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", - RREG32(mmUVD_RBC_RB_CNTL)); - dev_info(adev->dev, " UVD_STATUS=0x%08X\n", - RREG32(mmUVD_STATUS)); - dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", - RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); - dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", - RREG32(mmUVD_CONTEXT_ID)); - dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); -} - static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, @@ -754,14 +643,128 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, return 0; } +static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data1, data2, suvd_flags; + + data = RREG32(mmUVD_CGC_CTRL); + data1 = RREG32(mmUVD_SUVD_CGC_GATE); + data2 = RREG32(mmUVD_SUVD_CGC_CTRL); + + data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | + UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + + suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | + UVD_SUVD_CGC_GATE__SIT_MASK | + UVD_SUVD_CGC_GATE__SMP_MASK | + UVD_SUVD_CGC_GATE__SCM_MASK | + UVD_SUVD_CGC_GATE__SDB_MASK; + + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | + (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | + (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); + + data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | + UVD_CGC_CTRL__UDEC_CM_MODE_MASK | + UVD_CGC_CTRL__UDEC_IT_MODE_MASK | + UVD_CGC_CTRL__UDEC_DB_MODE_MASK | + UVD_CGC_CTRL__UDEC_MP_MODE_MASK | + UVD_CGC_CTRL__SYS_MODE_MASK | + UVD_CGC_CTRL__UDEC_MODE_MASK | + UVD_CGC_CTRL__MPEG2_MODE_MASK | + UVD_CGC_CTRL__REGS_MODE_MASK | + UVD_CGC_CTRL__RBC_MODE_MASK | + UVD_CGC_CTRL__LMI_MC_MODE_MASK | + UVD_CGC_CTRL__LMI_UMC_MODE_MASK | + UVD_CGC_CTRL__IDCT_MODE_MASK | + UVD_CGC_CTRL__MPRD_MODE_MASK | + UVD_CGC_CTRL__MPC_MODE_MASK | + UVD_CGC_CTRL__LBSI_MODE_MASK | + UVD_CGC_CTRL__LRBBM_MODE_MASK | + UVD_CGC_CTRL__WCB_MODE_MASK | + UVD_CGC_CTRL__VCPU_MODE_MASK | + UVD_CGC_CTRL__JPEG_MODE_MASK | + UVD_CGC_CTRL__SCPU_MODE_MASK); + data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | + UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | + UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | + UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | + UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); + data1 |= suvd_flags; + + WREG32(mmUVD_CGC_CTRL, data); + WREG32(mmUVD_CGC_GATE, 0); + WREG32(mmUVD_SUVD_CGC_GATE, data1); + WREG32(mmUVD_SUVD_CGC_CTRL, data2); +} + +#if 0 +static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data1, cgc_flags, suvd_flags; + + data = RREG32(mmUVD_CGC_GATE); + data1 = RREG32(mmUVD_SUVD_CGC_GATE); + + cgc_flags = UVD_CGC_GATE__SYS_MASK | + UVD_CGC_GATE__UDEC_MASK | + UVD_CGC_GATE__MPEG2_MASK | + UVD_CGC_GATE__RBC_MASK | + UVD_CGC_GATE__LMI_MC_MASK | + UVD_CGC_GATE__IDCT_MASK | + UVD_CGC_GATE__MPRD_MASK | + UVD_CGC_GATE__MPC_MASK | + UVD_CGC_GATE__LBSI_MASK | + UVD_CGC_GATE__LRBBM_MASK | + UVD_CGC_GATE__UDEC_RE_MASK | + UVD_CGC_GATE__UDEC_CM_MASK | + UVD_CGC_GATE__UDEC_IT_MASK | + UVD_CGC_GATE__UDEC_DB_MASK | + UVD_CGC_GATE__UDEC_MP_MASK | + UVD_CGC_GATE__WCB_MASK | + UVD_CGC_GATE__VCPU_MASK | + UVD_CGC_GATE__SCPU_MASK; + + suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | + UVD_SUVD_CGC_GATE__SIT_MASK | + UVD_SUVD_CGC_GATE__SMP_MASK | + UVD_SUVD_CGC_GATE__SCM_MASK | + UVD_SUVD_CGC_GATE__SDB_MASK; + + data |= cgc_flags; + data1 |= suvd_flags; + + WREG32(mmUVD_CGC_GATE, data); + WREG32(mmUVD_SUVD_CGC_GATE, data1); +} +#endif + static int uvd_v5_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + static int curstate = -1; if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; + if (curstate == state) + return 0; + + curstate = state; + if (enable) { + /* disable HW gating and enable Sw gating */ + uvd_v5_0_set_sw_clock_gating(adev); + } else { + /* wait for STATUS to clear */ + if (uvd_v5_0_wait_for_idle(handle)) + return -EBUSY; + + /* enable HW gates because UVD is idle */ +/* uvd_v5_0_set_hw_clock_gating(adev); */ + } + return 0; } @@ -789,6 +792,7 @@ static int uvd_v5_0_set_powergating_state(void *handle, } const struct amd_ip_funcs uvd_v5_0_ip_funcs = { + .name = "uvd_v5_0", .early_init = uvd_v5_0_early_init, .late_init = NULL, .sw_init = uvd_v5_0_sw_init, @@ -800,7 +804,6 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { .is_idle = uvd_v5_0_is_idle, .wait_for_idle = uvd_v5_0_wait_for_idle, .soft_reset = uvd_v5_0_soft_reset, - .print_status = uvd_v5_0_print_status, .set_clockgating_state = uvd_v5_0_set_clockgating_state, .set_powergating_state = uvd_v5_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index d49379145ef2..c9929d665c01 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -31,11 +31,15 @@ #include "uvd/uvd_6_0_sh_mask.h" #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#include "smu/smu_7_1_3_d.h" +#include "smu/smu_7_1_3_sh_mask.h" +#include "vi.h" static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v6_0_start(struct amdgpu_device *adev); static void uvd_v6_0_stop(struct amdgpu_device *adev); +static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); /** * uvd_v6_0_ring_get_rptr - get read pointer @@ -110,7 +114,7 @@ static int uvd_v6_0_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, + r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); return r; @@ -270,20 +274,24 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_VCPU_CACHE_SIZE0, size); offset += size; - size = AMDGPU_UVD_STACK_SIZE; + size = AMDGPU_UVD_HEAP_SIZE; WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE1, size); offset += size; - size = AMDGPU_UVD_HEAP_SIZE; + size = AMDGPU_UVD_STACK_SIZE + + (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE2, size); WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + + WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); } +#if 0 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, bool enable) { @@ -360,157 +368,7 @@ static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, WREG32(mmUVD_CGC_GATE, data); WREG32(mmUVD_SUVD_CGC_GATE, data1); } - -static void tonga_set_uvd_clock_gating_branches(struct amdgpu_device *adev, - bool enable) -{ - u32 data, data1; - - data = RREG32(mmUVD_CGC_GATE); - data1 = RREG32(mmUVD_SUVD_CGC_GATE); - if (enable) { - data |= UVD_CGC_GATE__SYS_MASK | - UVD_CGC_GATE__UDEC_MASK | - UVD_CGC_GATE__MPEG2_MASK | - UVD_CGC_GATE__RBC_MASK | - UVD_CGC_GATE__LMI_MC_MASK | - UVD_CGC_GATE__IDCT_MASK | - UVD_CGC_GATE__MPRD_MASK | - UVD_CGC_GATE__MPC_MASK | - UVD_CGC_GATE__LBSI_MASK | - UVD_CGC_GATE__LRBBM_MASK | - UVD_CGC_GATE__UDEC_RE_MASK | - UVD_CGC_GATE__UDEC_CM_MASK | - UVD_CGC_GATE__UDEC_IT_MASK | - UVD_CGC_GATE__UDEC_DB_MASK | - UVD_CGC_GATE__UDEC_MP_MASK | - UVD_CGC_GATE__WCB_MASK | - UVD_CGC_GATE__VCPU_MASK | - UVD_CGC_GATE__SCPU_MASK; - data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | - UVD_SUVD_CGC_GATE__SIT_MASK | - UVD_SUVD_CGC_GATE__SMP_MASK | - UVD_SUVD_CGC_GATE__SCM_MASK | - UVD_SUVD_CGC_GATE__SDB_MASK; - } else { - data &= ~(UVD_CGC_GATE__SYS_MASK | - UVD_CGC_GATE__UDEC_MASK | - UVD_CGC_GATE__MPEG2_MASK | - UVD_CGC_GATE__RBC_MASK | - UVD_CGC_GATE__LMI_MC_MASK | - UVD_CGC_GATE__LMI_UMC_MASK | - UVD_CGC_GATE__IDCT_MASK | - UVD_CGC_GATE__MPRD_MASK | - UVD_CGC_GATE__MPC_MASK | - UVD_CGC_GATE__LBSI_MASK | - UVD_CGC_GATE__LRBBM_MASK | - UVD_CGC_GATE__UDEC_RE_MASK | - UVD_CGC_GATE__UDEC_CM_MASK | - UVD_CGC_GATE__UDEC_IT_MASK | - UVD_CGC_GATE__UDEC_DB_MASK | - UVD_CGC_GATE__UDEC_MP_MASK | - UVD_CGC_GATE__WCB_MASK | - UVD_CGC_GATE__VCPU_MASK | - UVD_CGC_GATE__SCPU_MASK); - data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | - UVD_SUVD_CGC_GATE__SIT_MASK | - UVD_SUVD_CGC_GATE__SMP_MASK | - UVD_SUVD_CGC_GATE__SCM_MASK | - UVD_SUVD_CGC_GATE__SDB_MASK); - } - WREG32(mmUVD_CGC_GATE, data); - WREG32(mmUVD_SUVD_CGC_GATE, data1); -} - -static void uvd_v6_0_set_uvd_dynamic_clock_mode(struct amdgpu_device *adev, - bool swmode) -{ - u32 data, data1 = 0, data2; - - /* Always un-gate UVD REGS bit */ - data = RREG32(mmUVD_CGC_GATE); - data &= ~(UVD_CGC_GATE__REGS_MASK); - WREG32(mmUVD_CGC_GATE, data); - - data = RREG32(mmUVD_CGC_CTRL); - data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | - UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); - data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | - 1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER) | - 4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY); - - data2 = RREG32(mmUVD_SUVD_CGC_CTRL); - if (swmode) { - data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | - UVD_CGC_CTRL__UDEC_CM_MODE_MASK | - UVD_CGC_CTRL__UDEC_IT_MODE_MASK | - UVD_CGC_CTRL__UDEC_DB_MODE_MASK | - UVD_CGC_CTRL__UDEC_MP_MODE_MASK | - UVD_CGC_CTRL__SYS_MODE_MASK | - UVD_CGC_CTRL__UDEC_MODE_MASK | - UVD_CGC_CTRL__MPEG2_MODE_MASK | - UVD_CGC_CTRL__REGS_MODE_MASK | - UVD_CGC_CTRL__RBC_MODE_MASK | - UVD_CGC_CTRL__LMI_MC_MODE_MASK | - UVD_CGC_CTRL__LMI_UMC_MODE_MASK | - UVD_CGC_CTRL__IDCT_MODE_MASK | - UVD_CGC_CTRL__MPRD_MODE_MASK | - UVD_CGC_CTRL__MPC_MODE_MASK | - UVD_CGC_CTRL__LBSI_MODE_MASK | - UVD_CGC_CTRL__LRBBM_MODE_MASK | - UVD_CGC_CTRL__WCB_MODE_MASK | - UVD_CGC_CTRL__VCPU_MODE_MASK | - UVD_CGC_CTRL__JPEG_MODE_MASK | - UVD_CGC_CTRL__SCPU_MODE_MASK); - data1 |= UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | - UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK; - data1 &= ~UVD_CGC_CTRL2__GATER_DIV_ID_MASK; - data1 |= 7 << REG_FIELD_SHIFT(UVD_CGC_CTRL2, GATER_DIV_ID); - data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | - UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | - UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | - UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | - UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); - } else { - data |= UVD_CGC_CTRL__UDEC_RE_MODE_MASK | - UVD_CGC_CTRL__UDEC_CM_MODE_MASK | - UVD_CGC_CTRL__UDEC_IT_MODE_MASK | - UVD_CGC_CTRL__UDEC_DB_MODE_MASK | - UVD_CGC_CTRL__UDEC_MP_MODE_MASK | - UVD_CGC_CTRL__SYS_MODE_MASK | - UVD_CGC_CTRL__UDEC_MODE_MASK | - UVD_CGC_CTRL__MPEG2_MODE_MASK | - UVD_CGC_CTRL__REGS_MODE_MASK | - UVD_CGC_CTRL__RBC_MODE_MASK | - UVD_CGC_CTRL__LMI_MC_MODE_MASK | - UVD_CGC_CTRL__LMI_UMC_MODE_MASK | - UVD_CGC_CTRL__IDCT_MODE_MASK | - UVD_CGC_CTRL__MPRD_MODE_MASK | - UVD_CGC_CTRL__MPC_MODE_MASK | - UVD_CGC_CTRL__LBSI_MODE_MASK | - UVD_CGC_CTRL__LRBBM_MODE_MASK | - UVD_CGC_CTRL__WCB_MODE_MASK | - UVD_CGC_CTRL__VCPU_MODE_MASK | - UVD_CGC_CTRL__SCPU_MODE_MASK; - data2 |= UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | - UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | - UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | - UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | - UVD_SUVD_CGC_CTRL__SDB_MODE_MASK; - } - WREG32(mmUVD_CGC_CTRL, data); - WREG32(mmUVD_SUVD_CGC_CTRL, data2); - - data = RREG32_UVD_CTX(ixUVD_CGC_CTRL2); - data &= ~(REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) | - REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) | - REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID)); - data1 &= (REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) | - REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) | - REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID)); - data |= data1; - WREG32_UVD_CTX(ixUVD_CGC_CTRL2, data); -} +#endif /** * uvd_v6_0_start - start UVD block @@ -538,11 +396,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) /* Set dynamic clock gating in S/W control mode */ if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) { - if (adev->flags & AMD_IS_APU) - cz_set_uvd_clock_gating_branches(adev, false); - else - tonga_set_uvd_clock_gating_branches(adev, false); - uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true); + uvd_v6_0_set_sw_clock_gating(adev); } else { /* disable clock gating */ uint32_t data = RREG32(mmUVD_CGC_CTRL); @@ -777,7 +631,8 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) * Write ring commands to execute the indirect buffer */ static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, - struct amdgpu_ib *ib) + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) { amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); @@ -854,112 +709,6 @@ static int uvd_v6_0_soft_reset(void *handle) return uvd_v6_0_start(adev); } -static void uvd_v6_0_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - dev_info(adev->dev, "UVD 6.0 registers\n"); - dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", - RREG32(mmUVD_SEMA_ADDR_LOW)); - dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", - RREG32(mmUVD_SEMA_ADDR_HIGH)); - dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", - RREG32(mmUVD_SEMA_CMD)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_CMD)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_DATA0)); - dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", - RREG32(mmUVD_GPCOM_VCPU_DATA1)); - dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", - RREG32(mmUVD_ENGINE_CNTL)); - dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_CNTL)); - dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", - RREG32(mmUVD_LMI_EXT40_ADDR)); - dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", - RREG32(mmUVD_CTX_INDEX)); - dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", - RREG32(mmUVD_CTX_DATA)); - dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", - RREG32(mmUVD_CGC_GATE)); - dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", - RREG32(mmUVD_CGC_CTRL)); - dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", - RREG32(mmUVD_LMI_CTRL2)); - dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", - RREG32(mmUVD_MASTINT_EN)); - dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", - RREG32(mmUVD_LMI_ADDR_EXT)); - dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", - RREG32(mmUVD_LMI_CTRL)); - dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", - RREG32(mmUVD_LMI_SWAP_CNTL)); - dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", - RREG32(mmUVD_MP_SWAP_CNTL)); - dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXA0)); - dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXA1)); - dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXB0)); - dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUXB1)); - dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", - RREG32(mmUVD_MPC_SET_MUX)); - dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", - RREG32(mmUVD_MPC_SET_ALU)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET0)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE0)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET1)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE1)); - dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_OFFSET2)); - dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", - RREG32(mmUVD_VCPU_CACHE_SIZE2)); - dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", - RREG32(mmUVD_VCPU_CNTL)); - dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", - RREG32(mmUVD_SOFT_RESET)); - dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", - RREG32(mmUVD_RBC_IB_SIZE)); - dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", - RREG32(mmUVD_RBC_RB_RPTR)); - dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", - RREG32(mmUVD_RBC_RB_WPTR)); - dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", - RREG32(mmUVD_RBC_RB_WPTR_CNTL)); - dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", - RREG32(mmUVD_RBC_RB_CNTL)); - dev_info(adev->dev, " UVD_STATUS=0x%08X\n", - RREG32(mmUVD_STATUS)); - dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", - RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); - dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", - RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); - dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", - RREG32(mmUVD_CONTEXT_ID)); - dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); - dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", - RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); -} - static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, @@ -978,25 +727,146 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, return 0; } +static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data1, data2, suvd_flags; + + data = RREG32(mmUVD_CGC_CTRL); + data1 = RREG32(mmUVD_SUVD_CGC_GATE); + data2 = RREG32(mmUVD_SUVD_CGC_CTRL); + + data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | + UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + + suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | + UVD_SUVD_CGC_GATE__SIT_MASK | + UVD_SUVD_CGC_GATE__SMP_MASK | + UVD_SUVD_CGC_GATE__SCM_MASK | + UVD_SUVD_CGC_GATE__SDB_MASK; + + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | + (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | + (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); + + data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | + UVD_CGC_CTRL__UDEC_CM_MODE_MASK | + UVD_CGC_CTRL__UDEC_IT_MODE_MASK | + UVD_CGC_CTRL__UDEC_DB_MODE_MASK | + UVD_CGC_CTRL__UDEC_MP_MODE_MASK | + UVD_CGC_CTRL__SYS_MODE_MASK | + UVD_CGC_CTRL__UDEC_MODE_MASK | + UVD_CGC_CTRL__MPEG2_MODE_MASK | + UVD_CGC_CTRL__REGS_MODE_MASK | + UVD_CGC_CTRL__RBC_MODE_MASK | + UVD_CGC_CTRL__LMI_MC_MODE_MASK | + UVD_CGC_CTRL__LMI_UMC_MODE_MASK | + UVD_CGC_CTRL__IDCT_MODE_MASK | + UVD_CGC_CTRL__MPRD_MODE_MASK | + UVD_CGC_CTRL__MPC_MODE_MASK | + UVD_CGC_CTRL__LBSI_MODE_MASK | + UVD_CGC_CTRL__LRBBM_MODE_MASK | + UVD_CGC_CTRL__WCB_MODE_MASK | + UVD_CGC_CTRL__VCPU_MODE_MASK | + UVD_CGC_CTRL__JPEG_MODE_MASK | + UVD_CGC_CTRL__SCPU_MODE_MASK | + UVD_CGC_CTRL__JPEG2_MODE_MASK); + data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | + UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | + UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | + UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | + UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); + data1 |= suvd_flags; + + WREG32(mmUVD_CGC_CTRL, data); + WREG32(mmUVD_CGC_GATE, 0); + WREG32(mmUVD_SUVD_CGC_GATE, data1); + WREG32(mmUVD_SUVD_CGC_CTRL, data2); +} + +#if 0 +static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data1, cgc_flags, suvd_flags; + + data = RREG32(mmUVD_CGC_GATE); + data1 = RREG32(mmUVD_SUVD_CGC_GATE); + + cgc_flags = UVD_CGC_GATE__SYS_MASK | + UVD_CGC_GATE__UDEC_MASK | + UVD_CGC_GATE__MPEG2_MASK | + UVD_CGC_GATE__RBC_MASK | + UVD_CGC_GATE__LMI_MC_MASK | + UVD_CGC_GATE__IDCT_MASK | + UVD_CGC_GATE__MPRD_MASK | + UVD_CGC_GATE__MPC_MASK | + UVD_CGC_GATE__LBSI_MASK | + UVD_CGC_GATE__LRBBM_MASK | + UVD_CGC_GATE__UDEC_RE_MASK | + UVD_CGC_GATE__UDEC_CM_MASK | + UVD_CGC_GATE__UDEC_IT_MASK | + UVD_CGC_GATE__UDEC_DB_MASK | + UVD_CGC_GATE__UDEC_MP_MASK | + UVD_CGC_GATE__WCB_MASK | + UVD_CGC_GATE__VCPU_MASK | + UVD_CGC_GATE__SCPU_MASK | + UVD_CGC_GATE__JPEG_MASK | + UVD_CGC_GATE__JPEG2_MASK; + + suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | + UVD_SUVD_CGC_GATE__SIT_MASK | + UVD_SUVD_CGC_GATE__SMP_MASK | + UVD_SUVD_CGC_GATE__SCM_MASK | + UVD_SUVD_CGC_GATE__SDB_MASK; + + data |= cgc_flags; + data1 |= suvd_flags; + + WREG32(mmUVD_CGC_GATE, data); + WREG32(mmUVD_SUVD_CGC_GATE, data1); +} +#endif + +static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable) +{ + u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); + + if (enable) + tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | + GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); + else + tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | + GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); + + WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); +} + static int uvd_v6_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + static int curstate = -1; + + if (adev->asic_type == CHIP_FIJI) + uvd_v6_set_bypass_mode(adev, enable); if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; + if (curstate == state) + return 0; + + curstate = state; if (enable) { - if (adev->flags & AMD_IS_APU) - cz_set_uvd_clock_gating_branches(adev, enable); - else - tonga_set_uvd_clock_gating_branches(adev, enable); - uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true); + /* disable HW gating and enable Sw gating */ + uvd_v6_0_set_sw_clock_gating(adev); } else { - uint32_t data = RREG32(mmUVD_CGC_CTRL); - data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; - WREG32(mmUVD_CGC_CTRL, data); + /* wait for STATUS to clear */ + if (uvd_v6_0_wait_for_idle(handle)) + return -EBUSY; + + /* enable HW gates because UVD is idle */ +/* uvd_v6_0_set_hw_clock_gating(adev); */ } return 0; @@ -1026,6 +896,7 @@ static int uvd_v6_0_set_powergating_state(void *handle, } const struct amd_ip_funcs uvd_v6_0_ip_funcs = { + .name = "uvd_v6_0", .early_init = uvd_v6_0_early_init, .late_init = NULL, .sw_init = uvd_v6_0_sw_init, @@ -1037,7 +908,6 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = { .is_idle = uvd_v6_0_is_idle, .wait_for_idle = uvd_v6_0_wait_for_idle, .soft_reset = uvd_v6_0_soft_reset, - .print_status = uvd_v6_0_print_status, .set_clockgating_state = uvd_v6_0_set_clockgating_state, .set_powergating_state = uvd_v6_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index c7e885bcfd41..45d92aceb485 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -44,7 +44,7 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev); static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev); - +static int vce_v2_0_wait_for_idle(void *handle); /** * vce_v2_0_ring_get_rptr - get read pointer * @@ -201,14 +201,14 @@ static int vce_v2_0_sw_init(void *handle) ring = &adev->vce.ring[0]; sprintf(ring->name, "vce0"); - r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, + r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); if (r) return r; ring = &adev->vce.ring[1]; sprintf(ring->name, "vce1"); - r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, + r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); if (r) return r; @@ -240,7 +240,8 @@ static int vce_v2_0_hw_init(void *handle) r = vce_v2_0_start(adev); if (r) - return r; +/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */ + return 0; ring = &adev->vce.ring[0]; ring->ready = true; @@ -318,7 +319,7 @@ static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated) WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0); - } else { + } else { tmp = RREG32(mmVCE_CLOCK_GATING_B); tmp |= 0xe7; tmp &= ~0xe70000; @@ -339,6 +340,21 @@ static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated) { u32 orig, tmp; + if (gated) { + if (vce_v2_0_wait_for_idle(adev)) { + DRM_INFO("VCE is busy, Can't set clock gateing"); + return; + } + WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK); + WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(100); + WREG32(mmVCE_STATUS, 0); + } else { + WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK); + WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(100); + } + tmp = RREG32(mmVCE_CLOCK_GATING_B); tmp &= ~0x00060006; if (gated) { @@ -362,6 +378,7 @@ static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated) if (gated) WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0); + WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); } static void vce_v2_0_disable_cg(struct amdgpu_device *adev) @@ -478,75 +495,6 @@ static int vce_v2_0_soft_reset(void *handle) return vce_v2_0_start(adev); } -static void vce_v2_0_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "VCE 2.0 registers\n"); - dev_info(adev->dev, " VCE_STATUS=0x%08X\n", - RREG32(mmVCE_STATUS)); - dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n", - RREG32(mmVCE_VCPU_CNTL)); - dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_OFFSET0)); - dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_SIZE0)); - dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_OFFSET1)); - dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_SIZE1)); - dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_OFFSET2)); - dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_SIZE2)); - dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n", - RREG32(mmVCE_SOFT_RESET)); - dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n", - RREG32(mmVCE_RB_BASE_LO2)); - dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n", - RREG32(mmVCE_RB_BASE_HI2)); - dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n", - RREG32(mmVCE_RB_SIZE2)); - dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n", - RREG32(mmVCE_RB_RPTR2)); - dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n", - RREG32(mmVCE_RB_WPTR2)); - dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n", - RREG32(mmVCE_RB_BASE_LO)); - dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n", - RREG32(mmVCE_RB_BASE_HI)); - dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n", - RREG32(mmVCE_RB_SIZE)); - dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n", - RREG32(mmVCE_RB_RPTR)); - dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n", - RREG32(mmVCE_RB_WPTR)); - dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n", - RREG32(mmVCE_CLOCK_GATING_A)); - dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n", - RREG32(mmVCE_CLOCK_GATING_B)); - dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n", - RREG32(mmVCE_CGTT_CLK_OVERRIDE)); - dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n", - RREG32(mmVCE_UENC_CLOCK_GATING)); - dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n", - RREG32(mmVCE_UENC_REG_CLOCK_GATING)); - dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n", - RREG32(mmVCE_SYS_INT_EN)); - dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n", - RREG32(mmVCE_LMI_CTRL2)); - dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n", - RREG32(mmVCE_LMI_CTRL)); - dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n", - RREG32(mmVCE_LMI_VM_CTRL)); - dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n", - RREG32(mmVCE_LMI_SWAP_CNTL)); - dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n", - RREG32(mmVCE_LMI_SWAP_CNTL1)); - dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n", - RREG32(mmVCE_LMI_CACHE_CTRL)); -} - static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, @@ -619,6 +567,7 @@ static int vce_v2_0_set_powergating_state(void *handle, } const struct amd_ip_funcs vce_v2_0_ip_funcs = { + .name = "vce_v2_0", .early_init = vce_v2_0_early_init, .late_init = NULL, .sw_init = vce_v2_0_sw_init, @@ -630,7 +579,6 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { .is_idle = vce_v2_0_is_idle, .wait_for_idle = vce_v2_0_wait_for_idle, .soft_reset = vce_v2_0_soft_reset, - .print_status = vce_v2_0_print_status, .set_clockgating_state = vce_v2_0_set_clockgating_state, .set_powergating_state = vce_v2_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index ce468ee5da2a..30e8099e94c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -40,9 +40,9 @@ #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 -#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616 -#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617 -#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618 #define VCE_V3_0_FW_SIZE (384 * 1024) #define VCE_V3_0_STACK_SIZE (64 * 1024) @@ -315,9 +315,11 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) { u32 tmp; - /* Fiji, Stoney are single pipe */ + /* Fiji, Stoney, Polaris10, Polaris11 are single pipe */ if ((adev->asic_type == CHIP_FIJI) || - (adev->asic_type == CHIP_STONEY)) + (adev->asic_type == CHIP_STONEY) || + (adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) return AMDGPU_VCE_HARVEST_VCE1; /* Tonga and CZ are dual or single pipe */ @@ -381,14 +383,14 @@ static int vce_v3_0_sw_init(void *handle) ring = &adev->vce.ring[0]; sprintf(ring->name, "vce0"); - r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, + r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); if (r) return r; ring = &adev->vce.ring[1]; sprintf(ring->name, "vce1"); - r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, + r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); if (r) return r; @@ -564,73 +566,6 @@ static int vce_v3_0_soft_reset(void *handle) return vce_v3_0_start(adev); } -static void vce_v3_0_print_status(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "VCE 3.0 registers\n"); - dev_info(adev->dev, " VCE_STATUS=0x%08X\n", - RREG32(mmVCE_STATUS)); - dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n", - RREG32(mmVCE_VCPU_CNTL)); - dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_OFFSET0)); - dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_SIZE0)); - dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_OFFSET1)); - dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_SIZE1)); - dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_OFFSET2)); - dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n", - RREG32(mmVCE_VCPU_CACHE_SIZE2)); - dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n", - RREG32(mmVCE_SOFT_RESET)); - dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n", - RREG32(mmVCE_RB_BASE_LO2)); - dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n", - RREG32(mmVCE_RB_BASE_HI2)); - dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n", - RREG32(mmVCE_RB_SIZE2)); - dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n", - RREG32(mmVCE_RB_RPTR2)); - dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n", - RREG32(mmVCE_RB_WPTR2)); - dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n", - RREG32(mmVCE_RB_BASE_LO)); - dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n", - RREG32(mmVCE_RB_BASE_HI)); - dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n", - RREG32(mmVCE_RB_SIZE)); - dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n", - RREG32(mmVCE_RB_RPTR)); - dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n", - RREG32(mmVCE_RB_WPTR)); - dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n", - RREG32(mmVCE_CLOCK_GATING_A)); - dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n", - RREG32(mmVCE_CLOCK_GATING_B)); - dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n", - RREG32(mmVCE_UENC_CLOCK_GATING)); - dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n", - RREG32(mmVCE_UENC_REG_CLOCK_GATING)); - dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n", - RREG32(mmVCE_SYS_INT_EN)); - dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n", - RREG32(mmVCE_LMI_CTRL2)); - dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n", - RREG32(mmVCE_LMI_CTRL)); - dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n", - RREG32(mmVCE_LMI_VM_CTRL)); - dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n", - RREG32(mmVCE_LMI_SWAP_CNTL)); - dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n", - RREG32(mmVCE_LMI_SWAP_CNTL1)); - dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n", - RREG32(mmVCE_LMI_CACHE_CTRL)); -} - static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, @@ -739,6 +674,7 @@ static int vce_v3_0_set_powergating_state(void *handle, } const struct amd_ip_funcs vce_v3_0_ip_funcs = { + .name = "vce_v3_0", .early_init = vce_v3_0_early_init, .late_init = NULL, .sw_init = vce_v3_0_sw_init, @@ -750,7 +686,6 @@ const struct amd_ip_funcs vce_v3_0_ip_funcs = { .is_idle = vce_v3_0_is_idle, .wait_for_idle = vce_v3_0_wait_for_idle, .soft_reset = vce_v3_0_soft_reset, - .print_status = vce_v3_0_print_status, .set_clockgating_state = vce_v3_0_set_clockgating_state, .set_powergating_state = vce_v3_0_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 1c120efa292c..2c88d0b66cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -78,6 +78,11 @@ #include "amdgpu_acp.h" #endif +MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_smc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin"); + /* * Indirect registers accessor */ @@ -276,6 +281,8 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) stoney_mgcg_cgcg_init, (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); break; + case CHIP_POLARIS11: + case CHIP_POLARIS10: default: break; } @@ -414,11 +421,11 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, return true; } -static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { +static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { {mmGB_MACROTILE_MODE7, true}, }; -static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { +static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { {mmGB_TILE_MODE7, true}, {mmGB_TILE_MODE12, true}, {mmGB_TILE_MODE17, true}, @@ -426,7 +433,7 @@ static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { {mmGB_MACROTILE_MODE7, true}, }; -static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { +static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { {mmGRBM_STATUS, false}, {mmGRBM_STATUS2, false}, {mmGRBM_STATUS_SE0, false}, @@ -525,8 +532,8 @@ static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, static int vi_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) { - struct amdgpu_allowed_register_entry *asic_register_table = NULL; - struct amdgpu_allowed_register_entry *asic_register_entry; + const struct amdgpu_allowed_register_entry *asic_register_table = NULL; + const struct amdgpu_allowed_register_entry *asic_register_entry; uint32_t size, i; *value = 0; @@ -537,6 +544,8 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, break; case CHIP_FIJI: case CHIP_TONGA: + case CHIP_POLARIS11: + case CHIP_POLARIS10: case CHIP_CARRIZO: case CHIP_STONEY: asic_register_table = cz_allowed_read_registers; @@ -907,6 +916,74 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] = }, }; +static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMD_IP_BLOCK_TYPE_COMMON, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vi_common_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 8, + .minor = 1, + .rev = 0, + .funcs = &gmc_v8_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 3, + .minor = 1, + .rev = 0, + .funcs = &tonga_ih_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 2, + .rev = 0, + .funcs = &amdgpu_pp_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 11, + .minor = 2, + .rev = 0, + .funcs = &dce_v11_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gfx_v8_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 3, + .minor = 1, + .rev = 0, + .funcs = &sdma_v3_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 6, + .minor = 3, + .rev = 0, + .funcs = &uvd_v6_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 3, + .minor = 4, + .rev = 0, + .funcs = &vce_v3_0_ip_funcs, + }, +}; + static const struct amdgpu_ip_block_version cz_ip_blocks[] = { /* ORDER MATTERS! */ @@ -999,6 +1076,11 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) adev->ip_blocks = tonga_ip_blocks; adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); break; + case CHIP_POLARIS11: + case CHIP_POLARIS10: + adev->ip_blocks = polaris11_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks); + break; case CHIP_CARRIZO: case CHIP_STONEY: adev->ip_blocks = cz_ip_blocks; @@ -1036,7 +1118,6 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = .get_xclk = &vi_get_xclk, .set_uvd_clocks = &vi_set_uvd_clocks, .set_vce_clocks = &vi_set_vce_clocks, - .get_cu_info = &gfx_v8_0_get_cu_info, /* these should be moved to their own ip modules */ .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle, @@ -1076,19 +1157,69 @@ static int vi_common_early_init(void *handle) adev->external_rev_id = 0x1; break; case CHIP_FIJI: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_CGTS | + AMD_CG_SUPPORT_GFX_CGTS_LS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_ROM_MGCG | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x3c; break; case CHIP_TONGA: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x14; break; - case CHIP_CARRIZO: - case CHIP_STONEY: + case CHIP_POLARIS11: adev->cg_flags = 0; adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x5A; + break; + case CHIP_POLARIS10: + adev->cg_flags = 0; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x50; + break; + case CHIP_CARRIZO: + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | + AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_CGTS | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CGTS_LS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x1; + break; + case CHIP_STONEY: + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | + AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS; + adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x1; break; default: @@ -1164,24 +1295,19 @@ static int vi_common_wait_for_idle(void *handle) return 0; } -static void vi_common_print_status(void *handle) -{ - return; -} - static int vi_common_soft_reset(void *handle) { return 0; } -static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, - bool enable) +static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) { uint32_t temp, data; temp = data = RREG32_PCIE(ixPCIE_CNTL2); - if (enable) + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | PCIE_CNTL2__MST_MEM_LS_EN_MASK | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; @@ -1194,14 +1320,14 @@ static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, WREG32_PCIE(ixPCIE_CNTL2, data); } -static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, - bool enable) +static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) { uint32_t temp, data; temp = data = RREG32(mmHDP_HOST_PATH_CNTL); - if (enable) + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; else data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; @@ -1210,14 +1336,14 @@ static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev WREG32(mmHDP_HOST_PATH_CNTL, data); } -static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev, - bool enable) +static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, + bool enable) { uint32_t temp, data; temp = data = RREG32(mmHDP_MEM_POWER_LS); - if (enable) + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; else data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; @@ -1226,14 +1352,14 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev, WREG32(mmHDP_MEM_POWER_LS, data); } -static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, - bool enable) +static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) { uint32_t temp, data; temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); - if (enable) + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); else @@ -1245,19 +1371,28 @@ static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev } static int vi_common_set_clockgating_state(void *handle, - enum amd_clockgating_state state) + enum amd_clockgating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; switch (adev->asic_type) { case CHIP_FIJI: - fiji_update_bif_medium_grain_light_sleep(adev, + vi_update_bif_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE ? true : false); - fiji_update_hdp_medium_grain_clock_gating(adev, + vi_update_hdp_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); - fiji_update_hdp_light_sleep(adev, + vi_update_hdp_light_sleep(adev, state == AMD_CG_STATE_GATE ? true : false); - fiji_update_rom_medium_grain_clock_gating(adev, + vi_update_rom_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + break; + case CHIP_CARRIZO: + case CHIP_STONEY: + vi_update_bif_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + vi_update_hdp_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + vi_update_hdp_light_sleep(adev, state == AMD_CG_STATE_GATE ? true : false); break; default: @@ -1273,6 +1408,7 @@ static int vi_common_set_powergating_state(void *handle, } const struct amd_ip_funcs vi_common_ip_funcs = { + .name = "vi_common", .early_init = vi_common_early_init, .late_init = NULL, .sw_init = vi_common_sw_init, @@ -1284,7 +1420,6 @@ const struct amd_ip_funcs vi_common_ip_funcs = { .is_idle = vi_common_is_idle, .wait_for_idle = vi_common_wait_for_idle, .soft_reset = vi_common_soft_reset, - .print_status = vi_common_print_status, .set_clockgating_state = vi_common_set_clockgating_state, .set_powergating_state = vi_common_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h index ace49976f7be..062ee1676480 100644 --- a/drivers/gpu/drm/amd/amdgpu/vid.h +++ b/drivers/gpu/drm/amd/amdgpu/vid.h @@ -54,7 +54,8 @@ #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8) #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8) #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8) -#define AUD6_REGISTER_OFFSET (0x17c4 - 0x17a8) +#define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8) +#define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8) /* hpd instance offsets */ #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898) @@ -365,7 +366,7 @@ #define VCE_CMD_IB 0x00000002 #define VCE_CMD_FENCE 0x00000003 #define VCE_CMD_TRAP 0x00000004 -#define VCE_CMD_IB_AUTO 0x00000005 +#define VCE_CMD_IB_AUTO 0x00000005 #define VCE_CMD_SEMAPHORE 0x00000006 #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 07ac724e3ec9..ee3e04e10dae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -109,7 +109,7 @@ static int kfd_open(struct inode *inode, struct file *filep) is_32bit_user_mode = in_compat_syscall(); - if (is_32bit_user_mode == true) { + if (is_32bit_user_mode) { dev_warn(kfd_device, "Process %d (32-bit) failed to open /dev/kfd\n" "32-bit processes are not supported by amdkfd\n", @@ -131,12 +131,11 @@ static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, void *data) { struct kfd_ioctl_get_version_args *args = data; - int err = 0; args->major_version = KFD_IOCTL_MAJOR_VERSION; args->minor_version = KFD_IOCTL_MINOR_VERSION; - return err; + return 0; } static int set_queue_properties_from_user(struct queue_properties *q_properties, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 4bb7f4223762..f49c551195b3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -216,7 +216,7 @@ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) } } - if (set == false) + if (!set) return -EBUSY; pr_debug("kfd: DQM %s hqd slot - pipe (%d) queue(%d)\n", @@ -354,7 +354,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q) return -ENOMEM; } - if (q->properties.is_active == true) + if (q->properties.is_active) prev_active = true; /* @@ -363,9 +363,9 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q) * and modify counter accordingly */ retval = mqd->update_mqd(mqd, q->mqd, &q->properties); - if ((q->properties.is_active == true) && (prev_active == false)) + if ((q->properties.is_active) && (!prev_active)) dqm->queue_count++; - else if ((q->properties.is_active == false) && (prev_active == true)) + else if ((!q->properties.is_active) && (prev_active)) dqm->queue_count--; if (sched_policy != KFD_SCHED_POLICY_NO_HWS) @@ -954,7 +954,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, if (lock) mutex_lock(&dqm->lock); - if (dqm->active_runlist == false) + if (!dqm->active_runlist) goto out; pr_debug("kfd: Before destroying queues, sdma queue count is : %u\n", diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index b6e28dcaea1d..a6a4b2b1c0d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -177,9 +177,9 @@ static bool allocate_event_notification_slot(struct file *devkfd, bool ret; ret = allocate_free_slot(p, page, signal_slot_index); - if (ret == false) { + if (!ret) { ret = allocate_signal_page(devkfd, p); - if (ret == true) + if (ret) ret = allocate_free_slot(p, page, signal_slot_index); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index 8fa894100290..9beae87aadd5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -300,7 +300,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, break; } - if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE) == false) { + if (!kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE)) { pr_err("amdkfd: failed to init kernel queue\n"); kfree(kq); return NULL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 90f391434fa3..ca8c09326b31 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -98,7 +98,7 @@ static int pm_allocate_runlist_ib(struct packet_manager *pm, int retval; BUG_ON(!pm); - BUG_ON(pm->allocated == true); + BUG_ON(pm->allocated); BUG_ON(is_over_subscription == NULL); pm_calc_rlib_size(pm, rl_buffer_size, is_over_subscription); @@ -292,7 +292,7 @@ static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, q->properties.doorbell_off; packet->mes_map_queues_ordinals[0].bitfields3.is_static = - (use_static == true) ? 1 : 0; + (use_static) ? 1 : 0; packet->mes_map_queues_ordinals[0].mqd_addr_lo = lower_32_bits(q->gart_mqd_addr); @@ -357,7 +357,7 @@ static int pm_create_runlist_ib(struct packet_manager *pm, alloc_size_bytes); list_for_each_entry(kq, &qpd->priv_queue_list, list) { - if (kq->queue->properties.is_active != true) + if (!kq->queue->properties.is_active) continue; pr_debug("kfd: static_queue, mapping kernel q %d, is debug status %d\n", @@ -383,7 +383,7 @@ static int pm_create_runlist_ib(struct packet_manager *pm, } list_for_each_entry(q, &qpd->queues_list, list) { - if (q->properties.is_active != true) + if (!q->properties.is_active) continue; pr_debug("kfd: static_queue, mapping user queue %d, is debug status %d\n", @@ -531,7 +531,7 @@ fail_create_runlist: fail_acquire_packet_buffer: mutex_unlock(&pm->lock); fail_create_runlist_ib: - if (pm->allocated == true) + if (pm->allocated) pm_release_ib(pm); return retval; } @@ -647,7 +647,7 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, default: BUG(); break; - }; + } pm->priv_queue->ops.submit_packet(pm->priv_queue); diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 04e4090666fb..6080951d539d 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -48,6 +48,8 @@ enum amd_asic_type { CHIP_FIJI, CHIP_CARRIZO, CHIP_STONEY, + CHIP_POLARIS10, + CHIP_POLARIS11, CHIP_LAST, }; @@ -104,6 +106,7 @@ enum amd_powergating_state { #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) #define AMD_CG_SUPPORT_HDP_LS (1 << 15) #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) +#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) /* PG flags */ #define AMD_PG_SUPPORT_GFX_PG (1 << 0) @@ -140,6 +143,8 @@ enum amd_pm_state_type { }; struct amd_ip_funcs { + /* Name of IP block */ + char *name; /* sets up early driver state (pre sw_init), does not configure hw - Optional */ int (*early_init)(void *handle); /* sets up late driver/hw state (post hw_init) - Optional */ @@ -162,8 +167,6 @@ struct amd_ip_funcs { int (*wait_for_idle)(void *handle); /* soft reset the IP block */ int (*soft_reset)(void *handle); - /* dump the IP block status registers */ - void (*print_status)(void *handle); /* enable/disable cg for the IP block */ int (*set_clockgating_state)(void *handle, enum amd_clockgating_state state); diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h new file mode 100755 index 000000000000..09a7df17570d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h @@ -0,0 +1,10075 @@ +/* + * DCE_11_2 Register documentation + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_11_2_D_H +#define DCE_11_2_D_H + +#define mmPIPE0_PG_CONFIG 0x2c0 +#define mmPIPE0_PG_ENABLE 0x2c1 +#define mmPIPE0_PG_STATUS 0x2c2 +#define mmPIPE1_PG_CONFIG 0x2c3 +#define mmPIPE1_PG_ENABLE 0x2c4 +#define mmPIPE1_PG_STATUS 0x2c5 +#define mmPIPE2_PG_CONFIG 0x2c6 +#define mmPIPE2_PG_ENABLE 0x2c7 +#define mmPIPE2_PG_STATUS 0x2c8 +#define mmPIPE3_PG_CONFIG 0x2c9 +#define mmPIPE3_PG_ENABLE 0x2ca +#define mmPIPE3_PG_STATUS 0x2cb +#define mmPIPE4_PG_CONFIG 0x2cc +#define mmPIPE4_PG_ENABLE 0x2cd +#define mmPIPE4_PG_STATUS 0x2ce +#define mmPIPE5_PG_CONFIG 0x2cf +#define mmPIPE5_PG_ENABLE 0x2d0 +#define mmPIPE5_PG_STATUS 0x2d1 +#define mmDCPG_INTERRUPT_STATUS 0x2de +#define mmDCPG_INTERRUPT_CONTROL 0x2df +#define mmDCPG_INTERRUPT_CONTROL2 0x2e0 +#define mmDC_IP_REQUEST_CNTL 0x2d2 +#define mmDC_PGFSM_CONFIG_REG 0x2d3 +#define mmDC_PGFSM_WRITE_REG 0x2d4 +#define mmDC_PGCNTL_STATUS_REG 0x2d5 +#define mmDCPG_TEST_DEBUG_INDEX 0x2d6 +#define mmDCPG_TEST_DEBUG_DATA 0x2d7 +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define mmBL1_PWM_USER_LEVEL 0x1629 +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d +#define mmBL1_PWM_ABM_CNTL 0x162e +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f +#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define mmDC_ABM1_CNTL 0x1638 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e +#define mmDC_ABM1_ACE_THRES_12 0x163f +#define mmDC_ABM1_ACE_THRES_34 0x1640 +#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define mmDC_ABM1_DEBUG_MISC 0x1649 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a +#define mmDC_ABM1_HG_MISC_CTRL 0x164b +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e +#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a +#define mmDC_ABM1_HG_RESULT_1 0x165b +#define mmDC_ABM1_HG_RESULT_2 0x165c +#define mmDC_ABM1_HG_RESULT_3 0x165d +#define mmDC_ABM1_HG_RESULT_4 0x165e +#define mmDC_ABM1_HG_RESULT_5 0x165f +#define mmDC_ABM1_HG_RESULT_6 0x1660 +#define mmDC_ABM1_HG_RESULT_7 0x1661 +#define mmDC_ABM1_HG_RESULT_8 0x1662 +#define mmDC_ABM1_HG_RESULT_9 0x1663 +#define mmDC_ABM1_HG_RESULT_10 0x1664 +#define mmDC_ABM1_HG_RESULT_11 0x1665 +#define mmDC_ABM1_HG_RESULT_12 0x1666 +#define mmDC_ABM1_HG_RESULT_13 0x1667 +#define mmDC_ABM1_HG_RESULT_14 0x1668 +#define mmDC_ABM1_HG_RESULT_15 0x1669 +#define mmDC_ABM1_HG_RESULT_16 0x166a +#define mmDC_ABM1_HG_RESULT_17 0x166b +#define mmDC_ABM1_HG_RESULT_18 0x166c +#define mmDC_ABM1_HG_RESULT_19 0x166d +#define mmDC_ABM1_HG_RESULT_20 0x166e +#define mmDC_ABM1_HG_RESULT_21 0x166f +#define mmDC_ABM1_HG_RESULT_22 0x1670 +#define mmDC_ABM1_HG_RESULT_23 0x1671 +#define mmDC_ABM1_HG_RESULT_24 0x1672 +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b +#define mmDC_ABM1_BL_MASTER_LOCK 0x169c +#define mmABM_TEST_DEBUG_INDEX 0x169e +#define mmABM_TEST_DEBUG_DATA 0x169f +#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d +#define mmCRTC_H_TOTAL 0x1b80 +#define mmCRTC0_CRTC_H_TOTAL 0x1b80 +#define mmCRTC1_CRTC_H_TOTAL 0x1d80 +#define mmCRTC2_CRTC_H_TOTAL 0x1f80 +#define mmCRTC3_CRTC_H_TOTAL 0x4180 +#define mmCRTC4_CRTC_H_TOTAL 0x4380 +#define mmCRTC5_CRTC_H_TOTAL 0x4580 +#define mmCRTC_H_BLANK_START_END 0x1b81 +#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 +#define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 +#define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 +#define mmCRTC3_CRTC_H_BLANK_START_END 0x4181 +#define mmCRTC4_CRTC_H_BLANK_START_END 0x4381 +#define mmCRTC5_CRTC_H_BLANK_START_END 0x4581 +#define mmCRTC_H_SYNC_A 0x1b82 +#define mmCRTC0_CRTC_H_SYNC_A 0x1b82 +#define mmCRTC1_CRTC_H_SYNC_A 0x1d82 +#define mmCRTC2_CRTC_H_SYNC_A 0x1f82 +#define mmCRTC3_CRTC_H_SYNC_A 0x4182 +#define mmCRTC4_CRTC_H_SYNC_A 0x4382 +#define mmCRTC5_CRTC_H_SYNC_A 0x4582 +#define mmCRTC_H_SYNC_A_CNTL 0x1b83 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 +#define mmCRTC_H_SYNC_B 0x1b84 +#define mmCRTC0_CRTC_H_SYNC_B 0x1b84 +#define mmCRTC1_CRTC_H_SYNC_B 0x1d84 +#define mmCRTC2_CRTC_H_SYNC_B 0x1f84 +#define mmCRTC3_CRTC_H_SYNC_B 0x4184 +#define mmCRTC4_CRTC_H_SYNC_B 0x4384 +#define mmCRTC5_CRTC_H_SYNC_B 0x4584 +#define mmCRTC_H_SYNC_B_CNTL 0x1b85 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 +#define mmCRTC_VBI_END 0x1b86 +#define mmCRTC0_CRTC_VBI_END 0x1b86 +#define mmCRTC1_CRTC_VBI_END 0x1d86 +#define mmCRTC2_CRTC_VBI_END 0x1f86 +#define mmCRTC3_CRTC_VBI_END 0x4186 +#define mmCRTC4_CRTC_VBI_END 0x4386 +#define mmCRTC5_CRTC_VBI_END 0x4586 +#define mmCRTC_V_TOTAL 0x1b87 +#define mmCRTC0_CRTC_V_TOTAL 0x1b87 +#define mmCRTC1_CRTC_V_TOTAL 0x1d87 +#define mmCRTC2_CRTC_V_TOTAL 0x1f87 +#define mmCRTC3_CRTC_V_TOTAL 0x4187 +#define mmCRTC4_CRTC_V_TOTAL 0x4387 +#define mmCRTC5_CRTC_V_TOTAL 0x4587 +#define mmCRTC_V_TOTAL_MIN 0x1b88 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 +#define mmCRTC_V_TOTAL_MAX 0x1b89 +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 +#define mmCRTC_V_TOTAL_CONTROL 0x1b8a +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a +#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b +#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c +#define mmCRTC_V_BLANK_START_END 0x1b8d +#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d +#define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d +#define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d +#define mmCRTC3_CRTC_V_BLANK_START_END 0x418d +#define mmCRTC4_CRTC_V_BLANK_START_END 0x438d +#define mmCRTC5_CRTC_V_BLANK_START_END 0x458d +#define mmCRTC_V_SYNC_A 0x1b8e +#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e +#define mmCRTC1_CRTC_V_SYNC_A 0x1d8e +#define mmCRTC2_CRTC_V_SYNC_A 0x1f8e +#define mmCRTC3_CRTC_V_SYNC_A 0x418e +#define mmCRTC4_CRTC_V_SYNC_A 0x438e +#define mmCRTC5_CRTC_V_SYNC_A 0x458e +#define mmCRTC_V_SYNC_A_CNTL 0x1b8f +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f +#define mmCRTC_V_SYNC_B 0x1b90 +#define mmCRTC0_CRTC_V_SYNC_B 0x1b90 +#define mmCRTC1_CRTC_V_SYNC_B 0x1d90 +#define mmCRTC2_CRTC_V_SYNC_B 0x1f90 +#define mmCRTC3_CRTC_V_SYNC_B 0x4190 +#define mmCRTC4_CRTC_V_SYNC_B 0x4390 +#define mmCRTC5_CRTC_V_SYNC_B 0x4590 +#define mmCRTC_V_SYNC_B_CNTL 0x1b91 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 +#define mmCRTC_DTMTEST_CNTL 0x1b92 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 +#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 +#define mmCRTC_TRIGA_CNTL 0x1b94 +#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 +#define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 +#define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 +#define mmCRTC3_CRTC_TRIGA_CNTL 0x4194 +#define mmCRTC4_CRTC_TRIGA_CNTL 0x4394 +#define mmCRTC5_CRTC_TRIGA_CNTL 0x4594 +#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 +#define mmCRTC_TRIGB_CNTL 0x1b96 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x4196 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x4396 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x4596 +#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 +#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 +#define mmCRTC_FLOW_CONTROL 0x1b99 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x4199 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x4399 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x4599 +#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a +#define mmCRTC_AVSYNC_COUNTER 0x1b9b +#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b +#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b +#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b +#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b +#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b +#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b +#define mmCRTC_CONTROL 0x1b9c +#define mmCRTC0_CRTC_CONTROL 0x1b9c +#define mmCRTC1_CRTC_CONTROL 0x1d9c +#define mmCRTC2_CRTC_CONTROL 0x1f9c +#define mmCRTC3_CRTC_CONTROL 0x419c +#define mmCRTC4_CRTC_CONTROL 0x439c +#define mmCRTC5_CRTC_CONTROL 0x459c +#define mmCRTC_BLANK_CONTROL 0x1b9d +#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d +#define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d +#define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d +#define mmCRTC3_CRTC_BLANK_CONTROL 0x419d +#define mmCRTC4_CRTC_BLANK_CONTROL 0x439d +#define mmCRTC5_CRTC_BLANK_CONTROL 0x459d +#define mmCRTC_INTERLACE_CONTROL 0x1b9e +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e +#define mmCRTC_INTERLACE_STATUS 0x1b9f +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f +#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 +#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 +#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 +#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 +#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 +#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 +#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 +#define mmCRTC_STATUS 0x1ba3 +#define mmCRTC0_CRTC_STATUS 0x1ba3 +#define mmCRTC1_CRTC_STATUS 0x1da3 +#define mmCRTC2_CRTC_STATUS 0x1fa3 +#define mmCRTC3_CRTC_STATUS 0x41a3 +#define mmCRTC4_CRTC_STATUS 0x43a3 +#define mmCRTC5_CRTC_STATUS 0x45a3 +#define mmCRTC_STATUS_POSITION 0x1ba4 +#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 +#define mmCRTC1_CRTC_STATUS_POSITION 0x1da4 +#define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 +#define mmCRTC3_CRTC_STATUS_POSITION 0x41a4 +#define mmCRTC4_CRTC_STATUS_POSITION 0x43a4 +#define mmCRTC5_CRTC_STATUS_POSITION 0x45a4 +#define mmCRTC_NOM_VERT_POSITION 0x1ba5 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 +#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 +#define mmCRTC_STATUS_VF_COUNT 0x1ba7 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 +#define mmCRTC_STATUS_HV_COUNT 0x1ba8 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 +#define mmCRTC_COUNT_CONTROL 0x1ba9 +#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 +#define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 +#define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 +#define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 +#define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 +#define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 +#define mmCRTC_COUNT_RESET 0x1baa +#define mmCRTC0_CRTC_COUNT_RESET 0x1baa +#define mmCRTC1_CRTC_COUNT_RESET 0x1daa +#define mmCRTC2_CRTC_COUNT_RESET 0x1faa +#define mmCRTC3_CRTC_COUNT_RESET 0x41aa +#define mmCRTC4_CRTC_COUNT_RESET 0x43aa +#define mmCRTC5_CRTC_COUNT_RESET 0x45aa +#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab +#define mmCRTC_VERT_SYNC_CONTROL 0x1bac +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac +#define mmCRTC_STEREO_STATUS 0x1bad +#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad +#define mmCRTC1_CRTC_STEREO_STATUS 0x1dad +#define mmCRTC2_CRTC_STEREO_STATUS 0x1fad +#define mmCRTC3_CRTC_STEREO_STATUS 0x41ad +#define mmCRTC4_CRTC_STEREO_STATUS 0x43ad +#define mmCRTC5_CRTC_STEREO_STATUS 0x45ad +#define mmCRTC_STEREO_CONTROL 0x1bae +#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae +#define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae +#define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae +#define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae +#define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae +#define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae +#define mmCRTC_SNAPSHOT_STATUS 0x1baf +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af +#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 +#define mmCRTC_SNAPSHOT_POSITION 0x1bb1 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 +#define mmCRTC_SNAPSHOT_FRAME 0x1bb2 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 +#define mmCRTC_START_LINE_CONTROL 0x1bb3 +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 +#define mmCRTC_INTERRUPT_CONTROL 0x1bb4 +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 +#define mmCRTC_UPDATE_LOCK 0x1bb5 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 +#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 +#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 +#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba +#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb +#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc +#define mmCRTC_MASTER_UPDATE_LOCK 0x1bbd +#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd +#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd +#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd +#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd +#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd +#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd +#define mmCRTC_MASTER_UPDATE_MODE 0x1bbe +#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe +#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe +#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe +#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be +#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be +#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be +#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf +#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 +#define mmCRTC_MVP_STATUS 0x1bc1 +#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 +#define mmCRTC1_CRTC_MVP_STATUS 0x1dc1 +#define mmCRTC2_CRTC_MVP_STATUS 0x1fc1 +#define mmCRTC3_CRTC_MVP_STATUS 0x41c1 +#define mmCRTC4_CRTC_MVP_STATUS 0x43c1 +#define mmCRTC5_CRTC_MVP_STATUS 0x45c1 +#define mmCRTC_MASTER_EN 0x1bc2 +#define mmCRTC0_CRTC_MASTER_EN 0x1bc2 +#define mmCRTC1_CRTC_MASTER_EN 0x1dc2 +#define mmCRTC2_CRTC_MASTER_EN 0x1fc2 +#define mmCRTC3_CRTC_MASTER_EN 0x41c2 +#define mmCRTC4_CRTC_MASTER_EN 0x43c2 +#define mmCRTC5_CRTC_MASTER_EN 0x45c2 +#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 +#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 +#define mmCRTC_OVERSCAN_COLOR 0x1bc8 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 +#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 +#define mmCRTC_BLANK_DATA_COLOR 0x1bca +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca +#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb +#define mmCRTC_BLACK_COLOR 0x1bcc +#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc +#define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc +#define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc +#define mmCRTC3_CRTC_BLACK_COLOR 0x41cc +#define mmCRTC4_CRTC_BLACK_COLOR 0x43cc +#define mmCRTC5_CRTC_BLACK_COLOR 0x45cc +#define mmCRTC_BLACK_COLOR_EXT 0x1bcd +#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd +#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd +#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd +#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd +#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd +#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd +#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce +#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf +#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 +#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 +#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 +#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 +#define mmCRTC_CRC_CNTL 0x1bd4 +#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 +#define mmCRTC1_CRTC_CRC_CNTL 0x1dd4 +#define mmCRTC2_CRTC_CRC_CNTL 0x1fd4 +#define mmCRTC3_CRTC_CRC_CNTL 0x41d4 +#define mmCRTC4_CRTC_CRC_CNTL 0x43d4 +#define mmCRTC5_CRTC_CRC_CNTL 0x45d4 +#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 +#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 +#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 +#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 +#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 +#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 +#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 +#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 +#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 +#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 +#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 +#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 +#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 +#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 +#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 +#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 +#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 +#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 +#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 +#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 +#define mmCRTC_CRC0_DATA_RG 0x1bd9 +#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 +#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 +#define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 +#define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 +#define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 +#define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 +#define mmCRTC_CRC0_DATA_B 0x1bda +#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda +#define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda +#define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda +#define mmCRTC3_CRTC_CRC0_DATA_B 0x41da +#define mmCRTC4_CRTC_CRC0_DATA_B 0x43da +#define mmCRTC5_CRTC_CRC0_DATA_B 0x45da +#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb +#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb +#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db +#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db +#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db +#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc +#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc +#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc +#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc +#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc +#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd +#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd +#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd +#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd +#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd +#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde +#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde +#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de +#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de +#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de +#define mmCRTC_CRC1_DATA_RG 0x1bdf +#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf +#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf +#define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf +#define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df +#define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df +#define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df +#define mmCRTC_CRC1_DATA_B 0x1be0 +#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 +#define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 +#define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 +#define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 +#define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 +#define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 +#define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1de1 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x1fe1 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x43e1 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x45e1 +#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1de2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1fe2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x43e2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x45e2 +#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1de3 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1fe3 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x43e3 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x45e3 +#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1de4 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1fe4 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x43e4 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x45e4 +#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1de5 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1fe5 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x43e5 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x45e5 +#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1de6 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1fe6 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x43e6 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x45e6 +#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 +#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 +#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 +#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 +#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 +#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 +#define mmCRTC_GSL_VSYNC_GAP 0x1b79 +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 +#define mmCRTC_GSL_WINDOW 0x1b7a +#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a +#define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a +#define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a +#define mmCRTC3_CRTC_GSL_WINDOW 0x417a +#define mmCRTC4_CRTC_GSL_WINDOW 0x437a +#define mmCRTC5_CRTC_GSL_WINDOW 0x457a +#define mmCRTC_GSL_CONTROL 0x1b7b +#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b +#define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b +#define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b +#define mmCRTC3_CRTC_GSL_CONTROL 0x417b +#define mmCRTC4_CRTC_GSL_CONTROL 0x437b +#define mmCRTC5_CRTC_GSL_CONTROL 0x457b +#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 +#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 +#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 +#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 +#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 +#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 +#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 +#define mmCRTC_TEST_DEBUG_DATA 0x1bc7 +#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 +#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 +#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 +#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 +#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 +#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 +#define mmDAC_ENABLE 0x16aa +#define mmDAC_SOURCE_SELECT 0x16ab +#define mmDAC_CRC_EN 0x16ac +#define mmDAC_CRC_CONTROL 0x16ad +#define mmDAC_CRC_SIG_RGB_MASK 0x16ae +#define mmDAC_CRC_SIG_CONTROL_MASK 0x16af +#define mmDAC_CRC_SIG_RGB 0x16b0 +#define mmDAC_CRC_SIG_CONTROL 0x16b1 +#define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 +#define mmDAC_STEREOSYNC_SELECT 0x16b3 +#define mmDAC_AUTODETECT_CONTROL 0x16b4 +#define mmDAC_AUTODETECT_CONTROL2 0x16b5 +#define mmDAC_AUTODETECT_CONTROL3 0x16b6 +#define mmDAC_AUTODETECT_STATUS 0x16b7 +#define mmDAC_AUTODETECT_INT_CONTROL 0x16b8 +#define mmDAC_FORCE_OUTPUT_CNTL 0x16b9 +#define mmDAC_FORCE_DATA 0x16ba +#define mmDAC_POWERDOWN 0x16bb +#define mmDAC_CONTROL 0x16bc +#define mmDAC_COMPARATOR_ENABLE 0x16bd +#define mmDAC_COMPARATOR_OUTPUT 0x16be +#define mmDAC_PWR_CNTL 0x16bf +#define mmDAC_DFT_CONFIG 0x16c0 +#define mmDAC_FIFO_STATUS 0x16c1 +#define mmDAC_TEST_DEBUG_INDEX 0x16c2 +#define mmDAC_TEST_DEBUG_DATA 0x16c3 +#define mmPERFCOUNTER_CNTL 0x170 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x358 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x364 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x18c8 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1b24 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1d24 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x1f24 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4124 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4324 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4524 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x4724 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x59a0 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x5f68 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x9924 +#define mmPERFCOUNTER_STATE 0x171 +#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 +#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x359 +#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x365 +#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x18c9 +#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1b25 +#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1d25 +#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x1f25 +#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4125 +#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4325 +#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4525 +#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x4725 +#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x59a1 +#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x5f69 +#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x9925 +#define mmPERFMON_CNTL 0x173 +#define mmDC_PERFMON0_PERFMON_CNTL 0x173 +#define mmDC_PERFMON1_PERFMON_CNTL 0x35b +#define mmDC_PERFMON2_PERFMON_CNTL 0x367 +#define mmDC_PERFMON3_PERFMON_CNTL 0x18cb +#define mmDC_PERFMON4_PERFMON_CNTL 0x1b27 +#define mmDC_PERFMON5_PERFMON_CNTL 0x1d27 +#define mmDC_PERFMON6_PERFMON_CNTL 0x1f27 +#define mmDC_PERFMON7_PERFMON_CNTL 0x4127 +#define mmDC_PERFMON8_PERFMON_CNTL 0x4327 +#define mmDC_PERFMON9_PERFMON_CNTL 0x4527 +#define mmDC_PERFMON10_PERFMON_CNTL 0x4727 +#define mmDC_PERFMON11_PERFMON_CNTL 0x59a3 +#define mmDC_PERFMON12_PERFMON_CNTL 0x5f6b +#define mmDC_PERFMON13_PERFMON_CNTL 0x9927 +#define mmPERFMON_CNTL2 0x17a +#define mmDC_PERFMON0_PERFMON_CNTL2 0x17a +#define mmDC_PERFMON1_PERFMON_CNTL2 0x362 +#define mmDC_PERFMON2_PERFMON_CNTL2 0x36e +#define mmDC_PERFMON3_PERFMON_CNTL2 0x18d2 +#define mmDC_PERFMON4_PERFMON_CNTL2 0x1b2e +#define mmDC_PERFMON5_PERFMON_CNTL2 0x1d2e +#define mmDC_PERFMON6_PERFMON_CNTL2 0x1f2e +#define mmDC_PERFMON7_PERFMON_CNTL2 0x412e +#define mmDC_PERFMON8_PERFMON_CNTL2 0x432e +#define mmDC_PERFMON9_PERFMON_CNTL2 0x452e +#define mmDC_PERFMON10_PERFMON_CNTL2 0x472e +#define mmDC_PERFMON11_PERFMON_CNTL2 0x59aa +#define mmDC_PERFMON12_PERFMON_CNTL2 0x5f72 +#define mmDC_PERFMON13_PERFMON_CNTL2 0x992e +#define mmPERFMON_CVALUE_INT_MISC 0x172 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x35a +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x366 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x18ca +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1b26 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1d26 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x1f26 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4126 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4326 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4526 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x4726 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x59a2 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x5f6a +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x9926 +#define mmPERFMON_CVALUE_LOW 0x174 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x35c +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x368 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x18cc +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1b28 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1d28 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x1f28 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4128 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4328 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4528 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x4728 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x59a4 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x5f6c +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x9928 +#define mmPERFMON_HI 0x175 +#define mmDC_PERFMON0_PERFMON_HI 0x175 +#define mmDC_PERFMON1_PERFMON_HI 0x35d +#define mmDC_PERFMON2_PERFMON_HI 0x369 +#define mmDC_PERFMON3_PERFMON_HI 0x18cd +#define mmDC_PERFMON4_PERFMON_HI 0x1b29 +#define mmDC_PERFMON5_PERFMON_HI 0x1d29 +#define mmDC_PERFMON6_PERFMON_HI 0x1f29 +#define mmDC_PERFMON7_PERFMON_HI 0x4129 +#define mmDC_PERFMON8_PERFMON_HI 0x4329 +#define mmDC_PERFMON9_PERFMON_HI 0x4529 +#define mmDC_PERFMON10_PERFMON_HI 0x4729 +#define mmDC_PERFMON11_PERFMON_HI 0x59a5 +#define mmDC_PERFMON12_PERFMON_HI 0x5f6d +#define mmDC_PERFMON13_PERFMON_HI 0x9929 +#define mmPERFMON_LOW 0x176 +#define mmDC_PERFMON0_PERFMON_LOW 0x176 +#define mmDC_PERFMON1_PERFMON_LOW 0x35e +#define mmDC_PERFMON2_PERFMON_LOW 0x36a +#define mmDC_PERFMON3_PERFMON_LOW 0x18ce +#define mmDC_PERFMON4_PERFMON_LOW 0x1b2a +#define mmDC_PERFMON5_PERFMON_LOW 0x1d2a +#define mmDC_PERFMON6_PERFMON_LOW 0x1f2a +#define mmDC_PERFMON7_PERFMON_LOW 0x412a +#define mmDC_PERFMON8_PERFMON_LOW 0x432a +#define mmDC_PERFMON9_PERFMON_LOW 0x452a +#define mmDC_PERFMON10_PERFMON_LOW 0x472a +#define mmDC_PERFMON11_PERFMON_LOW 0x59a6 +#define mmDC_PERFMON12_PERFMON_LOW 0x5f6e +#define mmDC_PERFMON13_PERFMON_LOW 0x992a +#define mmPERFMON_TEST_DEBUG_INDEX 0x177 +#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 +#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x35f +#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x36b +#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x18cf +#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1b2b +#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1d2b +#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x1f2b +#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x412b +#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x432b +#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x452b +#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x472b +#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x59a7 +#define mmDC_PERFMON12_PERFMON_TEST_DEBUG_INDEX 0x5f6f +#define mmDC_PERFMON13_PERFMON_TEST_DEBUG_INDEX 0x992b +#define mmPERFMON_TEST_DEBUG_DATA 0x178 +#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 +#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x360 +#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x36c +#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x18d0 +#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1b2c +#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1d2c +#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x1f2c +#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x412c +#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x432c +#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x452c +#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x472c +#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x59a8 +#define mmDC_PERFMON12_PERFMON_TEST_DEBUG_DATA 0x5f70 +#define mmDC_PERFMON13_PERFMON_TEST_DEBUG_DATA 0x992c +#define mmREFCLK_CNTL 0x109 +#define mmDCCG_CBUS_ANTIGLITCH_RESETB 0x15c +#define mmDCCG_CBUS_SPARE 0x15d +#define mmDCCG_CBUS_WRCMD_DELAY 0x110 +#define mmDPREFCLK_CNTL 0x118 +#define mmDCE_VERSION 0x11e +#define mmAVSYNC_COUNTER_WRITE 0x12a +#define mmAVSYNC_COUNTER_CONTROL 0x12b +#define mmAVSYNC_COUNTER_READ 0x12f +#define mmDCCG_GTC_CNTL 0x120 +#define mmDCCG_GTC_DTO_INCR 0x121 +#define mmDCCG_GTC_DTO_MODULO 0x122 +#define mmDCCG_GTC_CURRENT 0x123 +#define mmDCCG_DS_DTO_INCR 0x113 +#define mmDCCG_DS_DTO_MODULO 0x114 +#define mmDCCG_DS_CNTL 0x115 +#define mmDCCG_DS_HW_CAL_INTERVAL 0x116 +#define mmDCCG_DS_DEBUG_CNTL 0x112 +#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c +#define mmSMU_CONTROL 0x12d +#define mmSMU_INTERRUPT_CONTROL 0x12e +#define mmDAC_CLK_ENABLE 0x128 +#define mmDVO_CLK_ENABLE 0x129 +#define mmDCCG_GATE_DISABLE_CNTL 0x134 +#define mmDCCG_GATE_DISABLE_CNTL2 0x13c +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 +#define mmSCLK_CGTT_BLK_CTRL_REG 0x136 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 +#define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b +#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d +#define mmDCCG_CAC_STATUS 0x137 +#define mmPIXCLK0_RESYNC_CNTL 0x13a +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x100 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x101 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x102 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x103 +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x10c +#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x13e +#define mmMICROSECOND_TIME_BASE_DIV 0x13b +#define mmDCCG_DISP_CNTL_REG 0x13f +#define mmMILLISECOND_TIME_BASE_DIV 0x130 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 +#define mmDCCG_PERFMON_CNTL 0x133 +#define mmDCCG_PERFMON_CNTL2 0x10e +#define mmCRTC0_PIXEL_RATE_CNTL 0x140 +#define mmDP_DTO0_PHASE 0x141 +#define mmDP_DTO0_MODULO 0x142 +#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x143 +#define mmCRTC1_PIXEL_RATE_CNTL 0x144 +#define mmDP_DTO1_PHASE 0x145 +#define mmDP_DTO1_MODULO 0x146 +#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x147 +#define mmCRTC2_PIXEL_RATE_CNTL 0x148 +#define mmDP_DTO2_PHASE 0x149 +#define mmDP_DTO2_MODULO 0x14a +#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x14b +#define mmCRTC3_PIXEL_RATE_CNTL 0x14c +#define mmDP_DTO3_PHASE 0x14d +#define mmDP_DTO3_MODULO 0x14e +#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x14f +#define mmCRTC4_PIXEL_RATE_CNTL 0x150 +#define mmDP_DTO4_PHASE 0x151 +#define mmDP_DTO4_MODULO 0x152 +#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x153 +#define mmCRTC5_PIXEL_RATE_CNTL 0x154 +#define mmDP_DTO5_PHASE 0x155 +#define mmDP_DTO5_MODULO 0x156 +#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x157 +#define mmDCCG_SOFT_RESET 0x15f +#define mmSYMCLKA_CLOCK_ENABLE 0x160 +#define mmSYMCLKB_CLOCK_ENABLE 0x161 +#define mmSYMCLKC_CLOCK_ENABLE 0x162 +#define mmSYMCLKD_CLOCK_ENABLE 0x163 +#define mmSYMCLKE_CLOCK_ENABLE 0x164 +#define mmSYMCLKF_CLOCK_ENABLE 0x165 +#define mmDPDBG_CLK_FORCE_CONTROL 0x10d +#define mmDCCG_AUDIO_DTO_SOURCE 0x16b +#define mmDCCG_AUDIO_DTO0_PHASE 0x16c +#define mmDCCG_AUDIO_DTO0_MODULE 0x16d +#define mmDCCG_AUDIO_DTO1_PHASE 0x16e +#define mmDCCG_AUDIO_DTO1_MODULE 0x16f +#define mmDCCG_TEST_DEBUG_INDEX 0x17c +#define mmDCCG_TEST_DEBUG_DATA 0x17d +#define mmDCCG_TEST_CLK_SEL 0x17e +#define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 +#define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 +#define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 +#define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 +#define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 +#define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 +#define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa +#define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb +#define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc +#define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd +#define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe +#define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff +#define mmPLL_MACRO_CNTL_RESERVED0 0x1700 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 +#define mmPLL_MACRO_CNTL_RESERVED1 0x1701 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 +#define mmPLL_MACRO_CNTL_RESERVED2 0x1702 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 +#define mmPLL_MACRO_CNTL_RESERVED3 0x1703 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 +#define mmPLL_MACRO_CNTL_RESERVED4 0x1704 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 +#define mmPLL_MACRO_CNTL_RESERVED5 0x1705 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 +#define mmPLL_MACRO_CNTL_RESERVED6 0x1706 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a +#define mmPLL_MACRO_CNTL_RESERVED7 0x1707 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b +#define mmPLL_MACRO_CNTL_RESERVED8 0x1708 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c +#define mmPLL_MACRO_CNTL_RESERVED9 0x1709 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d +#define mmPLL_MACRO_CNTL_RESERVED10 0x170a +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e +#define mmPLL_MACRO_CNTL_RESERVED11 0x170b +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f +#define mmPLL_MACRO_CNTL_RESERVED12 0x170c +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 +#define mmPLL_MACRO_CNTL_RESERVED13 0x170d +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 +#define mmPLL_MACRO_CNTL_RESERVED14 0x170e +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 +#define mmPLL_MACRO_CNTL_RESERVED15 0x170f +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 +#define mmPLL_MACRO_CNTL_RESERVED16 0x1710 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 +#define mmPLL_MACRO_CNTL_RESERVED17 0x1711 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 +#define mmPLL_MACRO_CNTL_RESERVED18 0x1712 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 +#define mmPLL_MACRO_CNTL_RESERVED19 0x1713 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 +#define mmPLL_MACRO_CNTL_RESERVED20 0x1714 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 +#define mmPLL_MACRO_CNTL_RESERVED21 0x1715 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 +#define mmPLL_MACRO_CNTL_RESERVED22 0x1716 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a +#define mmPLL_MACRO_CNTL_RESERVED23 0x1717 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b +#define mmPLL_MACRO_CNTL_RESERVED24 0x1718 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c +#define mmPLL_MACRO_CNTL_RESERVED25 0x1719 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d +#define mmPLL_MACRO_CNTL_RESERVED26 0x171a +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e +#define mmPLL_MACRO_CNTL_RESERVED27 0x171b +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f +#define mmPLL_MACRO_CNTL_RESERVED28 0x171c +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 +#define mmPLL_MACRO_CNTL_RESERVED29 0x171d +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 +#define mmPLL_MACRO_CNTL_RESERVED30 0x171e +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 +#define mmPLL_MACRO_CNTL_RESERVED31 0x171f +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 +#define mmPLL_MACRO_CNTL_RESERVED32 0x1720 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 +#define mmPLL_MACRO_CNTL_RESERVED33 0x1721 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 +#define mmPLL_MACRO_CNTL_RESERVED34 0x1722 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 +#define mmPLL_MACRO_CNTL_RESERVED35 0x1723 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 +#define mmPLL_MACRO_CNTL_RESERVED36 0x1724 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 +#define mmPLL_MACRO_CNTL_RESERVED37 0x1725 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 +#define mmPLL_MACRO_CNTL_RESERVED38 0x1726 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a +#define mmPLL_MACRO_CNTL_RESERVED39 0x1727 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b +#define mmPLL_MACRO_CNTL_RESERVED40 0x1728 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c +#define mmPLL_MACRO_CNTL_RESERVED41 0x1729 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d +#define mmDENTIST_DISPCLK_CNTL 0x124 +#define mmDCDEBUG_BUS_CLK1_SEL 0x16c4 +#define mmDCDEBUG_BUS_CLK2_SEL 0x16c5 +#define mmDCDEBUG_BUS_CLK3_SEL 0x16c6 +#define mmDCDEBUG_BUS_CLK4_SEL 0x16c7 +#define mmDCDEBUG_BUS_CLK5_SEL 0x16c8 +#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 +#define mmDCDEBUG_OUT_CNTL 0x16ca +#define mmDCDEBUG_OUT_DATA 0x16cb +#define mmDMIF_CONTROL 0x2f6 +#define mmDMIF_STATUS 0x2f7 +#define mmDMIFV_STATUS 0x2f5 +#define mmDMIF_HW_DEBUG 0x2f8 +#define mmDMIF_ARBITRATION_CONTROL 0x2f9 +#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa +#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb +#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc +#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd +#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe +#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff +#define mmPIPE6_ARBITRATION_CONTROL3 0x32a +#define mmPIPE7_ARBITRATION_CONTROL3 0x32b +#define mmDMIF_P_VMID 0x300 +#define mmDMIF_URG_OVERRIDE 0x329 +#define mmDMIF_TEST_DEBUG_INDEX 0x301 +#define mmDMIF_TEST_DEBUG_DATA 0x302 +#define ixDMIF_DEBUG02_CORE0 0x2 +#define ixDMIF_DEBUG02_CORE1 0xa +#define mmDMIF_ADDR_CALC 0x303 +#define mmDMIF_STATUS2 0x304 +#define mmPIPE0_MAX_REQUESTS 0x305 +#define mmPIPE1_MAX_REQUESTS 0x306 +#define mmPIPE2_MAX_REQUESTS 0x307 +#define mmPIPE3_MAX_REQUESTS 0x308 +#define mmPIPE4_MAX_REQUESTS 0x309 +#define mmPIPE5_MAX_REQUESTS 0x30a +#define mmPIPE6_MAX_REQUESTS 0x32c +#define mmPIPE7_MAX_REQUESTS 0x32d +#define mmDVMM_REG_RD_STATUS 0x32e +#define mmDVMM_REG_RD_DATA 0x32f +#define mmDVMM_PTE_REQ 0x330 +#define mmDVMM_CNTL 0x331 +#define mmDVMM_FAULT_STATUS 0x332 +#define mmDVMM_FAULT_ADDR 0x333 +#define mmLOW_POWER_TILING_CONTROL 0x30b +#define mmMCIF_CONTROL 0x30c +#define mmMCIF_WRITE_COMBINE_CONTROL 0x30d +#define mmMCIF_TEST_DEBUG_INDEX 0x30e +#define mmMCIF_TEST_DEBUG_DATA 0x30f +#define ixIDDCCIF02_DBG_DCCIF_C 0x9 +#define ixIDDCCIF04_DBG_DCCIF_E 0xb +#define ixIDDCCIF05_DBG_DCCIF_F 0xc +#define mmMCIF_VMID 0x310 +#define mmMCIF_MEM_CONTROL 0x311 +#define mmCC_DC_PIPE_DIS 0x312 +#define mmMC_DC_INTERFACE_NACK_STATUS 0x313 +#define mmRBBMIF_TIMEOUT 0x314 +#define mmRBBMIF_STATUS 0x315 +#define mmRBBMIF_TIMEOUT_DIS 0x316 +#define mmRBBMIF_STATUS_FLAG 0x327 +#define mmDCI_MEM_PWR_STATUS 0x317 +#define mmDCI_MEM_PWR_STATUS2 0x318 +#define mmDCI_MEM_PWR_STATUS3 0x33d +#define mmDCI_CLK_CNTL 0x319 +#define mmDCI_CLK_RAMP_CNTL 0x31a +#define mmDCI_MEM_PWR_CNTL 0x31b +#define mmDCI_MEM_PWR_CNTL2 0x31c +#define mmDCI_MEM_PWR_CNTL3 0x31d +#define mmDCI_MEM_PWR_CNTL4 0x33b +#define mmDVMM_PTE_PGMEM_CONTROL 0x335 +#define mmDVMM_PTE_PGMEM_STATE 0x336 +#define mmDCI_SOFT_RESET 0x328 +#define mmDCI_MISC 0x33c +#define mmDCI_TEST_DEBUG_INDEX 0x31e +#define mmDCI_TEST_DEBUG_DATA 0x31f +#define mmDCI_DEBUG_CONFIG 0x320 +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x321 +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x322 +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x323 +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x324 +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x325 +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x326 +#define mmDC_GENERICA 0x4800 +#define mmDC_GENERICB 0x4801 +#define mmDC_PAD_EXTERN_SIG 0x4802 +#define mmDC_REF_CLK_CNTL 0x4803 +#define mmDC_GPIO_DEBUG 0x4804 +#define mmUNIPHYA_LINK_CNTL 0x4805 +#define mmUNIPHYB_LINK_CNTL 0x4807 +#define mmUNIPHYC_LINK_CNTL 0x4809 +#define mmUNIPHYD_LINK_CNTL 0x480b +#define mmUNIPHYE_LINK_CNTL 0x480d +#define mmUNIPHYF_LINK_CNTL 0x480f +#define mmUNIPHYG_LINK_CNTL 0x4811 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a +#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c +#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e +#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 +#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 +#define mmUNIPHYLPA_LINK_CNTL 0x4847 +#define mmUNIPHYLPB_LINK_CNTL 0x4848 +#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849 +#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a +#define mmUNIPHY_IMPCAL_LINKA 0x4838 +#define mmUNIPHY_IMPCAL_LINKB 0x4839 +#define mmUNIPHY_IMPCAL_LINKC 0x483f +#define mmUNIPHY_IMPCAL_LINKD 0x4840 +#define mmUNIPHY_IMPCAL_LINKE 0x4843 +#define mmUNIPHY_IMPCAL_LINKF 0x4844 +#define mmUNIPHY_IMPCAL_PERIOD 0x483a +#define mmAUXP_IMPCAL 0x483b +#define mmAUXN_IMPCAL 0x483c +#define mmDCIO_IMPCAL_CNTL 0x483d +#define mmUNIPHY_IMPCAL_PSW_AB 0x483e +#define mmDCIO_IMPCAL_CNTL_CD 0x4841 +#define mmUNIPHY_IMPCAL_PSW_CD 0x4842 +#define mmDCIO_IMPCAL_CNTL_EF 0x4845 +#define mmUNIPHY_IMPCAL_PSW_EF 0x4846 +#define mmDCIO_WRCMD_DELAY 0x4816 +#define mmDC_PINSTRAPS 0x4818 +#define mmDC_DVODATA_CONFIG 0x481a +#define mmLVTMA_PWRSEQ_CNTL 0x481b +#define mmLVTMA_PWRSEQ_STATE 0x481c +#define mmLVTMA_PWRSEQ_REF_DIV 0x481d +#define mmLVTMA_PWRSEQ_DELAY1 0x481e +#define mmLVTMA_PWRSEQ_DELAY2 0x481f +#define mmBL_PWM_CNTL 0x4820 +#define mmBL_PWM_CNTL2 0x4821 +#define mmBL_PWM_PERIOD_CNTL 0x4822 +#define mmBL_PWM_GRP1_REG_LOCK 0x4823 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 +#define mmDCIO_GSL0_CNTL 0x4826 +#define mmDCIO_GSL1_CNTL 0x4827 +#define mmDCIO_GSL2_CNTL 0x4828 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a +#define mmDC_GPU_TIMER_READ 0x482b +#define mmDC_GPU_TIMER_READ_CNTL 0x482c +#define mmDCIO_CLOCK_CNTL 0x482d +#define mmDCIO_DEBUG 0x482f +#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 +#define mmDBG_OUT_CNTL 0x4834 +#define mmDCIO_DEBUG_CONFIG 0x4835 +#define mmDCIO_SOFT_RESET 0x4836 +#define mmDCIO_DPHY_SEL 0x4837 +#define mmDCIO_DPCS_TX_INTERRUPT 0x484b +#define mmDCIO_DPCS_RX_INTERRUPT 0x484c +#define mmDCIO_SEMAPHORE0 0x484d +#define mmDCIO_SEMAPHORE1 0x484e +#define mmDCIO_SEMAPHORE2 0x484f +#define mmDCIO_SEMAPHORE3 0x4850 +#define mmDCIO_SEMAPHORE4 0x4851 +#define mmDCIO_SEMAPHORE5 0x4852 +#define mmDCIO_SEMAPHORE6 0x4853 +#define mmDCIO_SEMAPHORE7 0x4854 +#define mmDCIO_TEST_DEBUG_INDEX 0x4831 +#define mmDCIO_TEST_DEBUG_DATA 0x4832 +#define ixDCIO_DEBUG1 0x1 +#define ixDCIO_DEBUG2 0x2 +#define ixDCIO_DEBUG3 0x3 +#define ixDCIO_DEBUG4 0x4 +#define ixDCIO_DEBUG5 0x5 +#define ixDCIO_DEBUG6 0x6 +#define ixDCIO_DEBUG7 0x7 +#define ixDCIO_DEBUG8 0x8 +#define ixDCIO_DEBUG9 0x9 +#define ixDCIO_DEBUGA 0xa +#define ixDCIO_DEBUGB 0xb +#define ixDCIO_DEBUGC 0xc +#define ixDCIO_DEBUGD 0xd +#define ixDCIO_DEBUGE 0xe +#define ixDCIO_DEBUGF 0xf +#define ixDCIO_DEBUG10 0x10 +#define ixDCIO_DEBUG11 0x11 +#define ixDCIO_DEBUG12 0x12 +#define ixDCIO_DEBUG13 0x13 +#define ixDCIO_DEBUG14 0x14 +#define ixDCIO_DEBUG15 0x15 +#define ixDCIO_DEBUG16 0x16 +#define ixDCIO_DEBUG17 0x17 +#define ixDCIO_DEBUG18 0x18 +#define ixDCIO_DEBUG19 0x19 +#define ixDCIO_DEBUG1A 0x1a +#define ixDCIO_DEBUG1B 0x1b +#define ixDCIO_DEBUG1C 0x1c +#define ixDCIO_DEBUG1D 0x1d +#define ixDCIO_DEBUG1E 0x1e +#define ixDCIO_DEBUG1F 0x1f +#define ixDCIO_DEBUG20 0x20 +#define ixDCIO_DEBUG21 0x21 +#define ixDCIO_DEBUG22 0x22 +#define ixDCIO_DEBUG23 0x23 +#define ixDCIO_DEBUG24 0x24 +#define ixDCIO_DEBUG25 0x25 +#define ixDCIO_DEBUG26 0x26 +#define ixDCIO_DEBUG27 0x27 +#define ixDCIO_DEBUG28 0x28 +#define ixDCIO_DEBUG_ID 0x0 +#define mmDC_GPIO_GENERIC_MASK 0x4860 +#define mmDC_GPIO_GENERIC_A 0x4861 +#define mmDC_GPIO_GENERIC_EN 0x4862 +#define mmDC_GPIO_GENERIC_Y 0x4863 +#define mmDC_GPIO_DDC1_MASK 0x4868 +#define mmDC_GPIO_DDC1_A 0x4869 +#define mmDC_GPIO_DDC1_EN 0x486a +#define mmDC_GPIO_DDC1_Y 0x486b +#define mmDC_GPIO_DDC2_MASK 0x486c +#define mmDC_GPIO_DDC2_A 0x486d +#define mmDC_GPIO_DDC2_EN 0x486e +#define mmDC_GPIO_DDC2_Y 0x486f +#define mmDC_GPIO_DDC3_MASK 0x4870 +#define mmDC_GPIO_DDC3_A 0x4871 +#define mmDC_GPIO_DDC3_EN 0x4872 +#define mmDC_GPIO_DDC3_Y 0x4873 +#define mmDC_GPIO_DDC4_MASK 0x4874 +#define mmDC_GPIO_DDC4_A 0x4875 +#define mmDC_GPIO_DDC4_EN 0x4876 +#define mmDC_GPIO_DDC4_Y 0x4877 +#define mmDC_GPIO_DDC5_MASK 0x4878 +#define mmDC_GPIO_DDC5_A 0x4879 +#define mmDC_GPIO_DDC5_EN 0x487a +#define mmDC_GPIO_DDC5_Y 0x487b +#define mmDC_GPIO_DDC6_MASK 0x487c +#define mmDC_GPIO_DDC6_A 0x487d +#define mmDC_GPIO_DDC6_EN 0x487e +#define mmDC_GPIO_DDC6_Y 0x487f +#define mmDC_GPIO_DDCVGA_MASK 0x4880 +#define mmDC_GPIO_DDCVGA_A 0x4881 +#define mmDC_GPIO_DDCVGA_EN 0x4882 +#define mmDC_GPIO_DDCVGA_Y 0x4883 +#define mmDC_GPIO_SYNCA_MASK 0x4884 +#define mmDC_GPIO_SYNCA_A 0x4885 +#define mmDC_GPIO_SYNCA_EN 0x4886 +#define mmDC_GPIO_SYNCA_Y 0x4887 +#define mmDC_GPIO_GENLK_MASK 0x4888 +#define mmDC_GPIO_GENLK_A 0x4889 +#define mmDC_GPIO_GENLK_EN 0x488a +#define mmDC_GPIO_GENLK_Y 0x488b +#define mmDC_GPIO_HPD_MASK 0x488c +#define mmDC_GPIO_HPD_A 0x488d +#define mmDC_GPIO_HPD_EN 0x488e +#define mmDC_GPIO_HPD_Y 0x488f +#define mmDC_GPIO_PWRSEQ_MASK 0x4890 +#define mmDC_GPIO_PWRSEQ_A 0x4891 +#define mmDC_GPIO_PWRSEQ_EN 0x4892 +#define mmDC_GPIO_PWRSEQ_Y 0x4893 +#define mmDC_GPIO_PAD_STRENGTH_1 0x4894 +#define mmDC_GPIO_PAD_STRENGTH_2 0x4895 +#define mmPHY_AUX_CNTL 0x4897 +#define mmDC_GPIO_I2CPAD_A 0x4899 +#define mmDC_GPIO_I2CPAD_EN 0x489a +#define mmDC_GPIO_I2CPAD_Y 0x489b +#define mmDC_GPIO_I2CPAD_STRENGTH 0x489c +#define mmDVO_VREF_CONTROL 0x489e +#define mmDVO_SKEW_ADJUST 0x489f +#define mmDC_GPIO_RECEIVER_EN0 0x48a0 +#define mmDC_GPIO_RECEIVER_EN1 0x48a1 +#define mmDC_GPIO_I2S_SPDIF_MASK 0x48a8 +#define mmDC_GPIO_I2S_SPDIF_A 0x48a9 +#define mmDC_GPIO_I2S_SPDIF_EN 0x48aa +#define mmDC_GPIO_I2S_SPDIF_Y 0x48ab +#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x48ac +#define mmDC_GPIO_TX12_EN 0x48ad +#define mmDC_GPIO_AUX_CTRL_0 0x48ae +#define mmDC_GPIO_AUX_CTRL_1 0x48af +#define mmDC_GPIO_AUX_CTRL_2 0x48b0 +#define mmDC_GPIO_HPD_CTRL_0 0x48b1 +#define mmDC_GPIO_HPD_CTRL_1 0x48b2 +#define mmDAC_MACRO_CNTL_RESERVED0 0x48b8 +#define mmDAC_MACRO_CNTL_RESERVED1 0x48b9 +#define mmDAC_MACRO_CNTL_RESERVED2 0x48ba +#define mmDAC_MACRO_CNTL_RESERVED3 0x48bb +#define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x9a00 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x9aa0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x9b40 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x9be0 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x9c80 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x9d20 +#define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x9a01 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x9aa1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x9b41 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x9be1 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x9c81 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x9d21 +#define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x9a02 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x9aa2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x9b42 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x9be2 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x9c82 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x9d22 +#define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x9a03 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x9aa3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x9b43 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x9be3 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x9c83 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x9d23 +#define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x9a04 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x9aa4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x9b44 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x9be4 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x9c84 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x9d24 +#define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x9a05 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x9aa5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x9b45 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x9be5 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x9c85 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x9d25 +#define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x9a06 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x9aa6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x9b46 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x9be6 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x9c86 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x9d26 +#define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x9a07 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x9aa7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x9b47 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x9be7 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x9c87 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x9d27 +#define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x9a08 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x9aa8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x9b48 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x9be8 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x9c88 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x9d28 +#define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x9a09 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x9aa9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x9b49 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x9be9 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x9c89 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x9d29 +#define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x496a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x9a0a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x9aaa +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x9b4a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x9bea +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x9c8a +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x9d2a +#define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x496b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x9a0b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x9aab +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x9b4b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x9beb +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x9c8b +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x9d2b +#define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x496c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x9a0c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x9aac +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x9b4c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x9bec +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x9c8c +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x9d2c +#define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x496d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x9a0d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x9aad +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x9b4d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x9bed +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x9c8d +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x9d2d +#define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x496e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x9a0e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x9aae +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x9b4e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x9bee +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x9c8e +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x9d2e +#define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x496f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x9a0f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x9aaf +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x9b4f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x9bef +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x9c8f +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x9d2f +#define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x9a10 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x9ab0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x9b50 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x9bf0 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x9c90 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x9d30 +#define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x9a11 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x9ab1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x9b51 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x9bf1 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x9c91 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x9d31 +#define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x9a12 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x9ab2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x9b52 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x9bf2 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x9c92 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x9d32 +#define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x9a13 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x9ab3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x9b53 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x9bf3 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x9c93 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x9d33 +#define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x9a14 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x9ab4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x9b54 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x9bf4 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x9c94 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x9d34 +#define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x9a15 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x9ab5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x9b55 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x9bf5 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x9c95 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x9d35 +#define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x9a16 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x9ab6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x9b56 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x9bf6 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x9c96 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x9d36 +#define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x9a17 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x9ab7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x9b57 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x9bf7 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x9c97 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x9d37 +#define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x9a18 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x9ab8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x9b58 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x9bf8 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x9c98 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x9d38 +#define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x9a19 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x9ab9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x9b59 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x9bf9 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x9c99 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x9d39 +#define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x497a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x9a1a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x9aba +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x9b5a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x9bfa +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x9c9a +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x9d3a +#define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x497b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x9a1b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x9abb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x9b5b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x9bfb +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x9c9b +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x9d3b +#define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x497c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x9a1c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x9abc +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x9b5c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x9bfc +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x9c9c +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x9d3c +#define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x497d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x9a1d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x9abd +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x9b5d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x9bfd +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x9c9d +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x9d3d +#define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x497e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x9a1e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x9abe +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x9b5e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x9bfe +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x9c9e +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x9d3e +#define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x497f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x9a1f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x9abf +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x9b5f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x9bff +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x9c9f +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x9d3f +#define mmUNIPHY_MACRO_CNTL_RESERVED32 0x48e0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x48e0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x4980 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x9a20 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x9ac0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x9b60 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x9c00 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x9ca0 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED32 0x9d40 +#define mmUNIPHY_MACRO_CNTL_RESERVED33 0x48e1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x48e1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x4981 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x9a21 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x9ac1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x9b61 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x9c01 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x9ca1 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED33 0x9d41 +#define mmUNIPHY_MACRO_CNTL_RESERVED34 0x48e2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x48e2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x4982 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x9a22 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x9ac2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x9b62 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x9c02 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x9ca2 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED34 0x9d42 +#define mmUNIPHY_MACRO_CNTL_RESERVED35 0x48e3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x48e3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x4983 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x9a23 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x9ac3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x9b63 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x9c03 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x9ca3 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED35 0x9d43 +#define mmUNIPHY_MACRO_CNTL_RESERVED36 0x48e4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x48e4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x4984 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x9a24 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x9ac4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x9b64 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x9c04 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x9ca4 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED36 0x9d44 +#define mmUNIPHY_MACRO_CNTL_RESERVED37 0x48e5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x48e5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x4985 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x9a25 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x9ac5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x9b65 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x9c05 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x9ca5 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED37 0x9d45 +#define mmUNIPHY_MACRO_CNTL_RESERVED38 0x48e6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x48e6 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x4986 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x9a26 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x9ac6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x9b66 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x9c06 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x9ca6 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED38 0x9d46 +#define mmUNIPHY_MACRO_CNTL_RESERVED39 0x48e7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x48e7 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x4987 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x9a27 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x9ac7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x9b67 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x9c07 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x9ca7 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED39 0x9d47 +#define mmUNIPHY_MACRO_CNTL_RESERVED40 0x48e8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x48e8 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x4988 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x9a28 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x9ac8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x9b68 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x9c08 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x9ca8 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED40 0x9d48 +#define mmUNIPHY_MACRO_CNTL_RESERVED41 0x48e9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x48e9 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x4989 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x9a29 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x9ac9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x9b69 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x9c09 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x9ca9 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED41 0x9d49 +#define mmUNIPHY_MACRO_CNTL_RESERVED42 0x48ea +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x48ea +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x498a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x9a2a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x9aca +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x9b6a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x9c0a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x9caa +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED42 0x9d4a +#define mmUNIPHY_MACRO_CNTL_RESERVED43 0x48eb +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x48eb +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x498b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x9a2b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x9acb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x9b6b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x9c0b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x9cab +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED43 0x9d4b +#define mmUNIPHY_MACRO_CNTL_RESERVED44 0x48ec +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x48ec +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x498c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x9a2c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x9acc +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x9b6c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x9c0c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x9cac +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED44 0x9d4c +#define mmUNIPHY_MACRO_CNTL_RESERVED45 0x48ed +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x48ed +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x498d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x9a2d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x9acd +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x9b6d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x9c0d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x9cad +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED45 0x9d4d +#define mmUNIPHY_MACRO_CNTL_RESERVED46 0x48ee +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x48ee +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x498e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x9a2e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x9ace +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x9b6e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x9c0e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x9cae +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED46 0x9d4e +#define mmUNIPHY_MACRO_CNTL_RESERVED47 0x48ef +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x48ef +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x498f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x9a2f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x9acf +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x9b6f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x9c0f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x9caf +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED47 0x9d4f +#define mmUNIPHY_MACRO_CNTL_RESERVED48 0x48f0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x48f0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x4990 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x9a30 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x9ad0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x9b70 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x9c10 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x9cb0 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED48 0x9d50 +#define mmUNIPHY_MACRO_CNTL_RESERVED49 0x48f1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x48f1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x4991 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x9a31 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x9ad1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x9b71 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x9c11 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x9cb1 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED49 0x9d51 +#define mmUNIPHY_MACRO_CNTL_RESERVED50 0x48f2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x48f2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x4992 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x9a32 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x9ad2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x9b72 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x9c12 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x9cb2 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED50 0x9d52 +#define mmUNIPHY_MACRO_CNTL_RESERVED51 0x48f3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x48f3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x4993 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x9a33 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x9ad3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x9b73 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x9c13 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x9cb3 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED51 0x9d53 +#define mmUNIPHY_MACRO_CNTL_RESERVED52 0x48f4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x48f4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x4994 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x9a34 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x9ad4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x9b74 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x9c14 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x9cb4 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED52 0x9d54 +#define mmUNIPHY_MACRO_CNTL_RESERVED53 0x48f5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x48f5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x4995 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x9a35 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x9ad5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x9b75 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x9c15 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x9cb5 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED53 0x9d55 +#define mmUNIPHY_MACRO_CNTL_RESERVED54 0x48f6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x48f6 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x4996 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x9a36 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x9ad6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x9b76 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x9c16 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x9cb6 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED54 0x9d56 +#define mmUNIPHY_MACRO_CNTL_RESERVED55 0x48f7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x48f7 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x4997 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x9a37 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x9ad7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x9b77 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x9c17 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x9cb7 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED55 0x9d57 +#define mmUNIPHY_MACRO_CNTL_RESERVED56 0x48f8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x48f8 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x4998 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x9a38 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x9ad8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x9b78 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x9c18 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x9cb8 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED56 0x9d58 +#define mmUNIPHY_MACRO_CNTL_RESERVED57 0x48f9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x48f9 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x4999 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x9a39 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x9ad9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x9b79 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x9c19 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x9cb9 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED57 0x9d59 +#define mmUNIPHY_MACRO_CNTL_RESERVED58 0x48fa +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x48fa +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x499a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x9a3a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x9ada +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x9b7a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x9c1a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0x9cba +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED58 0x9d5a +#define mmUNIPHY_MACRO_CNTL_RESERVED59 0x48fb +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x48fb +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x499b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x9a3b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x9adb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x9b7b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x9c1b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0x9cbb +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED59 0x9d5b +#define mmUNIPHY_MACRO_CNTL_RESERVED60 0x48fc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x48fc +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x499c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x9a3c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x9adc +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x9b7c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x9c1c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0x9cbc +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED60 0x9d5c +#define mmUNIPHY_MACRO_CNTL_RESERVED61 0x48fd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x48fd +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x499d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x9a3d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x9add +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x9b7d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x9c1d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0x9cbd +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED61 0x9d5d +#define mmUNIPHY_MACRO_CNTL_RESERVED62 0x48fe +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x48fe +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x499e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x9a3e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x9ade +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x9b7e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x9c1e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0x9cbe +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED62 0x9d5e +#define mmUNIPHY_MACRO_CNTL_RESERVED63 0x48ff +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x48ff +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x499f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x9a3f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x9adf +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x9b7f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x9c1f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0x9cbf +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED63 0x9d5f +#define mmUNIPHY_MACRO_CNTL_RESERVED64 0x4900 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x4900 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x49a0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x9a40 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x9ae0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x9b80 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x9c20 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0x9cc0 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED64 0x9d60 +#define mmUNIPHY_MACRO_CNTL_RESERVED65 0x4901 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x4901 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x49a1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x9a41 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x9ae1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x9b81 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x9c21 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0x9cc1 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED65 0x9d61 +#define mmUNIPHY_MACRO_CNTL_RESERVED66 0x4902 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x4902 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x49a2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x9a42 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x9ae2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x9b82 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x9c22 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0x9cc2 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED66 0x9d62 +#define mmUNIPHY_MACRO_CNTL_RESERVED67 0x4903 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x4903 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x49a3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x9a43 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x9ae3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x9b83 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x9c23 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0x9cc3 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED67 0x9d63 +#define mmUNIPHY_MACRO_CNTL_RESERVED68 0x4904 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x4904 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x49a4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x9a44 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x9ae4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x9b84 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x9c24 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0x9cc4 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED68 0x9d64 +#define mmUNIPHY_MACRO_CNTL_RESERVED69 0x4905 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x4905 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x49a5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x9a45 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x9ae5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x9b85 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x9c25 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0x9cc5 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED69 0x9d65 +#define mmUNIPHY_MACRO_CNTL_RESERVED70 0x4906 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x4906 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x49a6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x9a46 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x9ae6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x9b86 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x9c26 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0x9cc6 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED70 0x9d66 +#define mmUNIPHY_MACRO_CNTL_RESERVED71 0x4907 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x4907 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x49a7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x9a47 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x9ae7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x9b87 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x9c27 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0x9cc7 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED71 0x9d67 +#define mmUNIPHY_MACRO_CNTL_RESERVED72 0x4908 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x4908 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x49a8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x9a48 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x9ae8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x9b88 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x9c28 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0x9cc8 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED72 0x9d68 +#define mmUNIPHY_MACRO_CNTL_RESERVED73 0x4909 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x4909 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x49a9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x9a49 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x9ae9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x9b89 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x9c29 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0x9cc9 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED73 0x9d69 +#define mmUNIPHY_MACRO_CNTL_RESERVED74 0x490a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x490a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x49aa +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x9a4a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x9aea +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x9b8a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x9c2a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0x9cca +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED74 0x9d6a +#define mmUNIPHY_MACRO_CNTL_RESERVED75 0x490b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x490b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x49ab +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x9a4b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x9aeb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x9b8b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x9c2b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0x9ccb +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED75 0x9d6b +#define mmUNIPHY_MACRO_CNTL_RESERVED76 0x490c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x490c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x49ac +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x9a4c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x9aec +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x9b8c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x9c2c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0x9ccc +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED76 0x9d6c +#define mmUNIPHY_MACRO_CNTL_RESERVED77 0x490d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x490d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x49ad +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x9a4d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x9aed +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x9b8d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x9c2d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0x9ccd +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED77 0x9d6d +#define mmUNIPHY_MACRO_CNTL_RESERVED78 0x490e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x490e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x49ae +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x9a4e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x9aee +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x9b8e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x9c2e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0x9cce +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED78 0x9d6e +#define mmUNIPHY_MACRO_CNTL_RESERVED79 0x490f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x490f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x49af +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x9a4f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x9aef +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x9b8f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x9c2f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0x9ccf +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED79 0x9d6f +#define mmUNIPHY_MACRO_CNTL_RESERVED80 0x4910 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x4910 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x49b0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x9a50 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x9af0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x9b90 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x9c30 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0x9cd0 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED80 0x9d70 +#define mmUNIPHY_MACRO_CNTL_RESERVED81 0x4911 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x4911 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x49b1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x9a51 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x9af1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x9b91 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x9c31 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0x9cd1 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED81 0x9d71 +#define mmUNIPHY_MACRO_CNTL_RESERVED82 0x4912 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x4912 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x49b2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x9a52 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x9af2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x9b92 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x9c32 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0x9cd2 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED82 0x9d72 +#define mmUNIPHY_MACRO_CNTL_RESERVED83 0x4913 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x4913 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x49b3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x9a53 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x9af3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x9b93 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x9c33 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0x9cd3 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED83 0x9d73 +#define mmUNIPHY_MACRO_CNTL_RESERVED84 0x4914 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x4914 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x49b4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x9a54 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x9af4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x9b94 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x9c34 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0x9cd4 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED84 0x9d74 +#define mmUNIPHY_MACRO_CNTL_RESERVED85 0x4915 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x4915 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x49b5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x9a55 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x9af5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x9b95 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x9c35 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0x9cd5 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED85 0x9d75 +#define mmUNIPHY_MACRO_CNTL_RESERVED86 0x4916 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x4916 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x49b6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x9a56 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x9af6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x9b96 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x9c36 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0x9cd6 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED86 0x9d76 +#define mmUNIPHY_MACRO_CNTL_RESERVED87 0x4917 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x4917 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x49b7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x9a57 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x9af7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x9b97 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x9c37 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0x9cd7 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED87 0x9d77 +#define mmUNIPHY_MACRO_CNTL_RESERVED88 0x4918 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x4918 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x49b8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x9a58 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x9af8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x9b98 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x9c38 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0x9cd8 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED88 0x9d78 +#define mmUNIPHY_MACRO_CNTL_RESERVED89 0x4919 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x4919 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x49b9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x9a59 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x9af9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x9b99 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x9c39 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0x9cd9 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED89 0x9d79 +#define mmUNIPHY_MACRO_CNTL_RESERVED90 0x491a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x491a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x49ba +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x9a5a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x9afa +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x9b9a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x9c3a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0x9cda +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED90 0x9d7a +#define mmUNIPHY_MACRO_CNTL_RESERVED91 0x491b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x491b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x49bb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x9a5b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x9afb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x9b9b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x9c3b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0x9cdb +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED91 0x9d7b +#define mmUNIPHY_MACRO_CNTL_RESERVED92 0x491c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x491c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x49bc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x9a5c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x9afc +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x9b9c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x9c3c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0x9cdc +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED92 0x9d7c +#define mmUNIPHY_MACRO_CNTL_RESERVED93 0x491d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x491d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x49bd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x9a5d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x9afd +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x9b9d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x9c3d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0x9cdd +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED93 0x9d7d +#define mmUNIPHY_MACRO_CNTL_RESERVED94 0x491e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x491e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x49be +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x9a5e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x9afe +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x9b9e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x9c3e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0x9cde +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED94 0x9d7e +#define mmUNIPHY_MACRO_CNTL_RESERVED95 0x491f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x491f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x49bf +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x9a5f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x9aff +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x9b9f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x9c3f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0x9cdf +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED95 0x9d7f +#define mmUNIPHY_MACRO_CNTL_RESERVED96 0x4920 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x4920 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x49c0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x9a60 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x9b00 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x9ba0 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x9c40 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0x9ce0 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED96 0x9d80 +#define mmUNIPHY_MACRO_CNTL_RESERVED97 0x4921 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x4921 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x49c1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x9a61 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x9b01 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x9ba1 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x9c41 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0x9ce1 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED97 0x9d81 +#define mmUNIPHY_MACRO_CNTL_RESERVED98 0x4922 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x4922 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x49c2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x9a62 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x9b02 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x9ba2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x9c42 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0x9ce2 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED98 0x9d82 +#define mmUNIPHY_MACRO_CNTL_RESERVED99 0x4923 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x4923 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x49c3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x9a63 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x9b03 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x9ba3 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x9c43 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0x9ce3 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED99 0x9d83 +#define mmUNIPHY_MACRO_CNTL_RESERVED100 0x4924 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x4924 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x49c4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x9a64 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x9b04 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x9ba4 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x9c44 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0x9ce4 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED100 0x9d84 +#define mmUNIPHY_MACRO_CNTL_RESERVED101 0x4925 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x4925 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x49c5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x9a65 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x9b05 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x9ba5 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x9c45 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0x9ce5 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED101 0x9d85 +#define mmUNIPHY_MACRO_CNTL_RESERVED102 0x4926 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x4926 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x49c6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x9a66 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x9b06 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x9ba6 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x9c46 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0x9ce6 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED102 0x9d86 +#define mmUNIPHY_MACRO_CNTL_RESERVED103 0x4927 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x4927 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x49c7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x9a67 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x9b07 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x9ba7 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x9c47 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0x9ce7 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED103 0x9d87 +#define mmUNIPHY_MACRO_CNTL_RESERVED104 0x4928 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x4928 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x49c8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x9a68 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x9b08 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x9ba8 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x9c48 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0x9ce8 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED104 0x9d88 +#define mmUNIPHY_MACRO_CNTL_RESERVED105 0x4929 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x4929 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x49c9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x9a69 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x9b09 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x9ba9 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x9c49 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0x9ce9 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED105 0x9d89 +#define mmUNIPHY_MACRO_CNTL_RESERVED106 0x492a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x492a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x49ca +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x9a6a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x9b0a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x9baa +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x9c4a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0x9cea +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED106 0x9d8a +#define mmUNIPHY_MACRO_CNTL_RESERVED107 0x492b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x492b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x49cb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x9a6b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x9b0b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x9bab +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x9c4b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0x9ceb +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED107 0x9d8b +#define mmUNIPHY_MACRO_CNTL_RESERVED108 0x492c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x492c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x49cc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x9a6c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x9b0c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x9bac +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x9c4c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0x9cec +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED108 0x9d8c +#define mmUNIPHY_MACRO_CNTL_RESERVED109 0x492d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x492d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x49cd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x9a6d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x9b0d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x9bad +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x9c4d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0x9ced +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED109 0x9d8d +#define mmUNIPHY_MACRO_CNTL_RESERVED110 0x492e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x492e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x49ce +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x9a6e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x9b0e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x9bae +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x9c4e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0x9cee +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED110 0x9d8e +#define mmUNIPHY_MACRO_CNTL_RESERVED111 0x492f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x492f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x49cf +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x9a6f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x9b0f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x9baf +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x9c4f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0x9cef +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED111 0x9d8f +#define mmUNIPHY_MACRO_CNTL_RESERVED112 0x4930 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x4930 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x49d0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x9a70 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x9b10 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x9bb0 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x9c50 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0x9cf0 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED112 0x9d90 +#define mmUNIPHY_MACRO_CNTL_RESERVED113 0x4931 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x4931 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x49d1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x9a71 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x9b11 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x9bb1 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x9c51 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0x9cf1 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED113 0x9d91 +#define mmUNIPHY_MACRO_CNTL_RESERVED114 0x4932 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x4932 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x49d2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x9a72 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x9b12 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x9bb2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x9c52 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0x9cf2 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED114 0x9d92 +#define mmUNIPHY_MACRO_CNTL_RESERVED115 0x4933 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x4933 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x49d3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x9a73 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x9b13 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x9bb3 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x9c53 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0x9cf3 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED115 0x9d93 +#define mmUNIPHY_MACRO_CNTL_RESERVED116 0x4934 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x4934 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x49d4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x9a74 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x9b14 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x9bb4 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x9c54 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0x9cf4 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED116 0x9d94 +#define mmUNIPHY_MACRO_CNTL_RESERVED117 0x4935 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x4935 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x49d5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x9a75 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x9b15 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x9bb5 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x9c55 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0x9cf5 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED117 0x9d95 +#define mmUNIPHY_MACRO_CNTL_RESERVED118 0x4936 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x4936 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x49d6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x9a76 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x9b16 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x9bb6 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x9c56 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0x9cf6 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED118 0x9d96 +#define mmUNIPHY_MACRO_CNTL_RESERVED119 0x4937 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x4937 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x49d7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x9a77 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x9b17 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x9bb7 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x9c57 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0x9cf7 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED119 0x9d97 +#define mmUNIPHY_MACRO_CNTL_RESERVED120 0x4938 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x4938 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x49d8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x9a78 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x9b18 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x9bb8 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x9c58 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0x9cf8 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED120 0x9d98 +#define mmUNIPHY_MACRO_CNTL_RESERVED121 0x4939 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x4939 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x49d9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x9a79 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x9b19 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x9bb9 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x9c59 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0x9cf9 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED121 0x9d99 +#define mmUNIPHY_MACRO_CNTL_RESERVED122 0x493a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x493a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x49da +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x9a7a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x9b1a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x9bba +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x9c5a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0x9cfa +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED122 0x9d9a +#define mmUNIPHY_MACRO_CNTL_RESERVED123 0x493b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x493b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x49db +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x9a7b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x9b1b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x9bbb +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x9c5b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0x9cfb +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED123 0x9d9b +#define mmUNIPHY_MACRO_CNTL_RESERVED124 0x493c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x493c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x49dc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x9a7c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x9b1c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x9bbc +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x9c5c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0x9cfc +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED124 0x9d9c +#define mmUNIPHY_MACRO_CNTL_RESERVED125 0x493d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x493d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x49dd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x9a7d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x9b1d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x9bbd +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x9c5d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0x9cfd +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED125 0x9d9d +#define mmUNIPHY_MACRO_CNTL_RESERVED126 0x493e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x493e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x49de +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x9a7e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x9b1e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x9bbe +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x9c5e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0x9cfe +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED126 0x9d9e +#define mmUNIPHY_MACRO_CNTL_RESERVED127 0x493f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x493f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x49df +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x9a7f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x9b1f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x9bbf +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x9c5f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0x9cff +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED127 0x9d9f +#define mmUNIPHY_MACRO_CNTL_RESERVED128 0x4940 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x4940 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x49e0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x9a80 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x9b20 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x9bc0 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x9c60 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0x9d00 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED128 0x9da0 +#define mmUNIPHY_MACRO_CNTL_RESERVED129 0x4941 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x4941 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x49e1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x9a81 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x9b21 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x9bc1 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x9c61 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0x9d01 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED129 0x9da1 +#define mmUNIPHY_MACRO_CNTL_RESERVED130 0x4942 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x4942 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x49e2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x9a82 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x9b22 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x9bc2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x9c62 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0x9d02 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED130 0x9da2 +#define mmUNIPHY_MACRO_CNTL_RESERVED131 0x4943 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x4943 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x49e3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x9a83 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x9b23 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x9bc3 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x9c63 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0x9d03 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED131 0x9da3 +#define mmUNIPHY_MACRO_CNTL_RESERVED132 0x4944 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x4944 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x49e4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x9a84 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x9b24 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x9bc4 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x9c64 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0x9d04 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED132 0x9da4 +#define mmUNIPHY_MACRO_CNTL_RESERVED133 0x4945 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x4945 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x49e5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x9a85 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x9b25 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x9bc5 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x9c65 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0x9d05 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED133 0x9da5 +#define mmUNIPHY_MACRO_CNTL_RESERVED134 0x4946 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x4946 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x49e6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x9a86 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x9b26 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x9bc6 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x9c66 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0x9d06 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED134 0x9da6 +#define mmUNIPHY_MACRO_CNTL_RESERVED135 0x4947 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x4947 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x49e7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x9a87 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x9b27 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x9bc7 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x9c67 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0x9d07 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED135 0x9da7 +#define mmUNIPHY_MACRO_CNTL_RESERVED136 0x4948 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x4948 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x49e8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x9a88 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x9b28 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x9bc8 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x9c68 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0x9d08 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED136 0x9da8 +#define mmUNIPHY_MACRO_CNTL_RESERVED137 0x4949 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x4949 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x49e9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x9a89 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x9b29 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x9bc9 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x9c69 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0x9d09 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED137 0x9da9 +#define mmUNIPHY_MACRO_CNTL_RESERVED138 0x494a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x494a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x49ea +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x9a8a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x9b2a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x9bca +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x9c6a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0x9d0a +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED138 0x9daa +#define mmUNIPHY_MACRO_CNTL_RESERVED139 0x494b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x494b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x49eb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x9a8b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x9b2b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x9bcb +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x9c6b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0x9d0b +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED139 0x9dab +#define mmUNIPHY_MACRO_CNTL_RESERVED140 0x494c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x494c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x49ec +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x9a8c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x9b2c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x9bcc +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x9c6c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0x9d0c +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED140 0x9dac +#define mmUNIPHY_MACRO_CNTL_RESERVED141 0x494d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x494d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x49ed +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x9a8d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x9b2d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x9bcd +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x9c6d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0x9d0d +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED141 0x9dad +#define mmUNIPHY_MACRO_CNTL_RESERVED142 0x494e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x494e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x49ee +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x9a8e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x9b2e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x9bce +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x9c6e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0x9d0e +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED142 0x9dae +#define mmUNIPHY_MACRO_CNTL_RESERVED143 0x494f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x494f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x49ef +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x9a8f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x9b2f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x9bcf +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x9c6f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0x9d0f +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED143 0x9daf +#define mmUNIPHY_MACRO_CNTL_RESERVED144 0x4950 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x4950 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x49f0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x9a90 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x9b30 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x9bd0 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x9c70 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0x9d10 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED144 0x9db0 +#define mmUNIPHY_MACRO_CNTL_RESERVED145 0x4951 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x4951 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x49f1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x9a91 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x9b31 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x9bd1 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x9c71 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0x9d11 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED145 0x9db1 +#define mmUNIPHY_MACRO_CNTL_RESERVED146 0x4952 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x4952 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x49f2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x9a92 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x9b32 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x9bd2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x9c72 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0x9d12 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED146 0x9db2 +#define mmUNIPHY_MACRO_CNTL_RESERVED147 0x4953 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x4953 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x49f3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x9a93 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x9b33 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x9bd3 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x9c73 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0x9d13 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED147 0x9db3 +#define mmUNIPHY_MACRO_CNTL_RESERVED148 0x4954 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x4954 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x49f4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x9a94 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x9b34 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x9bd4 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x9c74 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0x9d14 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED148 0x9db4 +#define mmUNIPHY_MACRO_CNTL_RESERVED149 0x4955 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x4955 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x49f5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x9a95 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x9b35 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x9bd5 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x9c75 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0x9d15 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED149 0x9db5 +#define mmUNIPHY_MACRO_CNTL_RESERVED150 0x4956 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x4956 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x49f6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x9a96 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x9b36 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x9bd6 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x9c76 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0x9d16 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED150 0x9db6 +#define mmUNIPHY_MACRO_CNTL_RESERVED151 0x4957 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x4957 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x49f7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x9a97 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x9b37 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x9bd7 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x9c77 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0x9d17 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED151 0x9db7 +#define mmUNIPHY_MACRO_CNTL_RESERVED152 0x4958 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x4958 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x49f8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x9a98 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x9b38 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x9bd8 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x9c78 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0x9d18 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED152 0x9db8 +#define mmUNIPHY_MACRO_CNTL_RESERVED153 0x4959 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x4959 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x49f9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x9a99 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x9b39 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x9bd9 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x9c79 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0x9d19 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED153 0x9db9 +#define mmUNIPHY_MACRO_CNTL_RESERVED154 0x495a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x495a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x49fa +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x9a9a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x9b3a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x9bda +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x9c7a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0x9d1a +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED154 0x9dba +#define mmUNIPHY_MACRO_CNTL_RESERVED155 0x495b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x495b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x49fb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x9a9b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x9b3b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x9bdb +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x9c7b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0x9d1b +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED155 0x9dbb +#define mmUNIPHY_MACRO_CNTL_RESERVED156 0x495c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x495c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x49fc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x9a9c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x9b3c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x9bdc +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x9c7c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0x9d1c +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED156 0x9dbc +#define mmUNIPHY_MACRO_CNTL_RESERVED157 0x495d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x495d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x49fd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x9a9d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x9b3d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x9bdd +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x9c7d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0x9d1d +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED157 0x9dbd +#define mmUNIPHY_MACRO_CNTL_RESERVED158 0x495e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x495e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x49fe +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x9a9e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x9b3e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x9bde +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x9c7e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0x9d1e +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED158 0x9dbe +#define mmUNIPHY_MACRO_CNTL_RESERVED159 0x495f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x495f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x49ff +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x9a9f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x9b3f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x9bdf +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x9c7f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0x9d1f +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED159 0x9dbf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab +#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac +#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad +#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae +#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba +#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca +#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace +#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada +#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add +#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade +#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea +#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec +#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed +#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee +#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef +#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff +#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab +#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac +#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad +#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae +#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba +#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca +#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce +#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda +#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde +#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea +#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec +#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed +#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee +#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef +#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff +#define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 +#define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 +#define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a +#define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b +#define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c +#define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d +#define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e +#define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f +#define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 +#define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 +#define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 +#define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 +#define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 +#define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 +#define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 +#define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 +#define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 +#define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 +#define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa +#define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab +#define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac +#define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad +#define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae +#define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf +#define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 +#define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 +#define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 +#define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 +#define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 +#define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 +#define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 +#define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 +#define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 +#define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 +#define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba +#define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb +#define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc +#define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd +#define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe +#define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf +#define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 +#define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 +#define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 +#define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 +#define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 +#define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 +#define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 +#define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 +#define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 +#define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 +#define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca +#define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb +#define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc +#define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd +#define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce +#define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf +#define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 +#define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 +#define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 +#define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 +#define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 +#define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 +#define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 +#define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 +#define mmGRPH_ENABLE 0x1a00 +#define mmDCP0_GRPH_ENABLE 0x1a00 +#define mmDCP1_GRPH_ENABLE 0x1c00 +#define mmDCP2_GRPH_ENABLE 0x1e00 +#define mmDCP3_GRPH_ENABLE 0x4000 +#define mmDCP4_GRPH_ENABLE 0x4200 +#define mmDCP5_GRPH_ENABLE 0x4400 +#define mmGRPH_CONTROL 0x1a01 +#define mmDCP0_GRPH_CONTROL 0x1a01 +#define mmDCP1_GRPH_CONTROL 0x1c01 +#define mmDCP2_GRPH_CONTROL 0x1e01 +#define mmDCP3_GRPH_CONTROL 0x4001 +#define mmDCP4_GRPH_CONTROL 0x4201 +#define mmDCP5_GRPH_CONTROL 0x4401 +#define mmGRPH_LUT_10BIT_BYPASS 0x1a02 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 +#define mmGRPH_SWAP_CNTL 0x1a03 +#define mmDCP0_GRPH_SWAP_CNTL 0x1a03 +#define mmDCP1_GRPH_SWAP_CNTL 0x1c03 +#define mmDCP2_GRPH_SWAP_CNTL 0x1e03 +#define mmDCP3_GRPH_SWAP_CNTL 0x4003 +#define mmDCP4_GRPH_SWAP_CNTL 0x4203 +#define mmDCP5_GRPH_SWAP_CNTL 0x4403 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 +#define mmGRPH_PITCH 0x1a06 +#define mmDCP0_GRPH_PITCH 0x1a06 +#define mmDCP1_GRPH_PITCH 0x1c06 +#define mmDCP2_GRPH_PITCH 0x1e06 +#define mmDCP3_GRPH_PITCH 0x4006 +#define mmDCP4_GRPH_PITCH 0x4206 +#define mmDCP5_GRPH_PITCH 0x4406 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 +#define mmGRPH_SURFACE_OFFSET_X 0x1a09 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 +#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a +#define mmGRPH_X_START 0x1a0b +#define mmDCP0_GRPH_X_START 0x1a0b +#define mmDCP1_GRPH_X_START 0x1c0b +#define mmDCP2_GRPH_X_START 0x1e0b +#define mmDCP3_GRPH_X_START 0x400b +#define mmDCP4_GRPH_X_START 0x420b +#define mmDCP5_GRPH_X_START 0x440b +#define mmGRPH_Y_START 0x1a0c +#define mmDCP0_GRPH_Y_START 0x1a0c +#define mmDCP1_GRPH_Y_START 0x1c0c +#define mmDCP2_GRPH_Y_START 0x1e0c +#define mmDCP3_GRPH_Y_START 0x400c +#define mmDCP4_GRPH_Y_START 0x420c +#define mmDCP5_GRPH_Y_START 0x440c +#define mmGRPH_X_END 0x1a0d +#define mmDCP0_GRPH_X_END 0x1a0d +#define mmDCP1_GRPH_X_END 0x1c0d +#define mmDCP2_GRPH_X_END 0x1e0d +#define mmDCP3_GRPH_X_END 0x400d +#define mmDCP4_GRPH_X_END 0x420d +#define mmDCP5_GRPH_X_END 0x440d +#define mmGRPH_Y_END 0x1a0e +#define mmDCP0_GRPH_Y_END 0x1a0e +#define mmDCP1_GRPH_Y_END 0x1c0e +#define mmDCP2_GRPH_Y_END 0x1e0e +#define mmDCP3_GRPH_Y_END 0x400e +#define mmDCP4_GRPH_Y_END 0x420e +#define mmDCP5_GRPH_Y_END 0x440e +#define mmINPUT_GAMMA_CONTROL 0x1a10 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x4010 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x4210 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x4410 +#define mmGRPH_UPDATE 0x1a11 +#define mmDCP0_GRPH_UPDATE 0x1a11 +#define mmDCP1_GRPH_UPDATE 0x1c11 +#define mmDCP2_GRPH_UPDATE 0x1e11 +#define mmDCP3_GRPH_UPDATE 0x4011 +#define mmDCP4_GRPH_UPDATE 0x4211 +#define mmDCP5_GRPH_UPDATE 0x4411 +#define mmGRPH_FLIP_CONTROL 0x1a12 +#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 +#define mmDCP1_GRPH_FLIP_CONTROL 0x1c12 +#define mmDCP2_GRPH_FLIP_CONTROL 0x1e12 +#define mmDCP3_GRPH_FLIP_CONTROL 0x4012 +#define mmDCP4_GRPH_FLIP_CONTROL 0x4212 +#define mmDCP5_GRPH_FLIP_CONTROL 0x4412 +#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 +#define mmGRPH_DFQ_CONTROL 0x1a14 +#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 +#define mmDCP1_GRPH_DFQ_CONTROL 0x1c14 +#define mmDCP2_GRPH_DFQ_CONTROL 0x1e14 +#define mmDCP3_GRPH_DFQ_CONTROL 0x4014 +#define mmDCP4_GRPH_DFQ_CONTROL 0x4214 +#define mmDCP5_GRPH_DFQ_CONTROL 0x4414 +#define mmGRPH_DFQ_STATUS 0x1a15 +#define mmDCP0_GRPH_DFQ_STATUS 0x1a15 +#define mmDCP1_GRPH_DFQ_STATUS 0x1c15 +#define mmDCP2_GRPH_DFQ_STATUS 0x1e15 +#define mmDCP3_GRPH_DFQ_STATUS 0x4015 +#define mmDCP4_GRPH_DFQ_STATUS 0x4215 +#define mmDCP5_GRPH_DFQ_STATUS 0x4415 +#define mmGRPH_INTERRUPT_STATUS 0x1a16 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 +#define mmGRPH_INTERRUPT_CONTROL 0x1a17 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 +#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 +#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 +#define mmGRPH_COMPRESS_PITCH 0x1a1a +#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a +#define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a +#define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a +#define mmDCP3_GRPH_COMPRESS_PITCH 0x401a +#define mmDCP4_GRPH_COMPRESS_PITCH 0x421a +#define mmDCP5_GRPH_COMPRESS_PITCH 0x441a +#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b +#define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c +#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c +#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c +#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c +#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c +#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c +#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c +#define mmPRESCALE_GRPH_CONTROL 0x1a2d +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d +#define mmPRESCALE_VALUES_GRPH_R 0x1a2e +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e +#define mmPRESCALE_VALUES_GRPH_G 0x1a2f +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f +#define mmPRESCALE_VALUES_GRPH_B 0x1a30 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 +#define mmINPUT_CSC_CONTROL 0x1a35 +#define mmDCP0_INPUT_CSC_CONTROL 0x1a35 +#define mmDCP1_INPUT_CSC_CONTROL 0x1c35 +#define mmDCP2_INPUT_CSC_CONTROL 0x1e35 +#define mmDCP3_INPUT_CSC_CONTROL 0x4035 +#define mmDCP4_INPUT_CSC_CONTROL 0x4235 +#define mmDCP5_INPUT_CSC_CONTROL 0x4435 +#define mmINPUT_CSC_C11_C12 0x1a36 +#define mmDCP0_INPUT_CSC_C11_C12 0x1a36 +#define mmDCP1_INPUT_CSC_C11_C12 0x1c36 +#define mmDCP2_INPUT_CSC_C11_C12 0x1e36 +#define mmDCP3_INPUT_CSC_C11_C12 0x4036 +#define mmDCP4_INPUT_CSC_C11_C12 0x4236 +#define mmDCP5_INPUT_CSC_C11_C12 0x4436 +#define mmINPUT_CSC_C13_C14 0x1a37 +#define mmDCP0_INPUT_CSC_C13_C14 0x1a37 +#define mmDCP1_INPUT_CSC_C13_C14 0x1c37 +#define mmDCP2_INPUT_CSC_C13_C14 0x1e37 +#define mmDCP3_INPUT_CSC_C13_C14 0x4037 +#define mmDCP4_INPUT_CSC_C13_C14 0x4237 +#define mmDCP5_INPUT_CSC_C13_C14 0x4437 +#define mmINPUT_CSC_C21_C22 0x1a38 +#define mmDCP0_INPUT_CSC_C21_C22 0x1a38 +#define mmDCP1_INPUT_CSC_C21_C22 0x1c38 +#define mmDCP2_INPUT_CSC_C21_C22 0x1e38 +#define mmDCP3_INPUT_CSC_C21_C22 0x4038 +#define mmDCP4_INPUT_CSC_C21_C22 0x4238 +#define mmDCP5_INPUT_CSC_C21_C22 0x4438 +#define mmINPUT_CSC_C23_C24 0x1a39 +#define mmDCP0_INPUT_CSC_C23_C24 0x1a39 +#define mmDCP1_INPUT_CSC_C23_C24 0x1c39 +#define mmDCP2_INPUT_CSC_C23_C24 0x1e39 +#define mmDCP3_INPUT_CSC_C23_C24 0x4039 +#define mmDCP4_INPUT_CSC_C23_C24 0x4239 +#define mmDCP5_INPUT_CSC_C23_C24 0x4439 +#define mmINPUT_CSC_C31_C32 0x1a3a +#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a +#define mmDCP1_INPUT_CSC_C31_C32 0x1c3a +#define mmDCP2_INPUT_CSC_C31_C32 0x1e3a +#define mmDCP3_INPUT_CSC_C31_C32 0x403a +#define mmDCP4_INPUT_CSC_C31_C32 0x423a +#define mmDCP5_INPUT_CSC_C31_C32 0x443a +#define mmINPUT_CSC_C33_C34 0x1a3b +#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b +#define mmDCP1_INPUT_CSC_C33_C34 0x1c3b +#define mmDCP2_INPUT_CSC_C33_C34 0x1e3b +#define mmDCP3_INPUT_CSC_C33_C34 0x403b +#define mmDCP4_INPUT_CSC_C33_C34 0x423b +#define mmDCP5_INPUT_CSC_C33_C34 0x443b +#define mmOUTPUT_CSC_CONTROL 0x1a3c +#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c +#define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c +#define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c +#define mmDCP3_OUTPUT_CSC_CONTROL 0x403c +#define mmDCP4_OUTPUT_CSC_CONTROL 0x423c +#define mmDCP5_OUTPUT_CSC_CONTROL 0x443c +#define mmOUTPUT_CSC_C11_C12 0x1a3d +#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d +#define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d +#define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d +#define mmDCP3_OUTPUT_CSC_C11_C12 0x403d +#define mmDCP4_OUTPUT_CSC_C11_C12 0x423d +#define mmDCP5_OUTPUT_CSC_C11_C12 0x443d +#define mmOUTPUT_CSC_C13_C14 0x1a3e +#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e +#define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e +#define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e +#define mmDCP3_OUTPUT_CSC_C13_C14 0x403e +#define mmDCP4_OUTPUT_CSC_C13_C14 0x423e +#define mmDCP5_OUTPUT_CSC_C13_C14 0x443e +#define mmOUTPUT_CSC_C21_C22 0x1a3f +#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f +#define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f +#define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f +#define mmDCP3_OUTPUT_CSC_C21_C22 0x403f +#define mmDCP4_OUTPUT_CSC_C21_C22 0x423f +#define mmDCP5_OUTPUT_CSC_C21_C22 0x443f +#define mmOUTPUT_CSC_C23_C24 0x1a40 +#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 +#define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 +#define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 +#define mmDCP3_OUTPUT_CSC_C23_C24 0x4040 +#define mmDCP4_OUTPUT_CSC_C23_C24 0x4240 +#define mmDCP5_OUTPUT_CSC_C23_C24 0x4440 +#define mmOUTPUT_CSC_C31_C32 0x1a41 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x4041 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x4241 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x4441 +#define mmOUTPUT_CSC_C33_C34 0x1a42 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x4042 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x4242 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x4442 +#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 +#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 +#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 +#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 +#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 +#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 +#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 +#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a +#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b +#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c +#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d +#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e +#define mmDENORM_CONTROL 0x1a50 +#define mmDCP0_DENORM_CONTROL 0x1a50 +#define mmDCP1_DENORM_CONTROL 0x1c50 +#define mmDCP2_DENORM_CONTROL 0x1e50 +#define mmDCP3_DENORM_CONTROL 0x4050 +#define mmDCP4_DENORM_CONTROL 0x4250 +#define mmDCP5_DENORM_CONTROL 0x4450 +#define mmOUT_ROUND_CONTROL 0x1a51 +#define mmDCP0_OUT_ROUND_CONTROL 0x1a51 +#define mmDCP1_OUT_ROUND_CONTROL 0x1c51 +#define mmDCP2_OUT_ROUND_CONTROL 0x1e51 +#define mmDCP3_OUT_ROUND_CONTROL 0x4051 +#define mmDCP4_OUT_ROUND_CONTROL 0x4251 +#define mmDCP5_OUT_ROUND_CONTROL 0x4451 +#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 +#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 +#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 +#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 +#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 +#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 +#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 +#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c +#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c +#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c +#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c +#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c +#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c +#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c +#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d +#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d +#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d +#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d +#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d +#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d +#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d +#define mmKEY_CONTROL 0x1a53 +#define mmDCP0_KEY_CONTROL 0x1a53 +#define mmDCP1_KEY_CONTROL 0x1c53 +#define mmDCP2_KEY_CONTROL 0x1e53 +#define mmDCP3_KEY_CONTROL 0x4053 +#define mmDCP4_KEY_CONTROL 0x4253 +#define mmDCP5_KEY_CONTROL 0x4453 +#define mmKEY_RANGE_ALPHA 0x1a54 +#define mmDCP0_KEY_RANGE_ALPHA 0x1a54 +#define mmDCP1_KEY_RANGE_ALPHA 0x1c54 +#define mmDCP2_KEY_RANGE_ALPHA 0x1e54 +#define mmDCP3_KEY_RANGE_ALPHA 0x4054 +#define mmDCP4_KEY_RANGE_ALPHA 0x4254 +#define mmDCP5_KEY_RANGE_ALPHA 0x4454 +#define mmKEY_RANGE_RED 0x1a55 +#define mmDCP0_KEY_RANGE_RED 0x1a55 +#define mmDCP1_KEY_RANGE_RED 0x1c55 +#define mmDCP2_KEY_RANGE_RED 0x1e55 +#define mmDCP3_KEY_RANGE_RED 0x4055 +#define mmDCP4_KEY_RANGE_RED 0x4255 +#define mmDCP5_KEY_RANGE_RED 0x4455 +#define mmKEY_RANGE_GREEN 0x1a56 +#define mmDCP0_KEY_RANGE_GREEN 0x1a56 +#define mmDCP1_KEY_RANGE_GREEN 0x1c56 +#define mmDCP2_KEY_RANGE_GREEN 0x1e56 +#define mmDCP3_KEY_RANGE_GREEN 0x4056 +#define mmDCP4_KEY_RANGE_GREEN 0x4256 +#define mmDCP5_KEY_RANGE_GREEN 0x4456 +#define mmKEY_RANGE_BLUE 0x1a57 +#define mmDCP0_KEY_RANGE_BLUE 0x1a57 +#define mmDCP1_KEY_RANGE_BLUE 0x1c57 +#define mmDCP2_KEY_RANGE_BLUE 0x1e57 +#define mmDCP3_KEY_RANGE_BLUE 0x4057 +#define mmDCP4_KEY_RANGE_BLUE 0x4257 +#define mmDCP5_KEY_RANGE_BLUE 0x4457 +#define mmDEGAMMA_CONTROL 0x1a58 +#define mmDCP0_DEGAMMA_CONTROL 0x1a58 +#define mmDCP1_DEGAMMA_CONTROL 0x1c58 +#define mmDCP2_DEGAMMA_CONTROL 0x1e58 +#define mmDCP3_DEGAMMA_CONTROL 0x4058 +#define mmDCP4_DEGAMMA_CONTROL 0x4258 +#define mmDCP5_DEGAMMA_CONTROL 0x4458 +#define mmGAMUT_REMAP_CONTROL 0x1a59 +#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 +#define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 +#define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 +#define mmDCP3_GAMUT_REMAP_CONTROL 0x4059 +#define mmDCP4_GAMUT_REMAP_CONTROL 0x4259 +#define mmDCP5_GAMUT_REMAP_CONTROL 0x4459 +#define mmGAMUT_REMAP_C11_C12 0x1a5a +#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a +#define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a +#define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a +#define mmDCP3_GAMUT_REMAP_C11_C12 0x405a +#define mmDCP4_GAMUT_REMAP_C11_C12 0x425a +#define mmDCP5_GAMUT_REMAP_C11_C12 0x445a +#define mmGAMUT_REMAP_C13_C14 0x1a5b +#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b +#define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b +#define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b +#define mmDCP3_GAMUT_REMAP_C13_C14 0x405b +#define mmDCP4_GAMUT_REMAP_C13_C14 0x425b +#define mmDCP5_GAMUT_REMAP_C13_C14 0x445b +#define mmGAMUT_REMAP_C21_C22 0x1a5c +#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c +#define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c +#define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c +#define mmDCP3_GAMUT_REMAP_C21_C22 0x405c +#define mmDCP4_GAMUT_REMAP_C21_C22 0x425c +#define mmDCP5_GAMUT_REMAP_C21_C22 0x445c +#define mmGAMUT_REMAP_C23_C24 0x1a5d +#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d +#define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d +#define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d +#define mmDCP3_GAMUT_REMAP_C23_C24 0x405d +#define mmDCP4_GAMUT_REMAP_C23_C24 0x425d +#define mmDCP5_GAMUT_REMAP_C23_C24 0x445d +#define mmGAMUT_REMAP_C31_C32 0x1a5e +#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e +#define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e +#define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e +#define mmDCP3_GAMUT_REMAP_C31_C32 0x405e +#define mmDCP4_GAMUT_REMAP_C31_C32 0x425e +#define mmDCP5_GAMUT_REMAP_C31_C32 0x445e +#define mmGAMUT_REMAP_C33_C34 0x1a5f +#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f +#define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f +#define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f +#define mmDCP3_GAMUT_REMAP_C33_C34 0x405f +#define mmDCP4_GAMUT_REMAP_C33_C34 0x425f +#define mmDCP5_GAMUT_REMAP_C33_C34 0x445f +#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 +#define mmDCP_RANDOM_SEEDS 0x1a61 +#define mmDCP0_DCP_RANDOM_SEEDS 0x1a61 +#define mmDCP1_DCP_RANDOM_SEEDS 0x1c61 +#define mmDCP2_DCP_RANDOM_SEEDS 0x1e61 +#define mmDCP3_DCP_RANDOM_SEEDS 0x4061 +#define mmDCP4_DCP_RANDOM_SEEDS 0x4261 +#define mmDCP5_DCP_RANDOM_SEEDS 0x4461 +#define mmDCP_FP_CONVERTED_FIELD 0x1a65 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 +#define mmCUR_CONTROL 0x1a66 +#define mmDCP0_CUR_CONTROL 0x1a66 +#define mmDCP1_CUR_CONTROL 0x1c66 +#define mmDCP2_CUR_CONTROL 0x1e66 +#define mmDCP3_CUR_CONTROL 0x4066 +#define mmDCP4_CUR_CONTROL 0x4266 +#define mmDCP5_CUR_CONTROL 0x4466 +#define mmCUR_SURFACE_ADDRESS 0x1a67 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x4067 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x4267 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x4467 +#define mmCUR_SIZE 0x1a68 +#define mmDCP0_CUR_SIZE 0x1a68 +#define mmDCP1_CUR_SIZE 0x1c68 +#define mmDCP2_CUR_SIZE 0x1e68 +#define mmDCP3_CUR_SIZE 0x4068 +#define mmDCP4_CUR_SIZE 0x4268 +#define mmDCP5_CUR_SIZE 0x4468 +#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 +#define mmCUR_POSITION 0x1a6a +#define mmDCP0_CUR_POSITION 0x1a6a +#define mmDCP1_CUR_POSITION 0x1c6a +#define mmDCP2_CUR_POSITION 0x1e6a +#define mmDCP3_CUR_POSITION 0x406a +#define mmDCP4_CUR_POSITION 0x426a +#define mmDCP5_CUR_POSITION 0x446a +#define mmCUR_HOT_SPOT 0x1a6b +#define mmDCP0_CUR_HOT_SPOT 0x1a6b +#define mmDCP1_CUR_HOT_SPOT 0x1c6b +#define mmDCP2_CUR_HOT_SPOT 0x1e6b +#define mmDCP3_CUR_HOT_SPOT 0x406b +#define mmDCP4_CUR_HOT_SPOT 0x426b +#define mmDCP5_CUR_HOT_SPOT 0x446b +#define mmCUR_COLOR1 0x1a6c +#define mmDCP0_CUR_COLOR1 0x1a6c +#define mmDCP1_CUR_COLOR1 0x1c6c +#define mmDCP2_CUR_COLOR1 0x1e6c +#define mmDCP3_CUR_COLOR1 0x406c +#define mmDCP4_CUR_COLOR1 0x426c +#define mmDCP5_CUR_COLOR1 0x446c +#define mmCUR_COLOR2 0x1a6d +#define mmDCP0_CUR_COLOR2 0x1a6d +#define mmDCP1_CUR_COLOR2 0x1c6d +#define mmDCP2_CUR_COLOR2 0x1e6d +#define mmDCP3_CUR_COLOR2 0x406d +#define mmDCP4_CUR_COLOR2 0x426d +#define mmDCP5_CUR_COLOR2 0x446d +#define mmCUR_UPDATE 0x1a6e +#define mmDCP0_CUR_UPDATE 0x1a6e +#define mmDCP1_CUR_UPDATE 0x1c6e +#define mmDCP2_CUR_UPDATE 0x1e6e +#define mmDCP3_CUR_UPDATE 0x406e +#define mmDCP4_CUR_UPDATE 0x426e +#define mmDCP5_CUR_UPDATE 0x446e +#define mmCUR_REQUEST_FILTER_CNTL 0x1a99 +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 +#define mmCUR_STEREO_CONTROL 0x1a9a +#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a +#define mmDCP1_CUR_STEREO_CONTROL 0x1c9a +#define mmDCP2_CUR_STEREO_CONTROL 0x1e9a +#define mmDCP3_CUR_STEREO_CONTROL 0x409a +#define mmDCP4_CUR_STEREO_CONTROL 0x429a +#define mmDCP5_CUR_STEREO_CONTROL 0x449a +#define mmDC_LUT_RW_MODE 0x1a78 +#define mmDCP0_DC_LUT_RW_MODE 0x1a78 +#define mmDCP1_DC_LUT_RW_MODE 0x1c78 +#define mmDCP2_DC_LUT_RW_MODE 0x1e78 +#define mmDCP3_DC_LUT_RW_MODE 0x4078 +#define mmDCP4_DC_LUT_RW_MODE 0x4278 +#define mmDCP5_DC_LUT_RW_MODE 0x4478 +#define mmDC_LUT_RW_INDEX 0x1a79 +#define mmDCP0_DC_LUT_RW_INDEX 0x1a79 +#define mmDCP1_DC_LUT_RW_INDEX 0x1c79 +#define mmDCP2_DC_LUT_RW_INDEX 0x1e79 +#define mmDCP3_DC_LUT_RW_INDEX 0x4079 +#define mmDCP4_DC_LUT_RW_INDEX 0x4279 +#define mmDCP5_DC_LUT_RW_INDEX 0x4479 +#define mmDC_LUT_SEQ_COLOR 0x1a7a +#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a +#define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a +#define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a +#define mmDCP3_DC_LUT_SEQ_COLOR 0x407a +#define mmDCP4_DC_LUT_SEQ_COLOR 0x427a +#define mmDCP5_DC_LUT_SEQ_COLOR 0x447a +#define mmDC_LUT_PWL_DATA 0x1a7b +#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b +#define mmDCP1_DC_LUT_PWL_DATA 0x1c7b +#define mmDCP2_DC_LUT_PWL_DATA 0x1e7b +#define mmDCP3_DC_LUT_PWL_DATA 0x407b +#define mmDCP4_DC_LUT_PWL_DATA 0x427b +#define mmDCP5_DC_LUT_PWL_DATA 0x447b +#define mmDC_LUT_30_COLOR 0x1a7c +#define mmDCP0_DC_LUT_30_COLOR 0x1a7c +#define mmDCP1_DC_LUT_30_COLOR 0x1c7c +#define mmDCP2_DC_LUT_30_COLOR 0x1e7c +#define mmDCP3_DC_LUT_30_COLOR 0x407c +#define mmDCP4_DC_LUT_30_COLOR 0x427c +#define mmDCP5_DC_LUT_30_COLOR 0x447c +#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d +#define mmDC_LUT_WRITE_EN_MASK 0x1a7e +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e +#define mmDC_LUT_AUTOFILL 0x1a7f +#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f +#define mmDCP1_DC_LUT_AUTOFILL 0x1c7f +#define mmDCP2_DC_LUT_AUTOFILL 0x1e7f +#define mmDCP3_DC_LUT_AUTOFILL 0x407f +#define mmDCP4_DC_LUT_AUTOFILL 0x427f +#define mmDCP5_DC_LUT_AUTOFILL 0x447f +#define mmDC_LUT_CONTROL 0x1a80 +#define mmDCP0_DC_LUT_CONTROL 0x1a80 +#define mmDCP1_DC_LUT_CONTROL 0x1c80 +#define mmDCP2_DC_LUT_CONTROL 0x1e80 +#define mmDCP3_DC_LUT_CONTROL 0x4080 +#define mmDCP4_DC_LUT_CONTROL 0x4280 +#define mmDCP5_DC_LUT_CONTROL 0x4480 +#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 +#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 +#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 +#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 +#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 +#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 +#define mmDCP_CRC_CONTROL 0x1a87 +#define mmDCP0_DCP_CRC_CONTROL 0x1a87 +#define mmDCP1_DCP_CRC_CONTROL 0x1c87 +#define mmDCP2_DCP_CRC_CONTROL 0x1e87 +#define mmDCP3_DCP_CRC_CONTROL 0x4087 +#define mmDCP4_DCP_CRC_CONTROL 0x4287 +#define mmDCP5_DCP_CRC_CONTROL 0x4487 +#define mmDCP_CRC_MASK 0x1a88 +#define mmDCP0_DCP_CRC_MASK 0x1a88 +#define mmDCP1_DCP_CRC_MASK 0x1c88 +#define mmDCP2_DCP_CRC_MASK 0x1e88 +#define mmDCP3_DCP_CRC_MASK 0x4088 +#define mmDCP4_DCP_CRC_MASK 0x4288 +#define mmDCP5_DCP_CRC_MASK 0x4488 +#define mmDCP_CRC_CURRENT 0x1a89 +#define mmDCP0_DCP_CRC_CURRENT 0x1a89 +#define mmDCP1_DCP_CRC_CURRENT 0x1c89 +#define mmDCP2_DCP_CRC_CURRENT 0x1e89 +#define mmDCP3_DCP_CRC_CURRENT 0x4089 +#define mmDCP4_DCP_CRC_CURRENT 0x4289 +#define mmDCP5_DCP_CRC_CURRENT 0x4489 +#define mmDVMM_PTE_CONTROL 0x1a8a +#define mmDCP0_DVMM_PTE_CONTROL 0x1a8a +#define mmDCP1_DVMM_PTE_CONTROL 0x1c8a +#define mmDCP2_DVMM_PTE_CONTROL 0x1e8a +#define mmDCP3_DVMM_PTE_CONTROL 0x408a +#define mmDCP4_DVMM_PTE_CONTROL 0x428a +#define mmDCP5_DVMM_PTE_CONTROL 0x448a +#define mmDCP_CRC_LAST 0x1a8b +#define mmDCP0_DCP_CRC_LAST 0x1a8b +#define mmDCP1_DCP_CRC_LAST 0x1c8b +#define mmDCP2_DCP_CRC_LAST 0x1e8b +#define mmDCP3_DCP_CRC_LAST 0x408b +#define mmDCP4_DCP_CRC_LAST 0x428b +#define mmDCP5_DCP_CRC_LAST 0x448b +#define mmDCP_DEBUG 0x1a8d +#define mmDCP0_DCP_DEBUG 0x1a8d +#define mmDCP1_DCP_DEBUG 0x1c8d +#define mmDCP2_DCP_DEBUG 0x1e8d +#define mmDCP3_DCP_DEBUG 0x408d +#define mmDCP4_DCP_DEBUG 0x428d +#define mmDCP5_DCP_DEBUG 0x448d +#define mmGRPH_FLIP_RATE_CNTL 0x1a8e +#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e +#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e +#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e +#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e +#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e +#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e +#define mmDCP_GSL_CONTROL 0x1a90 +#define mmDCP0_DCP_GSL_CONTROL 0x1a90 +#define mmDCP1_DCP_GSL_CONTROL 0x1c90 +#define mmDCP2_DCP_GSL_CONTROL 0x1e90 +#define mmDCP3_DCP_GSL_CONTROL 0x4090 +#define mmDCP4_DCP_GSL_CONTROL 0x4290 +#define mmDCP5_DCP_GSL_CONTROL 0x4490 +#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 +#define mmDCP_DEBUG_SG 0x1a92 +#define mmDCP0_DCP_DEBUG_SG 0x1a92 +#define mmDCP1_DCP_DEBUG_SG 0x1c92 +#define mmDCP2_DCP_DEBUG_SG 0x1e92 +#define mmDCP3_DCP_DEBUG_SG 0x4092 +#define mmDCP4_DCP_DEBUG_SG 0x4292 +#define mmDCP5_DCP_DEBUG_SG 0x4492 +#define mmDCP_DEBUG_SG2 0x1a94 +#define mmDCP0_DCP_DEBUG_SG2 0x1a94 +#define mmDCP1_DCP_DEBUG_SG2 0x1c94 +#define mmDCP2_DCP_DEBUG_SG2 0x1e94 +#define mmDCP3_DCP_DEBUG_SG2 0x4094 +#define mmDCP4_DCP_DEBUG_SG2 0x4294 +#define mmDCP5_DCP_DEBUG_SG2 0x4494 +#define mmDCP_DVMM_DEBUG 0x1a93 +#define mmDCP0_DCP_DVMM_DEBUG 0x1a93 +#define mmDCP1_DCP_DVMM_DEBUG 0x1c93 +#define mmDCP2_DCP_DVMM_DEBUG 0x1e93 +#define mmDCP3_DCP_DVMM_DEBUG 0x4093 +#define mmDCP4_DCP_DVMM_DEBUG 0x4293 +#define mmDCP5_DCP_DVMM_DEBUG 0x4493 +#define mmDCP_TEST_DEBUG_INDEX 0x1a95 +#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 +#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 +#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 +#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 +#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 +#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 +#define mmDCP_TEST_DEBUG_DATA 0x1a96 +#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 +#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 +#define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 +#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 +#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 +#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 +#define mmGRPH_STEREOSYNC_FLIP 0x1a97 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 +#define mmDCP_DEBUG2 0x1a98 +#define mmDCP0_DCP_DEBUG2 0x1a98 +#define mmDCP1_DCP_DEBUG2 0x1c98 +#define mmDCP2_DCP_DEBUG2 0x1e98 +#define mmDCP3_DCP_DEBUG2 0x4098 +#define mmDCP4_DCP_DEBUG2 0x4298 +#define mmDCP5_DCP_DEBUG2 0x4498 +#define mmHW_ROTATION 0x1a9e +#define mmDCP0_HW_ROTATION 0x1a9e +#define mmDCP1_HW_ROTATION 0x1c9e +#define mmDCP2_HW_ROTATION 0x1e9e +#define mmDCP3_HW_ROTATION 0x409e +#define mmDCP4_HW_ROTATION 0x429e +#define mmDCP5_HW_ROTATION 0x449e +#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f +#define mmREGAMMA_CONTROL 0x1aa0 +#define mmDCP0_REGAMMA_CONTROL 0x1aa0 +#define mmDCP1_REGAMMA_CONTROL 0x1ca0 +#define mmDCP2_REGAMMA_CONTROL 0x1ea0 +#define mmDCP3_REGAMMA_CONTROL 0x40a0 +#define mmDCP4_REGAMMA_CONTROL 0x42a0 +#define mmDCP5_REGAMMA_CONTROL 0x44a0 +#define mmREGAMMA_LUT_INDEX 0x1aa1 +#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 +#define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 +#define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 +#define mmDCP3_REGAMMA_LUT_INDEX 0x40a1 +#define mmDCP4_REGAMMA_LUT_INDEX 0x42a1 +#define mmDCP5_REGAMMA_LUT_INDEX 0x44a1 +#define mmREGAMMA_LUT_DATA 0x1aa2 +#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 +#define mmDCP1_REGAMMA_LUT_DATA 0x1ca2 +#define mmDCP2_REGAMMA_LUT_DATA 0x1ea2 +#define mmDCP3_REGAMMA_LUT_DATA 0x40a2 +#define mmDCP4_REGAMMA_LUT_DATA 0x42a2 +#define mmDCP5_REGAMMA_LUT_DATA 0x44a2 +#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 +#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 +#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 +#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 +#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 +#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 +#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 +#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa +#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab +#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac +#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad +#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae +#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af +#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 +#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 +#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 +#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 +#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 +#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 +#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 +#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 +#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 +#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 +#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba +#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb +#define mmALPHA_CONTROL 0x1abc +#define mmDCP0_ALPHA_CONTROL 0x1abc +#define mmDCP1_ALPHA_CONTROL 0x1cbc +#define mmDCP2_ALPHA_CONTROL 0x1ebc +#define mmDCP3_ALPHA_CONTROL 0x40bc +#define mmDCP4_ALPHA_CONTROL 0x42bc +#define mmDCP5_ALPHA_CONTROL 0x44bc +#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd +#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be +#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf +#define mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f +#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f +#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f +#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f +#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f +#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f +#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f +#define mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d +#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d +#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d +#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d +#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d +#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d +#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d +#define mmDIG_FE_CNTL 0x4a00 +#define mmDIG0_DIG_FE_CNTL 0x4a00 +#define mmDIG1_DIG_FE_CNTL 0x4b00 +#define mmDIG2_DIG_FE_CNTL 0x4c00 +#define mmDIG3_DIG_FE_CNTL 0x4d00 +#define mmDIG4_DIG_FE_CNTL 0x4e00 +#define mmDIG5_DIG_FE_CNTL 0x4f00 +#define mmDIG6_DIG_FE_CNTL 0x5400 +#define mmDIG7_DIG_FE_CNTL 0x5600 +#define mmDIG8_DIG_FE_CNTL 0x5700 +#define mmDIG_OUTPUT_CRC_CNTL 0x4a01 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 +#define mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601 +#define mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701 +#define mmDIG_OUTPUT_CRC_RESULT 0x4a02 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 +#define mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602 +#define mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702 +#define mmDIG_CLOCK_PATTERN 0x4a03 +#define mmDIG0_DIG_CLOCK_PATTERN 0x4a03 +#define mmDIG1_DIG_CLOCK_PATTERN 0x4b03 +#define mmDIG2_DIG_CLOCK_PATTERN 0x4c03 +#define mmDIG3_DIG_CLOCK_PATTERN 0x4d03 +#define mmDIG4_DIG_CLOCK_PATTERN 0x4e03 +#define mmDIG5_DIG_CLOCK_PATTERN 0x4f03 +#define mmDIG6_DIG_CLOCK_PATTERN 0x5403 +#define mmDIG7_DIG_CLOCK_PATTERN 0x5603 +#define mmDIG8_DIG_CLOCK_PATTERN 0x5703 +#define mmDIG_TEST_PATTERN 0x4a04 +#define mmDIG0_DIG_TEST_PATTERN 0x4a04 +#define mmDIG1_DIG_TEST_PATTERN 0x4b04 +#define mmDIG2_DIG_TEST_PATTERN 0x4c04 +#define mmDIG3_DIG_TEST_PATTERN 0x4d04 +#define mmDIG4_DIG_TEST_PATTERN 0x4e04 +#define mmDIG5_DIG_TEST_PATTERN 0x4f04 +#define mmDIG6_DIG_TEST_PATTERN 0x5404 +#define mmDIG7_DIG_TEST_PATTERN 0x5604 +#define mmDIG8_DIG_TEST_PATTERN 0x5704 +#define mmDIG_RANDOM_PATTERN_SEED 0x4a05 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 +#define mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605 +#define mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705 +#define mmDIG_FIFO_STATUS 0x4a06 +#define mmDIG0_DIG_FIFO_STATUS 0x4a06 +#define mmDIG1_DIG_FIFO_STATUS 0x4b06 +#define mmDIG2_DIG_FIFO_STATUS 0x4c06 +#define mmDIG3_DIG_FIFO_STATUS 0x4d06 +#define mmDIG4_DIG_FIFO_STATUS 0x4e06 +#define mmDIG5_DIG_FIFO_STATUS 0x4f06 +#define mmDIG6_DIG_FIFO_STATUS 0x5406 +#define mmDIG7_DIG_FIFO_STATUS 0x5606 +#define mmDIG8_DIG_FIFO_STATUS 0x5706 +#define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 +#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 +#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 +#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 +#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 +#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 +#define mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607 +#define mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707 +#define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 +#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 +#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 +#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 +#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 +#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 +#define mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608 +#define mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708 +#define mmHDMI_CONTROL 0x4a09 +#define mmDIG0_HDMI_CONTROL 0x4a09 +#define mmDIG1_HDMI_CONTROL 0x4b09 +#define mmDIG2_HDMI_CONTROL 0x4c09 +#define mmDIG3_HDMI_CONTROL 0x4d09 +#define mmDIG4_HDMI_CONTROL 0x4e09 +#define mmDIG5_HDMI_CONTROL 0x4f09 +#define mmDIG6_HDMI_CONTROL 0x5409 +#define mmDIG7_HDMI_CONTROL 0x5609 +#define mmDIG8_HDMI_CONTROL 0x5709 +#define mmHDMI_STATUS 0x4a0a +#define mmDIG0_HDMI_STATUS 0x4a0a +#define mmDIG1_HDMI_STATUS 0x4b0a +#define mmDIG2_HDMI_STATUS 0x4c0a +#define mmDIG3_HDMI_STATUS 0x4d0a +#define mmDIG4_HDMI_STATUS 0x4e0a +#define mmDIG5_HDMI_STATUS 0x4f0a +#define mmDIG6_HDMI_STATUS 0x540a +#define mmDIG7_HDMI_STATUS 0x560a +#define mmDIG8_HDMI_STATUS 0x570a +#define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b +#define mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b +#define mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b +#define mmHDMI_ACR_PACKET_CONTROL 0x4a0c +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c +#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c +#define mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c +#define mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c +#define mmHDMI_VBI_PACKET_CONTROL 0x4a0d +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d +#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d +#define mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d +#define mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d +#define mmHDMI_INFOFRAME_CONTROL0 0x4a0e +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e +#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e +#define mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e +#define mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e +#define mmHDMI_INFOFRAME_CONTROL1 0x4a0f +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f +#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f +#define mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f +#define mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f +#define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 +#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610 +#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710 +#define mmAFMT_INTERRUPT_STATUS 0x4a11 +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 +#define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 +#define mmDIG7_AFMT_INTERRUPT_STATUS 0x5611 +#define mmDIG8_AFMT_INTERRUPT_STATUS 0x5711 +#define mmHDMI_GC 0x4a13 +#define mmDIG0_HDMI_GC 0x4a13 +#define mmDIG1_HDMI_GC 0x4b13 +#define mmDIG2_HDMI_GC 0x4c13 +#define mmDIG3_HDMI_GC 0x4d13 +#define mmDIG4_HDMI_GC 0x4e13 +#define mmDIG5_HDMI_GC 0x4f13 +#define mmDIG6_HDMI_GC 0x5413 +#define mmDIG7_HDMI_GC 0x5613 +#define mmDIG8_HDMI_GC 0x5713 +#define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 +#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614 +#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714 +#define mmAFMT_ISRC1_0 0x4a15 +#define mmDIG0_AFMT_ISRC1_0 0x4a15 +#define mmDIG1_AFMT_ISRC1_0 0x4b15 +#define mmDIG2_AFMT_ISRC1_0 0x4c15 +#define mmDIG3_AFMT_ISRC1_0 0x4d15 +#define mmDIG4_AFMT_ISRC1_0 0x4e15 +#define mmDIG5_AFMT_ISRC1_0 0x4f15 +#define mmDIG6_AFMT_ISRC1_0 0x5415 +#define mmDIG7_AFMT_ISRC1_0 0x5615 +#define mmDIG8_AFMT_ISRC1_0 0x5715 +#define mmAFMT_ISRC1_1 0x4a16 +#define mmDIG0_AFMT_ISRC1_1 0x4a16 +#define mmDIG1_AFMT_ISRC1_1 0x4b16 +#define mmDIG2_AFMT_ISRC1_1 0x4c16 +#define mmDIG3_AFMT_ISRC1_1 0x4d16 +#define mmDIG4_AFMT_ISRC1_1 0x4e16 +#define mmDIG5_AFMT_ISRC1_1 0x4f16 +#define mmDIG6_AFMT_ISRC1_1 0x5416 +#define mmDIG7_AFMT_ISRC1_1 0x5616 +#define mmDIG8_AFMT_ISRC1_1 0x5716 +#define mmAFMT_ISRC1_2 0x4a17 +#define mmDIG0_AFMT_ISRC1_2 0x4a17 +#define mmDIG1_AFMT_ISRC1_2 0x4b17 +#define mmDIG2_AFMT_ISRC1_2 0x4c17 +#define mmDIG3_AFMT_ISRC1_2 0x4d17 +#define mmDIG4_AFMT_ISRC1_2 0x4e17 +#define mmDIG5_AFMT_ISRC1_2 0x4f17 +#define mmDIG6_AFMT_ISRC1_2 0x5417 +#define mmDIG7_AFMT_ISRC1_2 0x5617 +#define mmDIG8_AFMT_ISRC1_2 0x5717 +#define mmAFMT_ISRC1_3 0x4a18 +#define mmDIG0_AFMT_ISRC1_3 0x4a18 +#define mmDIG1_AFMT_ISRC1_3 0x4b18 +#define mmDIG2_AFMT_ISRC1_3 0x4c18 +#define mmDIG3_AFMT_ISRC1_3 0x4d18 +#define mmDIG4_AFMT_ISRC1_3 0x4e18 +#define mmDIG5_AFMT_ISRC1_3 0x4f18 +#define mmDIG6_AFMT_ISRC1_3 0x5418 +#define mmDIG7_AFMT_ISRC1_3 0x5618 +#define mmDIG8_AFMT_ISRC1_3 0x5718 +#define mmAFMT_ISRC1_4 0x4a19 +#define mmDIG0_AFMT_ISRC1_4 0x4a19 +#define mmDIG1_AFMT_ISRC1_4 0x4b19 +#define mmDIG2_AFMT_ISRC1_4 0x4c19 +#define mmDIG3_AFMT_ISRC1_4 0x4d19 +#define mmDIG4_AFMT_ISRC1_4 0x4e19 +#define mmDIG5_AFMT_ISRC1_4 0x4f19 +#define mmDIG6_AFMT_ISRC1_4 0x5419 +#define mmDIG7_AFMT_ISRC1_4 0x5619 +#define mmDIG8_AFMT_ISRC1_4 0x5719 +#define mmAFMT_ISRC2_0 0x4a1a +#define mmDIG0_AFMT_ISRC2_0 0x4a1a +#define mmDIG1_AFMT_ISRC2_0 0x4b1a +#define mmDIG2_AFMT_ISRC2_0 0x4c1a +#define mmDIG3_AFMT_ISRC2_0 0x4d1a +#define mmDIG4_AFMT_ISRC2_0 0x4e1a +#define mmDIG5_AFMT_ISRC2_0 0x4f1a +#define mmDIG6_AFMT_ISRC2_0 0x541a +#define mmDIG7_AFMT_ISRC2_0 0x561a +#define mmDIG8_AFMT_ISRC2_0 0x571a +#define mmAFMT_ISRC2_1 0x4a1b +#define mmDIG0_AFMT_ISRC2_1 0x4a1b +#define mmDIG1_AFMT_ISRC2_1 0x4b1b +#define mmDIG2_AFMT_ISRC2_1 0x4c1b +#define mmDIG3_AFMT_ISRC2_1 0x4d1b +#define mmDIG4_AFMT_ISRC2_1 0x4e1b +#define mmDIG5_AFMT_ISRC2_1 0x4f1b +#define mmDIG6_AFMT_ISRC2_1 0x541b +#define mmDIG7_AFMT_ISRC2_1 0x561b +#define mmDIG8_AFMT_ISRC2_1 0x571b +#define mmAFMT_ISRC2_2 0x4a1c +#define mmDIG0_AFMT_ISRC2_2 0x4a1c +#define mmDIG1_AFMT_ISRC2_2 0x4b1c +#define mmDIG2_AFMT_ISRC2_2 0x4c1c +#define mmDIG3_AFMT_ISRC2_2 0x4d1c +#define mmDIG4_AFMT_ISRC2_2 0x4e1c +#define mmDIG5_AFMT_ISRC2_2 0x4f1c +#define mmDIG6_AFMT_ISRC2_2 0x541c +#define mmDIG7_AFMT_ISRC2_2 0x561c +#define mmDIG8_AFMT_ISRC2_2 0x571c +#define mmAFMT_ISRC2_3 0x4a1d +#define mmDIG0_AFMT_ISRC2_3 0x4a1d +#define mmDIG1_AFMT_ISRC2_3 0x4b1d +#define mmDIG2_AFMT_ISRC2_3 0x4c1d +#define mmDIG3_AFMT_ISRC2_3 0x4d1d +#define mmDIG4_AFMT_ISRC2_3 0x4e1d +#define mmDIG5_AFMT_ISRC2_3 0x4f1d +#define mmDIG6_AFMT_ISRC2_3 0x541d +#define mmDIG7_AFMT_ISRC2_3 0x561d +#define mmDIG8_AFMT_ISRC2_3 0x571d +#define mmAFMT_AVI_INFO0 0x4a1e +#define mmDIG0_AFMT_AVI_INFO0 0x4a1e +#define mmDIG1_AFMT_AVI_INFO0 0x4b1e +#define mmDIG2_AFMT_AVI_INFO0 0x4c1e +#define mmDIG3_AFMT_AVI_INFO0 0x4d1e +#define mmDIG4_AFMT_AVI_INFO0 0x4e1e +#define mmDIG5_AFMT_AVI_INFO0 0x4f1e +#define mmDIG6_AFMT_AVI_INFO0 0x541e +#define mmDIG7_AFMT_AVI_INFO0 0x561e +#define mmDIG8_AFMT_AVI_INFO0 0x571e +#define mmAFMT_AVI_INFO1 0x4a1f +#define mmDIG0_AFMT_AVI_INFO1 0x4a1f +#define mmDIG1_AFMT_AVI_INFO1 0x4b1f +#define mmDIG2_AFMT_AVI_INFO1 0x4c1f +#define mmDIG3_AFMT_AVI_INFO1 0x4d1f +#define mmDIG4_AFMT_AVI_INFO1 0x4e1f +#define mmDIG5_AFMT_AVI_INFO1 0x4f1f +#define mmDIG6_AFMT_AVI_INFO1 0x541f +#define mmDIG7_AFMT_AVI_INFO1 0x561f +#define mmDIG8_AFMT_AVI_INFO1 0x571f +#define mmAFMT_AVI_INFO2 0x4a20 +#define mmDIG0_AFMT_AVI_INFO2 0x4a20 +#define mmDIG1_AFMT_AVI_INFO2 0x4b20 +#define mmDIG2_AFMT_AVI_INFO2 0x4c20 +#define mmDIG3_AFMT_AVI_INFO2 0x4d20 +#define mmDIG4_AFMT_AVI_INFO2 0x4e20 +#define mmDIG5_AFMT_AVI_INFO2 0x4f20 +#define mmDIG6_AFMT_AVI_INFO2 0x5420 +#define mmDIG7_AFMT_AVI_INFO2 0x5620 +#define mmDIG8_AFMT_AVI_INFO2 0x5720 +#define mmAFMT_AVI_INFO3 0x4a21 +#define mmDIG0_AFMT_AVI_INFO3 0x4a21 +#define mmDIG1_AFMT_AVI_INFO3 0x4b21 +#define mmDIG2_AFMT_AVI_INFO3 0x4c21 +#define mmDIG3_AFMT_AVI_INFO3 0x4d21 +#define mmDIG4_AFMT_AVI_INFO3 0x4e21 +#define mmDIG5_AFMT_AVI_INFO3 0x4f21 +#define mmDIG6_AFMT_AVI_INFO3 0x5421 +#define mmDIG7_AFMT_AVI_INFO3 0x5621 +#define mmDIG8_AFMT_AVI_INFO3 0x5721 +#define mmAFMT_MPEG_INFO0 0x4a22 +#define mmDIG0_AFMT_MPEG_INFO0 0x4a22 +#define mmDIG1_AFMT_MPEG_INFO0 0x4b22 +#define mmDIG2_AFMT_MPEG_INFO0 0x4c22 +#define mmDIG3_AFMT_MPEG_INFO0 0x4d22 +#define mmDIG4_AFMT_MPEG_INFO0 0x4e22 +#define mmDIG5_AFMT_MPEG_INFO0 0x4f22 +#define mmDIG6_AFMT_MPEG_INFO0 0x5422 +#define mmDIG7_AFMT_MPEG_INFO0 0x5622 +#define mmDIG8_AFMT_MPEG_INFO0 0x5722 +#define mmAFMT_MPEG_INFO1 0x4a23 +#define mmDIG0_AFMT_MPEG_INFO1 0x4a23 +#define mmDIG1_AFMT_MPEG_INFO1 0x4b23 +#define mmDIG2_AFMT_MPEG_INFO1 0x4c23 +#define mmDIG3_AFMT_MPEG_INFO1 0x4d23 +#define mmDIG4_AFMT_MPEG_INFO1 0x4e23 +#define mmDIG5_AFMT_MPEG_INFO1 0x4f23 +#define mmDIG6_AFMT_MPEG_INFO1 0x5423 +#define mmDIG7_AFMT_MPEG_INFO1 0x5623 +#define mmDIG8_AFMT_MPEG_INFO1 0x5723 +#define mmAFMT_GENERIC_HDR 0x4a24 +#define mmDIG0_AFMT_GENERIC_HDR 0x4a24 +#define mmDIG1_AFMT_GENERIC_HDR 0x4b24 +#define mmDIG2_AFMT_GENERIC_HDR 0x4c24 +#define mmDIG3_AFMT_GENERIC_HDR 0x4d24 +#define mmDIG4_AFMT_GENERIC_HDR 0x4e24 +#define mmDIG5_AFMT_GENERIC_HDR 0x4f24 +#define mmDIG6_AFMT_GENERIC_HDR 0x5424 +#define mmDIG7_AFMT_GENERIC_HDR 0x5624 +#define mmDIG8_AFMT_GENERIC_HDR 0x5724 +#define mmAFMT_GENERIC_0 0x4a25 +#define mmDIG0_AFMT_GENERIC_0 0x4a25 +#define mmDIG1_AFMT_GENERIC_0 0x4b25 +#define mmDIG2_AFMT_GENERIC_0 0x4c25 +#define mmDIG3_AFMT_GENERIC_0 0x4d25 +#define mmDIG4_AFMT_GENERIC_0 0x4e25 +#define mmDIG5_AFMT_GENERIC_0 0x4f25 +#define mmDIG6_AFMT_GENERIC_0 0x5425 +#define mmDIG7_AFMT_GENERIC_0 0x5625 +#define mmDIG8_AFMT_GENERIC_0 0x5725 +#define mmAFMT_GENERIC_1 0x4a26 +#define mmDIG0_AFMT_GENERIC_1 0x4a26 +#define mmDIG1_AFMT_GENERIC_1 0x4b26 +#define mmDIG2_AFMT_GENERIC_1 0x4c26 +#define mmDIG3_AFMT_GENERIC_1 0x4d26 +#define mmDIG4_AFMT_GENERIC_1 0x4e26 +#define mmDIG5_AFMT_GENERIC_1 0x4f26 +#define mmDIG6_AFMT_GENERIC_1 0x5426 +#define mmDIG7_AFMT_GENERIC_1 0x5626 +#define mmDIG8_AFMT_GENERIC_1 0x5726 +#define mmAFMT_GENERIC_2 0x4a27 +#define mmDIG0_AFMT_GENERIC_2 0x4a27 +#define mmDIG1_AFMT_GENERIC_2 0x4b27 +#define mmDIG2_AFMT_GENERIC_2 0x4c27 +#define mmDIG3_AFMT_GENERIC_2 0x4d27 +#define mmDIG4_AFMT_GENERIC_2 0x4e27 +#define mmDIG5_AFMT_GENERIC_2 0x4f27 +#define mmDIG6_AFMT_GENERIC_2 0x5427 +#define mmDIG7_AFMT_GENERIC_2 0x5627 +#define mmDIG8_AFMT_GENERIC_2 0x5727 +#define mmAFMT_GENERIC_3 0x4a28 +#define mmDIG0_AFMT_GENERIC_3 0x4a28 +#define mmDIG1_AFMT_GENERIC_3 0x4b28 +#define mmDIG2_AFMT_GENERIC_3 0x4c28 +#define mmDIG3_AFMT_GENERIC_3 0x4d28 +#define mmDIG4_AFMT_GENERIC_3 0x4e28 +#define mmDIG5_AFMT_GENERIC_3 0x4f28 +#define mmDIG6_AFMT_GENERIC_3 0x5428 +#define mmDIG7_AFMT_GENERIC_3 0x5628 +#define mmDIG8_AFMT_GENERIC_3 0x5728 +#define mmAFMT_GENERIC_4 0x4a29 +#define mmDIG0_AFMT_GENERIC_4 0x4a29 +#define mmDIG1_AFMT_GENERIC_4 0x4b29 +#define mmDIG2_AFMT_GENERIC_4 0x4c29 +#define mmDIG3_AFMT_GENERIC_4 0x4d29 +#define mmDIG4_AFMT_GENERIC_4 0x4e29 +#define mmDIG5_AFMT_GENERIC_4 0x4f29 +#define mmDIG6_AFMT_GENERIC_4 0x5429 +#define mmDIG7_AFMT_GENERIC_4 0x5629 +#define mmDIG8_AFMT_GENERIC_4 0x5729 +#define mmAFMT_GENERIC_5 0x4a2a +#define mmDIG0_AFMT_GENERIC_5 0x4a2a +#define mmDIG1_AFMT_GENERIC_5 0x4b2a +#define mmDIG2_AFMT_GENERIC_5 0x4c2a +#define mmDIG3_AFMT_GENERIC_5 0x4d2a +#define mmDIG4_AFMT_GENERIC_5 0x4e2a +#define mmDIG5_AFMT_GENERIC_5 0x4f2a +#define mmDIG6_AFMT_GENERIC_5 0x542a +#define mmDIG7_AFMT_GENERIC_5 0x562a +#define mmDIG8_AFMT_GENERIC_5 0x572a +#define mmAFMT_GENERIC_6 0x4a2b +#define mmDIG0_AFMT_GENERIC_6 0x4a2b +#define mmDIG1_AFMT_GENERIC_6 0x4b2b +#define mmDIG2_AFMT_GENERIC_6 0x4c2b +#define mmDIG3_AFMT_GENERIC_6 0x4d2b +#define mmDIG4_AFMT_GENERIC_6 0x4e2b +#define mmDIG5_AFMT_GENERIC_6 0x4f2b +#define mmDIG6_AFMT_GENERIC_6 0x542b +#define mmDIG7_AFMT_GENERIC_6 0x562b +#define mmDIG8_AFMT_GENERIC_6 0x572b +#define mmAFMT_GENERIC_7 0x4a2c +#define mmDIG0_AFMT_GENERIC_7 0x4a2c +#define mmDIG1_AFMT_GENERIC_7 0x4b2c +#define mmDIG2_AFMT_GENERIC_7 0x4c2c +#define mmDIG3_AFMT_GENERIC_7 0x4d2c +#define mmDIG4_AFMT_GENERIC_7 0x4e2c +#define mmDIG5_AFMT_GENERIC_7 0x4f2c +#define mmDIG6_AFMT_GENERIC_7 0x542c +#define mmDIG7_AFMT_GENERIC_7 0x562c +#define mmDIG8_AFMT_GENERIC_7 0x572c +#define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d +#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d +#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d +#define mmHDMI_ACR_32_0 0x4a2e +#define mmDIG0_HDMI_ACR_32_0 0x4a2e +#define mmDIG1_HDMI_ACR_32_0 0x4b2e +#define mmDIG2_HDMI_ACR_32_0 0x4c2e +#define mmDIG3_HDMI_ACR_32_0 0x4d2e +#define mmDIG4_HDMI_ACR_32_0 0x4e2e +#define mmDIG5_HDMI_ACR_32_0 0x4f2e +#define mmDIG6_HDMI_ACR_32_0 0x542e +#define mmDIG7_HDMI_ACR_32_0 0x562e +#define mmDIG8_HDMI_ACR_32_0 0x572e +#define mmHDMI_ACR_32_1 0x4a2f +#define mmDIG0_HDMI_ACR_32_1 0x4a2f +#define mmDIG1_HDMI_ACR_32_1 0x4b2f +#define mmDIG2_HDMI_ACR_32_1 0x4c2f +#define mmDIG3_HDMI_ACR_32_1 0x4d2f +#define mmDIG4_HDMI_ACR_32_1 0x4e2f +#define mmDIG5_HDMI_ACR_32_1 0x4f2f +#define mmDIG6_HDMI_ACR_32_1 0x542f +#define mmDIG7_HDMI_ACR_32_1 0x562f +#define mmDIG8_HDMI_ACR_32_1 0x572f +#define mmHDMI_ACR_44_0 0x4a30 +#define mmDIG0_HDMI_ACR_44_0 0x4a30 +#define mmDIG1_HDMI_ACR_44_0 0x4b30 +#define mmDIG2_HDMI_ACR_44_0 0x4c30 +#define mmDIG3_HDMI_ACR_44_0 0x4d30 +#define mmDIG4_HDMI_ACR_44_0 0x4e30 +#define mmDIG5_HDMI_ACR_44_0 0x4f30 +#define mmDIG6_HDMI_ACR_44_0 0x5430 +#define mmDIG7_HDMI_ACR_44_0 0x5630 +#define mmDIG8_HDMI_ACR_44_0 0x5730 +#define mmHDMI_ACR_44_1 0x4a31 +#define mmDIG0_HDMI_ACR_44_1 0x4a31 +#define mmDIG1_HDMI_ACR_44_1 0x4b31 +#define mmDIG2_HDMI_ACR_44_1 0x4c31 +#define mmDIG3_HDMI_ACR_44_1 0x4d31 +#define mmDIG4_HDMI_ACR_44_1 0x4e31 +#define mmDIG5_HDMI_ACR_44_1 0x4f31 +#define mmDIG6_HDMI_ACR_44_1 0x5431 +#define mmDIG7_HDMI_ACR_44_1 0x5631 +#define mmDIG8_HDMI_ACR_44_1 0x5731 +#define mmHDMI_ACR_48_0 0x4a32 +#define mmDIG0_HDMI_ACR_48_0 0x4a32 +#define mmDIG1_HDMI_ACR_48_0 0x4b32 +#define mmDIG2_HDMI_ACR_48_0 0x4c32 +#define mmDIG3_HDMI_ACR_48_0 0x4d32 +#define mmDIG4_HDMI_ACR_48_0 0x4e32 +#define mmDIG5_HDMI_ACR_48_0 0x4f32 +#define mmDIG6_HDMI_ACR_48_0 0x5432 +#define mmDIG7_HDMI_ACR_48_0 0x5632 +#define mmDIG8_HDMI_ACR_48_0 0x5732 +#define mmHDMI_ACR_48_1 0x4a33 +#define mmDIG0_HDMI_ACR_48_1 0x4a33 +#define mmDIG1_HDMI_ACR_48_1 0x4b33 +#define mmDIG2_HDMI_ACR_48_1 0x4c33 +#define mmDIG3_HDMI_ACR_48_1 0x4d33 +#define mmDIG4_HDMI_ACR_48_1 0x4e33 +#define mmDIG5_HDMI_ACR_48_1 0x4f33 +#define mmDIG6_HDMI_ACR_48_1 0x5433 +#define mmDIG7_HDMI_ACR_48_1 0x5633 +#define mmDIG8_HDMI_ACR_48_1 0x5733 +#define mmHDMI_ACR_STATUS_0 0x4a34 +#define mmDIG0_HDMI_ACR_STATUS_0 0x4a34 +#define mmDIG1_HDMI_ACR_STATUS_0 0x4b34 +#define mmDIG2_HDMI_ACR_STATUS_0 0x4c34 +#define mmDIG3_HDMI_ACR_STATUS_0 0x4d34 +#define mmDIG4_HDMI_ACR_STATUS_0 0x4e34 +#define mmDIG5_HDMI_ACR_STATUS_0 0x4f34 +#define mmDIG6_HDMI_ACR_STATUS_0 0x5434 +#define mmDIG7_HDMI_ACR_STATUS_0 0x5634 +#define mmDIG8_HDMI_ACR_STATUS_0 0x5734 +#define mmHDMI_ACR_STATUS_1 0x4a35 +#define mmDIG0_HDMI_ACR_STATUS_1 0x4a35 +#define mmDIG1_HDMI_ACR_STATUS_1 0x4b35 +#define mmDIG2_HDMI_ACR_STATUS_1 0x4c35 +#define mmDIG3_HDMI_ACR_STATUS_1 0x4d35 +#define mmDIG4_HDMI_ACR_STATUS_1 0x4e35 +#define mmDIG5_HDMI_ACR_STATUS_1 0x4f35 +#define mmDIG6_HDMI_ACR_STATUS_1 0x5435 +#define mmDIG7_HDMI_ACR_STATUS_1 0x5635 +#define mmDIG8_HDMI_ACR_STATUS_1 0x5735 +#define mmAFMT_AUDIO_INFO0 0x4a36 +#define mmDIG0_AFMT_AUDIO_INFO0 0x4a36 +#define mmDIG1_AFMT_AUDIO_INFO0 0x4b36 +#define mmDIG2_AFMT_AUDIO_INFO0 0x4c36 +#define mmDIG3_AFMT_AUDIO_INFO0 0x4d36 +#define mmDIG4_AFMT_AUDIO_INFO0 0x4e36 +#define mmDIG5_AFMT_AUDIO_INFO0 0x4f36 +#define mmDIG6_AFMT_AUDIO_INFO0 0x5436 +#define mmDIG7_AFMT_AUDIO_INFO0 0x5636 +#define mmDIG8_AFMT_AUDIO_INFO0 0x5736 +#define mmAFMT_AUDIO_INFO1 0x4a37 +#define mmDIG0_AFMT_AUDIO_INFO1 0x4a37 +#define mmDIG1_AFMT_AUDIO_INFO1 0x4b37 +#define mmDIG2_AFMT_AUDIO_INFO1 0x4c37 +#define mmDIG3_AFMT_AUDIO_INFO1 0x4d37 +#define mmDIG4_AFMT_AUDIO_INFO1 0x4e37 +#define mmDIG5_AFMT_AUDIO_INFO1 0x4f37 +#define mmDIG6_AFMT_AUDIO_INFO1 0x5437 +#define mmDIG7_AFMT_AUDIO_INFO1 0x5637 +#define mmDIG8_AFMT_AUDIO_INFO1 0x5737 +#define mmAFMT_60958_0 0x4a38 +#define mmDIG0_AFMT_60958_0 0x4a38 +#define mmDIG1_AFMT_60958_0 0x4b38 +#define mmDIG2_AFMT_60958_0 0x4c38 +#define mmDIG3_AFMT_60958_0 0x4d38 +#define mmDIG4_AFMT_60958_0 0x4e38 +#define mmDIG5_AFMT_60958_0 0x4f38 +#define mmDIG6_AFMT_60958_0 0x5438 +#define mmDIG7_AFMT_60958_0 0x5638 +#define mmDIG8_AFMT_60958_0 0x5738 +#define mmAFMT_60958_1 0x4a39 +#define mmDIG0_AFMT_60958_1 0x4a39 +#define mmDIG1_AFMT_60958_1 0x4b39 +#define mmDIG2_AFMT_60958_1 0x4c39 +#define mmDIG3_AFMT_60958_1 0x4d39 +#define mmDIG4_AFMT_60958_1 0x4e39 +#define mmDIG5_AFMT_60958_1 0x4f39 +#define mmDIG6_AFMT_60958_1 0x5439 +#define mmDIG7_AFMT_60958_1 0x5639 +#define mmDIG8_AFMT_60958_1 0x5739 +#define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a +#define mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a +#define mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a +#define mmAFMT_RAMP_CONTROL0 0x4a3b +#define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b +#define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b +#define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b +#define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b +#define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b +#define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b +#define mmDIG6_AFMT_RAMP_CONTROL0 0x543b +#define mmDIG7_AFMT_RAMP_CONTROL0 0x563b +#define mmDIG8_AFMT_RAMP_CONTROL0 0x573b +#define mmAFMT_RAMP_CONTROL1 0x4a3c +#define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c +#define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c +#define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c +#define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c +#define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c +#define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c +#define mmDIG6_AFMT_RAMP_CONTROL1 0x543c +#define mmDIG7_AFMT_RAMP_CONTROL1 0x563c +#define mmDIG8_AFMT_RAMP_CONTROL1 0x573c +#define mmAFMT_RAMP_CONTROL2 0x4a3d +#define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d +#define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d +#define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d +#define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d +#define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d +#define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d +#define mmDIG6_AFMT_RAMP_CONTROL2 0x543d +#define mmDIG7_AFMT_RAMP_CONTROL2 0x563d +#define mmDIG8_AFMT_RAMP_CONTROL2 0x573d +#define mmAFMT_RAMP_CONTROL3 0x4a3e +#define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e +#define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e +#define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e +#define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e +#define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e +#define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e +#define mmDIG6_AFMT_RAMP_CONTROL3 0x543e +#define mmDIG7_AFMT_RAMP_CONTROL3 0x563e +#define mmDIG8_AFMT_RAMP_CONTROL3 0x573e +#define mmAFMT_60958_2 0x4a3f +#define mmDIG0_AFMT_60958_2 0x4a3f +#define mmDIG1_AFMT_60958_2 0x4b3f +#define mmDIG2_AFMT_60958_2 0x4c3f +#define mmDIG3_AFMT_60958_2 0x4d3f +#define mmDIG4_AFMT_60958_2 0x4e3f +#define mmDIG5_AFMT_60958_2 0x4f3f +#define mmDIG6_AFMT_60958_2 0x543f +#define mmDIG7_AFMT_60958_2 0x563f +#define mmDIG8_AFMT_60958_2 0x573f +#define mmAFMT_AUDIO_CRC_RESULT 0x4a40 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 +#define mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640 +#define mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740 +#define mmAFMT_STATUS 0x4a41 +#define mmDIG0_AFMT_STATUS 0x4a41 +#define mmDIG1_AFMT_STATUS 0x4b41 +#define mmDIG2_AFMT_STATUS 0x4c41 +#define mmDIG3_AFMT_STATUS 0x4d41 +#define mmDIG4_AFMT_STATUS 0x4e41 +#define mmDIG5_AFMT_STATUS 0x4f41 +#define mmDIG6_AFMT_STATUS 0x5441 +#define mmDIG7_AFMT_STATUS 0x5641 +#define mmDIG8_AFMT_STATUS 0x5741 +#define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 +#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642 +#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742 +#define mmAFMT_VBI_PACKET_CONTROL 0x4a43 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 +#define mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643 +#define mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743 +#define mmAFMT_INFOFRAME_CONTROL0 0x4a44 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 +#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 +#define mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644 +#define mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744 +#define mmAFMT_AUDIO_SRC_CONTROL 0x4a45 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 +#define mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645 +#define mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745 +#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 +#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 +#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 +#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 +#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 +#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 +#define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646 +#define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746 +#define mmAFMT_CNTL 0x4a7e +#define mmDIG0_AFMT_CNTL 0x4a7e +#define mmDIG1_AFMT_CNTL 0x4b7e +#define mmDIG2_AFMT_CNTL 0x4c7e +#define mmDIG3_AFMT_CNTL 0x4d7e +#define mmDIG4_AFMT_CNTL 0x4e7e +#define mmDIG5_AFMT_CNTL 0x4f7e +#define mmDIG6_AFMT_CNTL 0x547e +#define mmDIG7_AFMT_CNTL 0x567e +#define mmDIG8_AFMT_CNTL 0x577e +#define mmDIG_BE_CNTL 0x4a47 +#define mmDIG0_DIG_BE_CNTL 0x4a47 +#define mmDIG1_DIG_BE_CNTL 0x4b47 +#define mmDIG2_DIG_BE_CNTL 0x4c47 +#define mmDIG3_DIG_BE_CNTL 0x4d47 +#define mmDIG4_DIG_BE_CNTL 0x4e47 +#define mmDIG5_DIG_BE_CNTL 0x4f47 +#define mmDIG6_DIG_BE_CNTL 0x5447 +#define mmDIG7_DIG_BE_CNTL 0x5647 +#define mmDIG8_DIG_BE_CNTL 0x5747 +#define mmDIG_BE_EN_CNTL 0x4a48 +#define mmDIG0_DIG_BE_EN_CNTL 0x4a48 +#define mmDIG1_DIG_BE_EN_CNTL 0x4b48 +#define mmDIG2_DIG_BE_EN_CNTL 0x4c48 +#define mmDIG3_DIG_BE_EN_CNTL 0x4d48 +#define mmDIG4_DIG_BE_EN_CNTL 0x4e48 +#define mmDIG5_DIG_BE_EN_CNTL 0x4f48 +#define mmDIG6_DIG_BE_EN_CNTL 0x5448 +#define mmDIG7_DIG_BE_EN_CNTL 0x5648 +#define mmDIG8_DIG_BE_EN_CNTL 0x5748 +#define mmTMDS_CNTL 0x4a6b +#define mmDIG0_TMDS_CNTL 0x4a6b +#define mmDIG1_TMDS_CNTL 0x4b6b +#define mmDIG2_TMDS_CNTL 0x4c6b +#define mmDIG3_TMDS_CNTL 0x4d6b +#define mmDIG4_TMDS_CNTL 0x4e6b +#define mmDIG5_TMDS_CNTL 0x4f6b +#define mmDIG6_TMDS_CNTL 0x546b +#define mmDIG7_TMDS_CNTL 0x566b +#define mmDIG8_TMDS_CNTL 0x576b +#define mmTMDS_CONTROL_CHAR 0x4a6c +#define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c +#define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c +#define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c +#define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c +#define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c +#define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c +#define mmDIG6_TMDS_CONTROL_CHAR 0x546c +#define mmDIG7_TMDS_CONTROL_CHAR 0x566c +#define mmDIG8_TMDS_CONTROL_CHAR 0x576c +#define mmTMDS_CONTROL0_FEEDBACK 0x4a6d +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d +#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d +#define mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d +#define mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d +#define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e +#define mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e +#define mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e +#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f +#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f +#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f +#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 +#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670 +#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770 +#define mmTMDS_DEBUG 0x4a71 +#define mmDIG0_TMDS_DEBUG 0x4a71 +#define mmDIG1_TMDS_DEBUG 0x4b71 +#define mmDIG2_TMDS_DEBUG 0x4c71 +#define mmDIG3_TMDS_DEBUG 0x4d71 +#define mmDIG4_TMDS_DEBUG 0x4e71 +#define mmDIG5_TMDS_DEBUG 0x4f71 +#define mmDIG6_TMDS_DEBUG 0x5471 +#define mmDIG7_TMDS_DEBUG 0x5671 +#define mmDIG8_TMDS_DEBUG 0x5771 +#define mmTMDS_CTL_BITS 0x4a72 +#define mmDIG0_TMDS_CTL_BITS 0x4a72 +#define mmDIG1_TMDS_CTL_BITS 0x4b72 +#define mmDIG2_TMDS_CTL_BITS 0x4c72 +#define mmDIG3_TMDS_CTL_BITS 0x4d72 +#define mmDIG4_TMDS_CTL_BITS 0x4e72 +#define mmDIG5_TMDS_CTL_BITS 0x4f72 +#define mmDIG6_TMDS_CTL_BITS 0x5472 +#define mmDIG7_TMDS_CTL_BITS 0x5672 +#define mmDIG8_TMDS_CTL_BITS 0x5772 +#define mmTMDS_DCBALANCER_CONTROL 0x4a73 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 +#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 +#define mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673 +#define mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773 +#define mmTMDS_CTL0_1_GEN_CNTL 0x4a75 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 +#define mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675 +#define mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775 +#define mmTMDS_CTL2_3_GEN_CNTL 0x4a76 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 +#define mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676 +#define mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776 +#define mmDIG_VERSION 0x4a78 +#define mmDIG0_DIG_VERSION 0x4a78 +#define mmDIG1_DIG_VERSION 0x4b78 +#define mmDIG2_DIG_VERSION 0x4c78 +#define mmDIG3_DIG_VERSION 0x4d78 +#define mmDIG4_DIG_VERSION 0x4e78 +#define mmDIG5_DIG_VERSION 0x4f78 +#define mmDIG6_DIG_VERSION 0x5478 +#define mmDIG7_DIG_VERSION 0x5678 +#define mmDIG8_DIG_VERSION 0x5778 +#define mmDIG_LANE_ENABLE 0x4a79 +#define mmDIG0_DIG_LANE_ENABLE 0x4a79 +#define mmDIG1_DIG_LANE_ENABLE 0x4b79 +#define mmDIG2_DIG_LANE_ENABLE 0x4c79 +#define mmDIG3_DIG_LANE_ENABLE 0x4d79 +#define mmDIG4_DIG_LANE_ENABLE 0x4e79 +#define mmDIG5_DIG_LANE_ENABLE 0x4f79 +#define mmDIG6_DIG_LANE_ENABLE 0x5479 +#define mmDIG7_DIG_LANE_ENABLE 0x5679 +#define mmDIG8_DIG_LANE_ENABLE 0x5779 +#define mmDIG_TEST_DEBUG_INDEX 0x4a7a +#define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a +#define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a +#define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a +#define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a +#define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a +#define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a +#define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a +#define mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a +#define mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a +#define mmDIG_TEST_DEBUG_DATA 0x4a7b +#define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b +#define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b +#define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b +#define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b +#define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b +#define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b +#define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b +#define mmDIG7_DIG_TEST_DEBUG_DATA 0x567b +#define mmDIG8_DIG_TEST_DEBUG_DATA 0x577b +#define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c +#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c +#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c +#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c +#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c +#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c +#define mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c +#define mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c +#define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d +#define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d +#define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d +#define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d +#define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d +#define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d +#define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d +#define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d +#define mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d +#define mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d +#define mmDMCU_CTRL 0x1600 +#define mmDMCU_STATUS 0x1601 +#define mmDMCU_PC_START_ADDR 0x1602 +#define mmDMCU_FW_START_ADDR 0x1603 +#define mmDMCU_FW_END_ADDR 0x1604 +#define mmDMCU_FW_ISR_START_ADDR 0x1605 +#define mmDMCU_FW_CS_HI 0x1606 +#define mmDMCU_FW_CS_LO 0x1607 +#define mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define mmDMCU_ERAM_WR_CTRL 0x1609 +#define mmDMCU_ERAM_WR_DATA 0x160a +#define mmDMCU_ERAM_RD_CTRL 0x160b +#define mmDMCU_ERAM_RD_DATA 0x160c +#define mmDMCU_IRAM_WR_CTRL 0x160d +#define mmDMCU_IRAM_WR_DATA 0x160e +#define mmDMCU_IRAM_RD_CTRL 0x160f +#define mmDMCU_IRAM_RD_DATA 0x1610 +#define mmDMCU_EVENT_TRIGGER 0x1611 +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 +#define mmDMCU_INTERRUPT_STATUS 0x1614 +#define mmDMCU_INTERRUPT_STATUS_1 0x1633 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632 +#define mmDC_DMCU_SCRATCH 0x1618 +#define mmDMCU_INT_CNT 0x1619 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a +#define mmDMCU_UC_CLK_GATING_CNTL 0x161b +#define mmMASTER_COMM_DATA_REG1 0x161c +#define mmMASTER_COMM_DATA_REG2 0x161d +#define mmMASTER_COMM_DATA_REG3 0x161e +#define mmMASTER_COMM_CMD_REG 0x161f +#define mmMASTER_COMM_CNTL_REG 0x1620 +#define mmSLAVE_COMM_DATA_REG1 0x1621 +#define mmSLAVE_COMM_DATA_REG2 0x1622 +#define mmSLAVE_COMM_DATA_REG3 0x1623 +#define mmSLAVE_COMM_CMD_REG 0x1624 +#define mmSLAVE_COMM_CNTL_REG 0x1625 +#define mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define mmDMCU_TEST_DEBUG_DATA 0x1627 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 +#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 +#define mmDP_LINK_CNTL 0x4aa0 +#define mmDP0_DP_LINK_CNTL 0x4aa0 +#define mmDP1_DP_LINK_CNTL 0x4ba0 +#define mmDP2_DP_LINK_CNTL 0x4ca0 +#define mmDP3_DP_LINK_CNTL 0x4da0 +#define mmDP4_DP_LINK_CNTL 0x4ea0 +#define mmDP5_DP_LINK_CNTL 0x4fa0 +#define mmDP6_DP_LINK_CNTL 0x54a0 +#define mmDP7_DP_LINK_CNTL 0x56a0 +#define mmDP8_DP_LINK_CNTL 0x57a0 +#define mmDP_PIXEL_FORMAT 0x4aa1 +#define mmDP0_DP_PIXEL_FORMAT 0x4aa1 +#define mmDP1_DP_PIXEL_FORMAT 0x4ba1 +#define mmDP2_DP_PIXEL_FORMAT 0x4ca1 +#define mmDP3_DP_PIXEL_FORMAT 0x4da1 +#define mmDP4_DP_PIXEL_FORMAT 0x4ea1 +#define mmDP5_DP_PIXEL_FORMAT 0x4fa1 +#define mmDP6_DP_PIXEL_FORMAT 0x54a1 +#define mmDP7_DP_PIXEL_FORMAT 0x56a1 +#define mmDP8_DP_PIXEL_FORMAT 0x57a1 +#define mmDP_MSA_COLORIMETRY 0x4aa2 +#define mmDP0_DP_MSA_COLORIMETRY 0x4aa2 +#define mmDP1_DP_MSA_COLORIMETRY 0x4ba2 +#define mmDP2_DP_MSA_COLORIMETRY 0x4ca2 +#define mmDP3_DP_MSA_COLORIMETRY 0x4da2 +#define mmDP4_DP_MSA_COLORIMETRY 0x4ea2 +#define mmDP5_DP_MSA_COLORIMETRY 0x4fa2 +#define mmDP6_DP_MSA_COLORIMETRY 0x54a2 +#define mmDP7_DP_MSA_COLORIMETRY 0x56a2 +#define mmDP8_DP_MSA_COLORIMETRY 0x57a2 +#define mmDP_CONFIG 0x4aa3 +#define mmDP0_DP_CONFIG 0x4aa3 +#define mmDP1_DP_CONFIG 0x4ba3 +#define mmDP2_DP_CONFIG 0x4ca3 +#define mmDP3_DP_CONFIG 0x4da3 +#define mmDP4_DP_CONFIG 0x4ea3 +#define mmDP5_DP_CONFIG 0x4fa3 +#define mmDP6_DP_CONFIG 0x54a3 +#define mmDP7_DP_CONFIG 0x56a3 +#define mmDP8_DP_CONFIG 0x57a3 +#define mmDP_VID_STREAM_CNTL 0x4aa4 +#define mmDP0_DP_VID_STREAM_CNTL 0x4aa4 +#define mmDP1_DP_VID_STREAM_CNTL 0x4ba4 +#define mmDP2_DP_VID_STREAM_CNTL 0x4ca4 +#define mmDP3_DP_VID_STREAM_CNTL 0x4da4 +#define mmDP4_DP_VID_STREAM_CNTL 0x4ea4 +#define mmDP5_DP_VID_STREAM_CNTL 0x4fa4 +#define mmDP6_DP_VID_STREAM_CNTL 0x54a4 +#define mmDP7_DP_VID_STREAM_CNTL 0x56a4 +#define mmDP8_DP_VID_STREAM_CNTL 0x57a4 +#define mmDP_STEER_FIFO 0x4aa5 +#define mmDP0_DP_STEER_FIFO 0x4aa5 +#define mmDP1_DP_STEER_FIFO 0x4ba5 +#define mmDP2_DP_STEER_FIFO 0x4ca5 +#define mmDP3_DP_STEER_FIFO 0x4da5 +#define mmDP4_DP_STEER_FIFO 0x4ea5 +#define mmDP5_DP_STEER_FIFO 0x4fa5 +#define mmDP6_DP_STEER_FIFO 0x54a5 +#define mmDP7_DP_STEER_FIFO 0x56a5 +#define mmDP8_DP_STEER_FIFO 0x57a5 +#define mmDP_MSA_MISC 0x4aa6 +#define mmDP0_DP_MSA_MISC 0x4aa6 +#define mmDP1_DP_MSA_MISC 0x4ba6 +#define mmDP2_DP_MSA_MISC 0x4ca6 +#define mmDP3_DP_MSA_MISC 0x4da6 +#define mmDP4_DP_MSA_MISC 0x4ea6 +#define mmDP5_DP_MSA_MISC 0x4fa6 +#define mmDP6_DP_MSA_MISC 0x54a6 +#define mmDP7_DP_MSA_MISC 0x56a6 +#define mmDP8_DP_MSA_MISC 0x57a6 +#define mmDP_VID_TIMING 0x4aa8 +#define mmDP0_DP_VID_TIMING 0x4aa8 +#define mmDP1_DP_VID_TIMING 0x4ba8 +#define mmDP2_DP_VID_TIMING 0x4ca8 +#define mmDP3_DP_VID_TIMING 0x4da8 +#define mmDP4_DP_VID_TIMING 0x4ea8 +#define mmDP5_DP_VID_TIMING 0x4fa8 +#define mmDP6_DP_VID_TIMING 0x54a8 +#define mmDP7_DP_VID_TIMING 0x56a8 +#define mmDP8_DP_VID_TIMING 0x57a8 +#define mmDP_VID_N 0x4aa9 +#define mmDP0_DP_VID_N 0x4aa9 +#define mmDP1_DP_VID_N 0x4ba9 +#define mmDP2_DP_VID_N 0x4ca9 +#define mmDP3_DP_VID_N 0x4da9 +#define mmDP4_DP_VID_N 0x4ea9 +#define mmDP5_DP_VID_N 0x4fa9 +#define mmDP6_DP_VID_N 0x54a9 +#define mmDP7_DP_VID_N 0x56a9 +#define mmDP8_DP_VID_N 0x57a9 +#define mmDP_VID_M 0x4aaa +#define mmDP0_DP_VID_M 0x4aaa +#define mmDP1_DP_VID_M 0x4baa +#define mmDP2_DP_VID_M 0x4caa +#define mmDP3_DP_VID_M 0x4daa +#define mmDP4_DP_VID_M 0x4eaa +#define mmDP5_DP_VID_M 0x4faa +#define mmDP6_DP_VID_M 0x54aa +#define mmDP7_DP_VID_M 0x56aa +#define mmDP8_DP_VID_M 0x57aa +#define mmDP_LINK_FRAMING_CNTL 0x4aab +#define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab +#define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab +#define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab +#define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab +#define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab +#define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab +#define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab +#define mmDP7_DP_LINK_FRAMING_CNTL 0x56ab +#define mmDP8_DP_LINK_FRAMING_CNTL 0x57ab +#define mmDP_HBR2_EYE_PATTERN 0x4aac +#define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac +#define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac +#define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac +#define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac +#define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac +#define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac +#define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac +#define mmDP7_DP_HBR2_EYE_PATTERN 0x56ac +#define mmDP8_DP_HBR2_EYE_PATTERN 0x57ac +#define mmDP_VID_MSA_VBID 0x4aad +#define mmDP0_DP_VID_MSA_VBID 0x4aad +#define mmDP1_DP_VID_MSA_VBID 0x4bad +#define mmDP2_DP_VID_MSA_VBID 0x4cad +#define mmDP3_DP_VID_MSA_VBID 0x4dad +#define mmDP4_DP_VID_MSA_VBID 0x4ead +#define mmDP5_DP_VID_MSA_VBID 0x4fad +#define mmDP6_DP_VID_MSA_VBID 0x54ad +#define mmDP7_DP_VID_MSA_VBID 0x56ad +#define mmDP8_DP_VID_MSA_VBID 0x57ad +#define mmDP_VID_INTERRUPT_CNTL 0x4aae +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae +#define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae +#define mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae +#define mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae +#define mmDP_DPHY_CNTL 0x4aaf +#define mmDP0_DP_DPHY_CNTL 0x4aaf +#define mmDP1_DP_DPHY_CNTL 0x4baf +#define mmDP2_DP_DPHY_CNTL 0x4caf +#define mmDP3_DP_DPHY_CNTL 0x4daf +#define mmDP4_DP_DPHY_CNTL 0x4eaf +#define mmDP5_DP_DPHY_CNTL 0x4faf +#define mmDP6_DP_DPHY_CNTL 0x54af +#define mmDP7_DP_DPHY_CNTL 0x56af +#define mmDP8_DP_DPHY_CNTL 0x57af +#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 +#define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0 +#define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0 +#define mmDP_DPHY_SYM0 0x4ab1 +#define mmDP0_DP_DPHY_SYM0 0x4ab1 +#define mmDP1_DP_DPHY_SYM0 0x4bb1 +#define mmDP2_DP_DPHY_SYM0 0x4cb1 +#define mmDP3_DP_DPHY_SYM0 0x4db1 +#define mmDP4_DP_DPHY_SYM0 0x4eb1 +#define mmDP5_DP_DPHY_SYM0 0x4fb1 +#define mmDP6_DP_DPHY_SYM0 0x54b1 +#define mmDP7_DP_DPHY_SYM0 0x56b1 +#define mmDP8_DP_DPHY_SYM0 0x57b1 +#define mmDP_DPHY_SYM1 0x4ab2 +#define mmDP0_DP_DPHY_SYM1 0x4ab2 +#define mmDP1_DP_DPHY_SYM1 0x4bb2 +#define mmDP2_DP_DPHY_SYM1 0x4cb2 +#define mmDP3_DP_DPHY_SYM1 0x4db2 +#define mmDP4_DP_DPHY_SYM1 0x4eb2 +#define mmDP5_DP_DPHY_SYM1 0x4fb2 +#define mmDP6_DP_DPHY_SYM1 0x54b2 +#define mmDP7_DP_DPHY_SYM1 0x56b2 +#define mmDP8_DP_DPHY_SYM1 0x57b2 +#define mmDP_DPHY_SYM2 0x4ab3 +#define mmDP0_DP_DPHY_SYM2 0x4ab3 +#define mmDP1_DP_DPHY_SYM2 0x4bb3 +#define mmDP2_DP_DPHY_SYM2 0x4cb3 +#define mmDP3_DP_DPHY_SYM2 0x4db3 +#define mmDP4_DP_DPHY_SYM2 0x4eb3 +#define mmDP5_DP_DPHY_SYM2 0x4fb3 +#define mmDP6_DP_DPHY_SYM2 0x54b3 +#define mmDP7_DP_DPHY_SYM2 0x56b3 +#define mmDP8_DP_DPHY_SYM2 0x57b3 +#define mmDP_DPHY_8B10B_CNTL 0x4ab4 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 +#define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 +#define mmDP7_DP_DPHY_8B10B_CNTL 0x56b4 +#define mmDP8_DP_DPHY_8B10B_CNTL 0x57b4 +#define mmDP_DPHY_PRBS_CNTL 0x4ab5 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 +#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 +#define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 +#define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 +#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc +#define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc +#define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc +#define mmDP_DPHY_CRC_EN 0x4ab7 +#define mmDP0_DP_DPHY_CRC_EN 0x4ab7 +#define mmDP1_DP_DPHY_CRC_EN 0x4bb7 +#define mmDP2_DP_DPHY_CRC_EN 0x4cb7 +#define mmDP3_DP_DPHY_CRC_EN 0x4db7 +#define mmDP4_DP_DPHY_CRC_EN 0x4eb7 +#define mmDP5_DP_DPHY_CRC_EN 0x4fb7 +#define mmDP6_DP_DPHY_CRC_EN 0x54b7 +#define mmDP7_DP_DPHY_CRC_EN 0x56b7 +#define mmDP8_DP_DPHY_CRC_EN 0x57b7 +#define mmDP_DPHY_CRC_CNTL 0x4ab8 +#define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 +#define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 +#define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 +#define mmDP3_DP_DPHY_CRC_CNTL 0x4db8 +#define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 +#define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 +#define mmDP6_DP_DPHY_CRC_CNTL 0x54b8 +#define mmDP7_DP_DPHY_CRC_CNTL 0x56b8 +#define mmDP8_DP_DPHY_CRC_CNTL 0x57b8 +#define mmDP_DPHY_CRC_RESULT 0x4ab9 +#define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 +#define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 +#define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 +#define mmDP3_DP_DPHY_CRC_RESULT 0x4db9 +#define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 +#define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 +#define mmDP6_DP_DPHY_CRC_RESULT 0x54b9 +#define mmDP7_DP_DPHY_CRC_RESULT 0x56b9 +#define mmDP8_DP_DPHY_CRC_RESULT 0x57b9 +#define mmDP_DPHY_CRC_MST_CNTL 0x4aba +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba +#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba +#define mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba +#define mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba +#define mmDP_DPHY_CRC_MST_STATUS 0x4abb +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb +#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb +#define mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb +#define mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb +#define mmDP_DPHY_FAST_TRAINING 0x4abc +#define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc +#define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc +#define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc +#define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc +#define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc +#define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc +#define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc +#define mmDP7_DP_DPHY_FAST_TRAINING 0x56bc +#define mmDP8_DP_DPHY_FAST_TRAINING 0x57bc +#define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd +#define mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd +#define mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd +#define mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd +#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd +#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd +#define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd +#define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd +#define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be +#define mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be +#define mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be +#define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf +#define mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf +#define mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf +#define mmDP_SEC_CNTL 0x4ac3 +#define mmDP0_DP_SEC_CNTL 0x4ac3 +#define mmDP1_DP_SEC_CNTL 0x4bc3 +#define mmDP2_DP_SEC_CNTL 0x4cc3 +#define mmDP3_DP_SEC_CNTL 0x4dc3 +#define mmDP4_DP_SEC_CNTL 0x4ec3 +#define mmDP5_DP_SEC_CNTL 0x4fc3 +#define mmDP6_DP_SEC_CNTL 0x54c3 +#define mmDP7_DP_SEC_CNTL 0x56c3 +#define mmDP8_DP_SEC_CNTL 0x57c3 +#define mmDP_SEC_CNTL1 0x4ac4 +#define mmDP0_DP_SEC_CNTL1 0x4ac4 +#define mmDP1_DP_SEC_CNTL1 0x4bc4 +#define mmDP2_DP_SEC_CNTL1 0x4cc4 +#define mmDP3_DP_SEC_CNTL1 0x4dc4 +#define mmDP4_DP_SEC_CNTL1 0x4ec4 +#define mmDP5_DP_SEC_CNTL1 0x4fc4 +#define mmDP6_DP_SEC_CNTL1 0x54c4 +#define mmDP7_DP_SEC_CNTL1 0x56c4 +#define mmDP8_DP_SEC_CNTL1 0x57c4 +#define mmDP_SEC_FRAMING1 0x4ac5 +#define mmDP0_DP_SEC_FRAMING1 0x4ac5 +#define mmDP1_DP_SEC_FRAMING1 0x4bc5 +#define mmDP2_DP_SEC_FRAMING1 0x4cc5 +#define mmDP3_DP_SEC_FRAMING1 0x4dc5 +#define mmDP4_DP_SEC_FRAMING1 0x4ec5 +#define mmDP5_DP_SEC_FRAMING1 0x4fc5 +#define mmDP6_DP_SEC_FRAMING1 0x54c5 +#define mmDP7_DP_SEC_FRAMING1 0x56c5 +#define mmDP8_DP_SEC_FRAMING1 0x57c5 +#define mmDP_SEC_FRAMING2 0x4ac6 +#define mmDP0_DP_SEC_FRAMING2 0x4ac6 +#define mmDP1_DP_SEC_FRAMING2 0x4bc6 +#define mmDP2_DP_SEC_FRAMING2 0x4cc6 +#define mmDP3_DP_SEC_FRAMING2 0x4dc6 +#define mmDP4_DP_SEC_FRAMING2 0x4ec6 +#define mmDP5_DP_SEC_FRAMING2 0x4fc6 +#define mmDP6_DP_SEC_FRAMING2 0x54c6 +#define mmDP7_DP_SEC_FRAMING2 0x56c6 +#define mmDP8_DP_SEC_FRAMING2 0x57c6 +#define mmDP_SEC_FRAMING3 0x4ac7 +#define mmDP0_DP_SEC_FRAMING3 0x4ac7 +#define mmDP1_DP_SEC_FRAMING3 0x4bc7 +#define mmDP2_DP_SEC_FRAMING3 0x4cc7 +#define mmDP3_DP_SEC_FRAMING3 0x4dc7 +#define mmDP4_DP_SEC_FRAMING3 0x4ec7 +#define mmDP5_DP_SEC_FRAMING3 0x4fc7 +#define mmDP6_DP_SEC_FRAMING3 0x54c7 +#define mmDP7_DP_SEC_FRAMING3 0x56c7 +#define mmDP8_DP_SEC_FRAMING3 0x57c7 +#define mmDP_SEC_FRAMING4 0x4ac8 +#define mmDP0_DP_SEC_FRAMING4 0x4ac8 +#define mmDP1_DP_SEC_FRAMING4 0x4bc8 +#define mmDP2_DP_SEC_FRAMING4 0x4cc8 +#define mmDP3_DP_SEC_FRAMING4 0x4dc8 +#define mmDP4_DP_SEC_FRAMING4 0x4ec8 +#define mmDP5_DP_SEC_FRAMING4 0x4fc8 +#define mmDP6_DP_SEC_FRAMING4 0x54c8 +#define mmDP7_DP_SEC_FRAMING4 0x56c8 +#define mmDP8_DP_SEC_FRAMING4 0x57c8 +#define mmDP_SEC_AUD_N 0x4ac9 +#define mmDP0_DP_SEC_AUD_N 0x4ac9 +#define mmDP1_DP_SEC_AUD_N 0x4bc9 +#define mmDP2_DP_SEC_AUD_N 0x4cc9 +#define mmDP3_DP_SEC_AUD_N 0x4dc9 +#define mmDP4_DP_SEC_AUD_N 0x4ec9 +#define mmDP5_DP_SEC_AUD_N 0x4fc9 +#define mmDP6_DP_SEC_AUD_N 0x54c9 +#define mmDP7_DP_SEC_AUD_N 0x56c9 +#define mmDP8_DP_SEC_AUD_N 0x57c9 +#define mmDP_SEC_AUD_N_READBACK 0x4aca +#define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca +#define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca +#define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca +#define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca +#define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca +#define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca +#define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca +#define mmDP7_DP_SEC_AUD_N_READBACK 0x56ca +#define mmDP8_DP_SEC_AUD_N_READBACK 0x57ca +#define mmDP_SEC_AUD_M 0x4acb +#define mmDP0_DP_SEC_AUD_M 0x4acb +#define mmDP1_DP_SEC_AUD_M 0x4bcb +#define mmDP2_DP_SEC_AUD_M 0x4ccb +#define mmDP3_DP_SEC_AUD_M 0x4dcb +#define mmDP4_DP_SEC_AUD_M 0x4ecb +#define mmDP5_DP_SEC_AUD_M 0x4fcb +#define mmDP6_DP_SEC_AUD_M 0x54cb +#define mmDP7_DP_SEC_AUD_M 0x56cb +#define mmDP8_DP_SEC_AUD_M 0x57cb +#define mmDP_SEC_AUD_M_READBACK 0x4acc +#define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc +#define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc +#define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc +#define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc +#define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc +#define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc +#define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc +#define mmDP7_DP_SEC_AUD_M_READBACK 0x56cc +#define mmDP8_DP_SEC_AUD_M_READBACK 0x57cc +#define mmDP_SEC_TIMESTAMP 0x4acd +#define mmDP0_DP_SEC_TIMESTAMP 0x4acd +#define mmDP1_DP_SEC_TIMESTAMP 0x4bcd +#define mmDP2_DP_SEC_TIMESTAMP 0x4ccd +#define mmDP3_DP_SEC_TIMESTAMP 0x4dcd +#define mmDP4_DP_SEC_TIMESTAMP 0x4ecd +#define mmDP5_DP_SEC_TIMESTAMP 0x4fcd +#define mmDP6_DP_SEC_TIMESTAMP 0x54cd +#define mmDP7_DP_SEC_TIMESTAMP 0x56cd +#define mmDP8_DP_SEC_TIMESTAMP 0x57cd +#define mmDP_SEC_PACKET_CNTL 0x4ace +#define mmDP0_DP_SEC_PACKET_CNTL 0x4ace +#define mmDP1_DP_SEC_PACKET_CNTL 0x4bce +#define mmDP2_DP_SEC_PACKET_CNTL 0x4cce +#define mmDP3_DP_SEC_PACKET_CNTL 0x4dce +#define mmDP4_DP_SEC_PACKET_CNTL 0x4ece +#define mmDP5_DP_SEC_PACKET_CNTL 0x4fce +#define mmDP6_DP_SEC_PACKET_CNTL 0x54ce +#define mmDP7_DP_SEC_PACKET_CNTL 0x56ce +#define mmDP8_DP_SEC_PACKET_CNTL 0x57ce +#define mmDP_MSE_RATE_CNTL 0x4acf +#define mmDP0_DP_MSE_RATE_CNTL 0x4acf +#define mmDP1_DP_MSE_RATE_CNTL 0x4bcf +#define mmDP2_DP_MSE_RATE_CNTL 0x4ccf +#define mmDP3_DP_MSE_RATE_CNTL 0x4dcf +#define mmDP4_DP_MSE_RATE_CNTL 0x4ecf +#define mmDP5_DP_MSE_RATE_CNTL 0x4fcf +#define mmDP6_DP_MSE_RATE_CNTL 0x54cf +#define mmDP7_DP_MSE_RATE_CNTL 0x56cf +#define mmDP8_DP_MSE_RATE_CNTL 0x57cf +#define mmDP_MSE_RATE_UPDATE 0x4ad1 +#define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 +#define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 +#define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 +#define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 +#define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 +#define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 +#define mmDP6_DP_MSE_RATE_UPDATE 0x54d1 +#define mmDP7_DP_MSE_RATE_UPDATE 0x56d1 +#define mmDP8_DP_MSE_RATE_UPDATE 0x57d1 +#define mmDP_MSE_SAT0 0x4ad2 +#define mmDP0_DP_MSE_SAT0 0x4ad2 +#define mmDP1_DP_MSE_SAT0 0x4bd2 +#define mmDP2_DP_MSE_SAT0 0x4cd2 +#define mmDP3_DP_MSE_SAT0 0x4dd2 +#define mmDP4_DP_MSE_SAT0 0x4ed2 +#define mmDP5_DP_MSE_SAT0 0x4fd2 +#define mmDP6_DP_MSE_SAT0 0x54d2 +#define mmDP7_DP_MSE_SAT0 0x56d2 +#define mmDP8_DP_MSE_SAT0 0x57d2 +#define mmDP_MSE_SAT1 0x4ad3 +#define mmDP0_DP_MSE_SAT1 0x4ad3 +#define mmDP1_DP_MSE_SAT1 0x4bd3 +#define mmDP2_DP_MSE_SAT1 0x4cd3 +#define mmDP3_DP_MSE_SAT1 0x4dd3 +#define mmDP4_DP_MSE_SAT1 0x4ed3 +#define mmDP5_DP_MSE_SAT1 0x4fd3 +#define mmDP6_DP_MSE_SAT1 0x54d3 +#define mmDP7_DP_MSE_SAT1 0x56d3 +#define mmDP8_DP_MSE_SAT1 0x57d3 +#define mmDP_MSE_SAT2 0x4ad4 +#define mmDP0_DP_MSE_SAT2 0x4ad4 +#define mmDP1_DP_MSE_SAT2 0x4bd4 +#define mmDP2_DP_MSE_SAT2 0x4cd4 +#define mmDP3_DP_MSE_SAT2 0x4dd4 +#define mmDP4_DP_MSE_SAT2 0x4ed4 +#define mmDP5_DP_MSE_SAT2 0x4fd4 +#define mmDP6_DP_MSE_SAT2 0x54d4 +#define mmDP7_DP_MSE_SAT2 0x56d4 +#define mmDP8_DP_MSE_SAT2 0x57d4 +#define mmDP_MSE_SAT_UPDATE 0x4ad5 +#define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 +#define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 +#define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 +#define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 +#define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 +#define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 +#define mmDP6_DP_MSE_SAT_UPDATE 0x54d5 +#define mmDP7_DP_MSE_SAT_UPDATE 0x56d5 +#define mmDP8_DP_MSE_SAT_UPDATE 0x57d5 +#define mmDP_MSE_LINK_TIMING 0x4ad6 +#define mmDP0_DP_MSE_LINK_TIMING 0x4ad6 +#define mmDP1_DP_MSE_LINK_TIMING 0x4bd6 +#define mmDP2_DP_MSE_LINK_TIMING 0x4cd6 +#define mmDP3_DP_MSE_LINK_TIMING 0x4dd6 +#define mmDP4_DP_MSE_LINK_TIMING 0x4ed6 +#define mmDP5_DP_MSE_LINK_TIMING 0x4fd6 +#define mmDP6_DP_MSE_LINK_TIMING 0x54d6 +#define mmDP7_DP_MSE_LINK_TIMING 0x56d6 +#define mmDP8_DP_MSE_LINK_TIMING 0x57d6 +#define mmDP_MSE_MISC_CNTL 0x4ad7 +#define mmDP0_DP_MSE_MISC_CNTL 0x4ad7 +#define mmDP1_DP_MSE_MISC_CNTL 0x4bd7 +#define mmDP2_DP_MSE_MISC_CNTL 0x4cd7 +#define mmDP3_DP_MSE_MISC_CNTL 0x4dd7 +#define mmDP4_DP_MSE_MISC_CNTL 0x4ed7 +#define mmDP5_DP_MSE_MISC_CNTL 0x4fd7 +#define mmDP6_DP_MSE_MISC_CNTL 0x54d7 +#define mmDP7_DP_MSE_MISC_CNTL 0x56d7 +#define mmDP8_DP_MSE_MISC_CNTL 0x57d7 +#define mmDP_MSE_SAT0_STATUS 0x4adf +#define mmDP0_DP_MSE_SAT0_STATUS 0x4adf +#define mmDP1_DP_MSE_SAT0_STATUS 0x4bdf +#define mmDP2_DP_MSE_SAT0_STATUS 0x4cdf +#define mmDP3_DP_MSE_SAT0_STATUS 0x4ddf +#define mmDP4_DP_MSE_SAT0_STATUS 0x4edf +#define mmDP5_DP_MSE_SAT0_STATUS 0x4fdf +#define mmDP6_DP_MSE_SAT0_STATUS 0x54df +#define mmDP7_DP_MSE_SAT0_STATUS 0x56df +#define mmDP8_DP_MSE_SAT0_STATUS 0x57df +#define mmDP_MSE_SAT1_STATUS 0x4ae0 +#define mmDP0_DP_MSE_SAT1_STATUS 0x4ae0 +#define mmDP1_DP_MSE_SAT1_STATUS 0x4be0 +#define mmDP2_DP_MSE_SAT1_STATUS 0x4ce0 +#define mmDP3_DP_MSE_SAT1_STATUS 0x4de0 +#define mmDP4_DP_MSE_SAT1_STATUS 0x4ee0 +#define mmDP5_DP_MSE_SAT1_STATUS 0x4fe0 +#define mmDP6_DP_MSE_SAT1_STATUS 0x54e0 +#define mmDP7_DP_MSE_SAT1_STATUS 0x56e0 +#define mmDP8_DP_MSE_SAT1_STATUS 0x57e0 +#define mmDP_MSE_SAT2_STATUS 0x4ae1 +#define mmDP0_DP_MSE_SAT2_STATUS 0x4ae1 +#define mmDP1_DP_MSE_SAT2_STATUS 0x4be1 +#define mmDP2_DP_MSE_SAT2_STATUS 0x4ce1 +#define mmDP3_DP_MSE_SAT2_STATUS 0x4de1 +#define mmDP4_DP_MSE_SAT2_STATUS 0x4ee1 +#define mmDP5_DP_MSE_SAT2_STATUS 0x4fe1 +#define mmDP6_DP_MSE_SAT2_STATUS 0x54e1 +#define mmDP7_DP_MSE_SAT2_STATUS 0x56e1 +#define mmDP8_DP_MSE_SAT2_STATUS 0x57e1 +#define mmDP_TEST_DEBUG_INDEX 0x4ad8 +#define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 +#define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 +#define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 +#define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 +#define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 +#define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 +#define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 +#define mmDP7_DP_TEST_DEBUG_INDEX 0x56d8 +#define mmDP8_DP_TEST_DEBUG_INDEX 0x57d8 +#define mmDP_TEST_DEBUG_DATA 0x4ad9 +#define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 +#define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 +#define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 +#define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 +#define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 +#define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 +#define mmDP6_DP_TEST_DEBUG_DATA 0x54d9 +#define mmDP7_DP_TEST_DEBUG_DATA 0x56d9 +#define mmDP8_DP_TEST_DEBUG_DATA 0x57d9 +#define mmDP_FE_TEST_DEBUG_INDEX 0x4ada +#define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada +#define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda +#define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda +#define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda +#define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda +#define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda +#define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da +#define mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da +#define mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da +#define mmDP_FE_TEST_DEBUG_DATA 0x4adb +#define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb +#define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb +#define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb +#define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb +#define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb +#define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb +#define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db +#define mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db +#define mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db +#define mmAUX_CONTROL 0x5c00 +#define mmDP_AUX0_AUX_CONTROL 0x5c00 +#define mmDP_AUX1_AUX_CONTROL 0x5c1c +#define mmDP_AUX2_AUX_CONTROL 0x5c38 +#define mmDP_AUX3_AUX_CONTROL 0x5c54 +#define mmDP_AUX4_AUX_CONTROL 0x5c70 +#define mmDP_AUX5_AUX_CONTROL 0x5c8c +#define mmAUX_SW_CONTROL 0x5c01 +#define mmDP_AUX0_AUX_SW_CONTROL 0x5c01 +#define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d +#define mmDP_AUX2_AUX_SW_CONTROL 0x5c39 +#define mmDP_AUX3_AUX_SW_CONTROL 0x5c55 +#define mmDP_AUX4_AUX_SW_CONTROL 0x5c71 +#define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d +#define mmAUX_ARB_CONTROL 0x5c02 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e +#define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a +#define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e +#define mmAUX_INTERRUPT_CONTROL 0x5c03 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f +#define mmAUX_SW_STATUS 0x5c04 +#define mmDP_AUX0_AUX_SW_STATUS 0x5c04 +#define mmDP_AUX1_AUX_SW_STATUS 0x5c20 +#define mmDP_AUX2_AUX_SW_STATUS 0x5c3c +#define mmDP_AUX3_AUX_SW_STATUS 0x5c58 +#define mmDP_AUX4_AUX_SW_STATUS 0x5c74 +#define mmDP_AUX5_AUX_SW_STATUS 0x5c90 +#define mmAUX_LS_STATUS 0x5c05 +#define mmDP_AUX0_AUX_LS_STATUS 0x5c05 +#define mmDP_AUX1_AUX_LS_STATUS 0x5c21 +#define mmDP_AUX2_AUX_LS_STATUS 0x5c3d +#define mmDP_AUX3_AUX_LS_STATUS 0x5c59 +#define mmDP_AUX4_AUX_LS_STATUS 0x5c75 +#define mmDP_AUX5_AUX_LS_STATUS 0x5c91 +#define mmAUX_SW_DATA 0x5c06 +#define mmDP_AUX0_AUX_SW_DATA 0x5c06 +#define mmDP_AUX1_AUX_SW_DATA 0x5c22 +#define mmDP_AUX2_AUX_SW_DATA 0x5c3e +#define mmDP_AUX3_AUX_SW_DATA 0x5c5a +#define mmDP_AUX4_AUX_SW_DATA 0x5c76 +#define mmDP_AUX5_AUX_SW_DATA 0x5c92 +#define mmAUX_LS_DATA 0x5c07 +#define mmDP_AUX0_AUX_LS_DATA 0x5c07 +#define mmDP_AUX1_AUX_LS_DATA 0x5c23 +#define mmDP_AUX2_AUX_LS_DATA 0x5c3f +#define mmDP_AUX3_AUX_LS_DATA 0x5c5b +#define mmDP_AUX4_AUX_LS_DATA 0x5c77 +#define mmDP_AUX5_AUX_LS_DATA 0x5c93 +#define mmAUX_DPHY_TX_REF_CONTROL 0x5c08 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 +#define mmAUX_DPHY_TX_CONTROL 0x5c09 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 +#define mmAUX_DPHY_RX_CONTROL0 0x5c0a +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 +#define mmAUX_DPHY_RX_CONTROL1 0x5c0b +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 +#define mmAUX_DPHY_TX_STATUS 0x5c0c +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 +#define mmAUX_DPHY_RX_STATUS 0x5c0d +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 +#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b +#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c +#define mmAUX_GTC_SYNC_STATUS 0x5c11 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d +#define mmAUX_TEST_DEBUG_INDEX 0x5c14 +#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 +#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 +#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c +#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 +#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 +#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 +#define mmAUX_TEST_DEBUG_DATA 0x5c15 +#define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 +#define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 +#define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d +#define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 +#define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 +#define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 +#define ixDP_AUX_DEBUG_A 0x10 +#define ixDP_AUX_DEBUG_B 0x11 +#define ixDP_AUX_DEBUG_C 0x12 +#define ixDP_AUX_DEBUG_D 0x13 +#define ixDP_AUX_DEBUG_E 0x14 +#define ixDP_AUX_DEBUG_F 0x15 +#define ixDP_AUX_DEBUG_G 0x16 +#define ixDP_AUX_DEBUG_H 0x17 +#define ixDP_AUX_DEBUG_I 0x18 +#define ixDP_AUX_DEBUG_J 0x19 +#define ixDP_AUX_DEBUG_K 0x1a +#define ixDP_AUX_DEBUG_L 0x1b +#define ixDP_AUX_DEBUG_M 0x1c +#define ixDP_AUX_DEBUG_N 0x1d +#define ixDP_AUX_DEBUG_O 0x1e +#define ixDP_AUX_DEBUG_P 0x1f +#define ixDP_AUX_DEBUG_Q 0x20 +#define mmDVO_ENABLE 0x16a0 +#define mmDVO_SOURCE_SELECT 0x16a1 +#define mmDVO_OUTPUT 0x16a2 +#define mmDVO_CONTROL 0x16a3 +#define mmDVO_CRC_EN 0x16a4 +#define mmDVO_CRC2_SIG_MASK 0x16a5 +#define mmDVO_CRC2_SIG_RESULT 0x16a6 +#define mmDVO_FIFO_ERROR_STATUS 0x16a7 +#define mmDVO_TEST_DEBUG_INDEX 0x16a8 +#define mmDVO_TEST_DEBUG_DATA 0x16a9 +#define mmFBC_CNTL 0x280 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 +#define mmFBC_START_STOP_DELAY 0x283 +#define mmFBC_COMP_CNTL 0x284 +#define mmFBC_COMP_MODE 0x285 +#define mmFBC_DEBUG0 0x286 +#define mmFBC_DEBUG1 0x287 +#define mmFBC_DEBUG2 0x288 +#define mmFBC_IND_LUT0 0x289 +#define mmFBC_IND_LUT1 0x28a +#define mmFBC_IND_LUT2 0x28b +#define mmFBC_IND_LUT3 0x28c +#define mmFBC_IND_LUT4 0x28d +#define mmFBC_IND_LUT5 0x28e +#define mmFBC_IND_LUT6 0x28f +#define mmFBC_IND_LUT7 0x290 +#define mmFBC_IND_LUT8 0x291 +#define mmFBC_IND_LUT9 0x292 +#define mmFBC_IND_LUT10 0x293 +#define mmFBC_IND_LUT11 0x294 +#define mmFBC_IND_LUT12 0x295 +#define mmFBC_IND_LUT13 0x296 +#define mmFBC_IND_LUT14 0x297 +#define mmFBC_IND_LUT15 0x298 +#define mmFBC_CSM_REGION_OFFSET_01 0x299 +#define mmFBC_CSM_REGION_OFFSET_23 0x29a +#define mmFBC_CLIENT_REGION_MASK 0x29b +#define mmFBC_DEBUG_COMP 0x29c +#define mmFBC_DEBUG_CSR 0x29d +#define mmFBC_DEBUG_CSR_RDATA 0x29e +#define mmFBC_DEBUG_CSR_WDATA 0x29f +#define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 +#define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 +#define mmFBC_MISC 0x2a2 +#define mmFBC_STATUS 0x2a3 +#define mmFBC_ALPHA_CNTL 0x2a6 +#define mmFBC_ALPHA_RGB_OVERRIDE 0x2a7 +#define mmFBC_TEST_DEBUG_INDEX 0x2a4 +#define mmFBC_TEST_DEBUG_DATA 0x2a5 +#define mmFMT_CLAMP_COMPONENT_R 0x1be8 +#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 +#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 +#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 +#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 +#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 +#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 +#define mmFMT_CLAMP_COMPONENT_G 0x1be9 +#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 +#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 +#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 +#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 +#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 +#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 +#define mmFMT_CLAMP_COMPONENT_B 0x1bea +#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea +#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea +#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea +#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea +#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea +#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea +#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed +#define mmFMT_CONTROL 0x1bee +#define mmFMT0_FMT_CONTROL 0x1bee +#define mmFMT1_FMT_CONTROL 0x1dee +#define mmFMT2_FMT_CONTROL 0x1fee +#define mmFMT3_FMT_CONTROL 0x41ee +#define mmFMT4_FMT_CONTROL 0x43ee +#define mmFMT5_FMT_CONTROL 0x45ee +#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 +#define mmFMT_DITHER_RAND_R_SEED 0x1bf3 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 +#define mmFMT_DITHER_RAND_G_SEED 0x1bf4 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 +#define mmFMT_DITHER_RAND_B_SEED 0x1bf5 +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 +#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 +#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 +#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 +#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 +#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 +#define mmFMT_CLAMP_CNTL 0x1bf9 +#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 +#define mmFMT1_FMT_CLAMP_CNTL 0x1df9 +#define mmFMT2_FMT_CLAMP_CNTL 0x1ff9 +#define mmFMT3_FMT_CLAMP_CNTL 0x41f9 +#define mmFMT4_FMT_CLAMP_CNTL 0x43f9 +#define mmFMT5_FMT_CLAMP_CNTL 0x45f9 +#define mmFMT_CRC_CNTL 0x1bfa +#define mmFMT0_FMT_CRC_CNTL 0x1bfa +#define mmFMT1_FMT_CRC_CNTL 0x1dfa +#define mmFMT2_FMT_CRC_CNTL 0x1ffa +#define mmFMT3_FMT_CRC_CNTL 0x41fa +#define mmFMT4_FMT_CRC_CNTL 0x43fa +#define mmFMT5_FMT_CRC_CNTL 0x45fa +#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb +#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc +#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd +#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe +#define mmFMT_DEBUG_CNTL 0x1bff +#define mmFMT0_FMT_DEBUG_CNTL 0x1bff +#define mmFMT1_FMT_DEBUG_CNTL 0x1dff +#define mmFMT2_FMT_DEBUG_CNTL 0x1fff +#define mmFMT3_FMT_DEBUG_CNTL 0x41ff +#define mmFMT4_FMT_DEBUG_CNTL 0x43ff +#define mmFMT5_FMT_DEBUG_CNTL 0x45ff +#define mmFMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1bf0 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1bf0 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1df0 +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1ff0 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x41f0 +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x43f0 +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x45f0 +#define mmFMT_420_HBLANK_EARLY_START 0x1bf1 +#define mmFMT0_FMT_420_HBLANK_EARLY_START 0x1bf1 +#define mmFMT1_FMT_420_HBLANK_EARLY_START 0x1df1 +#define mmFMT2_FMT_420_HBLANK_EARLY_START 0x1ff1 +#define mmFMT3_FMT_420_HBLANK_EARLY_START 0x41f1 +#define mmFMT4_FMT_420_HBLANK_EARLY_START 0x43f1 +#define mmFMT5_FMT_420_HBLANK_EARLY_START 0x45f1 +#define mmFMT_TEST_DEBUG_INDEX 0x1beb +#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb +#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb +#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb +#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb +#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb +#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb +#define mmFMT_TEST_DEBUG_DATA 0x1bec +#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec +#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec +#define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec +#define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec +#define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec +#define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec +#define ixFMT_DEBUG0 0x1 +#define ixFMT_DEBUG1 0x2 +#define ixFMT_DEBUG2 0x3 +#define ixFMT_DEBUG3 0x4 +#define ixFMT_DEBUG_ID 0x0 +#define mmLB_DATA_FORMAT 0x1ac0 +#define mmLB0_LB_DATA_FORMAT 0x1ac0 +#define mmLB1_LB_DATA_FORMAT 0x1cc0 +#define mmLB2_LB_DATA_FORMAT 0x1ec0 +#define mmLB3_LB_DATA_FORMAT 0x40c0 +#define mmLB4_LB_DATA_FORMAT 0x42c0 +#define mmLB5_LB_DATA_FORMAT 0x44c0 +#define mmLB_MEMORY_CTRL 0x1ac1 +#define mmLB0_LB_MEMORY_CTRL 0x1ac1 +#define mmLB1_LB_MEMORY_CTRL 0x1cc1 +#define mmLB2_LB_MEMORY_CTRL 0x1ec1 +#define mmLB3_LB_MEMORY_CTRL 0x40c1 +#define mmLB4_LB_MEMORY_CTRL 0x42c1 +#define mmLB5_LB_MEMORY_CTRL 0x44c1 +#define mmLB_MEMORY_SIZE_STATUS 0x1ac2 +#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 +#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 +#define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 +#define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 +#define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 +#define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 +#define mmLB_DESKTOP_HEIGHT 0x1ac3 +#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 +#define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 +#define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 +#define mmLB3_LB_DESKTOP_HEIGHT 0x40c3 +#define mmLB4_LB_DESKTOP_HEIGHT 0x42c3 +#define mmLB5_LB_DESKTOP_HEIGHT 0x44c3 +#define mmLB_VLINE_START_END 0x1ac4 +#define mmLB0_LB_VLINE_START_END 0x1ac4 +#define mmLB1_LB_VLINE_START_END 0x1cc4 +#define mmLB2_LB_VLINE_START_END 0x1ec4 +#define mmLB3_LB_VLINE_START_END 0x40c4 +#define mmLB4_LB_VLINE_START_END 0x42c4 +#define mmLB5_LB_VLINE_START_END 0x44c4 +#define mmLB_VLINE2_START_END 0x1ac5 +#define mmLB0_LB_VLINE2_START_END 0x1ac5 +#define mmLB1_LB_VLINE2_START_END 0x1cc5 +#define mmLB2_LB_VLINE2_START_END 0x1ec5 +#define mmLB3_LB_VLINE2_START_END 0x40c5 +#define mmLB4_LB_VLINE2_START_END 0x42c5 +#define mmLB5_LB_VLINE2_START_END 0x44c5 +#define mmLB_V_COUNTER 0x1ac6 +#define mmLB0_LB_V_COUNTER 0x1ac6 +#define mmLB1_LB_V_COUNTER 0x1cc6 +#define mmLB2_LB_V_COUNTER 0x1ec6 +#define mmLB3_LB_V_COUNTER 0x40c6 +#define mmLB4_LB_V_COUNTER 0x42c6 +#define mmLB5_LB_V_COUNTER 0x44c6 +#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 +#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 +#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 +#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 +#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 +#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 +#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 +#define mmLB_INTERRUPT_MASK 0x1ac8 +#define mmLB0_LB_INTERRUPT_MASK 0x1ac8 +#define mmLB1_LB_INTERRUPT_MASK 0x1cc8 +#define mmLB2_LB_INTERRUPT_MASK 0x1ec8 +#define mmLB3_LB_INTERRUPT_MASK 0x40c8 +#define mmLB4_LB_INTERRUPT_MASK 0x42c8 +#define mmLB5_LB_INTERRUPT_MASK 0x44c8 +#define mmLB_VLINE_STATUS 0x1ac9 +#define mmLB0_LB_VLINE_STATUS 0x1ac9 +#define mmLB1_LB_VLINE_STATUS 0x1cc9 +#define mmLB2_LB_VLINE_STATUS 0x1ec9 +#define mmLB3_LB_VLINE_STATUS 0x40c9 +#define mmLB4_LB_VLINE_STATUS 0x42c9 +#define mmLB5_LB_VLINE_STATUS 0x44c9 +#define mmLB_VLINE2_STATUS 0x1aca +#define mmLB0_LB_VLINE2_STATUS 0x1aca +#define mmLB1_LB_VLINE2_STATUS 0x1cca +#define mmLB2_LB_VLINE2_STATUS 0x1eca +#define mmLB3_LB_VLINE2_STATUS 0x40ca +#define mmLB4_LB_VLINE2_STATUS 0x42ca +#define mmLB5_LB_VLINE2_STATUS 0x44ca +#define mmLB_VBLANK_STATUS 0x1acb +#define mmLB0_LB_VBLANK_STATUS 0x1acb +#define mmLB1_LB_VBLANK_STATUS 0x1ccb +#define mmLB2_LB_VBLANK_STATUS 0x1ecb +#define mmLB3_LB_VBLANK_STATUS 0x40cb +#define mmLB4_LB_VBLANK_STATUS 0x42cb +#define mmLB5_LB_VBLANK_STATUS 0x44cb +#define mmLB_SYNC_RESET_SEL 0x1acc +#define mmLB0_LB_SYNC_RESET_SEL 0x1acc +#define mmLB1_LB_SYNC_RESET_SEL 0x1ccc +#define mmLB2_LB_SYNC_RESET_SEL 0x1ecc +#define mmLB3_LB_SYNC_RESET_SEL 0x40cc +#define mmLB4_LB_SYNC_RESET_SEL 0x42cc +#define mmLB5_LB_SYNC_RESET_SEL 0x44cc +#define mmLB_BLACK_KEYER_R_CR 0x1acd +#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd +#define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd +#define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd +#define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd +#define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd +#define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd +#define mmLB_BLACK_KEYER_G_Y 0x1ace +#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace +#define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce +#define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece +#define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce +#define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce +#define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce +#define mmLB_BLACK_KEYER_B_CB 0x1acf +#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf +#define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf +#define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf +#define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf +#define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf +#define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf +#define mmLB_KEYER_COLOR_CTRL 0x1ad0 +#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 +#define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 +#define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 +#define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 +#define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 +#define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 +#define mmLB_KEYER_COLOR_R_CR 0x1ad1 +#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 +#define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 +#define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 +#define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 +#define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 +#define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 +#define mmLB_KEYER_COLOR_G_Y 0x1ad2 +#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 +#define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 +#define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 +#define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 +#define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 +#define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 +#define mmLB_KEYER_COLOR_B_CB 0x1ad3 +#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 +#define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 +#define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 +#define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 +#define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 +#define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 +#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 +#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 +#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 +#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 +#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 +#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 +#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 +#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 +#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 +#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 +#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 +#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 +#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 +#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 +#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 +#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 +#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 +#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 +#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 +#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 +#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 +#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 +#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 +#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 +#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 +#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 +#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 +#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 +#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 +#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 +#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 +#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 +#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 +#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 +#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 +#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 +#define mmLB_BUFFER_STATUS 0x1ada +#define mmLB0_LB_BUFFER_STATUS 0x1ada +#define mmLB1_LB_BUFFER_STATUS 0x1cda +#define mmLB2_LB_BUFFER_STATUS 0x1eda +#define mmLB3_LB_BUFFER_STATUS 0x40da +#define mmLB4_LB_BUFFER_STATUS 0x42da +#define mmLB5_LB_BUFFER_STATUS 0x44da +#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc +#define mmMVP_AFR_FLIP_MODE 0x1ae0 +#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 +#define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 +#define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 +#define mmLB3_MVP_AFR_FLIP_MODE 0x40e0 +#define mmLB4_MVP_AFR_FLIP_MODE 0x42e0 +#define mmLB5_MVP_AFR_FLIP_MODE 0x44e0 +#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 +#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 +#define mmDC_MVP_LB_CONTROL 0x1ae3 +#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 +#define mmLB1_DC_MVP_LB_CONTROL 0x1ce3 +#define mmLB2_DC_MVP_LB_CONTROL 0x1ee3 +#define mmLB3_DC_MVP_LB_CONTROL 0x40e3 +#define mmLB4_DC_MVP_LB_CONTROL 0x42e3 +#define mmLB5_DC_MVP_LB_CONTROL 0x44e3 +#define mmLB_DEBUG 0x1ae4 +#define mmLB0_LB_DEBUG 0x1ae4 +#define mmLB1_LB_DEBUG 0x1ce4 +#define mmLB2_LB_DEBUG 0x1ee4 +#define mmLB3_LB_DEBUG 0x40e4 +#define mmLB4_LB_DEBUG 0x42e4 +#define mmLB5_LB_DEBUG 0x44e4 +#define mmLB_DEBUG2 0x1ae5 +#define mmLB0_LB_DEBUG2 0x1ae5 +#define mmLB1_LB_DEBUG2 0x1ce5 +#define mmLB2_LB_DEBUG2 0x1ee5 +#define mmLB3_LB_DEBUG2 0x40e5 +#define mmLB4_LB_DEBUG2 0x42e5 +#define mmLB5_LB_DEBUG2 0x44e5 +#define mmLB_DEBUG3 0x1ae6 +#define mmLB0_LB_DEBUG3 0x1ae6 +#define mmLB1_LB_DEBUG3 0x1ce6 +#define mmLB2_LB_DEBUG3 0x1ee6 +#define mmLB3_LB_DEBUG3 0x40e6 +#define mmLB4_LB_DEBUG3 0x42e6 +#define mmLB5_LB_DEBUG3 0x44e6 +#define mmLB_TEST_DEBUG_INDEX 0x1afe +#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe +#define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe +#define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe +#define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe +#define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe +#define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe +#define mmLB_TEST_DEBUG_DATA 0x1aff +#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff +#define mmLB1_LB_TEST_DEBUG_DATA 0x1cff +#define mmLB2_LB_TEST_DEBUG_DATA 0x1eff +#define mmLB3_LB_TEST_DEBUG_DATA 0x40ff +#define mmLB4_LB_TEST_DEBUG_DATA 0x42ff +#define mmLB5_LB_TEST_DEBUG_DATA 0x44ff +#define mmLBV_DATA_FORMAT 0x463c +#define mmLBV0_LBV_DATA_FORMAT 0x463c +#define mmLBV1_LBV_DATA_FORMAT 0x983c +#define mmLBV_MEMORY_CTRL 0x463d +#define mmLBV0_LBV_MEMORY_CTRL 0x463d +#define mmLBV1_LBV_MEMORY_CTRL 0x983d +#define mmLBV_MEMORY_SIZE_STATUS 0x463e +#define mmLBV0_LBV_MEMORY_SIZE_STATUS 0x463e +#define mmLBV1_LBV_MEMORY_SIZE_STATUS 0x983e +#define mmLBV_DESKTOP_HEIGHT 0x463f +#define mmLBV0_LBV_DESKTOP_HEIGHT 0x463f +#define mmLBV1_LBV_DESKTOP_HEIGHT 0x983f +#define mmLBV_VLINE_START_END 0x4640 +#define mmLBV0_LBV_VLINE_START_END 0x4640 +#define mmLBV1_LBV_VLINE_START_END 0x9840 +#define mmLBV_VLINE2_START_END 0x4641 +#define mmLBV0_LBV_VLINE2_START_END 0x4641 +#define mmLBV1_LBV_VLINE2_START_END 0x9841 +#define mmLBV_V_COUNTER 0x4642 +#define mmLBV0_LBV_V_COUNTER 0x4642 +#define mmLBV1_LBV_V_COUNTER 0x9842 +#define mmLBV_SNAPSHOT_V_COUNTER 0x4643 +#define mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x4643 +#define mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x9843 +#define mmLBV_V_COUNTER_CHROMA 0x4644 +#define mmLBV0_LBV_V_COUNTER_CHROMA 0x4644 +#define mmLBV1_LBV_V_COUNTER_CHROMA 0x9844 +#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 +#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 +#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x9845 +#define mmLBV_INTERRUPT_MASK 0x4646 +#define mmLBV0_LBV_INTERRUPT_MASK 0x4646 +#define mmLBV1_LBV_INTERRUPT_MASK 0x9846 +#define mmLBV_VLINE_STATUS 0x4647 +#define mmLBV0_LBV_VLINE_STATUS 0x4647 +#define mmLBV1_LBV_VLINE_STATUS 0x9847 +#define mmLBV_VLINE2_STATUS 0x4648 +#define mmLBV0_LBV_VLINE2_STATUS 0x4648 +#define mmLBV1_LBV_VLINE2_STATUS 0x9848 +#define mmLBV_VBLANK_STATUS 0x4649 +#define mmLBV0_LBV_VBLANK_STATUS 0x4649 +#define mmLBV1_LBV_VBLANK_STATUS 0x9849 +#define mmLBV_SYNC_RESET_SEL 0x464a +#define mmLBV0_LBV_SYNC_RESET_SEL 0x464a +#define mmLBV1_LBV_SYNC_RESET_SEL 0x984a +#define mmLBV_BLACK_KEYER_R_CR 0x464b +#define mmLBV0_LBV_BLACK_KEYER_R_CR 0x464b +#define mmLBV1_LBV_BLACK_KEYER_R_CR 0x984b +#define mmLBV_BLACK_KEYER_G_Y 0x464c +#define mmLBV0_LBV_BLACK_KEYER_G_Y 0x464c +#define mmLBV1_LBV_BLACK_KEYER_G_Y 0x984c +#define mmLBV_BLACK_KEYER_B_CB 0x464d +#define mmLBV0_LBV_BLACK_KEYER_B_CB 0x464d +#define mmLBV1_LBV_BLACK_KEYER_B_CB 0x984d +#define mmLBV_KEYER_COLOR_CTRL 0x464e +#define mmLBV0_LBV_KEYER_COLOR_CTRL 0x464e +#define mmLBV1_LBV_KEYER_COLOR_CTRL 0x984e +#define mmLBV_KEYER_COLOR_R_CR 0x464f +#define mmLBV0_LBV_KEYER_COLOR_R_CR 0x464f +#define mmLBV1_LBV_KEYER_COLOR_R_CR 0x984f +#define mmLBV_KEYER_COLOR_G_Y 0x4650 +#define mmLBV0_LBV_KEYER_COLOR_G_Y 0x4650 +#define mmLBV1_LBV_KEYER_COLOR_G_Y 0x9850 +#define mmLBV_KEYER_COLOR_B_CB 0x4651 +#define mmLBV0_LBV_KEYER_COLOR_B_CB 0x4651 +#define mmLBV1_LBV_KEYER_COLOR_B_CB 0x9851 +#define mmLBV_KEYER_COLOR_REP_R_CR 0x4652 +#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x4652 +#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x9852 +#define mmLBV_KEYER_COLOR_REP_G_Y 0x4653 +#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x4653 +#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x9853 +#define mmLBV_KEYER_COLOR_REP_B_CB 0x4654 +#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x4654 +#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x9854 +#define mmLBV_BUFFER_LEVEL_STATUS 0x4655 +#define mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x4655 +#define mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x9855 +#define mmLBV_BUFFER_URGENCY_CTRL 0x4656 +#define mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x4656 +#define mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x9856 +#define mmLBV_BUFFER_URGENCY_STATUS 0x4657 +#define mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x4657 +#define mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x9857 +#define mmLBV_BUFFER_STATUS 0x4658 +#define mmLBV0_LBV_BUFFER_STATUS 0x4658 +#define mmLBV1_LBV_BUFFER_STATUS 0x9858 +#define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 +#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x4659 +#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x9859 +#define mmLBV_DEBUG 0x465a +#define mmLBV0_LBV_DEBUG 0x465a +#define mmLBV1_LBV_DEBUG 0x985a +#define mmLBV_DEBUG2 0x465b +#define mmLBV0_LBV_DEBUG2 0x465b +#define mmLBV1_LBV_DEBUG2 0x985b +#define mmLBV_DEBUG3 0x465c +#define mmLBV0_LBV_DEBUG3 0x465c +#define mmLBV1_LBV_DEBUG3 0x985c +#define mmLBV_TEST_DEBUG_INDEX 0x4666 +#define mmLBV0_LBV_TEST_DEBUG_INDEX 0x4666 +#define mmLBV1_LBV_TEST_DEBUG_INDEX 0x9866 +#define mmLBV_TEST_DEBUG_DATA 0x4667 +#define mmLBV0_LBV_TEST_DEBUG_DATA 0x4667 +#define mmLBV1_LBV_TEST_DEBUG_DATA 0x9867 +#define mmMVP_CONTROL1 0x2ac +#define mmMVP_CONTROL2 0x2ad +#define mmMVP_FIFO_CONTROL 0x2ae +#define mmMVP_FIFO_STATUS 0x2af +#define mmMVP_SLAVE_STATUS 0x2b0 +#define mmMVP_INBAND_CNTL_CAP 0x2b1 +#define mmMVP_BLACK_KEYER 0x2b2 +#define mmMVP_CRC_CNTL 0x2b3 +#define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 +#define mmMVP_CRC_RESULT_RED 0x2b5 +#define mmMVP_CONTROL3 0x2b6 +#define mmMVP_RECEIVE_CNT_CNTL1 0x2b7 +#define mmMVP_RECEIVE_CNT_CNTL2 0x2b8 +#define mmMVP_DEBUG 0x2bb +#define mmMVP_TEST_DEBUG_INDEX 0x2b9 +#define mmMVP_TEST_DEBUG_DATA 0x2ba +#define ixMVP_DEBUG_12 0xc +#define ixMVP_DEBUG_13 0xd +#define ixMVP_DEBUG_14 0xe +#define ixMVP_DEBUG_15 0xf +#define ixMVP_DEBUG_16 0x10 +#define ixMVP_DEBUG_17 0x11 +#define mmSCL_COEF_RAM_SELECT 0x1b40 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x4140 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x4340 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x4540 +#define mmSCL_COEF_RAM_TAP_DATA 0x1b41 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 +#define mmSCL_MODE 0x1b42 +#define mmSCL0_SCL_MODE 0x1b42 +#define mmSCL1_SCL_MODE 0x1d42 +#define mmSCL2_SCL_MODE 0x1f42 +#define mmSCL3_SCL_MODE 0x4142 +#define mmSCL4_SCL_MODE 0x4342 +#define mmSCL5_SCL_MODE 0x4542 +#define mmSCL_TAP_CONTROL 0x1b43 +#define mmSCL0_SCL_TAP_CONTROL 0x1b43 +#define mmSCL1_SCL_TAP_CONTROL 0x1d43 +#define mmSCL2_SCL_TAP_CONTROL 0x1f43 +#define mmSCL3_SCL_TAP_CONTROL 0x4143 +#define mmSCL4_SCL_TAP_CONTROL 0x4343 +#define mmSCL5_SCL_TAP_CONTROL 0x4543 +#define mmSCL_CONTROL 0x1b44 +#define mmSCL0_SCL_CONTROL 0x1b44 +#define mmSCL1_SCL_CONTROL 0x1d44 +#define mmSCL2_SCL_CONTROL 0x1f44 +#define mmSCL3_SCL_CONTROL 0x4144 +#define mmSCL4_SCL_CONTROL 0x4344 +#define mmSCL5_SCL_CONTROL 0x4544 +#define mmSCL_BYPASS_CONTROL 0x1b45 +#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 +#define mmSCL1_SCL_BYPASS_CONTROL 0x1d45 +#define mmSCL2_SCL_BYPASS_CONTROL 0x1f45 +#define mmSCL3_SCL_BYPASS_CONTROL 0x4145 +#define mmSCL4_SCL_BYPASS_CONTROL 0x4345 +#define mmSCL5_SCL_BYPASS_CONTROL 0x4545 +#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 +#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 +#define mmSCL_HORZ_FILTER_CONTROL 0x1b48 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 +#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 +#define mmSCL_HORZ_FILTER_INIT 0x1b4a +#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a +#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a +#define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a +#define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a +#define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a +#define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a +#define mmSCL_VERT_FILTER_CONTROL 0x1b4b +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b +#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c +#define mmSCL_VERT_FILTER_INIT 0x1b4d +#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d +#define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d +#define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d +#define mmSCL3_SCL_VERT_FILTER_INIT 0x414d +#define mmSCL4_SCL_VERT_FILTER_INIT 0x434d +#define mmSCL5_SCL_VERT_FILTER_INIT 0x454d +#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e +#define mmSCL_ROUND_OFFSET 0x1b4f +#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f +#define mmSCL1_SCL_ROUND_OFFSET 0x1d4f +#define mmSCL2_SCL_ROUND_OFFSET 0x1f4f +#define mmSCL3_SCL_ROUND_OFFSET 0x414f +#define mmSCL4_SCL_ROUND_OFFSET 0x434f +#define mmSCL5_SCL_ROUND_OFFSET 0x454f +#define mmSCL_UPDATE 0x1b51 +#define mmSCL0_SCL_UPDATE 0x1b51 +#define mmSCL1_SCL_UPDATE 0x1d51 +#define mmSCL2_SCL_UPDATE 0x1f51 +#define mmSCL3_SCL_UPDATE 0x4151 +#define mmSCL4_SCL_UPDATE 0x4351 +#define mmSCL5_SCL_UPDATE 0x4551 +#define mmSCL_F_SHARP_CONTROL 0x1b53 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x4153 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x4353 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x4553 +#define mmSCL_ALU_CONTROL 0x1b54 +#define mmSCL0_SCL_ALU_CONTROL 0x1b54 +#define mmSCL1_SCL_ALU_CONTROL 0x1d54 +#define mmSCL2_SCL_ALU_CONTROL 0x1f54 +#define mmSCL3_SCL_ALU_CONTROL 0x4154 +#define mmSCL4_SCL_ALU_CONTROL 0x4354 +#define mmSCL5_SCL_ALU_CONTROL 0x4554 +#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 +#define mmVIEWPORT_START_SECONDARY 0x1b5b +#define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b +#define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b +#define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b +#define mmSCL3_VIEWPORT_START_SECONDARY 0x415b +#define mmSCL4_VIEWPORT_START_SECONDARY 0x435b +#define mmSCL5_VIEWPORT_START_SECONDARY 0x455b +#define mmVIEWPORT_START 0x1b5c +#define mmSCL0_VIEWPORT_START 0x1b5c +#define mmSCL1_VIEWPORT_START 0x1d5c +#define mmSCL2_VIEWPORT_START 0x1f5c +#define mmSCL3_VIEWPORT_START 0x415c +#define mmSCL4_VIEWPORT_START 0x435c +#define mmSCL5_VIEWPORT_START 0x455c +#define mmVIEWPORT_SIZE 0x1b5d +#define mmSCL0_VIEWPORT_SIZE 0x1b5d +#define mmSCL1_VIEWPORT_SIZE 0x1d5d +#define mmSCL2_VIEWPORT_SIZE 0x1f5d +#define mmSCL3_VIEWPORT_SIZE 0x415d +#define mmSCL4_VIEWPORT_SIZE 0x435d +#define mmSCL5_VIEWPORT_SIZE 0x455d +#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e +#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f +#define mmSCL_MODE_CHANGE_DET1 0x1b60 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 +#define mmSCL_MODE_CHANGE_DET2 0x1b61 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 +#define mmSCL_MODE_CHANGE_DET3 0x1b62 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 +#define mmSCL_MODE_CHANGE_MASK 0x1b63 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 +#define mmSCL_DEBUG2 0x1b69 +#define mmSCL0_SCL_DEBUG2 0x1b69 +#define mmSCL1_SCL_DEBUG2 0x1d69 +#define mmSCL2_SCL_DEBUG2 0x1f69 +#define mmSCL3_SCL_DEBUG2 0x4169 +#define mmSCL4_SCL_DEBUG2 0x4369 +#define mmSCL5_SCL_DEBUG2 0x4569 +#define mmSCL_DEBUG 0x1b6a +#define mmSCL0_SCL_DEBUG 0x1b6a +#define mmSCL1_SCL_DEBUG 0x1d6a +#define mmSCL2_SCL_DEBUG 0x1f6a +#define mmSCL3_SCL_DEBUG 0x416a +#define mmSCL4_SCL_DEBUG 0x436a +#define mmSCL5_SCL_DEBUG 0x456a +#define mmSCL_TEST_DEBUG_INDEX 0x1b6b +#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b +#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b +#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b +#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b +#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b +#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b +#define mmSCL_TEST_DEBUG_DATA 0x1b6c +#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c +#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c +#define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c +#define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c +#define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c +#define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c +#define mmSCLV_COEF_RAM_SELECT 0x4670 +#define mmSCLV0_SCLV_COEF_RAM_SELECT 0x4670 +#define mmSCLV1_SCLV_COEF_RAM_SELECT 0x9870 +#define mmSCLV_COEF_RAM_TAP_DATA 0x4671 +#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x4671 +#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x9871 +#define mmSCLV_MODE 0x4672 +#define mmSCLV0_SCLV_MODE 0x4672 +#define mmSCLV1_SCLV_MODE 0x9872 +#define mmSCLV_TAP_CONTROL 0x4673 +#define mmSCLV0_SCLV_TAP_CONTROL 0x4673 +#define mmSCLV1_SCLV_TAP_CONTROL 0x9873 +#define mmSCLV_CONTROL 0x4674 +#define mmSCLV0_SCLV_CONTROL 0x4674 +#define mmSCLV1_SCLV_CONTROL 0x9874 +#define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 +#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x4675 +#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x9875 +#define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 +#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x4676 +#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x9876 +#define mmSCLV_HORZ_FILTER_CONTROL 0x4677 +#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x4677 +#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x9877 +#define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 +#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x4678 +#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x9878 +#define mmSCLV_HORZ_FILTER_INIT 0x4679 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT 0x4679 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT 0x9879 +#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a +#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a +#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x987a +#define mmSCLV_HORZ_FILTER_INIT_C 0x467b +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x467b +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x987b +#define mmSCLV_VERT_FILTER_CONTROL 0x467c +#define mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x467c +#define mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x987c +#define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d +#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x467d +#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x987d +#define mmSCLV_VERT_FILTER_INIT 0x467e +#define mmSCLV0_SCLV_VERT_FILTER_INIT 0x467e +#define mmSCLV1_SCLV_VERT_FILTER_INIT 0x987e +#define mmSCLV_VERT_FILTER_INIT_BOT 0x467f +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x467f +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x987f +#define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 +#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 +#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x9880 +#define mmSCLV_VERT_FILTER_INIT_C 0x4681 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x4681 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x9881 +#define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x4682 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x9882 +#define mmSCLV_ROUND_OFFSET 0x4683 +#define mmSCLV0_SCLV_ROUND_OFFSET 0x4683 +#define mmSCLV1_SCLV_ROUND_OFFSET 0x9883 +#define mmSCLV_UPDATE 0x4684 +#define mmSCLV0_SCLV_UPDATE 0x4684 +#define mmSCLV1_SCLV_UPDATE 0x9884 +#define mmSCLV_ALU_CONTROL 0x4685 +#define mmSCLV0_SCLV_ALU_CONTROL 0x4685 +#define mmSCLV1_SCLV_ALU_CONTROL 0x9885 +#define mmSCLV_VIEWPORT_START 0x4686 +#define mmSCLV0_SCLV_VIEWPORT_START 0x4686 +#define mmSCLV1_SCLV_VIEWPORT_START 0x9886 +#define mmSCLV_VIEWPORT_START_SECONDARY 0x4687 +#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x4687 +#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x9887 +#define mmSCLV_VIEWPORT_SIZE 0x4688 +#define mmSCLV0_SCLV_VIEWPORT_SIZE 0x4688 +#define mmSCLV1_SCLV_VIEWPORT_SIZE 0x9888 +#define mmSCLV_VIEWPORT_START_C 0x4689 +#define mmSCLV0_SCLV_VIEWPORT_START_C 0x4689 +#define mmSCLV1_SCLV_VIEWPORT_START_C 0x9889 +#define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a +#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x468a +#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x988a +#define mmSCLV_VIEWPORT_SIZE_C 0x468b +#define mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x468b +#define mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x988b +#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c +#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c +#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x988c +#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d +#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d +#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x988d +#define mmSCLV_MODE_CHANGE_DET1 0x468e +#define mmSCLV0_SCLV_MODE_CHANGE_DET1 0x468e +#define mmSCLV1_SCLV_MODE_CHANGE_DET1 0x988e +#define mmSCLV_MODE_CHANGE_DET2 0x468f +#define mmSCLV0_SCLV_MODE_CHANGE_DET2 0x468f +#define mmSCLV1_SCLV_MODE_CHANGE_DET2 0x988f +#define mmSCLV_MODE_CHANGE_DET3 0x4690 +#define mmSCLV0_SCLV_MODE_CHANGE_DET3 0x4690 +#define mmSCLV1_SCLV_MODE_CHANGE_DET3 0x9890 +#define mmSCLV_MODE_CHANGE_MASK 0x4691 +#define mmSCLV0_SCLV_MODE_CHANGE_MASK 0x4691 +#define mmSCLV1_SCLV_MODE_CHANGE_MASK 0x9891 +#define mmSCLV_HORZ_FILTER_INIT_BOT 0x4692 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x4692 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x9892 +#define mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x4693 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x9893 +#define mmSCLV_DEBUG2 0x4694 +#define mmSCLV0_SCLV_DEBUG2 0x4694 +#define mmSCLV1_SCLV_DEBUG2 0x9894 +#define mmSCLV_DEBUG 0x4695 +#define mmSCLV0_SCLV_DEBUG 0x4695 +#define mmSCLV1_SCLV_DEBUG 0x9895 +#define mmSCLV_TEST_DEBUG_INDEX 0x4696 +#define mmSCLV0_SCLV_TEST_DEBUG_INDEX 0x4696 +#define mmSCLV1_SCLV_TEST_DEBUG_INDEX 0x9896 +#define mmSCLV_TEST_DEBUG_DATA 0x4697 +#define mmSCLV0_SCLV_TEST_DEBUG_DATA 0x4697 +#define mmSCLV1_SCLV_TEST_DEBUG_DATA 0x9897 +#define mmCOL_MAN_UPDATE 0x46a4 +#define mmCOL_MAN0_COL_MAN_UPDATE 0x46a4 +#define mmCOL_MAN1_COL_MAN_UPDATE 0x98a4 +#define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 +#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x46a5 +#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x98a5 +#define mmINPUT_CSC_C11_C12_A 0x46a6 +#define mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x46a6 +#define mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x98a6 +#define mmINPUT_CSC_C13_C14_A 0x46a7 +#define mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x46a7 +#define mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x98a7 +#define mmINPUT_CSC_C21_C22_A 0x46a8 +#define mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x46a8 +#define mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x98a8 +#define mmINPUT_CSC_C23_C24_A 0x46a9 +#define mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x46a9 +#define mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x98a9 +#define mmINPUT_CSC_C31_C32_A 0x46aa +#define mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x46aa +#define mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x98aa +#define mmINPUT_CSC_C33_C34_A 0x46ab +#define mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x46ab +#define mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x98ab +#define mmINPUT_CSC_C11_C12_B 0x46ac +#define mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x46ac +#define mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x98ac +#define mmINPUT_CSC_C13_C14_B 0x46ad +#define mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x46ad +#define mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x98ad +#define mmINPUT_CSC_C21_C22_B 0x46ae +#define mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x46ae +#define mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x98ae +#define mmINPUT_CSC_C23_C24_B 0x46af +#define mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x46af +#define mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x98af +#define mmINPUT_CSC_C31_C32_B 0x46b0 +#define mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x46b0 +#define mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x98b0 +#define mmINPUT_CSC_C33_C34_B 0x46b1 +#define mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x46b1 +#define mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x98b1 +#define mmPRESCALE_CONTROL 0x46b2 +#define mmCOL_MAN0_PRESCALE_CONTROL 0x46b2 +#define mmCOL_MAN1_PRESCALE_CONTROL 0x98b2 +#define mmPRESCALE_VALUES_R 0x46b3 +#define mmCOL_MAN0_PRESCALE_VALUES_R 0x46b3 +#define mmCOL_MAN1_PRESCALE_VALUES_R 0x98b3 +#define mmPRESCALE_VALUES_G 0x46b4 +#define mmCOL_MAN0_PRESCALE_VALUES_G 0x46b4 +#define mmCOL_MAN1_PRESCALE_VALUES_G 0x98b4 +#define mmPRESCALE_VALUES_B 0x46b5 +#define mmCOL_MAN0_PRESCALE_VALUES_B 0x46b5 +#define mmCOL_MAN1_PRESCALE_VALUES_B 0x98b5 +#define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 +#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x46b6 +#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x98b6 +#define mmOUTPUT_CSC_C11_C12_A 0x46b7 +#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x46b7 +#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x98b7 +#define mmOUTPUT_CSC_C13_C14_A 0x46b8 +#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x46b8 +#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x98b8 +#define mmOUTPUT_CSC_C21_C22_A 0x46b9 +#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x46b9 +#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x98b9 +#define mmOUTPUT_CSC_C23_C24_A 0x46ba +#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x46ba +#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x98ba +#define mmOUTPUT_CSC_C31_C32_A 0x46bb +#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x46bb +#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x98bb +#define mmOUTPUT_CSC_C33_C34_A 0x46bc +#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x46bc +#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x98bc +#define mmOUTPUT_CSC_C11_C12_B 0x46bd +#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x46bd +#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x98bd +#define mmOUTPUT_CSC_C13_C14_B 0x46be +#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x46be +#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x98be +#define mmOUTPUT_CSC_C21_C22_B 0x46bf +#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x46bf +#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x98bf +#define mmOUTPUT_CSC_C23_C24_B 0x46c0 +#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x46c0 +#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x98c0 +#define mmOUTPUT_CSC_C31_C32_B 0x46c1 +#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x46c1 +#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x98c1 +#define mmOUTPUT_CSC_C33_C34_B 0x46c2 +#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x46c2 +#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x98c2 +#define mmDENORM_CLAMP_CONTROL 0x46c3 +#define mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x46c3 +#define mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x98c3 +#define mmDENORM_CLAMP_RANGE_R_CR 0x46c4 +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x46c4 +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x98c4 +#define mmDENORM_CLAMP_RANGE_G_Y 0x46c5 +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x46c5 +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x98c5 +#define mmDENORM_CLAMP_RANGE_B_CB 0x46c6 +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x46c6 +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x98c6 +#define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 +#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x46c7 +#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x98c7 +#define mmGAMMA_CORR_CONTROL 0x46c8 +#define mmCOL_MAN0_GAMMA_CORR_CONTROL 0x46c8 +#define mmCOL_MAN1_GAMMA_CORR_CONTROL 0x98c8 +#define mmGAMMA_CORR_LUT_INDEX 0x46c9 +#define mmCOL_MAN0_GAMMA_CORR_LUT_INDEX 0x46c9 +#define mmCOL_MAN1_GAMMA_CORR_LUT_INDEX 0x98c9 +#define mmGAMMA_CORR_LUT_DATA 0x46ca +#define mmCOL_MAN0_GAMMA_CORR_LUT_DATA 0x46ca +#define mmCOL_MAN1_GAMMA_CORR_LUT_DATA 0x98ca +#define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb +#define mmCOL_MAN0_GAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb +#define mmCOL_MAN1_GAMMA_CORR_LUT_WRITE_EN_MASK 0x98cb +#define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_START_CNTL 0x46cc +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_START_CNTL 0x98cc +#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_SLOPE_CNTL 0x98cd +#define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL1 0x46ce +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL1 0x98ce +#define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL2 0x46cf +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL2 0x98cf +#define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_0_1 0x46d0 +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_0_1 0x98d0 +#define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_2_3 0x46d1 +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_2_3 0x98d1 +#define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_4_5 0x46d2 +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_4_5 0x98d2 +#define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_6_7 0x46d3 +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_6_7 0x98d3 +#define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_8_9 0x46d4 +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_8_9 0x98d4 +#define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_10_11 0x46d5 +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_10_11 0x98d5 +#define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_12_13 0x46d6 +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_12_13 0x98d6 +#define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 +#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_14_15 0x46d7 +#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_14_15 0x98d7 +#define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_START_CNTL 0x46d8 +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_START_CNTL 0x98d8 +#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_SLOPE_CNTL 0x98d9 +#define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL1 0x46da +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL1 0x98da +#define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL2 0x46db +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL2 0x98db +#define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_0_1 0x46dc +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_0_1 0x98dc +#define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_2_3 0x46dd +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_2_3 0x98dd +#define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_4_5 0x46de +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_4_5 0x98de +#define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_6_7 0x46df +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_6_7 0x98df +#define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_8_9 0x46e0 +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_8_9 0x98e0 +#define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_10_11 0x46e1 +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_10_11 0x98e1 +#define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_12_13 0x46e2 +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_12_13 0x98e2 +#define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 +#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_14_15 0x46e3 +#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_14_15 0x98e3 +#define mmPACK_FIFO_ERROR 0x46e4 +#define mmCOL_MAN0_PACK_FIFO_ERROR 0x46e4 +#define mmCOL_MAN1_PACK_FIFO_ERROR 0x98e4 +#define mmOUTPUT_FIFO_ERROR 0x46e5 +#define mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x46e5 +#define mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x98e5 +#define mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x46e6 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x98e6 +#define mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x46e7 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x98e7 +#define mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x98e8 +#define mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x46e9 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x98e9 +#define mmINPUT_GAMMA_LUT_30_COLOR 0x46ea +#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x46ea +#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x98ea +#define mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb +#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x46eb +#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x98eb +#define mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec +#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x46ec +#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x98ec +#define mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x46ed +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x98ed +#define mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x46ee +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x98ee +#define mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x46ef +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x98ef +#define mmCOL_MAN_DEBUG_CONTROL 0x46f0 +#define mmCOL_MAN0_COL_MAN_DEBUG_CONTROL 0x46f0 +#define mmCOL_MAN1_COL_MAN_DEBUG_CONTROL 0x98f0 +#define mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1 +#define mmCOL_MAN0_COL_MAN_TEST_DEBUG_INDEX 0x46f1 +#define mmCOL_MAN1_COL_MAN_TEST_DEBUG_INDEX 0x98f1 +#define mmCOL_MAN_TEST_DEBUG_DATA 0x46f3 +#define mmCOL_MAN0_COL_MAN_TEST_DEBUG_DATA 0x46f3 +#define mmCOL_MAN1_COL_MAN_TEST_DEBUG_DATA 0x98f3 +#define mmUNP_GRPH_ENABLE 0x4600 +#define mmUNP0_UNP_GRPH_ENABLE 0x4600 +#define mmUNP1_UNP_GRPH_ENABLE 0x9800 +#define mmUNP_GRPH_CONTROL 0x4601 +#define mmUNP0_UNP_GRPH_CONTROL 0x4601 +#define mmUNP1_UNP_GRPH_CONTROL 0x9801 +#define mmUNP_GRPH_CONTROL_C 0x4602 +#define mmUNP0_UNP_GRPH_CONTROL_C 0x4602 +#define mmUNP1_UNP_GRPH_CONTROL_C 0x9802 +#define mmUNP_GRPH_CONTROL_EXP 0x4603 +#define mmUNP0_UNP_GRPH_CONTROL_EXP 0x4603 +#define mmUNP1_UNP_GRPH_CONTROL_EXP 0x9803 +#define mmUNP_GRPH_SWAP_CNTL 0x4605 +#define mmUNP0_UNP_GRPH_SWAP_CNTL 0x4605 +#define mmUNP1_UNP_GRPH_SWAP_CNTL 0x9805 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x9806 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x9807 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x9808 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x9809 +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x980a +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x980b +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x980c +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x980d +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x980e +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x980f +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x9810 +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x9811 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x9812 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x9813 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x9814 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x9815 +#define mmUNP_GRPH_PITCH_L 0x4616 +#define mmUNP0_UNP_GRPH_PITCH_L 0x4616 +#define mmUNP1_UNP_GRPH_PITCH_L 0x9816 +#define mmUNP_GRPH_PITCH_C 0x4617 +#define mmUNP0_UNP_GRPH_PITCH_C 0x4617 +#define mmUNP1_UNP_GRPH_PITCH_C 0x9817 +#define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x4618 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x9818 +#define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x4619 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x9819 +#define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x461a +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x981a +#define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x461b +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x981b +#define mmUNP_GRPH_X_START_L 0x461c +#define mmUNP0_UNP_GRPH_X_START_L 0x461c +#define mmUNP1_UNP_GRPH_X_START_L 0x981c +#define mmUNP_GRPH_X_START_C 0x461d +#define mmUNP0_UNP_GRPH_X_START_C 0x461d +#define mmUNP1_UNP_GRPH_X_START_C 0x981d +#define mmUNP_GRPH_Y_START_L 0x461e +#define mmUNP0_UNP_GRPH_Y_START_L 0x461e +#define mmUNP1_UNP_GRPH_Y_START_L 0x981e +#define mmUNP_GRPH_Y_START_C 0x461f +#define mmUNP0_UNP_GRPH_Y_START_C 0x461f +#define mmUNP1_UNP_GRPH_Y_START_C 0x981f +#define mmUNP_GRPH_X_END_L 0x4620 +#define mmUNP0_UNP_GRPH_X_END_L 0x4620 +#define mmUNP1_UNP_GRPH_X_END_L 0x9820 +#define mmUNP_GRPH_X_END_C 0x4621 +#define mmUNP0_UNP_GRPH_X_END_C 0x4621 +#define mmUNP1_UNP_GRPH_X_END_C 0x9821 +#define mmUNP_GRPH_Y_END_L 0x4622 +#define mmUNP0_UNP_GRPH_Y_END_L 0x4622 +#define mmUNP1_UNP_GRPH_Y_END_L 0x9822 +#define mmUNP_GRPH_Y_END_C 0x4623 +#define mmUNP0_UNP_GRPH_Y_END_C 0x4623 +#define mmUNP1_UNP_GRPH_Y_END_C 0x9823 +#define mmUNP_GRPH_UPDATE 0x4624 +#define mmUNP0_UNP_GRPH_UPDATE 0x4624 +#define mmUNP1_UNP_GRPH_UPDATE 0x9824 +#define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a +#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a +#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x983a +#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x9825 +#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x9826 +#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x9827 +#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x9828 +#define mmUNP_DVMM_PTE_CONTROL 0x4629 +#define mmUNP_GRPH_INTERRUPT_STATUS 0x462b +#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x462b +#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x982b +#define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c +#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x462c +#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x982c +#define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e +#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x462e +#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x982e +#define mmUNP_FLIP_CONTROL 0x462f +#define mmUNP0_UNP_FLIP_CONTROL 0x462f +#define mmUNP1_UNP_FLIP_CONTROL 0x982f +#define mmUNP_CRC_CONTROL 0x4630 +#define mmUNP0_UNP_CRC_CONTROL 0x4630 +#define mmUNP1_UNP_CRC_CONTROL 0x9830 +#define mmUNP_CRC_MASK 0x4631 +#define mmUNP0_UNP_CRC_MASK 0x4631 +#define mmUNP1_UNP_CRC_MASK 0x9831 +#define mmUNP_CRC_CURRENT 0x4632 +#define mmUNP0_UNP_CRC_CURRENT 0x4632 +#define mmUNP1_UNP_CRC_CURRENT 0x9832 +#define mmUNP_CRC_LAST 0x4633 +#define mmUNP0_UNP_CRC_LAST 0x4633 +#define mmUNP1_UNP_CRC_LAST 0x9833 +#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 +#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 +#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x9834 +#define mmUNP_HW_ROTATION 0x4635 +#define mmUNP0_UNP_HW_ROTATION 0x4635 +#define mmUNP1_UNP_HW_ROTATION 0x9835 +#define mmUNP_DEBUG 0x4636 +#define mmUNP0_UNP_DEBUG 0x4636 +#define mmUNP1_UNP_DEBUG 0x9836 +#define mmUNP_DEBUG2 0x4637 +#define mmUNP0_UNP_DEBUG2 0x4637 +#define mmUNP1_UNP_DEBUG2 0x9837 +#define mmUNP_DVMM_DEBUG 0x463b +#define mmUNP0_UNP_DVMM_DEBUG 0x463b +#define mmUNP1_UNP_DVMM_DEBUG 0x983b +#define mmUNP_TEST_DEBUG_INDEX 0x4638 +#define mmUNP0_UNP_TEST_DEBUG_INDEX 0x4638 +#define mmUNP1_UNP_TEST_DEBUG_INDEX 0x9838 +#define mmUNP_TEST_DEBUG_DATA 0x4639 +#define mmUNP0_UNP_TEST_DEBUG_DATA 0x4639 +#define mmUNP1_UNP_TEST_DEBUG_DATA 0x9839 +#define mmGENMO_WT 0xf0 +#define mmGENMO_RD 0xf3 +#define mmGENENB 0xf0 +#define mmGENFC_WT 0xee +#define mmVGA0_GENFC_WT 0xee +#define mmVGA1_GENFC_WT 0xf6 +#define mmGENFC_RD 0xf2 +#define mmGENS0 0xf0 +#define mmGENS1 0xee +#define mmVGA0_GENS1 0xee +#define mmVGA1_GENS1 0xf6 +#define mmDAC_DATA 0xf2 +#define mmDAC_MASK 0xf1 +#define mmDAC_R_INDEX 0xf1 +#define mmDAC_W_INDEX 0xf2 +#define mmSEQ8_IDX 0xf1 +#define mmSEQ8_DATA 0xf1 +#define ixSEQ00 0x0 +#define ixSEQ01 0x1 +#define ixSEQ02 0x2 +#define ixSEQ03 0x3 +#define ixSEQ04 0x4 +#define mmCRTC8_IDX 0xed +#define mmVGA0_CRTC8_IDX 0xed +#define mmVGA1_CRTC8_IDX 0xf5 +#define mmCRTC8_DATA 0xed +#define mmVGA0_CRTC8_DATA 0xed +#define mmVGA1_CRTC8_DATA 0xf5 +#define ixCRT00 0x0 +#define ixCRT01 0x1 +#define ixCRT02 0x2 +#define ixCRT03 0x3 +#define ixCRT04 0x4 +#define ixCRT05 0x5 +#define ixCRT06 0x6 +#define ixCRT07 0x7 +#define ixCRT08 0x8 +#define ixCRT09 0x9 +#define ixCRT0A 0xa +#define ixCRT0B 0xb +#define ixCRT0C 0xc +#define ixCRT0D 0xd +#define ixCRT0E 0xe +#define ixCRT0F 0xf +#define ixCRT10 0x10 +#define ixCRT11 0x11 +#define ixCRT12 0x12 +#define ixCRT13 0x13 +#define ixCRT14 0x14 +#define ixCRT15 0x15 +#define ixCRT16 0x16 +#define ixCRT17 0x17 +#define ixCRT18 0x18 +#define ixCRT1E 0x1e +#define ixCRT1F 0x1f +#define ixCRT22 0x22 +#define mmGRPH8_IDX 0xf3 +#define mmGRPH8_DATA 0xf3 +#define ixGRA00 0x0 +#define ixGRA01 0x1 +#define ixGRA02 0x2 +#define ixGRA03 0x3 +#define ixGRA04 0x4 +#define ixGRA05 0x5 +#define ixGRA06 0x6 +#define ixGRA07 0x7 +#define ixGRA08 0x8 +#define mmATTRX 0xf0 +#define mmATTRDW 0xf0 +#define mmATTRDR 0xf0 +#define ixATTR00 0x0 +#define ixATTR01 0x1 +#define ixATTR02 0x2 +#define ixATTR03 0x3 +#define ixATTR04 0x4 +#define ixATTR05 0x5 +#define ixATTR06 0x6 +#define ixATTR07 0x7 +#define ixATTR08 0x8 +#define ixATTR09 0x9 +#define ixATTR0A 0xa +#define ixATTR0B 0xb +#define ixATTR0C 0xc +#define ixATTR0D 0xd +#define ixATTR0E 0xe +#define ixATTR0F 0xf +#define ixATTR10 0x10 +#define ixATTR11 0x11 +#define ixATTR12 0x12 +#define ixATTR13 0x13 +#define ixATTR14 0x14 +#define mmVGA_RENDER_CONTROL 0xc0 +#define mmVGA_SOURCE_SELECT 0xfc +#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 +#define mmVGA_MODE_CONTROL 0xc2 +#define mmVGA_SURFACE_PITCH_SELECT 0xc3 +#define mmVGA_MEMORY_BASE_ADDRESS 0xc4 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 +#define mmVGA_HDP_CONTROL 0xca +#define mmVGA_CACHE_CONTROL 0xcb +#define mmD1VGA_CONTROL 0xcc +#define mmD2VGA_CONTROL 0xce +#define mmD3VGA_CONTROL 0xf8 +#define mmD4VGA_CONTROL 0xf9 +#define mmD5VGA_CONTROL 0xfa +#define mmD6VGA_CONTROL 0xfb +#define mmVGA_HW_DEBUG 0xcf +#define mmVGA_STATUS 0xd0 +#define mmVGA_INTERRUPT_CONTROL 0xd1 +#define mmVGA_STATUS_CLEAR 0xd2 +#define mmVGA_INTERRUPT_STATUS 0xd3 +#define mmVGA_MAIN_CONTROL 0xd4 +#define mmVGA_TEST_CONTROL 0xd5 +#define mmVGA_DEBUG_READBACK_INDEX 0xd6 +#define mmVGA_DEBUG_READBACK_DATA 0xd7 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 +#define mmVGA_MEM_READ_PAGE_ADDR 0x13 +#define mmVGA_TEST_DEBUG_INDEX 0xc5 +#define mmVGA_TEST_DEBUG_DATA 0xc7 +#define ixVGADCC_DBG_DCCIF_C 0x7e +#define mmBPHYC_DAC_MACRO_CNTL 0x48b9 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba +#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 +#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 +#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 +#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 +#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 +#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 +#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 +#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 +#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 +#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 +#define mmDPG_PIPE_DPM_CONTROL 0x1b34 +#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 +#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 +#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 +#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 +#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 +#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 +#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 +#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 +#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 +#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 +#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 +#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 +#define mmDPG_REPEATER_PROGRAM 0x1b3a +#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a +#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a +#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a +#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a +#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a +#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a +#define mmDPG_HW_DEBUG_A 0x1b3b +#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b +#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b +#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b +#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b +#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b +#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b +#define mmDPG_HW_DEBUG_B 0x1b3c +#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c +#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c +#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c +#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c +#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c +#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c +#define mmDPG_HW_DEBUG_11 0x1b3d +#define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d +#define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d +#define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d +#define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d +#define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d +#define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d +#define mmDPG_CHK_PRE_PROC_CNTL 0x1b3e +#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e +#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e +#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e +#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e +#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e +#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e +#define mmDPG_DVMM_STATUS 0x1b3f +#define mmDMIF_PG0_DPG_DVMM_STATUS 0x1b3f +#define mmDMIF_PG1_DPG_DVMM_STATUS 0x1d3f +#define mmDMIF_PG2_DPG_DVMM_STATUS 0x1f3f +#define mmDMIF_PG3_DPG_DVMM_STATUS 0x413f +#define mmDMIF_PG4_DPG_DVMM_STATUS 0x433f +#define mmDMIF_PG5_DPG_DVMM_STATUS 0x453f +#define mmDPG_TEST_DEBUG_INDEX 0x1b38 +#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 +#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 +#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 +#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 +#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 +#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 +#define mmDPG_TEST_DEBUG_DATA 0x1b39 +#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 +#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 +#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 +#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 +#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 +#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 +#define mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x9930 +#define mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d +#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x473d +#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x993d +#define mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x9931 +#define mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e +#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x473e +#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x993e +#define mmDPGV0_WATERMARK_MASK_CONTROL 0x4732 +#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x4732 +#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x9932 +#define mmDPGV1_WATERMARK_MASK_CONTROL 0x473f +#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x473f +#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x993f +#define mmDPGV0_PIPE_URGENCY_CONTROL 0x4733 +#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x4733 +#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x9933 +#define mmDPGV1_PIPE_URGENCY_CONTROL 0x4740 +#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x4740 +#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x9940 +#define mmDPGV0_PIPE_DPM_CONTROL 0x4734 +#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x4734 +#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x9934 +#define mmDPGV1_PIPE_DPM_CONTROL 0x4741 +#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x4741 +#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x9941 +#define mmDPGV0_PIPE_STUTTER_CONTROL 0x4735 +#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x4735 +#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x9935 +#define mmDPGV1_PIPE_STUTTER_CONTROL 0x4742 +#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x4742 +#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x9942 +#define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x9936 +#define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 +#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 +#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x9943 +#define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x9937 +#define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 +#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 +#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x9944 +#define mmDPGV0_REPEATER_PROGRAM 0x4738 +#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x4738 +#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x9938 +#define mmDPGV1_REPEATER_PROGRAM 0x4745 +#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x4745 +#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x9945 +#define mmDPGV0_HW_DEBUG_A 0x4739 +#define mmDMIFV_PG0_DPGV0_HW_DEBUG_A 0x4739 +#define mmDMIFV_PG1_DPGV0_HW_DEBUG_A 0x9939 +#define mmDPGV1_HW_DEBUG_A 0x4746 +#define mmDMIFV_PG0_DPGV1_HW_DEBUG_A 0x4746 +#define mmDMIFV_PG1_DPGV1_HW_DEBUG_A 0x9946 +#define mmDPGV0_HW_DEBUG_B 0x473a +#define mmDMIFV_PG0_DPGV0_HW_DEBUG_B 0x473a +#define mmDMIFV_PG1_DPGV0_HW_DEBUG_B 0x993a +#define mmDPGV1_HW_DEBUG_B 0x4747 +#define mmDMIFV_PG0_DPGV1_HW_DEBUG_B 0x4747 +#define mmDMIFV_PG1_DPGV1_HW_DEBUG_B 0x9947 +#define mmDPGV0_HW_DEBUG_11 0x473b +#define mmDMIFV_PG0_DPGV0_HW_DEBUG_11 0x473b +#define mmDMIFV_PG1_DPGV0_HW_DEBUG_11 0x993b +#define mmDPGV1_HW_DEBUG_11 0x4748 +#define mmDMIFV_PG0_DPGV1_HW_DEBUG_11 0x4748 +#define mmDMIFV_PG1_DPGV1_HW_DEBUG_11 0x9948 +#define mmDPGV0_CHK_PRE_PROC_CNTL 0x473c +#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x473c +#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x993c +#define mmDPGV1_CHK_PRE_PROC_CNTL 0x4749 +#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x4749 +#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x9949 +#define mmDPGV_TEST_DEBUG_INDEX 0x474e +#define mmDMIFV_PG0_DPGV_TEST_DEBUG_INDEX 0x474e +#define mmDMIFV_PG1_DPGV_TEST_DEBUG_INDEX 0x994e +#define mmDPGV_TEST_DEBUG_DATA 0x474f +#define mmDMIFV_PG0_DPGV_TEST_DEBUG_DATA 0x474f +#define mmDMIFV_PG1_DPGV_TEST_DEBUG_DATA 0x994f +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 +#define mmAZALIA_F0_CODEC_DEBUG 0x1836 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a +#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b +#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c +#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d +#define mmGLOBAL_CAPABILITIES 0x0 +#define mmMINOR_VERSION 0x0 +#define mmMAJOR_VERSION 0x0 +#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 +#define mmINPUT_PAYLOAD_CAPABILITY 0x1 +#define mmGLOBAL_CONTROL 0x2 +#define mmWAKE_ENABLE 0x3 +#define mmSTATE_CHANGE_STATUS 0x3 +#define mmGLOBAL_STATUS 0x4 +#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define mmINTERRUPT_CONTROL 0x8 +#define mmINTERRUPT_STATUS 0x9 +#define mmWALL_CLOCK_COUNTER 0xc +#define mmSTREAM_SYNCHRONIZATION 0xe +#define mmCORB_LOWER_BASE_ADDRESS 0x10 +#define mmCORB_UPPER_BASE_ADDRESS 0x11 +#define mmCORB_WRITE_POINTER 0x12 +#define mmCORB_READ_POINTER 0x12 +#define mmCORB_CONTROL 0x13 +#define mmCORB_STATUS 0x13 +#define mmCORB_SIZE 0x13 +#define mmRIRB_LOWER_BASE_ADDRESS 0x14 +#define mmRIRB_UPPER_BASE_ADDRESS 0x15 +#define mmRIRB_WRITE_POINTER 0x16 +#define mmRESPONSE_INTERRUPT_COUNT 0x16 +#define mmRIRB_CONTROL 0x17 +#define mmRIRB_STATUS 0x17 +#define mmRIRB_SIZE 0x17 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 +#define mmIMMEDIATE_COMMAND_STATUS 0x1a +#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c +#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d +#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c +#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 +#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 +#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 +#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 +#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 +#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 +#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 +#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 +#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAUDIO_DESCRIPTOR0 0x1 +#define ixAUDIO_DESCRIPTOR1 0x2 +#define ixAUDIO_DESCRIPTOR2 0x3 +#define ixAUDIO_DESCRIPTOR3 0x4 +#define ixAUDIO_DESCRIPTOR4 0x5 +#define ixAUDIO_DESCRIPTOR5 0x6 +#define ixAUDIO_DESCRIPTOR6 0x7 +#define ixAUDIO_DESCRIPTOR7 0x8 +#define ixAUDIO_DESCRIPTOR8 0x9 +#define ixAUDIO_DESCRIPTOR9 0xa +#define ixAUDIO_DESCRIPTOR10 0xb +#define ixAUDIO_DESCRIPTOR11 0xc +#define ixAUDIO_DESCRIPTOR12 0xd +#define ixAUDIO_DESCRIPTOR13 0xe +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 +#define ixSINK_DESCRIPTION0 0x5 +#define ixSINK_DESCRIPTION1 0x6 +#define ixSINK_DESCRIPTION2 0x7 +#define ixSINK_DESCRIPTION3 0x8 +#define ixSINK_DESCRIPTION4 0x9 +#define ixSINK_DESCRIPTION5 0xa +#define ixSINK_DESCRIPTION6 0xb +#define ixSINK_DESCRIPTION7 0xc +#define ixSINK_DESCRIPTION8 0xd +#define ixSINK_DESCRIPTION9 0xe +#define ixSINK_DESCRIPTION10 0xf +#define ixSINK_DESCRIPTION11 0x10 +#define ixSINK_DESCRIPTION12 0x11 +#define ixSINK_DESCRIPTION13 0x12 +#define ixSINK_DESCRIPTION14 0x13 +#define ixSINK_DESCRIPTION15 0x14 +#define ixSINK_DESCRIPTION16 0x15 +#define ixSINK_DESCRIPTION17 0x16 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 +#define mmAZALIA_AUDIO_DTO 0x17e5 +#define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 +#define mmAZALIA_SCLK_CONTROL 0x17e7 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 +#define mmAZALIA_DATA_DMA_CONTROL 0x17e9 +#define mmAZALIA_BDL_DMA_CONTROL 0x17ea +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb +#define mmAZALIA_CORB_DMA_CONTROL 0x17ec +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 +#define mmAZALIA_CONTROLLER_DEBUG 0x17f9 +#define mmAZALIA_MEM_PWR_CTRL 0x1810 +#define mmAZALIA_MEM_PWR_STATUS 0x1811 +#define mmDCI_PG_DEBUG_CONFIG 0x1812 +#define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb +#define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc +#define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd +#define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe +#define mmAZALIA_INPUT_CRC0_RESULT 0x17ff +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 +#define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 +#define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 +#define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 +#define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 +#define mmAZALIA_INPUT_CRC1_RESULT 0x1804 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 +#define mmAZALIA_CRC0_CONTROL0 0x1805 +#define mmAZALIA_CRC0_CONTROL1 0x1806 +#define mmAZALIA_CRC0_CONTROL2 0x1807 +#define mmAZALIA_CRC0_CONTROL3 0x1808 +#define mmAZALIA_CRC0_RESULT 0x1809 +#define ixAZALIA_CRC0_CHANNEL0 0x0 +#define ixAZALIA_CRC0_CHANNEL1 0x1 +#define ixAZALIA_CRC0_CHANNEL2 0x2 +#define ixAZALIA_CRC0_CHANNEL3 0x3 +#define ixAZALIA_CRC0_CHANNEL4 0x4 +#define ixAZALIA_CRC0_CHANNEL5 0x5 +#define ixAZALIA_CRC0_CHANNEL6 0x6 +#define ixAZALIA_CRC0_CHANNEL7 0x7 +#define mmAZALIA_CRC1_CONTROL0 0x180a +#define mmAZALIA_CRC1_CONTROL1 0x180b +#define mmAZALIA_CRC1_CONTROL2 0x180c +#define mmAZALIA_CRC1_CONTROL3 0x180d +#define mmAZALIA_CRC1_RESULT 0x180e +#define ixAZALIA_CRC1_CHANNEL0 0x0 +#define ixAZALIA_CRC1_CHANNEL1 0x1 +#define ixAZALIA_CRC1_CHANNEL2 0x2 +#define ixAZALIA_CRC1_CHANNEL3 0x3 +#define ixAZALIA_CRC1_CHANNEL4 0x4 +#define ixAZALIA_CRC1_CHANNEL5 0x5 +#define ixAZALIA_CRC1_CHANNEL6 0x6 +#define ixAZALIA_CRC1_CHANNEL7 0x7 +#define mmAZ_TEST_DEBUG_INDEX 0x181f +#define mmAZ_TEST_DEBUG_DATA 0x1820 +#define mmAZALIA_STREAM_INDEX 0x1780 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce +#define mmAZALIA_STREAM_DATA 0x1781 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b +#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d +#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f +#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb +#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd +#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf +#define ixAZALIA_FIFO_SIZE_CONTROL 0x0 +#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 +#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 +#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 +#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 +#define ixAZALIA_STREAM_DEBUG 0x5 +#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 +#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 +#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 +#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a +#define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b +#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c +#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d +#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e +#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 +#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define mmBLND_CONTROL 0x1b6d +#define mmBLND0_BLND_CONTROL 0x1b6d +#define mmBLND1_BLND_CONTROL 0x1d6d +#define mmBLND2_BLND_CONTROL 0x1f6d +#define mmBLND3_BLND_CONTROL 0x416d +#define mmBLND4_BLND_CONTROL 0x436d +#define mmBLND5_BLND_CONTROL 0x456d +#define mmBLND_SM_CONTROL2 0x1b6e +#define mmBLND0_BLND_SM_CONTROL2 0x1b6e +#define mmBLND1_BLND_SM_CONTROL2 0x1d6e +#define mmBLND2_BLND_SM_CONTROL2 0x1f6e +#define mmBLND3_BLND_SM_CONTROL2 0x416e +#define mmBLND4_BLND_SM_CONTROL2 0x436e +#define mmBLND5_BLND_SM_CONTROL2 0x456e +#define mmBLND_CONTROL2 0x1b6f +#define mmBLND0_BLND_CONTROL2 0x1b6f +#define mmBLND1_BLND_CONTROL2 0x1d6f +#define mmBLND2_BLND_CONTROL2 0x1f6f +#define mmBLND3_BLND_CONTROL2 0x416f +#define mmBLND4_BLND_CONTROL2 0x436f +#define mmBLND5_BLND_CONTROL2 0x456f +#define mmBLND_UPDATE 0x1b70 +#define mmBLND0_BLND_UPDATE 0x1b70 +#define mmBLND1_BLND_UPDATE 0x1d70 +#define mmBLND2_BLND_UPDATE 0x1f70 +#define mmBLND3_BLND_UPDATE 0x4170 +#define mmBLND4_BLND_UPDATE 0x4370 +#define mmBLND5_BLND_UPDATE 0x4570 +#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 +#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 +#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 +#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 +#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 +#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 +#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 +#define mmBLND_V_UPDATE_LOCK 0x1b73 +#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 +#define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 +#define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 +#define mmBLND3_BLND_V_UPDATE_LOCK 0x4173 +#define mmBLND4_BLND_V_UPDATE_LOCK 0x4373 +#define mmBLND5_BLND_V_UPDATE_LOCK 0x4573 +#define mmBLND_REG_UPDATE_STATUS 0x1b77 +#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 +#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 +#define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 +#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 +#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 +#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 +#define mmBLND_DEBUG 0x1b74 +#define mmBLND0_BLND_DEBUG 0x1b74 +#define mmBLND1_BLND_DEBUG 0x1d74 +#define mmBLND2_BLND_DEBUG 0x1f74 +#define mmBLND3_BLND_DEBUG 0x4174 +#define mmBLND4_BLND_DEBUG 0x4374 +#define mmBLND5_BLND_DEBUG 0x4574 +#define mmBLND_TEST_DEBUG_INDEX 0x1b75 +#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 +#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 +#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 +#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 +#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 +#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 +#define mmBLND_TEST_DEBUG_DATA 0x1b76 +#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 +#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 +#define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 +#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 +#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 +#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 +#define mmWB_ENABLE 0x5e18 +#define mmWB_EC_CONFIG 0x5e19 +#define mmCNV_MODE 0x5e1a +#define mmCNV_WINDOW_START 0x5e1b +#define mmCNV_WINDOW_SIZE 0x5e1c +#define mmCNV_UPDATE 0x5e1d +#define mmCNV_SOURCE_SIZE 0x5e1e +#define mmCNV_CSC_CONTROL 0x5e1f +#define mmCNV_CSC_C11_C12 0x5e20 +#define mmCNV_CSC_C13_C14 0x5e21 +#define mmCNV_CSC_C21_C22 0x5e22 +#define mmCNV_CSC_C23_C24 0x5e23 +#define mmCNV_CSC_C31_C32 0x5e24 +#define mmCNV_CSC_C33_C34 0x5e25 +#define mmCNV_CSC_ROUND_OFFSET_R 0x5e26 +#define mmCNV_CSC_ROUND_OFFSET_G 0x5e27 +#define mmCNV_CSC_ROUND_OFFSET_B 0x5e28 +#define mmCNV_CSC_CLAMP_R 0x5e29 +#define mmCNV_CSC_CLAMP_G 0x5e2a +#define mmCNV_CSC_CLAMP_B 0x5e2b +#define mmCNV_TEST_CNTL 0x5e2c +#define mmCNV_TEST_CRC_RED 0x5e2d +#define mmCNV_TEST_CRC_GREEN 0x5e2e +#define mmCNV_TEST_CRC_BLUE 0x5e2f +#define mmWB_DEBUG_CTRL 0x5e30 +#define mmWB_DBG_MODE 0x5e31 +#define mmWB_HW_DEBUG 0x5e32 +#define mmCNV_INPUT_SELECT 0x5e33 +#define mmWB_SOFT_RESET 0x5e36 +#define mmWB_WARM_UP_MODE_CTL1 0x5e37 +#define mmWB_WARM_UP_MODE_CTL2 0x5e38 +#define mmCNV_TEST_DEBUG_INDEX 0x5e34 +#define mmCNV_TEST_DEBUG_DATA 0x5e35 +#define mmDCFE_CLOCK_CONTROL 0x1b00 +#define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 +#define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 +#define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 +#define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 +#define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 +#define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 +#define mmDCFE_SOFT_RESET 0x1b01 +#define mmDCFE0_DCFE_SOFT_RESET 0x1b01 +#define mmDCFE1_DCFE_SOFT_RESET 0x1d01 +#define mmDCFE2_DCFE_SOFT_RESET 0x1f01 +#define mmDCFE3_DCFE_SOFT_RESET 0x4101 +#define mmDCFE4_DCFE_SOFT_RESET 0x4301 +#define mmDCFE5_DCFE_SOFT_RESET 0x4501 +#define mmDCFE_DBG_CONFIG 0x1b02 +#define mmDCFE0_DCFE_DBG_CONFIG 0x1b02 +#define mmDCFE1_DCFE_DBG_CONFIG 0x1d02 +#define mmDCFE2_DCFE_DBG_CONFIG 0x1f02 +#define mmDCFE3_DCFE_DBG_CONFIG 0x4102 +#define mmDCFE4_DCFE_DBG_CONFIG 0x4302 +#define mmDCFE5_DCFE_DBG_CONFIG 0x4502 +#define mmDCFE_MEM_PWR_CTRL 0x1b03 +#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03 +#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03 +#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03 +#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103 +#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303 +#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503 +#define mmDCFE_MEM_PWR_CTRL2 0x1b04 +#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04 +#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04 +#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04 +#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104 +#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304 +#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504 +#define mmDCFE_MEM_PWR_STATUS 0x1b05 +#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05 +#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05 +#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05 +#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105 +#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305 +#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505 +#define mmDCFE_MISC 0x1b06 +#define mmDCFE0_DCFE_MISC 0x1b06 +#define mmDCFE1_DCFE_MISC 0x1d06 +#define mmDCFE2_DCFE_MISC 0x1f06 +#define mmDCFE3_DCFE_MISC 0x4106 +#define mmDCFE4_DCFE_MISC 0x4306 +#define mmDCFE5_DCFE_MISC 0x4506 +#define mmDCFE_FLUSH 0x1b07 +#define mmDCFE0_DCFE_FLUSH 0x1b07 +#define mmDCFE1_DCFE_FLUSH 0x1d07 +#define mmDCFE2_DCFE_FLUSH 0x1f07 +#define mmDCFE3_DCFE_FLUSH 0x4107 +#define mmDCFE4_DCFE_FLUSH 0x4307 +#define mmDCFE5_DCFE_FLUSH 0x4507 +#define mmDCFEV_CLOCK_CONTROL 0x46f4 +#define mmDCFEV0_DCFEV_CLOCK_CONTROL 0x46f4 +#define mmDCFEV1_DCFEV_CLOCK_CONTROL 0x98f4 +#define mmDCFEV_SOFT_RESET 0x46f5 +#define mmDCFEV0_DCFEV_SOFT_RESET 0x46f5 +#define mmDCFEV1_DCFEV_SOFT_RESET 0x98f5 +#define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 +#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x46f6 +#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x98f6 +#define mmDCFEV_DBG_CONFIG 0x46f7 +#define mmDCFEV0_DCFEV_DBG_CONFIG 0x46f7 +#define mmDCFEV1_DCFEV_DBG_CONFIG 0x98f7 +#define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 +#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 +#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x98f8 +#define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 +#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 +#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x98f9 +#define mmDCFEV_MEM_PWR_CTRL 0x46fa +#define mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x46fa +#define mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x98fa +#define mmDCFEV_MEM_PWR_CTRL2 0x46fb +#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x46fb +#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x98fb +#define mmDCFEV_MEM_PWR_STATUS 0x46fc +#define mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x46fc +#define mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x98fc +#define mmDCFEV_L_FLUSH 0x46ff +#define mmDCFEV0_DCFEV_L_FLUSH 0x46ff +#define mmDCFEV1_DCFEV_L_FLUSH 0x98ff +#define mmDCFEV_C_FLUSH 0x4700 +#define mmDCFEV0_DCFEV_C_FLUSH 0x4700 +#define mmDCFEV1_DCFEV_C_FLUSH 0x9900 +#define mmDCFEV_DMIFV_DEBUG 0x46fd +#define mmDCFEV0_DCFEV_DMIFV_DEBUG 0x46fd +#define mmDCFEV1_DCFEV_DMIFV_DEBUG 0x98fd +#define mmDCFEV_MISC 0x46fe +#define mmDCFEV0_DCFEV_MISC 0x46fe +#define mmDCFEV1_DCFEV_MISC 0x98fe +#define mmDC_HPD_INT_STATUS 0x1898 +#define mmHPD0_DC_HPD_INT_STATUS 0x1898 +#define mmHPD1_DC_HPD_INT_STATUS 0x18a0 +#define mmHPD2_DC_HPD_INT_STATUS 0x18a8 +#define mmHPD3_DC_HPD_INT_STATUS 0x18b0 +#define mmHPD4_DC_HPD_INT_STATUS 0x18b8 +#define mmHPD5_DC_HPD_INT_STATUS 0x18c0 +#define mmDC_HPD_INT_CONTROL 0x1899 +#define mmHPD0_DC_HPD_INT_CONTROL 0x1899 +#define mmHPD1_DC_HPD_INT_CONTROL 0x18a1 +#define mmHPD2_DC_HPD_INT_CONTROL 0x18a9 +#define mmHPD3_DC_HPD_INT_CONTROL 0x18b1 +#define mmHPD4_DC_HPD_INT_CONTROL 0x18b9 +#define mmHPD5_DC_HPD_INT_CONTROL 0x18c1 +#define mmDC_HPD_CONTROL 0x189a +#define mmHPD0_DC_HPD_CONTROL 0x189a +#define mmHPD1_DC_HPD_CONTROL 0x18a2 +#define mmHPD2_DC_HPD_CONTROL 0x18aa +#define mmHPD3_DC_HPD_CONTROL 0x18b2 +#define mmHPD4_DC_HPD_CONTROL 0x18ba +#define mmHPD5_DC_HPD_CONTROL 0x18c2 +#define mmDC_HPD_FAST_TRAIN_CNTL 0x189b +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 +#define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 +#define mmDCO_SCRATCH0 0x184e +#define mmDCO_SCRATCH1 0x184f +#define mmDCO_SCRATCH2 0x1850 +#define mmDCO_SCRATCH3 0x1851 +#define mmDCO_SCRATCH4 0x1852 +#define mmDCO_SCRATCH5 0x1853 +#define mmDCO_SCRATCH6 0x1854 +#define mmDCO_SCRATCH7 0x1855 +#define mmDCE_VCE_CONTROL 0x1856 +#define mmDISP_INTERRUPT_STATUS 0x1857 +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c +#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d +#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e +#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f +#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875 +#define mmDCO_MEM_PWR_STATUS 0x1861 +#define mmDCO_MEM_PWR_STATUS1 0x1874 +#define mmDCO_MEM_PWR_CTRL 0x1862 +#define mmDCO_MEM_PWR_CTRL2 0x1863 +#define mmFMT_MEMORY0_CONTROL 0x1888 +#define mmFMT_MEMORY1_CONTROL 0x1889 +#define mmFMT_MEMORY2_CONTROL 0x188a +#define mmFMT_MEMORY3_CONTROL 0x188b +#define mmFMT_MEMORY4_CONTROL 0x188c +#define mmFMT_MEMORY5_CONTROL 0x188d +#define mmDCO_CLK_CNTL 0x1864 +#define mmDCO_CLK_CNTL2 0x1876 +#define mmDCO_CLK_CNTL3 0x1877 +#define mmDPDBG_CNTL 0x1866 +#define mmDPDBG_INTERRUPT 0x1867 +#define mmDCO_POWER_MANAGEMENT_CNTL 0x1868 +#define mmDCO_SOFT_RESET 0x1871 +#define mmDIG_SOFT_RESET 0x1872 +#define mmDIG_SOFT_RESET_2 0x186a +#define mmDCO_STEREOSYNC_SEL 0x186e +#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x1883 +#define mmDCO_PSP_INTERRUPT_STATUS 0x1884 +#define mmDCO_PSP_INTERRUPT_CLEAR 0x1885 +#define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x1886 +#define mmDCO_GENERIC_INTERRUPT_CLEAR 0x1887 +#define mmDCO_TEST_DEBUG_INDEX 0x186f +#define mmDCO_TEST_DEBUG_DATA 0x1870 +#define mmDC_I2C_CONTROL 0x16d4 +#define mmDC_I2C_ARBITRATION 0x16d5 +#define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 +#define mmDC_I2C_SW_STATUS 0x16d7 +#define mmDC_I2C_DDC1_HW_STATUS 0x16d8 +#define mmDC_I2C_DDC2_HW_STATUS 0x16d9 +#define mmDC_I2C_DDC3_HW_STATUS 0x16da +#define mmDC_I2C_DDC4_HW_STATUS 0x16db +#define mmDC_I2C_DDC5_HW_STATUS 0x16dc +#define mmDC_I2C_DDC6_HW_STATUS 0x16dd +#define mmDC_I2C_DDC1_SPEED 0x16de +#define mmDC_I2C_DDC1_SETUP 0x16df +#define mmDC_I2C_DDC2_SPEED 0x16e0 +#define mmDC_I2C_DDC2_SETUP 0x16e1 +#define mmDC_I2C_DDC3_SPEED 0x16e2 +#define mmDC_I2C_DDC3_SETUP 0x16e3 +#define mmDC_I2C_DDC4_SPEED 0x16e4 +#define mmDC_I2C_DDC4_SETUP 0x16e5 +#define mmDC_I2C_DDC5_SPEED 0x16e6 +#define mmDC_I2C_DDC5_SETUP 0x16e7 +#define mmDC_I2C_DDC6_SPEED 0x16e8 +#define mmDC_I2C_DDC6_SETUP 0x16e9 +#define mmDC_I2C_TRANSACTION0 0x16ea +#define mmDC_I2C_TRANSACTION1 0x16eb +#define mmDC_I2C_TRANSACTION2 0x16ec +#define mmDC_I2C_TRANSACTION3 0x16ed +#define mmDC_I2C_DATA 0x16ee +#define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef +#define mmDC_I2C_DDCVGA_SPEED 0x16f0 +#define mmDC_I2C_DDCVGA_SETUP 0x16f1 +#define mmDC_I2C_EDID_DETECT_CTRL 0x16f2 +#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 +#define mmGENERIC_I2C_CONTROL 0x16f4 +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 +#define mmGENERIC_I2C_STATUS 0x16f6 +#define mmGENERIC_I2C_SPEED 0x16f7 +#define mmGENERIC_I2C_SETUP 0x16f8 +#define mmGENERIC_I2C_TRANSACTION 0x16f9 +#define mmGENERIC_I2C_DATA 0x16fa +#define mmGENERIC_I2C_PIN_SELECTION 0x16fb +#define mmGENERIC_I2C_PIN_DEBUG 0x16fc +#define mmBLNDV_CONTROL 0x476d +#define mmBLNDV0_BLNDV_CONTROL 0x476d +#define mmBLNDV1_BLNDV_CONTROL 0x996d +#define mmBLNDV_SM_CONTROL2 0x476e +#define mmBLNDV0_BLNDV_SM_CONTROL2 0x476e +#define mmBLNDV1_BLNDV_SM_CONTROL2 0x996e +#define mmBLNDV_CONTROL2 0x476f +#define mmBLNDV0_BLNDV_CONTROL2 0x476f +#define mmBLNDV1_BLNDV_CONTROL2 0x996f +#define mmBLNDV_UPDATE 0x4770 +#define mmBLNDV0_BLNDV_UPDATE 0x4770 +#define mmBLNDV1_BLNDV_UPDATE 0x9970 +#define mmBLNDV_UNDERFLOW_INTERRUPT 0x4771 +#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x4771 +#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x9971 +#define mmBLNDV_V_UPDATE_LOCK 0x4773 +#define mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x4773 +#define mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x9973 +#define mmBLNDV_REG_UPDATE_STATUS 0x4777 +#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x4777 +#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x9977 +#define mmBLNDV_DEBUG 0x4774 +#define mmBLNDV0_BLNDV_DEBUG 0x4774 +#define mmBLNDV1_BLNDV_DEBUG 0x9974 +#define mmBLNDV_TEST_DEBUG_INDEX 0x4775 +#define mmBLNDV0_BLNDV_TEST_DEBUG_INDEX 0x4775 +#define mmBLNDV1_BLNDV_TEST_DEBUG_INDEX 0x9975 +#define mmBLNDV_TEST_DEBUG_DATA 0x4776 +#define mmBLNDV0_BLNDV_TEST_DEBUG_DATA 0x4776 +#define mmBLNDV1_BLNDV_TEST_DEBUG_DATA 0x9976 +#define mmCRTCV_H_TOTAL 0x4780 +#define mmCRTCV0_CRTCV_H_TOTAL 0x4780 +#define mmCRTCV1_CRTCV_H_TOTAL 0x9980 +#define mmCRTCV_H_BLANK_START_END 0x4781 +#define mmCRTCV0_CRTCV_H_BLANK_START_END 0x4781 +#define mmCRTCV1_CRTCV_H_BLANK_START_END 0x9981 +#define mmCRTCV_H_SYNC_A 0x4782 +#define mmCRTCV0_CRTCV_H_SYNC_A 0x4782 +#define mmCRTCV1_CRTCV_H_SYNC_A 0x9982 +#define mmCRTCV_V_TOTAL 0x4787 +#define mmCRTCV0_CRTCV_V_TOTAL 0x4787 +#define mmCRTCV1_CRTCV_V_TOTAL 0x9987 +#define mmCRTCV_V_BLANK_START_END 0x478d +#define mmCRTCV0_CRTCV_V_BLANK_START_END 0x478d +#define mmCRTCV1_CRTCV_V_BLANK_START_END 0x998d +#define mmCRTCV_V_SYNC_A 0x478e +#define mmCRTCV0_CRTCV_V_SYNC_A 0x478e +#define mmCRTCV1_CRTCV_V_SYNC_A 0x998e +#define mmCRTCV_CONTROL 0x479c +#define mmCRTCV0_CRTCV_CONTROL 0x479c +#define mmCRTCV1_CRTCV_CONTROL 0x999c +#define mmCRTCV_START_LINE_CONTROL 0x47b3 +#define mmCRTCV0_CRTCV_START_LINE_CONTROL 0x47b3 +#define mmCRTCV1_CRTCV_START_LINE_CONTROL 0x99b3 +#define mmCRTCV_OVERSCAN_COLOR 0x47c8 +#define mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x47c8 +#define mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x99c8 +#define mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9 +#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x47c9 +#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x99c9 +#define mmCRTCV_BLACK_COLOR 0x47cc +#define mmCRTCV0_CRTCV_BLACK_COLOR 0x47cc +#define mmCRTCV1_CRTCV_BLACK_COLOR 0x99cc +#define mmCRTCV_BLACK_COLOR_EXT 0x47cd +#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x47cd +#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x99cd +#define mmCRTCV_CRC_CNTL 0x47d4 +#define mmCRTCV0_CRTCV_CRC_CNTL 0x47d4 +#define mmCRTCV1_CRTCV_CRC_CNTL 0x99d4 +#define mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 +#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 +#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x99d5 +#define mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 +#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 +#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x99d6 +#define mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 +#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 +#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x99d7 +#define mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 +#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 +#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x99d8 +#define mmCRTCV_CRC0_DATA_RG 0x47d9 +#define mmCRTCV0_CRTCV_CRC0_DATA_RG 0x47d9 +#define mmCRTCV1_CRTCV_CRC0_DATA_RG 0x99d9 +#define mmCRTCV_CRC0_DATA_B 0x47da +#define mmCRTCV0_CRTCV_CRC0_DATA_B 0x47da +#define mmCRTCV1_CRTCV_CRC0_DATA_B 0x99da +#define mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db +#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x47db +#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x99db +#define mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc +#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc +#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x99dc +#define mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd +#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd +#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x99dd +#define mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de +#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de +#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x99de +#define mmCRTCV_CRC1_DATA_RG 0x47df +#define mmCRTCV0_CRTCV_CRC1_DATA_RG 0x47df +#define mmCRTCV1_CRTCV_CRC1_DATA_RG 0x99df +#define mmCRTCV_CRC1_DATA_B 0x47e0 +#define mmCRTCV0_CRTCV_CRC1_DATA_B 0x47e0 +#define mmCRTCV1_CRTCV_CRC1_DATA_B 0x99e0 +#define mmCRTCV_TEST_DEBUG_INDEX 0x47c6 +#define mmCRTCV0_CRTCV_TEST_DEBUG_INDEX 0x47c6 +#define mmCRTCV1_CRTCV_TEST_DEBUG_INDEX 0x99c6 +#define mmCRTCV_TEST_DEBUG_DATA 0x47c7 +#define mmCRTCV0_CRTCV_TEST_DEBUG_DATA 0x47c7 +#define mmCRTCV1_CRTCV_TEST_DEBUG_DATA 0x99c7 +#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 +#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 +#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 +#define mmXDMA_INTERRUPT 0x3e3 +#define mmXDMA_CLOCK_GATING_CNTL 0x3e4 +#define mmXDMA_MEM_POWER_CNTL 0x3e6 +#define mmXDMA_IF_BIF_STATUS 0x3e7 +#define mmXDMA_PERF_MEAS_STATUS 0x3e8 +#define mmXDMA_IF_STATUS 0x3e9 +#define mmXDMA_TEST_DEBUG_INDEX 0x3ea +#define mmXDMA_TEST_DEBUG_DATA 0x3eb +#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 +#define mmXDMA_PG_CONTROL 0x3f9 +#define mmXDMA_PG_WDATA 0x3fa +#define mmXDMA_PG_STATUS 0x3fb +#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc +#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd +#define mmXDMA_MSTR_CNTL 0x3ec +#define mmXDMA_MSTR_STATUS 0x3ed +#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 +#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 +#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 +#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 +#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 +#define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 +#define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 +#define mmXDMA_MSTR_PIPE_CNTL 0x400 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 +#define mmXDMA_MSTR_READ_COMMAND 0x401 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 +#define mmXDMA_MSTR_CHANNEL_DIM 0x402 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 +#define mmXDMA_MSTR_HEIGHT 0x403 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 +#define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 +#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 +#define mmXDMA_MSTR_CACHE 0x40a +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a +#define mmXDMA_MSTR_CHANNEL_START 0x40b +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b +#define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e +#define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f +#define mmXDMA_SLV_CNTL 0x460 +#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 +#define mmXDMA_SLV_SLS_PITCH 0x462 +#define mmXDMA_SLV_READ_URGENT_CNTL 0x463 +#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 +#define mmXDMA_SLV_WB_RATE_CNTL 0x465 +#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 +#define mmXDMA_SLV_READ_LATENCY_AVE 0x467 +#define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 +#define mmXDMA_SLV_MEM_NACK_STATUS 0x469 +#define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a +#define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b +#define mmXDMA_SLV_FLIP_PENDING 0x46c +#define mmXDMA_SLV_CHANNEL_CNTL 0x470 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a +#define mmCMD_BUS_TX_CONTROL_LANE0 0x48e0 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x48e0 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x4980 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x9a20 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x9ac0 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x9b60 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x9c00 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0x9ca0 +#define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE0 0x9d40 +#define mmCMD_BUS_TX_CONTROL_LANE1 0x48f0 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x48f0 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x4990 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x9a30 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x9ad0 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x9b70 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x9c10 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0x9cb0 +#define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE1 0x9d50 +#define mmCMD_BUS_TX_CONTROL_LANE2 0x4900 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x4900 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x49a0 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x9a40 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x9ae0 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x9b80 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x9c20 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0x9cc0 +#define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE2 0x9d60 +#define mmCMD_BUS_TX_CONTROL_LANE3 0x4910 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x4910 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x49b0 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x9a50 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x9af0 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x9b90 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x9c30 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0x9cd0 +#define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE3 0x9d70 +#define mmMARGIN_DEEMPH_LANE0 0x48e1 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x48e1 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x4981 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x9a21 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x9ac1 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x9b61 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x9c01 +#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0x9ca1 +#define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE0 0x9d41 +#define mmMARGIN_DEEMPH_LANE1 0x48f1 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x48f1 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x4991 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x9a31 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x9ad1 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x9b71 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x9c11 +#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0x9cb1 +#define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE1 0x9d51 +#define mmMARGIN_DEEMPH_LANE2 0x4901 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x4901 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x49a1 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x9a41 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x9ae1 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x9b81 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x9c21 +#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0x9cc1 +#define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE2 0x9d61 +#define mmMARGIN_DEEMPH_LANE3 0x4911 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x4911 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x49b1 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x9a51 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x9af1 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x9b91 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x9c31 +#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0x9cd1 +#define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE3 0x9d71 +#define mmCMD_BUS_GLOBAL_FOR_TX_LANE0 0x48e2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x48e2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x4982 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9a22 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9ac2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9b62 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9c02 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9ca2 +#define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9d42 +#define mmCMD_BUS_GLOBAL_FOR_TX_LANE1 0x48f2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x48f2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x4992 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9a32 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9ad2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9b72 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9c12 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9cb2 +#define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9d52 +#define mmCMD_BUS_GLOBAL_FOR_TX_LANE2 0x4902 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x4902 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x49a2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9a42 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9ae2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9b82 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9c22 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9cc2 +#define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9d62 +#define mmCMD_BUS_GLOBAL_FOR_TX_LANE3 0x4912 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x4912 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x49b2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9a52 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9af2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9b92 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9c32 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9cd2 +#define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9d72 +#define mmTX_DISP_RFU0_LANE0 0x48e3 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x48e3 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x4983 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x9a23 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x9ac3 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x9b63 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x9c03 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0x9ca3 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE0 0x9d43 +#define mmTX_DISP_RFU0_LANE1 0x48f3 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x48f3 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x4993 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x9a33 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x9ad3 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x9b73 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x9c13 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0x9cb3 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE1 0x9d53 +#define mmTX_DISP_RFU0_LANE2 0x4903 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x4903 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x49a3 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x9a43 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x9ae3 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x9b83 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x9c23 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0x9cc3 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE2 0x9d63 +#define mmTX_DISP_RFU0_LANE3 0x4913 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x4913 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x49b3 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x9a53 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x9af3 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x9b93 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x9c33 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0x9cd3 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE3 0x9d73 +#define mmTX_DISP_RFU1_LANE0 0x48e4 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x48e4 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x4984 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x9a24 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x9ac4 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x9b64 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x9c04 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0x9ca4 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE0 0x9d44 +#define mmTX_DISP_RFU1_LANE1 0x48f4 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x48f4 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x4994 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x9a34 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x9ad4 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x9b74 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x9c14 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0x9cb4 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE1 0x9d54 +#define mmTX_DISP_RFU1_LANE2 0x4904 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x4904 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x49a4 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x9a44 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x9ae4 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x9b84 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x9c24 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0x9cc4 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE2 0x9d64 +#define mmTX_DISP_RFU1_LANE3 0x4914 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x4914 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x49b4 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x9a54 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x9af4 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x9b94 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x9c34 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0x9cd4 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE3 0x9d74 +#define mmTX_DISP_RFU2_LANE0 0x48e5 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x48e5 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x4985 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x9a25 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x9ac5 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x9b65 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x9c05 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0x9ca5 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE0 0x9d45 +#define mmTX_DISP_RFU2_LANE1 0x48f5 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x48f5 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x4995 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x9a35 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x9ad5 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x9b75 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x9c15 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0x9cb5 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE1 0x9d55 +#define mmTX_DISP_RFU2_LANE2 0x4905 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x4905 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x49a5 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x9a45 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x9ae5 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x9b85 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x9c25 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0x9cc5 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE2 0x9d65 +#define mmTX_DISP_RFU2_LANE3 0x4915 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x4915 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x49b5 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x9a55 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x9af5 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x9b95 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x9c35 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0x9cd5 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE3 0x9d75 +#define mmTX_DISP_RFU3_LANE0 0x48e6 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x48e6 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x4986 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x9a26 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x9ac6 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x9b66 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x9c06 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0x9ca6 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE0 0x9d46 +#define mmTX_DISP_RFU3_LANE1 0x48f6 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x48f6 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x4996 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x9a36 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x9ad6 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x9b76 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x9c16 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0x9cb6 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE1 0x9d56 +#define mmTX_DISP_RFU3_LANE2 0x4906 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x4906 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x49a6 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x9a46 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x9ae6 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x9b86 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x9c26 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0x9cc6 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE2 0x9d66 +#define mmTX_DISP_RFU3_LANE3 0x4916 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x4916 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x49b6 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x9a56 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x9af6 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x9b96 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x9c36 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0x9cd6 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE3 0x9d76 +#define mmTX_DISP_RFU4_LANE0 0x48e7 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x48e7 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x4987 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x9a27 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x9ac7 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x9b67 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x9c07 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0x9ca7 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE0 0x9d47 +#define mmTX_DISP_RFU4_LANE1 0x48f7 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x48f7 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x4997 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x9a37 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x9ad7 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x9b77 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x9c17 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0x9cb7 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE1 0x9d57 +#define mmTX_DISP_RFU4_LANE2 0x4907 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x4907 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x49a7 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x9a47 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x9ae7 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x9b87 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x9c27 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0x9cc7 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE2 0x9d67 +#define mmTX_DISP_RFU4_LANE3 0x4917 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x4917 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x49b7 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x9a57 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x9af7 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x9b97 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x9c37 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0x9cd7 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE3 0x9d77 +#define mmTX_DISP_RFU5_LANE0 0x48e8 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x48e8 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x4988 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x9a28 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x9ac8 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x9b68 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x9c08 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0x9ca8 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE0 0x9d48 +#define mmTX_DISP_RFU5_LANE1 0x48f8 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x48f8 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x4998 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x9a38 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x9ad8 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x9b78 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x9c18 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0x9cb8 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE1 0x9d58 +#define mmTX_DISP_RFU5_LANE2 0x4908 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x4908 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x49a8 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x9a48 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x9ae8 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x9b88 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x9c28 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0x9cc8 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE2 0x9d68 +#define mmTX_DISP_RFU5_LANE3 0x4918 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x4918 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x49b8 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x9a58 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x9af8 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x9b98 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x9c38 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0x9cd8 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE3 0x9d78 +#define mmTX_DISP_RFU6_LANE0 0x48e9 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x48e9 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x4989 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x9a29 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x9ac9 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x9b69 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x9c09 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0x9ca9 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE0 0x9d49 +#define mmTX_DISP_RFU6_LANE1 0x48f9 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x48f9 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x4999 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x9a39 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x9ad9 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x9b79 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x9c19 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0x9cb9 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE1 0x9d59 +#define mmTX_DISP_RFU6_LANE2 0x4909 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x4909 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x49a9 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x9a49 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x9ae9 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x9b89 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x9c29 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0x9cc9 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE2 0x9d69 +#define mmTX_DISP_RFU6_LANE3 0x4919 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x4919 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x49b9 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x9a59 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x9af9 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x9b99 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x9c39 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0x9cd9 +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE3 0x9d79 +#define mmTX_DISP_RFU7_LANE0 0x48ea +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x48ea +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x498a +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x9a2a +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x9aca +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x9b6a +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x9c0a +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0x9caa +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE0 0x9d4a +#define mmTX_DISP_RFU7_LANE1 0x48fa +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x48fa +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x499a +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x9a3a +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x9ada +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x9b7a +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x9c1a +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0x9cba +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE1 0x9d5a +#define mmTX_DISP_RFU7_LANE2 0x490a +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x490a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x49aa +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x9a4a +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x9aea +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x9b8a +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x9c2a +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0x9cca +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE2 0x9d6a +#define mmTX_DISP_RFU7_LANE3 0x491a +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x491a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x49ba +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x9a5a +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x9afa +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x9b9a +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x9c3a +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0x9cda +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE3 0x9d7a +#define mmTX_DISP_RFU8_LANE0 0x48eb +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x48eb +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x498b +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x9a2b +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x9acb +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x9b6b +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x9c0b +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0x9cab +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE0 0x9d4b +#define mmTX_DISP_RFU8_LANE1 0x48fb +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x48fb +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x499b +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x9a3b +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x9adb +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x9b7b +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x9c1b +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0x9cbb +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE1 0x9d5b +#define mmTX_DISP_RFU8_LANE2 0x490b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x490b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x49ab +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x9a4b +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x9aeb +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x9b8b +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x9c2b +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0x9ccb +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE2 0x9d6b +#define mmTX_DISP_RFU8_LANE3 0x491b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x491b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x49bb +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x9a5b +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x9afb +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x9b9b +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x9c3b +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0x9cdb +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE3 0x9d7b +#define mmTX_DISP_RFU9_LANE0 0x48ec +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x48ec +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x498c +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x9a2c +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x9acc +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x9b6c +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x9c0c +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0x9cac +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE0 0x9d4c +#define mmTX_DISP_RFU9_LANE1 0x48fc +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x48fc +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x499c +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x9a3c +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x9adc +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x9b7c +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x9c1c +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0x9cbc +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE1 0x9d5c +#define mmTX_DISP_RFU9_LANE2 0x490c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x490c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x49ac +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x9a4c +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x9aec +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x9b8c +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x9c2c +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0x9ccc +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE2 0x9d6c +#define mmTX_DISP_RFU9_LANE3 0x491c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x491c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x49bc +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x9a5c +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x9afc +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x9b9c +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x9c3c +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0x9cdc +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE3 0x9d7c +#define mmTX_DISP_RFU10_LANE0 0x48ed +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x48ed +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x498d +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x9a2d +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x9acd +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x9b6d +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x9c0d +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0x9cad +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE0 0x9d4d +#define mmTX_DISP_RFU10_LANE1 0x48fd +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x48fd +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x499d +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x9a3d +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x9add +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x9b7d +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x9c1d +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0x9cbd +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE1 0x9d5d +#define mmTX_DISP_RFU10_LANE2 0x490d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x490d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x49ad +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x9a4d +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x9aed +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x9b8d +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x9c2d +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0x9ccd +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE2 0x9d6d +#define mmTX_DISP_RFU10_LANE3 0x491d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x491d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x49bd +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x9a5d +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x9afd +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x9b9d +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x9c3d +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0x9cdd +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE3 0x9d7d +#define mmTX_DISP_RFU11_LANE0 0x48ee +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x48ee +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x498e +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x9a2e +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x9ace +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x9b6e +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x9c0e +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0x9cae +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE0 0x9d4e +#define mmTX_DISP_RFU11_LANE1 0x48fe +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x48fe +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x499e +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x9a3e +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x9ade +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x9b7e +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x9c1e +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0x9cbe +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE1 0x9d5e +#define mmTX_DISP_RFU11_LANE2 0x490e +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x490e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x49ae +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x9a4e +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x9aee +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x9b8e +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x9c2e +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0x9cce +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE2 0x9d6e +#define mmTX_DISP_RFU11_LANE3 0x491e +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x491e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x49be +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x9a5e +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x9afe +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x9b9e +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x9c3e +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0x9cde +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE3 0x9d7e +#define mmTX_DISP_RFU12_LANE0 0x48ef +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x48ef +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x498f +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x9a2f +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x9acf +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x9b6f +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x9c0f +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0x9caf +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE0 0x9d4f +#define mmTX_DISP_RFU12_LANE1 0x48ff +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x48ff +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x499f +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x9a3f +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x9adf +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x9b7f +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x9c1f +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0x9cbf +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE1 0x9d5f +#define mmTX_DISP_RFU12_LANE2 0x490f +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x490f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x49af +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x9a4f +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x9aef +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x9b8f +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x9c2f +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0x9ccf +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE2 0x9d6f +#define mmTX_DISP_RFU12_LANE3 0x491f +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x491f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x49bf +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x9a5f +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x9aff +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x9b9f +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x9c3f +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0x9cdf +#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE3 0x9d7f +#define mmCOMMON_MAR_DEEMPH_NOM 0x48c3 +#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x48c3 +#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x4963 +#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x9a03 +#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x9aa3 +#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x9b43 +#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x9be3 +#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0x9c83 +#define mmDC_COMBOPHYCMREGS7_COMMON_MAR_DEEMPH_NOM 0x9d23 +#define mmCOMMON_LANE_PWRMGMT 0x48c4 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x48c4 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x4964 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x9a04 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x9aa4 +#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x9b44 +#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x9be4 +#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0x9c84 +#define mmDC_COMBOPHYCMREGS7_COMMON_LANE_PWRMGMT 0x9d24 +#define mmCOMMON_TXCNTRL 0x48c5 +#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x48c5 +#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x4965 +#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x9a05 +#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x9aa5 +#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x9b45 +#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x9be5 +#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0x9c85 +#define mmDC_COMBOPHYCMREGS7_COMMON_TXCNTRL 0x9d25 +#define mmCOMMON_TMDP 0x48c6 +#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x48c6 +#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x4966 +#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x9a06 +#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x9aa6 +#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x9b46 +#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x9be6 +#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0x9c86 +#define mmDC_COMBOPHYCMREGS7_COMMON_TMDP 0x9d26 +#define mmCOMMON_LANE_RESETS 0x48c7 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x48c7 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x4967 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x9a07 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x9aa7 +#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x9b47 +#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x9be7 +#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0x9c87 +#define mmDC_COMBOPHYCMREGS7_COMMON_LANE_RESETS 0x9d27 +#define mmCOMMON_ZCALCODE_CTRL 0x48c8 +#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x48c8 +#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x4968 +#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x9a08 +#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x9aa8 +#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x9b48 +#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x9be8 +#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0x9c88 +#define mmDC_COMBOPHYCMREGS7_COMMON_ZCALCODE_CTRL 0x9d28 +#define mmCOMMON_DISP_RFU1 0x48c9 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x48c9 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x4969 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x9a09 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x9aa9 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x9b49 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x9be9 +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0x9c89 +#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU1 0x9d29 +#define mmCOMMON_DISP_RFU2 0x48ca +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x48ca +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x496a +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x9a0a +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x9aaa +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x9b4a +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x9bea +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0x9c8a +#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU2 0x9d2a +#define mmCOMMON_DISP_RFU3 0x48cb +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x48cb +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x496b +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x9a0b +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x9aab +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x9b4b +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x9beb +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0x9c8b +#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU3 0x9d2b +#define mmCOMMON_DISP_RFU4 0x48cc +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x48cc +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x496c +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x9a0c +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x9aac +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x9b4c +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x9bec +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0x9c8c +#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU4 0x9d2c +#define mmCOMMON_DISP_RFU5 0x48cd +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x48cd +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x496d +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x9a0d +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x9aad +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x9b4d +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x9bed +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0x9c8d +#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU5 0x9d2d +#define mmCOMMON_DISP_RFU6 0x48ce +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x48ce +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x496e +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x9a0e +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x9aae +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x9b4e +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x9bee +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0x9c8e +#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU6 0x9d2e +#define mmCOMMON_DISP_RFU7 0x48cf +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x48cf +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x496f +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x9a0f +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x9aaf +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x9b4f +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x9bef +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0x9c8f +#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU7 0x9d2f +#define mmFREQ_CTRL0 0x4920 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x4920 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x49c0 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x9a60 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x9b00 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x9ba0 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x9c40 +#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0x9ce0 +#define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL0 0x9d80 +#define mmFREQ_CTRL1 0x4921 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x4921 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x49c1 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x9a61 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x9b01 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x9ba1 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x9c41 +#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0x9ce1 +#define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL1 0x9d81 +#define mmFREQ_CTRL2 0x4922 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x4922 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x49c2 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x9a62 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x9b02 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x9ba2 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x9c42 +#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0x9ce2 +#define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL2 0x9d82 +#define mmFREQ_CTRL3 0x4923 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x4923 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x49c3 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x9a63 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x9b03 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x9ba3 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x9c43 +#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0x9ce3 +#define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL3 0x9d83 +#define mmBW_CTRL_COARSE 0x4924 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x4924 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x49c4 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x9a64 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x9b04 +#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x9ba4 +#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x9c44 +#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0x9ce4 +#define mmDC_COMBOPHYPLLREGS7_BW_CTRL_COARSE 0x9d84 +#define mmBW_CTRL_FINE 0x4925 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x4925 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x49c5 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x9a65 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x9b05 +#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x9ba5 +#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x9c45 +#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0x9ce5 +#define mmDC_COMBOPHYPLLREGS7_BW_CTRL_FINE 0x9d85 +#define mmCAL_CTRL 0x4926 +#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x4926 +#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x49c6 +#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x9a66 +#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x9b06 +#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x9ba6 +#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x9c46 +#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0x9ce6 +#define mmDC_COMBOPHYPLLREGS7_CAL_CTRL 0x9d86 +#define mmLOOP_CTRL 0x4927 +#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x4927 +#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x49c7 +#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x9a67 +#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x9b07 +#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x9ba7 +#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x9c47 +#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0x9ce7 +#define mmDC_COMBOPHYPLLREGS7_LOOP_CTRL 0x9d87 +#define mmDEBUG0 0x4928 +#define mmDC_COMBOPHYPLLREGS0_DEBUG0 0x4928 +#define mmDC_COMBOPHYPLLREGS1_DEBUG0 0x49c8 +#define mmDC_COMBOPHYPLLREGS2_DEBUG0 0x9a68 +#define mmDC_COMBOPHYPLLREGS3_DEBUG0 0x9b08 +#define mmDC_COMBOPHYPLLREGS4_DEBUG0 0x9ba8 +#define mmDC_COMBOPHYPLLREGS5_DEBUG0 0x9c48 +#define mmDC_COMBOPHYPLLREGS6_DEBUG0 0x9ce8 +#define mmDC_COMBOPHYPLLREGS7_DEBUG0 0x9d88 +#define mmVREG_CFG 0x4929 +#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x4929 +#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x49c9 +#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x9a69 +#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x9b09 +#define mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x9ba9 +#define mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x9c49 +#define mmDC_COMBOPHYPLLREGS6_VREG_CFG 0x9ce9 +#define mmDC_COMBOPHYPLLREGS7_VREG_CFG 0x9d89 +#define mmOBSERVE0 0x492a +#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x492a +#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x49ca +#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x9a6a +#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x9b0a +#define mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x9baa +#define mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x9c4a +#define mmDC_COMBOPHYPLLREGS6_OBSERVE0 0x9cea +#define mmDC_COMBOPHYPLLREGS7_OBSERVE0 0x9d8a +#define mmOBSERVE1 0x492b +#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x492b +#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x49cb +#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x9a6b +#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x9b0b +#define mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x9bab +#define mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x9c4b +#define mmDC_COMBOPHYPLLREGS6_OBSERVE1 0x9ceb +#define mmDC_COMBOPHYPLLREGS7_OBSERVE1 0x9d8b +#define mmDFT_OUT 0x492c +#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x492c +#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x49cc +#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x9a6c +#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x9b0c +#define mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x9bac +#define mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x9c4c +#define mmDC_COMBOPHYPLLREGS6_DFT_OUT 0x9cec +#define mmDC_COMBOPHYPLLREGS7_DFT_OUT 0x9d8c +#define mmPLL_WRAP_CNTRL1 0x495e +#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 0x495e +#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 0x49fe +#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 0x9a9e +#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 0x9b3e +#define mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL1 0x9bde +#define mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL1 0x9c7e +#define mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL1 0x9d1e +#define mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL1 0x9dbe +#define mmPLL_WRAP_CNTRL 0x495f +#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL 0x495f +#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL 0x49ff +#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL 0x9a9f +#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL 0x9b3f +#define mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL 0x9bdf +#define mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL 0x9c7f +#define mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL 0x9d1f +#define mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL 0x9dbf +#define mmPPLL_VREG_CFG 0x1700 +#define mmDC_DISPLAYPLLREGS0_PPLL_VREG_CFG 0x1700 +#define mmDC_DISPLAYPLLREGS1_PPLL_VREG_CFG 0x172a +#define mmDC_DISPLAYPLLREGS2_PPLL_VREG_CFG 0x1754 +#define mmPPLL_MODE_CNTL 0x1701 +#define mmDC_DISPLAYPLLREGS0_PPLL_MODE_CNTL 0x1701 +#define mmDC_DISPLAYPLLREGS1_PPLL_MODE_CNTL 0x172b +#define mmDC_DISPLAYPLLREGS2_PPLL_MODE_CNTL 0x1755 +#define mmPPLL_FREQ_CTRL0 0x1702 +#define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL0 0x1702 +#define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL0 0x172c +#define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL0 0x1756 +#define mmPPLL_FREQ_CTRL1 0x1703 +#define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL1 0x1703 +#define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL1 0x172d +#define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL1 0x1757 +#define mmPPLL_FREQ_CTRL2 0x1704 +#define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL2 0x1704 +#define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL2 0x172e +#define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL2 0x1758 +#define mmPPLL_FREQ_CTRL3 0x1705 +#define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL3 0x1705 +#define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL3 0x172f +#define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL3 0x1759 +#define mmPPLL_BW_CTRL_COARSE 0x1706 +#define mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_COARSE 0x1706 +#define mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_COARSE 0x1730 +#define mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_COARSE 0x175a +#define mmPPLL_BW_CTRL_FINE 0x1708 +#define mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_FINE 0x1708 +#define mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_FINE 0x1732 +#define mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_FINE 0x175c +#define mmPPLL_CAL_CTRL 0x1709 +#define mmDC_DISPLAYPLLREGS0_PPLL_CAL_CTRL 0x1709 +#define mmDC_DISPLAYPLLREGS1_PPLL_CAL_CTRL 0x1733 +#define mmDC_DISPLAYPLLREGS2_PPLL_CAL_CTRL 0x175d +#define mmPPLL_LOOP_CTRL 0x170a +#define mmDC_DISPLAYPLLREGS0_PPLL_LOOP_CTRL 0x170a +#define mmDC_DISPLAYPLLREGS1_PPLL_LOOP_CTRL 0x1734 +#define mmDC_DISPLAYPLLREGS2_PPLL_LOOP_CTRL 0x175e +#define mmPPLL_REFCLK_CNTL 0x1718 +#define mmDC_DISPLAYPLLREGS0_PPLL_REFCLK_CNTL 0x1718 +#define mmDC_DISPLAYPLLREGS1_PPLL_REFCLK_CNTL 0x1742 +#define mmDC_DISPLAYPLLREGS2_PPLL_REFCLK_CNTL 0x176c +#define mmPPLL_CLKOUT_CNTL 0x1719 +#define mmDC_DISPLAYPLLREGS0_PPLL_CLKOUT_CNTL 0x1719 +#define mmDC_DISPLAYPLLREGS1_PPLL_CLKOUT_CNTL 0x1743 +#define mmDC_DISPLAYPLLREGS2_PPLL_CLKOUT_CNTL 0x176d +#define mmPPLL_DFT_CNTL 0x171a +#define mmDC_DISPLAYPLLREGS0_PPLL_DFT_CNTL 0x171a +#define mmDC_DISPLAYPLLREGS1_PPLL_DFT_CNTL 0x1744 +#define mmDC_DISPLAYPLLREGS2_PPLL_DFT_CNTL 0x176e +#define mmPPLL_ANALOG_CNTL 0x171b +#define mmDC_DISPLAYPLLREGS0_PPLL_ANALOG_CNTL 0x171b +#define mmDC_DISPLAYPLLREGS1_PPLL_ANALOG_CNTL 0x1745 +#define mmDC_DISPLAYPLLREGS2_PPLL_ANALOG_CNTL 0x176f +#define mmPPLL_POSTDIV 0x171c +#define mmDC_DISPLAYPLLREGS0_PPLL_POSTDIV 0x171c +#define mmDC_DISPLAYPLLREGS1_PPLL_POSTDIV 0x1746 +#define mmDC_DISPLAYPLLREGS2_PPLL_POSTDIV 0x1770 +#define mmPPLL_DEBUG0 0x1720 +#define mmDC_DISPLAYPLLREGS0_PPLL_DEBUG0 0x1720 +#define mmDC_DISPLAYPLLREGS1_PPLL_DEBUG0 0x174a +#define mmDC_DISPLAYPLLREGS2_PPLL_DEBUG0 0x1774 +#define mmPPLL_OBSERVE0 0x1721 +#define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0 0x1721 +#define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0 0x174b +#define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0 0x1775 +#define mmPPLL_OBSERVE1 0x1722 +#define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE1 0x1722 +#define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE1 0x174c +#define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE1 0x1776 +#define mmPPLL_UPDATE_CNTL 0x1724 +#define mmDC_DISPLAYPLLREGS0_PPLL_UPDATE_CNTL 0x1724 +#define mmDC_DISPLAYPLLREGS1_PPLL_UPDATE_CNTL 0x174e +#define mmDC_DISPLAYPLLREGS2_PPLL_UPDATE_CNTL 0x1778 +#define mmPPLL_OBSERVE0_OUT 0x1725 +#define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0_OUT 0x1725 +#define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0_OUT 0x174f +#define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0_OUT 0x1779 +#define mmPPLL_STATUS_DEBUG1 0x1726 +#define mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG1 0x1726 +#define mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG1 0x1750 +#define mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG1 0x177a +#define mmPPLL_DEBUG_MUX_CNTL 0x1727 +#define mmDC_DISPLAYPLLREGS0_PPLL_DEBUG_MUX_CNTL 0x1727 +#define mmDC_DISPLAYPLLREGS1_PPLL_DEBUG_MUX_CNTL 0x1751 +#define mmDC_DISPLAYPLLREGS2_PPLL_DEBUG_MUX_CNTL 0x177b +#define mmPPLL_DIV_UPDATE_DEBUG 0x1728 +#define mmDC_DISPLAYPLLREGS0_PPLL_DIV_UPDATE_DEBUG 0x1728 +#define mmDC_DISPLAYPLLREGS1_PPLL_DIV_UPDATE_DEBUG 0x1752 +#define mmDC_DISPLAYPLLREGS2_PPLL_DIV_UPDATE_DEBUG 0x177c +#define mmPPLL_STATUS_DEBUG0 0x1729 +#define mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG0 0x1729 +#define mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG0 0x1753 +#define mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG0 0x177d +#define mmCOMP_EN_CTL 0x9dc0 +#define mmDPCSTX_PHY_CNTL 0x48d0 +#define mmDPCSTX0_DPCSTX_PHY_CNTL 0x48d0 +#define mmDPCSTX1_DPCSTX_PHY_CNTL 0x4970 +#define mmDPCSTX2_DPCSTX_PHY_CNTL 0x9a10 +#define mmDPCSTX3_DPCSTX_PHY_CNTL 0x9ab0 +#define mmDPCSTX4_DPCSTX_PHY_CNTL 0x9b50 +#define mmDPCSTX5_DPCSTX_PHY_CNTL 0x9bf0 +#define mmDPCSTX6_DPCSTX_PHY_CNTL 0x9c90 +#define mmDPCSTX7_DPCSTX_PHY_CNTL 0x9d30 +#define mmDPCSTX_TX_CLOCK_CNTL 0x48d1 +#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x48d1 +#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x4971 +#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x9a11 +#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x9ab1 +#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x9b51 +#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL 0x9bf1 +#define mmDPCSTX6_DPCSTX_TX_CLOCK_CNTL 0x9c91 +#define mmDPCSTX7_DPCSTX_TX_CLOCK_CNTL 0x9d31 +#define mmDPCSTX_TX_CNTL 0x48d3 +#define mmDPCSTX0_DPCSTX_TX_CNTL 0x48d3 +#define mmDPCSTX1_DPCSTX_TX_CNTL 0x4973 +#define mmDPCSTX2_DPCSTX_TX_CNTL 0x9a13 +#define mmDPCSTX3_DPCSTX_TX_CNTL 0x9ab3 +#define mmDPCSTX4_DPCSTX_TX_CNTL 0x9b53 +#define mmDPCSTX5_DPCSTX_TX_CNTL 0x9bf3 +#define mmDPCSTX6_DPCSTX_TX_CNTL 0x9c93 +#define mmDPCSTX7_DPCSTX_TX_CNTL 0x9d33 +#define mmDPCSTX_CBUS_CNTL 0x48d5 +#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x48d5 +#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x4975 +#define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x9a15 +#define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x9ab5 +#define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x9b55 +#define mmDPCSTX5_DPCSTX_CBUS_CNTL 0x9bf5 +#define mmDPCSTX6_DPCSTX_CBUS_CNTL 0x9c95 +#define mmDPCSTX7_DPCSTX_CBUS_CNTL 0x9d35 +#define mmDPCSTX_REG_ERROR_STATUS 0x48d6 +#define mmDPCSTX0_DPCSTX_REG_ERROR_STATUS 0x48d6 +#define mmDPCSTX1_DPCSTX_REG_ERROR_STATUS 0x4976 +#define mmDPCSTX2_DPCSTX_REG_ERROR_STATUS 0x9a16 +#define mmDPCSTX3_DPCSTX_REG_ERROR_STATUS 0x9ab6 +#define mmDPCSTX4_DPCSTX_REG_ERROR_STATUS 0x9b56 +#define mmDPCSTX5_DPCSTX_REG_ERROR_STATUS 0x9bf6 +#define mmDPCSTX6_DPCSTX_REG_ERROR_STATUS 0x9c96 +#define mmDPCSTX7_DPCSTX_REG_ERROR_STATUS 0x9d36 +#define mmDPCSTX_TX_ERROR_STATUS 0x48d7 +#define mmDPCSTX0_DPCSTX_TX_ERROR_STATUS 0x48d7 +#define mmDPCSTX1_DPCSTX_TX_ERROR_STATUS 0x4977 +#define mmDPCSTX2_DPCSTX_TX_ERROR_STATUS 0x9a17 +#define mmDPCSTX3_DPCSTX_TX_ERROR_STATUS 0x9ab7 +#define mmDPCSTX4_DPCSTX_TX_ERROR_STATUS 0x9b57 +#define mmDPCSTX5_DPCSTX_TX_ERROR_STATUS 0x9bf7 +#define mmDPCSTX6_DPCSTX_TX_ERROR_STATUS 0x9c97 +#define mmDPCSTX7_DPCSTX_TX_ERROR_STATUS 0x9d37 +#define mmDPCSTX_PLL_UPDATE_ADDR 0x48d8 +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x48d8 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x4978 +#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x9a18 +#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x9ab8 +#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x9b58 +#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR 0x9bf8 +#define mmDPCSTX6_DPCSTX_PLL_UPDATE_ADDR 0x9c98 +#define mmDPCSTX7_DPCSTX_PLL_UPDATE_ADDR 0x9d38 +#define mmDPCSTX_PLL_UPDATE_DATA 0x48d9 +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x48d9 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x4979 +#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x9a19 +#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x9ab9 +#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x9b59 +#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA 0x9bf9 +#define mmDPCSTX6_DPCSTX_PLL_UPDATE_DATA 0x9c99 +#define mmDPCSTX7_DPCSTX_PLL_UPDATE_DATA 0x9d39 +#define mmDPCSTX_INDEX_MODE_ADDR 0x48da +#define mmDPCSTX0_DPCSTX_INDEX_MODE_ADDR 0x48da +#define mmDPCSTX1_DPCSTX_INDEX_MODE_ADDR 0x497a +#define mmDPCSTX2_DPCSTX_INDEX_MODE_ADDR 0x9a1a +#define mmDPCSTX3_DPCSTX_INDEX_MODE_ADDR 0x9aba +#define mmDPCSTX4_DPCSTX_INDEX_MODE_ADDR 0x9b5a +#define mmDPCSTX5_DPCSTX_INDEX_MODE_ADDR 0x9bfa +#define mmDPCSTX6_DPCSTX_INDEX_MODE_ADDR 0x9c9a +#define mmDPCSTX7_DPCSTX_INDEX_MODE_ADDR 0x9d3a +#define mmDPCSTX_INDEX_MODE_DATA 0x48db +#define mmDPCSTX0_DPCSTX_INDEX_MODE_DATA 0x48db +#define mmDPCSTX1_DPCSTX_INDEX_MODE_DATA 0x497b +#define mmDPCSTX2_DPCSTX_INDEX_MODE_DATA 0x9a1b +#define mmDPCSTX3_DPCSTX_INDEX_MODE_DATA 0x9abb +#define mmDPCSTX4_DPCSTX_INDEX_MODE_DATA 0x9b5b +#define mmDPCSTX5_DPCSTX_INDEX_MODE_DATA 0x9bfb +#define mmDPCSTX6_DPCSTX_INDEX_MODE_DATA 0x9c9b +#define mmDPCSTX7_DPCSTX_INDEX_MODE_DATA 0x9d3b +#define mmDPCSTX_DEBUG_CONFIG 0x48dc +#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x48dc +#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x497c +#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x9a1c +#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x9abc +#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x9b5c +#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG 0x9bfc +#define mmDPCSTX6_DPCSTX_DEBUG_CONFIG 0x9c9c +#define mmDPCSTX7_DPCSTX_DEBUG_CONFIG 0x9d3c +#define mmDPCSTX_TEST_DEBUG_DATA 0x48dd +#define mmDPCSTX0_DPCSTX_TEST_DEBUG_DATA 0x48dd +#define mmDPCSTX1_DPCSTX_TEST_DEBUG_DATA 0x497d +#define mmDPCSTX2_DPCSTX_TEST_DEBUG_DATA 0x9a1d +#define mmDPCSTX3_DPCSTX_TEST_DEBUG_DATA 0x9abd +#define mmDPCSTX4_DPCSTX_TEST_DEBUG_DATA 0x9b5d +#define mmDPCSTX5_DPCSTX_TEST_DEBUG_DATA 0x9bfd +#define mmDPCSTX6_DPCSTX_TEST_DEBUG_DATA 0x9c9d +#define mmDPCSTX7_DPCSTX_TEST_DEBUG_DATA 0x9d3d + +#endif /* DCE_11_2_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h new file mode 100644 index 000000000000..b2ea4202d7bd --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h @@ -0,0 +1,6813 @@ +/* + * DCE_11_2 Register documentation + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_11_2_ENUM_H +#define DCE_11_2_ENUM_H + +typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL { + CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0, + CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1, +} CRTC_CONTROL_CRTC_START_POINT_CNTL; +typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL { + CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0, + CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1, +} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL; +typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL { + CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0, + CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1, + CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2, + CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3, +} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL; +typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY { + CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0, + CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1, +} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY; +typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE { + CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0, + CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1, +} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE; +typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN { + CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x0, + CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1, +} CRTC_CONTROL_CRTC_SOF_PULL_EN; +typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL { + CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x0, + CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1, +} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL { + CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL { + CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN { + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC { + CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT { + CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK { + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf, +} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK; +typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK { + CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0, + CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1, +} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK; +typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR { + CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0, + CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1, +} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR; +typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL { + CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x0, + CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x1, +} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL; +typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN { + CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x0, + CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x1, +} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN; +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT { + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x7, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x8, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x9, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0xa, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0xb, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0xc, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x10, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x11, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x12, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x13, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT; +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT { + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT; +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN { + CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0, + CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN; +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR { + CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x0, + CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x1, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR; +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT { + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x7, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x8, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x9, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0xa, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0xb, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0xc, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x10, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x11, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x12, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x13, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT; +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT { + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT; +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN { + CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0, + CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN; +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR { + CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x0, + CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x1, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR; +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE { + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE; +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK { + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK; +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL { + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL; +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR { + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR; +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT { + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT; +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY { + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY; +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY { + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY; +typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE { + CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0, + CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1, + CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2, + CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3, +} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE; +typedef enum CRTC_CONTROL_CRTC_MASTER_EN { + CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x0, + CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x1, +} CRTC_CONTROL_CRTC_MASTER_EN; +typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN { + CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x0, + CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x1, +} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN; +typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE { + CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x0, + CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x1, +} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE; +typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE { + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0, + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1, +} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE; +typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD { + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0, + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1, + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2, + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3, +} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD; +typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY { + CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0, + CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1, +} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY; +typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT { + CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0, + CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1, +} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT; +typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN { + CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x0, + CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x1, +} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN; +typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE { + CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0, + CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1, +} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE; +typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR { + CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0, + CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1, +} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR; +typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE { + CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0, + CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1, + CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2, + CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3, +} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE; +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY { + CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0, + CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1, +} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY; +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY { + CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0, + CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1, +} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY; +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY { + CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0, + CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1, +} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY; +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN { + CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x0, + CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x1, +} CRTC_STEREO_CONTROL_CRTC_STEREO_EN; +typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR { + CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x0, + CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x1, +} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR; +typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL { + CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0, + CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1, + CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2, + CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3, +} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL; +typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY { + CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0, + CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1, +} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY; +typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY { + CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0, + CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1, +} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY; +typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN { + CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0, + CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1, +} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN; +typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN { + CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x0, + CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x1, +} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE; +typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK { + CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x0, + CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x1, +} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK; +typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY { + CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0, + CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1, +} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY; +typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN { + CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0, + CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1, +} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN; +typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE { + CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0, + CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1, +} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE; +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN { + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN; +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE { + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE; +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE { + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE; +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT { + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT; +typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { + MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x0, + MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x1, +} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; +typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK { + MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0, + MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1, +} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK; +typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK { + MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x0, + MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x1, +} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK; +typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE { + MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x0, + MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x1, + MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2, + MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x3, +} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE; +typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { + MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0, + MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1, + MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2, + MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3, +} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; +typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE { + CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0, + CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1, + CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2, +} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE; +typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR { + CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x0, + CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x1, +} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR; +typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR { + CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0, + CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1, +} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR; +typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR { + CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0, + CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1, +} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR; +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE { + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE; +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR { + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR; +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE { + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE; +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR { + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR; +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE { + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE; +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE { + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE; +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR { + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR; +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE { + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE; +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE { + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN { + CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x0, + CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x1, +} CRTC_CRC_CNTL_CRTC_CRC_EN; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN { + CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x0, + CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x1, +} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE { + CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x0, + CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x1, + CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2, + CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x3, +} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE { + CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x0, + CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x1, + CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2, + CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3, +} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS { + CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0, + CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1, +} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS; +typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT { + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x0, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x1, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x3, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x4, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x5, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x6, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x7, +} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT; +typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT { + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x0, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x1, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x3, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x4, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x5, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x6, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x7, +} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT= 0x1, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS= 0x2, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED= 0x3, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel= 0x1, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel= 0x2, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel= 0x3, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY; +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE { + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE; +typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE { + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE; +typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR { + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR; +typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE { + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE; +typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT { + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME= 0x0, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME= 0x1, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME= 0x2, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME= 0x3, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME= 0x4, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME= 0x5, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME= 0x6, + CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME= 0x7, +} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT; +typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE { + CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE; +typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR { + CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR; +typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE { + CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE; +typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE { + CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE; +typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR { + CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR; +typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE { + CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE= 0x0, + CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE= 0x1, +} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE; +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE { + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0, + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE; +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR { + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0, + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR; +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE { + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0, + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE; +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE { + CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE= 0x0, + CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE= 0x1, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE; +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE { + CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF= 0x0, + CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON= 0x1, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE; +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN { + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN; +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB { + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB; +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE { + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE; +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR { + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR; +typedef enum CRTC_V_SYNC_A_POL { + CRTC_V_SYNC_A_POL_HIGH = 0x0, + CRTC_V_SYNC_A_POL_LOW = 0x1, +} CRTC_V_SYNC_A_POL; +typedef enum CRTC_H_SYNC_A_POL { + CRTC_H_SYNC_A_POL_HIGH = 0x0, + CRTC_H_SYNC_A_POL_LOW = 0x1, +} CRTC_H_SYNC_A_POL; +typedef enum CRTC_HORZ_REPETITION_COUNT { + CRTC_HORZ_REPETITION_COUNT_0 = 0x0, + CRTC_HORZ_REPETITION_COUNT_1 = 0x1, + CRTC_HORZ_REPETITION_COUNT_2 = 0x2, + CRTC_HORZ_REPETITION_COUNT_3 = 0x3, + CRTC_HORZ_REPETITION_COUNT_4 = 0x4, + CRTC_HORZ_REPETITION_COUNT_5 = 0x5, + CRTC_HORZ_REPETITION_COUNT_6 = 0x6, + CRTC_HORZ_REPETITION_COUNT_7 = 0x7, + CRTC_HORZ_REPETITION_COUNT_8 = 0x8, + CRTC_HORZ_REPETITION_COUNT_9 = 0x9, + CRTC_HORZ_REPETITION_COUNT_10 = 0xa, + CRTC_HORZ_REPETITION_COUNT_11 = 0xb, + CRTC_HORZ_REPETITION_COUNT_12 = 0xc, + CRTC_HORZ_REPETITION_COUNT_13 = 0xd, + CRTC_HORZ_REPETITION_COUNT_14 = 0xe, + CRTC_HORZ_REPETITION_COUNT_15 = 0xf, +} CRTC_HORZ_REPETITION_COUNT; +typedef enum PERFCOUNTER_CVALUE_SEL { + PERFCOUNTER_CVALUE_SEL_47_0 = 0x0, + PERFCOUNTER_CVALUE_SEL_15_0 = 0x1, + PERFCOUNTER_CVALUE_SEL_31_16 = 0x2, + PERFCOUNTER_CVALUE_SEL_47_32 = 0x3, + PERFCOUNTER_CVALUE_SEL_11_0 = 0x4, + PERFCOUNTER_CVALUE_SEL_23_12 = 0x5, + PERFCOUNTER_CVALUE_SEL_35_24 = 0x6, + PERFCOUNTER_CVALUE_SEL_47_36 = 0x7, +} PERFCOUNTER_CVALUE_SEL; +typedef enum PERFCOUNTER_INC_MODE { + PERFCOUNTER_INC_MODE_MULTI_BIT = 0x0, + PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x1, + PERFCOUNTER_INC_MODE_LSB = 0x2, + PERFCOUNTER_INC_MODE_POS_EDGE = 0x3, +} PERFCOUNTER_INC_MODE; +typedef enum PERFCOUNTER_HW_CNTL_SEL { + PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x0, + PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x1, +} PERFCOUNTER_HW_CNTL_SEL; +typedef enum PERFCOUNTER_RUNEN_MODE { + PERFCOUNTER_RUNEN_MODE_LEVEL = 0x0, + PERFCOUNTER_RUNEN_MODE_EDGE = 0x1, +} PERFCOUNTER_RUNEN_MODE; +typedef enum PERFCOUNTER_CNTOFF_START_DIS { + PERFCOUNTER_CNTOFF_START_ENABLE = 0x0, + PERFCOUNTER_CNTOFF_START_DISABLE = 0x1, +} PERFCOUNTER_CNTOFF_START_DIS; +typedef enum PERFCOUNTER_RESTART_EN { + PERFCOUNTER_RESTART_DISABLE = 0x0, + PERFCOUNTER_RESTART_ENABLE = 0x1, +} PERFCOUNTER_RESTART_EN; +typedef enum PERFCOUNTER_INT_EN { + PERFCOUNTER_INT_DISABLE = 0x0, + PERFCOUNTER_INT_ENABLE = 0x1, +} PERFCOUNTER_INT_EN; +typedef enum PERFCOUNTER_OFF_MASK { + PERFCOUNTER_OFF_MASK_DISABLE = 0x0, + PERFCOUNTER_OFF_MASK_ENABLE = 0x1, +} PERFCOUNTER_OFF_MASK; +typedef enum PERFCOUNTER_ACTIVE { + PERFCOUNTER_IS_IDLE = 0x0, + PERFCOUNTER_IS_ACTIVE = 0x1, +} PERFCOUNTER_ACTIVE; +typedef enum PERFCOUNTER_INT_TYPE { + PERFCOUNTER_INT_TYPE_LEVEL = 0x0, + PERFCOUNTER_INT_TYPE_PULSE = 0x1, +} PERFCOUNTER_INT_TYPE; +typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { + PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x0, + PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x1, +} PERFCOUNTER_COUNTED_VALUE_TYPE; +typedef enum PERFCOUNTER_CNTL_SEL { + PERFCOUNTER_CNTL_SEL_0 = 0x0, + PERFCOUNTER_CNTL_SEL_1 = 0x1, + PERFCOUNTER_CNTL_SEL_2 = 0x2, + PERFCOUNTER_CNTL_SEL_3 = 0x3, + PERFCOUNTER_CNTL_SEL_4 = 0x4, + PERFCOUNTER_CNTL_SEL_5 = 0x5, + PERFCOUNTER_CNTL_SEL_6 = 0x6, + PERFCOUNTER_CNTL_SEL_7 = 0x7, +} PERFCOUNTER_CNTL_SEL; +typedef enum PERFCOUNTER_CNT0_STATE { + PERFCOUNTER_CNT0_STATE_RESET = 0x0, + PERFCOUNTER_CNT0_STATE_START = 0x1, + PERFCOUNTER_CNT0_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT0_STATE_HW = 0x3, +} PERFCOUNTER_CNT0_STATE; +typedef enum PERFCOUNTER_STATE_SEL0 { + PERFCOUNTER_STATE_SEL0_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL0_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL0; +typedef enum PERFCOUNTER_CNT1_STATE { + PERFCOUNTER_CNT1_STATE_RESET = 0x0, + PERFCOUNTER_CNT1_STATE_START = 0x1, + PERFCOUNTER_CNT1_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT1_STATE_HW = 0x3, +} PERFCOUNTER_CNT1_STATE; +typedef enum PERFCOUNTER_STATE_SEL1 { + PERFCOUNTER_STATE_SEL1_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL1_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL1; +typedef enum PERFCOUNTER_CNT2_STATE { + PERFCOUNTER_CNT2_STATE_RESET = 0x0, + PERFCOUNTER_CNT2_STATE_START = 0x1, + PERFCOUNTER_CNT2_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT2_STATE_HW = 0x3, +} PERFCOUNTER_CNT2_STATE; +typedef enum PERFCOUNTER_STATE_SEL2 { + PERFCOUNTER_STATE_SEL2_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL2_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL2; +typedef enum PERFCOUNTER_CNT3_STATE { + PERFCOUNTER_CNT3_STATE_RESET = 0x0, + PERFCOUNTER_CNT3_STATE_START = 0x1, + PERFCOUNTER_CNT3_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT3_STATE_HW = 0x3, +} PERFCOUNTER_CNT3_STATE; +typedef enum PERFCOUNTER_STATE_SEL3 { + PERFCOUNTER_STATE_SEL3_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL3_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL3; +typedef enum PERFCOUNTER_CNT4_STATE { + PERFCOUNTER_CNT4_STATE_RESET = 0x0, + PERFCOUNTER_CNT4_STATE_START = 0x1, + PERFCOUNTER_CNT4_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT4_STATE_HW = 0x3, +} PERFCOUNTER_CNT4_STATE; +typedef enum PERFCOUNTER_STATE_SEL4 { + PERFCOUNTER_STATE_SEL4_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL4_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL4; +typedef enum PERFCOUNTER_CNT5_STATE { + PERFCOUNTER_CNT5_STATE_RESET = 0x0, + PERFCOUNTER_CNT5_STATE_START = 0x1, + PERFCOUNTER_CNT5_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT5_STATE_HW = 0x3, +} PERFCOUNTER_CNT5_STATE; +typedef enum PERFCOUNTER_STATE_SEL5 { + PERFCOUNTER_STATE_SEL5_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL5_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL5; +typedef enum PERFCOUNTER_CNT6_STATE { + PERFCOUNTER_CNT6_STATE_RESET = 0x0, + PERFCOUNTER_CNT6_STATE_START = 0x1, + PERFCOUNTER_CNT6_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT6_STATE_HW = 0x3, +} PERFCOUNTER_CNT6_STATE; +typedef enum PERFCOUNTER_STATE_SEL6 { + PERFCOUNTER_STATE_SEL6_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL6_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL6; +typedef enum PERFCOUNTER_CNT7_STATE { + PERFCOUNTER_CNT7_STATE_RESET = 0x0, + PERFCOUNTER_CNT7_STATE_START = 0x1, + PERFCOUNTER_CNT7_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT7_STATE_HW = 0x3, +} PERFCOUNTER_CNT7_STATE; +typedef enum PERFCOUNTER_STATE_SEL7 { + PERFCOUNTER_STATE_SEL7_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL7_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL7; +typedef enum PERFMON_STATE { + PERFMON_STATE_RESET = 0x0, + PERFMON_STATE_START = 0x1, + PERFMON_STATE_FREEZE = 0x2, + PERFMON_STATE_HW = 0x3, +} PERFMON_STATE; +typedef enum PERFMON_CNTOFF_AND_OR { + PERFMON_CNTOFF_OR = 0x0, + PERFMON_CNTOFF_AND = 0x1, +} PERFMON_CNTOFF_AND_OR; +typedef enum PERFMON_CNTOFF_INT_EN { + PERFMON_CNTOFF_INT_DISABLE = 0x0, + PERFMON_CNTOFF_INT_ENABLE = 0x1, +} PERFMON_CNTOFF_INT_EN; +typedef enum PERFMON_CNTOFF_INT_TYPE { + PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x0, + PERFMON_CNTOFF_INT_TYPE_PULSE = 0x1, +} PERFMON_CNTOFF_INT_TYPE; +typedef enum ENABLE { + DISABLE_THE_FEATURE = 0x0, + ENABLE_THE_FEATURE = 0x1, +} ENABLE; +typedef enum ENABLE_CLOCK { + DISABLE_THE_CLOCK = 0x0, + ENABLE_THE_CLOCK = 0x1, +} ENABLE_CLOCK; +typedef enum FORCE_VBI { + FORCE_VBI_LOW = 0x0, + FORCE_VBI_HIGH = 0x1, +} FORCE_VBI; +typedef enum OVERRIDE_CGTT_SCLK { + OVERRIDE_CGTT_SCLK_NOOP = 0x0, + SET_OVERRIDE_CGTT_SCLK = 0x1, +} OVERRIDE_CGTT_SCLK; +typedef enum CLEAR_SMU_INTR { + SMU_INTR_STATUS_NOOP = 0x0, + SMU_INTR_STATUS_CLEAR = 0x1, +} CLEAR_SMU_INTR; +typedef enum STATIC_SCREEN_SMU_INTR { + STATIC_SCREEN_SMU_INTR_NOOP = 0x0, + SET_STATIC_SCREEN_SMU_INTR = 0x1, +} STATIC_SCREEN_SMU_INTR; +typedef enum JITTER_REMOVE_DISABLE { + ENABLE_JITTER_REMOVAL = 0x0, + DISABLE_JITTER_REMOVAL = 0x1, +} JITTER_REMOVE_DISABLE; +typedef enum DISABLE_CLOCK_GATING { + CLOCK_GATING_ENABLED = 0x0, + CLOCK_GATING_DISABLED = 0x1, +} DISABLE_CLOCK_GATING; +typedef enum DISABLE_CLOCK_GATING_IN_DCO { + CLOCK_GATING_ENABLED_IN_DCO = 0x0, + CLOCK_GATING_DISABLED_IN_DCO = 0x1, +} DISABLE_CLOCK_GATING_IN_DCO; +typedef enum DCCG_DEEP_COLOR_CNTL { + DCCG_DEEP_COLOR_DTO_DISABLE = 0x0, + DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x1, + DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x2, + DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x3, +} DCCG_DEEP_COLOR_CNTL; +typedef enum REFCLK_CLOCK_EN { + REFCLK_CLOCK_EN_PCIE_REFCLK = 0x0, + REFCLK_CLOCK_EN_ALLOW_SRC = 0x1, +} REFCLK_CLOCK_EN; +typedef enum REFCLK_SRC_SEL { + REFCLK_SRC_SEL_XTALIN = 0x0, + REFCLK_SRC_SEL_DISPPLL = 0x1, +} REFCLK_SRC_SEL; +typedef enum DPREFCLK_SRC_SEL { + DPREFCLK_SRC_SEL_CK = 0x0, + DPREFCLK_SRC_SEL_P0PLL = 0x1, + DPREFCLK_SRC_SEL_P1PLL = 0x2, + DPREFCLK_SRC_SEL_P2PLL = 0x3, + DPREFCLK_SRC_SEL_P3PLL = 0x4, +} DPREFCLK_SRC_SEL; +typedef enum XTAL_REF_SEL { + XTAL_REF_SEL_1X = 0x0, + XTAL_REF_SEL_2X = 0x1, +} XTAL_REF_SEL; +typedef enum XTAL_REF_CLOCK_SOURCE_SEL { + XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x0, + XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 0x1, +} XTAL_REF_CLOCK_SOURCE_SEL; +typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL { + MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x0, + MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x1, +} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; +typedef enum ALLOW_SR_ON_TRANS_REQ { + ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x0, + ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x1, +} ALLOW_SR_ON_TRANS_REQ; +typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL { + MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x0, + MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x1, +} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; +typedef enum PIPE_PIXEL_RATE_SOURCE { + PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x0, + PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x1, + PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x2, +} PIPE_PIXEL_RATE_SOURCE; +typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE { + PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x0, + PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x1, + PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x2, + PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x3, + PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x4, + PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x5, + PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 0x6, +} PIPE_PHYPLL_PIXEL_RATE_SOURCE; +typedef enum PIPE_PIXEL_RATE_PLL_SOURCE { + PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x0, + PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x1, +} PIPE_PIXEL_RATE_PLL_SOURCE; +typedef enum DP_DTO_DS_DISABLE { + DP_DTO_DESPREAD_DISABLE = 0x0, + DP_DTO_DESPREAD_ENABLE = 0x1, +} DP_DTO_DS_DISABLE; +typedef enum CRTC_ADD_PIXEL { + CRTC_ADD_PIXEL_NOOP = 0x0, + CRTC_ADD_PIXEL_FORCE = 0x1, +} CRTC_ADD_PIXEL; +typedef enum CRTC_DROP_PIXEL { + CRTC_DROP_PIXEL_NOOP = 0x0, + CRTC_DROP_PIXEL_FORCE = 0x1, +} CRTC_DROP_PIXEL; +typedef enum SYMCLK_FE_FORCE_EN { + SYMCLK_FE_FORCE_EN_DISABLE = 0x0, + SYMCLK_FE_FORCE_EN_ENABLE = 0x1, +} SYMCLK_FE_FORCE_EN; +typedef enum SYMCLK_FE_FORCE_SRC { + SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x0, + SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x1, + SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x2, + SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x3, + SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x4, + SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x5, + SYMCLK_FE_FORCE_SRC_UNIPHYG = 0x6, +} SYMCLK_FE_FORCE_SRC; +typedef enum DPDBG_CLK_FORCE_EN { + DPDBG_CLK_FORCE_EN_DISABLE = 0x0, + DPDBG_CLK_FORCE_EN_ENABLE = 0x1, +} DPDBG_CLK_FORCE_EN; +typedef enum DVOACLK_COARSE_SKEW_CNTL { + DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x0, + DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x1, + DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x2, + DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x3, + DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x4, + DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x5, + DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x6, + DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x7, + DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x8, + DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x9, + DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0xa, + DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0xb, + DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0xc, + DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0xd, + DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0xe, + DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0xf, + DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x10, + DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x11, + DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x12, + DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x13, + DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x14, + DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x15, + DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x16, + DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x17, + DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x18, + DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x19, + DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x1a, + DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x1b, + DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x1c, + DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x1d, + DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x1e, +} DVOACLK_COARSE_SKEW_CNTL; +typedef enum DVOACLK_FINE_SKEW_CNTL { + DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x0, + DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x1, + DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x2, + DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x3, + DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x4, + DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x5, + DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x6, + DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x7, +} DVOACLK_FINE_SKEW_CNTL; +typedef enum DVOACLKD_IN_PHASE { + DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0, + DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x1, +} DVOACLKD_IN_PHASE; +typedef enum DVOACLKC_IN_PHASE { + DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0, + DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x1, +} DVOACLKC_IN_PHASE; +typedef enum DVOACLKC_MVP_IN_PHASE { + DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0, + DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x1, +} DVOACLKC_MVP_IN_PHASE; +typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE { + DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x0, + DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x1, +} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; +typedef enum MVP_CLK_SRC_SEL { + MVP_CLK_SRC_SEL_RSRV = 0x0, + MVP_CLK_SRC_SEL_IO_1 = 0x1, + MVP_CLK_SRC_SEL_IO_2 = 0x2, + MVP_CLK_SRC_SEL_REFCLK = 0x3, +} MVP_CLK_SRC_SEL; +typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL { + DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0x0, + DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 0x1, + DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 0x2, + DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 0x3, + DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 0x4, + DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 0x5, + DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x6, +} DCCG_AUDIO_DTO0_SOURCE_SEL; +typedef enum DCCG_AUDIO_DTO_SEL { + DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x0, + DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x1, + DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x2, +} DCCG_AUDIO_DTO_SEL; +typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL { + DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x0, + DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x1, +} DCCG_AUDIO_DTO2_SOURCE_SEL; +typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO { + DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x0, + DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x1, +} DCCG_AUDIO_DTO_USE_512FBR_DTO; +typedef enum DCCG_DBG_EN { + DCCG_DBG_EN_DISABLE = 0x0, + DCCG_DBG_EN_ENABLE = 0x1, +} DCCG_DBG_EN; +typedef enum DCCG_DBG_BLOCK_SEL { + DCCG_DBG_BLOCK_SEL_DCCG = 0x0, + DCCG_DBG_BLOCK_SEL_PMON = 0x1, + DCCG_DBG_BLOCK_SEL_PMON2 = 0x2, +} DCCG_DBG_BLOCK_SEL; +typedef enum DCCG_DBG_CLOCK_SEL { + DCCG_DBG_CLOCK_SEL_DISPCLK = 0x0, + DCCG_DBG_CLOCK_SEL_SCLK = 0x1, + DCCG_DBG_CLOCK_SEL_MVPCLK = 0x2, + DCCG_DBG_CLOCK_SEL_DVOCLK = 0x3, + DCCG_DBG_CLOCK_SEL_DACCLK = 0x4, + DCCG_DBG_CLOCK_SEL_REFCLK = 0x5, + DCCG_DBG_CLOCK_SEL_SYMCLKA = 0x6, + DCCG_DBG_CLOCK_SEL_SYMCLKB = 0x7, + DCCG_DBG_CLOCK_SEL_SYMCLKC = 0x8, + DCCG_DBG_CLOCK_SEL_SYMCLKD = 0x9, + DCCG_DBG_CLOCK_SEL_SYMCLKE = 0xa, + DCCG_DBG_CLOCK_SEL_SYMCLKG = 0xb, + DCCG_DBG_CLOCK_SEL_SYMCLKF = 0xc, + DCCG_DBG_CLOCK_SEL_RSRV = 0xd, + DCCG_DBG_CLOCK_SEL_AOMCLK0 = 0xe, + DCCG_DBG_CLOCK_SEL_AOMCLK1 = 0xf, + DCCG_DBG_CLOCK_SEL_AOMCLK2 = 0x10, + DCCG_DBG_CLOCK_SEL_DPREFCLK = 0x11, + DCCG_DBG_CLOCK_SEL_UNB_DB_CLK = 0x12, + DCCG_DBG_CLOCK_SEL_DSICLK = 0x13, + DCCG_DBG_CLOCK_SEL_BYTECLK = 0x14, + DCCG_DBG_CLOCK_SEL_ESCCLK = 0x15, + DCCG_DBG_CLOCK_SEL_SYMCLKLPA = 0x16, + DCCG_DBG_CLOCK_SEL_SYMCLKLPB = 0x17, +} DCCG_DBG_CLOCK_SEL; +typedef enum DCCG_DBG_OUT_BLOCK_SEL { + DCCG_DBG_OUT_BLOCK_SEL_DCCG = 0x0, + DCCG_DBG_OUT_BLOCK_SEL_DCO = 0x1, + DCCG_DBG_OUT_BLOCK_SEL_DCIO = 0x2, + DCCG_DBG_OUT_BLOCK_SEL_DSI = 0x3, +} DCCG_DBG_OUT_BLOCK_SEL; +typedef enum DISPCLK_FREQ_RAMP_DONE { + DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x0, + DISPCLK_FREQ_RAMP_COMPLETED = 0x1, +} DISPCLK_FREQ_RAMP_DONE; +typedef enum DCCG_FIFO_ERRDET_RESET { + DCCG_FIFO_ERRDET_RESET_NOOP = 0x0, + DCCG_FIFO_ERRDET_RESET_FORCE = 0x1, +} DCCG_FIFO_ERRDET_RESET; +typedef enum DCCG_FIFO_ERRDET_STATE { + DCCG_FIFO_ERRDET_STATE_DETECTION = 0x0, + DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x1, +} DCCG_FIFO_ERRDET_STATE; +typedef enum DCCG_FIFO_ERRDET_OVR_EN { + DCCG_FIFO_ERRDET_OVR_DISABLE = 0x0, + DCCG_FIFO_ERRDET_OVR_ENABLE = 0x1, +} DCCG_FIFO_ERRDET_OVR_EN; +typedef enum DISPCLK_CHG_FWD_CORR_DISABLE { + DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x0, + DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x1, +} DISPCLK_CHG_FWD_CORR_DISABLE; +typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS { + DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x0, + DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x1, +} DC_MEM_GLOBAL_PWR_REQ_DIS; +typedef enum DCCG_PERF_RUN { + DCCG_PERF_RUN_NOOP = 0x0, + DCCG_PERF_RUN_START = 0x1, +} DCCG_PERF_RUN; +typedef enum DCCG_PERF_MODE_VSYNC { + DCCG_PERF_MODE_VSYNC_NOOP = 0x0, + DCCG_PERF_MODE_VSYNC_START = 0x1, +} DCCG_PERF_MODE_VSYNC; +typedef enum DCCG_PERF_MODE_HSYNC { + DCCG_PERF_MODE_HSYNC_NOOP = 0x0, + DCCG_PERF_MODE_HSYNC_START = 0x1, +} DCCG_PERF_MODE_HSYNC; +typedef enum DCCG_PERF_CRTC_SELECT { + DCCG_PERF_SEL_CRTC0 = 0x0, + DCCG_PERF_SEL_CRTC1 = 0x1, + DCCG_PERF_SEL_CRTC2 = 0x2, + DCCG_PERF_SEL_CRTC3 = 0x3, + DCCG_PERF_SEL_CRTC4 = 0x4, + DCCG_PERF_SEL_CRTC5 = 0x5, +} DCCG_PERF_CRTC_SELECT; +typedef enum CLOCK_BRANCH_SOFT_RESET { + CLOCK_BRANCH_SOFT_RESET_NOOP = 0x0, + CLOCK_BRANCH_SOFT_RESET_FORCE = 0x1, +} CLOCK_BRANCH_SOFT_RESET; +typedef enum PLL_CFG_IF_SOFT_RESET { + PLL_CFG_IF_SOFT_RESET_NOOP = 0x0, + PLL_CFG_IF_SOFT_RESET_FORCE = 0x1, +} PLL_CFG_IF_SOFT_RESET; +typedef enum DVO_ENABLE_RST { + DVO_ENABLE_RST_DISABLE = 0x0, + DVO_ENABLE_RST_ENABLE = 0x1, +} DVO_ENABLE_RST; +typedef enum LptNumBanks { + LPT_NUM_BANKS_2BANK = 0x0, + LPT_NUM_BANKS_4BANK = 0x1, + LPT_NUM_BANKS_8BANK = 0x2, + LPT_NUM_BANKS_16BANK = 0x3, + LPT_NUM_BANKS_32BANK = 0x4, +} LptNumBanks; +typedef enum DCIO_DC_GENERICA_SEL { + DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0, + DCIO_GENERICA_SEL_STEREOSYNC = 0x1, + DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2, + DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3, + DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4, + DCIO_GENERICA_SEL_P1_PLLCLK = 0x5, + DCIO_GENERICA_SEL_P2_PLLCLK = 0x6, + DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7, + DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8, + DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9, + DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa, + DCIO_GENERICA_SEL_SYNCEN = 0xb, + DCIO_GENERICA_SEL_GENERICA_SCG = 0xc, + DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd, + DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe, + DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf, + DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10, + DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11, +} DCIO_DC_GENERICA_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { + DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0, + DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1, + DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2, + DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3, + DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4, + DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5, + DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x6, + DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x7, + DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x8, +} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { + DCIO_UNIPHYA_FBDIV_CLK = 0x0, + DCIO_UNIPHYB_FBDIV_CLK = 0x1, + DCIO_UNIPHYC_FBDIV_CLK = 0x2, + DCIO_UNIPHYD_FBDIV_CLK = 0x3, + DCIO_UNIPHYE_FBDIV_CLK = 0x4, + DCIO_UNIPHYF_FBDIV_CLK = 0x5, + DCIO_UNIPHYG_FBDIV_CLK = 0x6, + DCIO_UNIPHYLPA_FBDIV_CLK = 0x7, + DCIO_UNIPHYLPB_FBDIV_CLK = 0x8, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { + DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0, + DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1, + DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2, + DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3, + DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4, + DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5, + DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x6, + DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x7, + DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x8, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { + DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0, + DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1, + DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2, + DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3, + DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4, + DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5, + DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x6, + DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x7, + DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x8, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; +typedef enum DCIO_DC_GENERICB_SEL { + DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0, + DCIO_GENERICB_SEL_STEREOSYNC = 0x1, + DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2, + DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3, + DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4, + DCIO_GENERICB_SEL_P1_PLLCLK = 0x5, + DCIO_GENERICB_SEL_P2_PLLCLK = 0x6, + DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7, + DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8, + DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9, + DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa, + DCIO_GENERICB_SEL_SYNCEN = 0xb, + DCIO_GENERICB_SEL_GENERICA_SCG = 0xc, + DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd, + DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe, + DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf, +} DCIO_DC_GENERICB_SEL; +typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL { + DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0, + DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6, + DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7, + DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc, + DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd, + DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe, + DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf, +} DCIO_DC_PAD_EXTERN_SIG_SEL; +typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS { + DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0, + DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1, + DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2, + DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3, +} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; +typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { + DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0, + DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1, + DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2, + DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3, +} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; +typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { + DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0, + DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1, + DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2, + DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3, +} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; +typedef enum DCIO_DC_GPIO_VIP_DEBUG { + DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0, + DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1, +} DCIO_DC_GPIO_VIP_DEBUG; +typedef enum DCIO_DC_GPIO_MACRO_DEBUG { + DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0, + DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1, + DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2, + DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3, +} DCIO_DC_GPIO_MACRO_DEBUG; +typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL { + DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0, + DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1, +} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; +typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN { + DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0, + DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1, +} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; +typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { + DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0, + DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1, +} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; +typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7, +} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; +typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { + DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0, + DCIO_UNIPHY_CHANNEL_INVERTED = 0x1, +} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; +typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3, +} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; +typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3, +} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; +typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { + DCIO_VIP_MUX_EN_DVO = 0x0, + DCIO_VIP_MUX_EN_VIP = 0x1, +} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; +typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { + DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0, + DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, +} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; +typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { + DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0, + DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, +} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { + DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0, + DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { + DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0, + DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { + DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0, + DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { + DCIO_LVTMA_DIGON_OFF = 0x0, + DCIO_LVTMA_DIGON_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { + DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0, + DCIO_LVTMA_DIGON_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { + DCIO_LVTMA_BLON_OFF = 0x0, + DCIO_LVTMA_BLON_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { + DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0, + DCIO_LVTMA_BLON_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; +typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { + DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0, + DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1, +} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; +typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { + DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0, + DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; +typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { + DCIO_BL_PWM_DISABLE = 0x0, + DCIO_BL_PWM_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL_BL_PWM_EN; +typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3, +} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; +typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { + DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0, + DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; +typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { + DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0, + DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1, +} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; +typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { + DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0, + DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1, +} DCIO_BL_PWM_GRP1_REG_LOCK; +typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { + DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0, + DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1, +} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; +typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5, +} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; +typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { + DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0, + DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1, +} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; +typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { + DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0, + DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1, +} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; +typedef enum DCIO_GSL_SEL { + DCIO_GSL_SEL_GROUP_0 = 0x0, + DCIO_GSL_SEL_GROUP_1 = 0x1, + DCIO_GSL_SEL_GROUP_2 = 0x2, +} DCIO_GSL_SEL; +typedef enum DCIO_GENLK_CLK_GSL_MASK { + DCIO_GENLK_CLK_GSL_MASK_NO = 0x0, + DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1, + DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2, +} DCIO_GENLK_CLK_GSL_MASK; +typedef enum DCIO_GENLK_VSYNC_GSL_MASK { + DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0, + DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, + DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2, +} DCIO_GENLK_VSYNC_GSL_MASK; +typedef enum DCIO_SWAPLOCK_A_GSL_MASK { + DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0, + DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1, + DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2, +} DCIO_SWAPLOCK_A_GSL_MASK; +typedef enum DCIO_SWAPLOCK_B_GSL_MASK { + DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0, + DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1, + DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2, +} DCIO_SWAPLOCK_B_GSL_MASK; +typedef enum DCIO_GSL_VSYNC_SEL { + DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, + DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1, + DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2, + DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3, + DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4, + DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, +} DCIO_GSL_VSYNC_SEL; +typedef enum DCIO_GSL0_TIMING_SYNC_SEL { + DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL0_TIMING_SYNC_SEL; +typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL { + DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL0_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_GSL1_TIMING_SYNC_SEL { + DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL1_TIMING_SYNC_SEL; +typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL { + DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL1_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_GSL2_TIMING_SYNC_SEL { + DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL2_TIMING_SYNC_SEL; +typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL { + DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL2_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_DC_GPU_TIMER_START_POSITION { + DCIO_GPU_TIMER_START_0_END_27 = 0x0, + DCIO_GPU_TIMER_START_1_END_28 = 0x1, + DCIO_GPU_TIMER_START_2_END_29 = 0x2, + DCIO_GPU_TIMER_START_3_END_30 = 0x3, + DCIO_GPU_TIMER_START_4_END_31 = 0x4, + DCIO_GPU_TIMER_START_6_END_33 = 0x5, + DCIO_GPU_TIMER_START_8_END_35 = 0x6, + DCIO_GPU_TIMER_START_10_END_37 = 0x7, +} DCIO_DC_GPU_TIMER_START_POSITION; +typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { + DCIO_TEST_CLK_SEL_DISPCLK = 0x0, + DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1, + DCIO_TEST_CLK_SEL_SCLK = 0x2, +} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; +typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { + DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0, + DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1, +} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; +typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX { + DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0, + DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1, + DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2, + DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3, + DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4, + DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5, + DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6, + DCIO_EXT_VSYNC_MUX_GENERICB = 0x7, +} DCIO_DCO_DCFE_EXT_VSYNC_MUX; +typedef enum DCIO_DCO_EXT_VSYNC_MASK { + DCIO_EXT_VSYNC_MASK_NONE = 0x0, + DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1, + DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2, + DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3, + DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4, + DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5, + DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6, + DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7, +} DCIO_DCO_EXT_VSYNC_MASK; +typedef enum DCIO_DBG_OUT_PIN_SEL { + DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0, + DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1, +} DCIO_DBG_OUT_PIN_SEL; +typedef enum DCIO_DBG_OUT_12BIT_SEL { + DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0, + DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1, + DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2, + DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3, +} DCIO_DBG_OUT_12BIT_SEL; +typedef enum DCIO_DSYNC_SOFT_RESET { + DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0, + DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1, +} DCIO_DSYNC_SOFT_RESET; +typedef enum DCIO_DACA_SOFT_RESET { + DCIO_DACA_SOFT_RESET_DEASSERT = 0x0, + DCIO_DACA_SOFT_RESET_ASSERT = 0x1, +} DCIO_DACA_SOFT_RESET; +typedef enum DCIO_DCRXPHY_SOFT_RESET { + DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0, + DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1, +} DCIO_DCRXPHY_SOFT_RESET; +typedef enum DCIO_DPHY_LANE_SEL { + DCIO_DPHY_LANE_SEL_LANE0 = 0x0, + DCIO_DPHY_LANE_SEL_LANE1 = 0x1, + DCIO_DPHY_LANE_SEL_LANE2 = 0x2, + DCIO_DPHY_LANE_SEL_LANE3 = 0x3, +} DCIO_DPHY_LANE_SEL; +typedef enum DCIO_DPCS_INTERRUPT_TYPE { + DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x0, + DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x1, +} DCIO_DPCS_INTERRUPT_TYPE; +typedef enum DCIO_DPCS_INTERRUPT_MASK { + DCIO_DPCS_INTERRUPT_DISABLE = 0x0, + DCIO_DPCS_INTERRUPT_ENABLE = 0x1, +} DCIO_DPCS_INTERRUPT_MASK; +typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x6, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x7, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x8, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0xb, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x12, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x13, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x14, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x15, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x16, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x17, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x1e, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x1f, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x20, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x21, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x22, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x23, +} DCIO_DC_GPU_TIMER_READ_SELECT; +typedef enum DCIO_IMPCAL_STEP_DELAY { + DCIO_IMPCAL_STEP_DELAY_1us = 0x0, + DCIO_IMPCAL_STEP_DELAY_2us = 0x1, + DCIO_IMPCAL_STEP_DELAY_3us = 0x2, + DCIO_IMPCAL_STEP_DELAY_4us = 0x3, + DCIO_IMPCAL_STEP_DELAY_5us = 0x4, + DCIO_IMPCAL_STEP_DELAY_6us = 0x5, + DCIO_IMPCAL_STEP_DELAY_7us = 0x6, + DCIO_IMPCAL_STEP_DELAY_8us = 0x7, + DCIO_IMPCAL_STEP_DELAY_9us = 0x8, + DCIO_IMPCAL_STEP_DELAY_10us = 0x9, + DCIO_IMPCAL_STEP_DELAY_11us = 0xa, + DCIO_IMPCAL_STEP_DELAY_12us = 0xb, + DCIO_IMPCAL_STEP_DELAY_13us = 0xc, + DCIO_IMPCAL_STEP_DELAY_14us = 0xd, + DCIO_IMPCAL_STEP_DELAY_15us = 0xe, + DCIO_IMPCAL_STEP_DELAY_16us = 0xf, +} DCIO_IMPCAL_STEP_DELAY; +typedef enum DCIO_UNIPHY_IMPCAL_SEL { + DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0, + DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1, +} DCIO_UNIPHY_IMPCAL_SEL; +typedef enum DCIO_DBG_CLOCK_SEL { + DCIO_DBG_CLOCK_SEL_DISPCLK = 0x0, + DCIO_DBG_CLOCK_SEL_SYMCLKA = 0x1, + DCIO_DBG_CLOCK_SEL_SYMCLKB = 0x2, + DCIO_DBG_CLOCK_SEL_SYMCLKC = 0x3, + DCIO_DBG_CLOCK_SEL_SYMCLKD = 0x4, + DCIO_DBG_CLOCK_SEL_SYMCLKE = 0x5, + DCIO_DBG_CLOCK_SEL_SYMCLKF = 0x6, + DCIO_DBG_CLOCK_SEL_REFCLK = 0xb, +} DCIO_DBG_CLOCK_SEL; +typedef enum DCIOCHIP_HPD_SEL { + DCIOCHIP_HPD_SEL_ASYNC = 0x0, + DCIOCHIP_HPD_SEL_CLOCKED = 0x1, +} DCIOCHIP_HPD_SEL; +typedef enum DCIOCHIP_PAD_MODE { + DCIOCHIP_PAD_MODE_DDC = 0x0, + DCIOCHIP_PAD_MODE_DP = 0x1, +} DCIOCHIP_PAD_MODE; +typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { + DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0, + DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1, +} DCIOCHIP_AUXSLAVE_PAD_MODE; +typedef enum DCIOCHIP_INVERT { + DCIOCHIP_POL_NON_INVERT = 0x0, + DCIOCHIP_POL_INVERT = 0x1, +} DCIOCHIP_INVERT; +typedef enum DCIOCHIP_PD_EN { + DCIOCHIP_PD_EN_NOTALLOW = 0x0, + DCIOCHIP_PD_EN_ALLOW = 0x1, +} DCIOCHIP_PD_EN; +typedef enum DCIOCHIP_GPIO_MASK_EN { + DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0, + DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1, +} DCIOCHIP_GPIO_MASK_EN; +typedef enum DCIOCHIP_MASK { + DCIOCHIP_MASK_DISABLE = 0x0, + DCIOCHIP_MASK_ENABLE = 0x1, +} DCIOCHIP_MASK; +typedef enum DCIOCHIP_GPIO_I2C_MASK { + DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0, + DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1, +} DCIOCHIP_GPIO_I2C_MASK; +typedef enum DCIOCHIP_GPIO_I2C_DRIVE { + DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0, + DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1, +} DCIOCHIP_GPIO_I2C_DRIVE; +typedef enum DCIOCHIP_GPIO_I2C_EN { + DCIOCHIP_GPIO_I2C_DISABLE = 0x0, + DCIOCHIP_GPIO_I2C_ENABLE = 0x1, +} DCIOCHIP_GPIO_I2C_EN; +typedef enum DCIOCHIP_MASK_4BIT { + DCIOCHIP_MASK_4BIT_DISABLE = 0x0, + DCIOCHIP_MASK_4BIT_ENABLE = 0xf, +} DCIOCHIP_MASK_4BIT; +typedef enum DCIOCHIP_ENABLE_4BIT { + DCIOCHIP_4BIT_DISABLE = 0x0, + DCIOCHIP_4BIT_ENABLE = 0xf, +} DCIOCHIP_ENABLE_4BIT; +typedef enum DCIOCHIP_MASK_5BIT { + DCIOCHIP_MASIK_5BIT_DISABLE = 0x0, + DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f, +} DCIOCHIP_MASK_5BIT; +typedef enum DCIOCHIP_ENABLE_5BIT { + DCIOCHIP_5BIT_DISABLE = 0x0, + DCIOCHIP_5BIT_ENABLE = 0x1f, +} DCIOCHIP_ENABLE_5BIT; +typedef enum DCIOCHIP_MASK_2BIT { + DCIOCHIP_MASK_2BIT_DISABLE = 0x0, + DCIOCHIP_MASK_2BIT_ENABLE = 0x3, +} DCIOCHIP_MASK_2BIT; +typedef enum DCIOCHIP_ENABLE_2BIT { + DCIOCHIP_2BIT_DISABLE = 0x0, + DCIOCHIP_2BIT_ENABLE = 0x3, +} DCIOCHIP_ENABLE_2BIT; +typedef enum DCIOCHIP_REF_27_SRC_SEL { + DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0, + DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1, + DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2, + DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3, +} DCIOCHIP_REF_27_SRC_SEL; +typedef enum DCIOCHIP_DVO_VREFPON { + DCIOCHIP_DVO_VREFPON_DISABLE = 0x0, + DCIOCHIP_DVO_VREFPON_ENABLE = 0x1, +} DCIOCHIP_DVO_VREFPON; +typedef enum DCIOCHIP_DVO_VREFSEL { + DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0, + DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1, +} DCIOCHIP_DVO_VREFSEL; +typedef enum DCIOCHIP_SPDIF1_IMODE { + DCIOCHIP_SPDIF1_IMODE_OE_A = 0x0, + DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x1, +} DCIOCHIP_SPDIF1_IMODE; +typedef enum DCIOCHIP_AUX_FALLSLEWSEL { + DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x0, + DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x1, + DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x2, + DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x3, +} DCIOCHIP_AUX_FALLSLEWSEL; +typedef enum DCIOCHIP_AUX_SPIKESEL { + DCIOCHIP_AUX_SPIKESEL_50NS = 0x0, + DCIOCHIP_AUX_SPIKESEL_10NS = 0x1, +} DCIOCHIP_AUX_SPIKESEL; +typedef enum DCIOCHIP_AUX_CSEL0P9 { + DCIOCHIP_AUX_CSEL_DEC1P0 = 0x0, + DCIOCHIP_AUX_CSEL_DEC0P9 = 0x1, +} DCIOCHIP_AUX_CSEL0P9; +typedef enum DCIOCHIP_AUX_CSEL1P1 { + DCIOCHIP_AUX_CSEL_INC1P0 = 0x0, + DCIOCHIP_AUX_CSEL_INC1P1 = 0x1, +} DCIOCHIP_AUX_CSEL1P1; +typedef enum DCIOCHIP_AUX_RSEL0P9 { + DCIOCHIP_AUX_RSEL_DEC1P0 = 0x0, + DCIOCHIP_AUX_RSEL_DEC0P9 = 0x1, +} DCIOCHIP_AUX_RSEL0P9; +typedef enum DCIOCHIP_AUX_RSEL1P1 { + DCIOCHIP_AUX_RSEL_INC1P0 = 0x0, + DCIOCHIP_AUX_RSEL_INC1P1 = 0x1, +} DCIOCHIP_AUX_RSEL1P1; +typedef enum DCP_GRPH_ENABLE { + DCP_GRPH_ENABLE_FALSE = 0x0, + DCP_GRPH_ENABLE_TRUE = 0x1, +} DCP_GRPH_ENABLE; +typedef enum DCP_GRPH_KEYER_ALPHA_SEL { + DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x0, + DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x1, +} DCP_GRPH_KEYER_ALPHA_SEL; +typedef enum DCP_GRPH_DEPTH { + DCP_GRPH_DEPTH_8BPP = 0x0, + DCP_GRPH_DEPTH_16BPP = 0x1, + DCP_GRPH_DEPTH_32BPP = 0x2, + DCP_GRPH_DEPTH_64BPP = 0x3, +} DCP_GRPH_DEPTH; +typedef enum DCP_GRPH_NUM_BANKS { + DCP_GRPH_NUM_BANKS_2BANK = 0x0, + DCP_GRPH_NUM_BANKS_4BANK = 0x1, + DCP_GRPH_NUM_BANKS_8BANK = 0x2, + DCP_GRPH_NUM_BANKS_16BANK = 0x3, +} DCP_GRPH_NUM_BANKS; +typedef enum DCP_GRPH_BANK_WIDTH { + DCP_GRPH_BANK_WIDTH_1 = 0x0, + DCP_GRPH_BANK_WIDTH_2 = 0x1, + DCP_GRPH_BANK_WIDTH_4 = 0x2, + DCP_GRPH_BANK_WIDTH_8 = 0x3, +} DCP_GRPH_BANK_WIDTH; +typedef enum DCP_GRPH_FORMAT { + DCP_GRPH_FORMAT_8BPP = 0x0, + DCP_GRPH_FORMAT_16BPP = 0x1, + DCP_GRPH_FORMAT_32BPP = 0x2, + DCP_GRPH_FORMAT_64BPP = 0x3, +} DCP_GRPH_FORMAT; +typedef enum DCP_GRPH_BANK_HEIGHT { + DCP_GRPH_BANK_HEIGHT_1 = 0x0, + DCP_GRPH_BANK_HEIGHT_2 = 0x1, + DCP_GRPH_BANK_HEIGHT_4 = 0x2, + DCP_GRPH_BANK_HEIGHT_8 = 0x3, +} DCP_GRPH_BANK_HEIGHT; +typedef enum DCP_GRPH_TILE_SPLIT { + DCP_GRPH_TILE_SPLIT_64B = 0x0, + DCP_GRPH_TILE_SPLIT_128B = 0x1, + DCP_GRPH_TILE_SPLIT_256B = 0x2, + DCP_GRPH_TILE_SPLIT_512B = 0x3, + DCP_GRPH_TILE_SPLIT_1B = 0x4, + DCP_GRPH_TILE_SPLIT_2B = 0x5, + DCP_GRPH_TILE_SPLIT_4B = 0x6, +} DCP_GRPH_TILE_SPLIT; +typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE { + DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x0, + DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x1, +} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE; +typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE { + DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE = 0x0, + DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE = 0x1, +} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE; +typedef enum DCP_GRPH_MACRO_TILE_ASPECT { + DCP_GRPH_MACRO_TILE_ASPECT_1 = 0x0, + DCP_GRPH_MACRO_TILE_ASPECT_2 = 0x1, + DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2, + DCP_GRPH_MACRO_TILE_ASPECT_8 = 0x3, +} DCP_GRPH_MACRO_TILE_ASPECT; +typedef enum DCP_GRPH_ARRAY_MODE { + DCP_GRPH_ARRAY_MODE_0 = 0x0, + DCP_GRPH_ARRAY_MODE_1 = 0x1, + DCP_GRPH_ARRAY_MODE_2 = 0x2, + DCP_GRPH_ARRAY_MODE_3 = 0x3, + DCP_GRPH_ARRAY_MODE_4 = 0x4, + DCP_GRPH_ARRAY_MODE_7 = 0x7, + DCP_GRPH_ARRAY_MODE_12 = 0xc, + DCP_GRPH_ARRAY_MODE_13 = 0xd, +} DCP_GRPH_ARRAY_MODE; +typedef enum DCP_GRPH_MICRO_TILE_MODE { + DCP_GRPH_MICRO_TILE_MODE_0 = 0x0, + DCP_GRPH_MICRO_TILE_MODE_1 = 0x1, + DCP_GRPH_MICRO_TILE_MODE_2 = 0x2, + DCP_GRPH_MICRO_TILE_MODE_3 = 0x3, +} DCP_GRPH_MICRO_TILE_MODE; +typedef enum DCP_GRPH_COLOR_EXPANSION_MODE { + DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x0, + DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x1, +} DCP_GRPH_COLOR_EXPANSION_MODE; +typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN { + DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x0, + DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x1, +} DCP_GRPH_LUT_10BIT_BYPASS_EN; +typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN { + DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x0, + DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x1, +} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN; +typedef enum DCP_GRPH_ENDIAN_SWAP { + DCP_GRPH_ENDIAN_SWAP_NONE = 0x0, + DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x1, + DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2, + DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x3, +} DCP_GRPH_ENDIAN_SWAP; +typedef enum DCP_GRPH_RED_CROSSBAR { + DCP_GRPH_RED_CROSSBAR_FROM_R = 0x0, + DCP_GRPH_RED_CROSSBAR_FROM_G = 0x1, + DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2, + DCP_GRPH_RED_CROSSBAR_FROM_A = 0x3, +} DCP_GRPH_RED_CROSSBAR; +typedef enum DCP_GRPH_GREEN_CROSSBAR { + DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x0, + DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x1, + DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2, + DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x3, +} DCP_GRPH_GREEN_CROSSBAR; +typedef enum DCP_GRPH_BLUE_CROSSBAR { + DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x0, + DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x1, + DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2, + DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x3, +} DCP_GRPH_BLUE_CROSSBAR; +typedef enum DCP_GRPH_ALPHA_CROSSBAR { + DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x0, + DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x1, + DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2, + DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x3, +} DCP_GRPH_ALPHA_CROSSBAR; +typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE { + DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x0, + DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x1, +} DCP_GRPH_PRIMARY_DFQ_ENABLE; +typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE { + DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x0, + DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x1, +} DCP_GRPH_SECONDARY_DFQ_ENABLE; +typedef enum DCP_GRPH_INPUT_GAMMA_MODE { + DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x0, + DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x1, +} DCP_GRPH_INPUT_GAMMA_MODE; +typedef enum DCP_GRPH_MODE_UPDATE_PENDING { + DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x0, + DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x1, +} DCP_GRPH_MODE_UPDATE_PENDING; +typedef enum DCP_GRPH_MODE_UPDATE_TAKEN { + DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x0, + DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x1, +} DCP_GRPH_MODE_UPDATE_TAKEN; +typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING { + DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x0, + DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x1, +} DCP_GRPH_SURFACE_UPDATE_PENDING; +typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN { + DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x0, + DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x1, +} DCP_GRPH_SURFACE_UPDATE_TAKEN; +typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE { + DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x0, + DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x1, +} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE; +typedef enum DCP_GRPH_UPDATE_LOCK { + DCP_GRPH_UPDATE_LOCK_FALSE = 0x0, + DCP_GRPH_UPDATE_LOCK_TRUE = 0x1, +} DCP_GRPH_UPDATE_LOCK; +typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { + DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x0, + DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x1, +} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; +typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { + DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, + DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, +} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; +typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { + DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, + DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, +} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; +typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN { + DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x0, + DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x1, +} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN; +typedef enum DCP_GRPH_XDMA_SUPER_AA_EN { + DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x0, + DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x1, +} DCP_GRPH_XDMA_SUPER_AA_EN; +typedef enum DCP_GRPH_DFQ_RESET { + DCP_GRPH_DFQ_RESET_FALSE = 0x0, + DCP_GRPH_DFQ_RESET_TRUE = 0x1, +} DCP_GRPH_DFQ_RESET; +typedef enum DCP_GRPH_DFQ_SIZE { + DCP_GRPH_DFQ_SIZE_DEEP1 = 0x0, + DCP_GRPH_DFQ_SIZE_DEEP2 = 0x1, + DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2, + DCP_GRPH_DFQ_SIZE_DEEP4 = 0x3, + DCP_GRPH_DFQ_SIZE_DEEP5 = 0x4, + DCP_GRPH_DFQ_SIZE_DEEP6 = 0x5, + DCP_GRPH_DFQ_SIZE_DEEP7 = 0x6, + DCP_GRPH_DFQ_SIZE_DEEP8 = 0x7, +} DCP_GRPH_DFQ_SIZE; +typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES { + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x0, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x1, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x3, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x4, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x5, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x6, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x7, +} DCP_GRPH_DFQ_MIN_FREE_ENTRIES; +typedef enum DCP_GRPH_DFQ_RESET_ACK { + DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x0, + DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x1, +} DCP_GRPH_DFQ_RESET_ACK; +typedef enum DCP_GRPH_PFLIP_INT_CLEAR { + DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x0, + DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x1, +} DCP_GRPH_PFLIP_INT_CLEAR; +typedef enum DCP_GRPH_PFLIP_INT_MASK { + DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x0, + DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x1, +} DCP_GRPH_PFLIP_INT_MASK; +typedef enum DCP_GRPH_PFLIP_INT_TYPE { + DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x0, + DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x1, +} DCP_GRPH_PFLIP_INT_TYPE; +typedef enum DCP_GRPH_PRESCALE_SELECT { + DCP_GRPH_PRESCALE_SELECT_FIXED = 0x0, + DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x1, +} DCP_GRPH_PRESCALE_SELECT; +typedef enum DCP_GRPH_PRESCALE_R_SIGN { + DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x0, + DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x1, +} DCP_GRPH_PRESCALE_R_SIGN; +typedef enum DCP_GRPH_PRESCALE_G_SIGN { + DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x0, + DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x1, +} DCP_GRPH_PRESCALE_G_SIGN; +typedef enum DCP_GRPH_PRESCALE_B_SIGN { + DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x0, + DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x1, +} DCP_GRPH_PRESCALE_B_SIGN; +typedef enum DCP_GRPH_PRESCALE_BYPASS { + DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x0, + DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x1, +} DCP_GRPH_PRESCALE_BYPASS; +typedef enum DCP_INPUT_CSC_GRPH_MODE { + DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x0, + DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x1, + DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2, + DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x3, +} DCP_INPUT_CSC_GRPH_MODE; +typedef enum DCP_OUTPUT_CSC_GRPH_MODE { + DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x0, + DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x1, + DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2, + DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x3, + DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x4, + DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x5, + DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x6, + DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x7, +} DCP_OUTPUT_CSC_GRPH_MODE; +typedef enum DCP_DENORM_MODE { + DCP_DENORM_MODE_UNITY = 0x0, + DCP_DENORM_MODE_6BIT = 0x1, + DCP_DENORM_MODE_8BIT = 0x2, + DCP_DENORM_MODE_10BIT = 0x3, + DCP_DENORM_MODE_11BIT = 0x4, + DCP_DENORM_MODE_12BIT = 0x5, + DCP_DENORM_MODE_RESERVED0 = 0x6, + DCP_DENORM_MODE_RESERVED1 = 0x7, +} DCP_DENORM_MODE; +typedef enum DCP_DENORM_14BIT_OUT { + DCP_DENORM_14BIT_OUT_FALSE = 0x0, + DCP_DENORM_14BIT_OUT_TRUE = 0x1, +} DCP_DENORM_14BIT_OUT; +typedef enum DCP_OUT_ROUND_TRUNC_MODE { + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x0, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x1, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x3, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x4, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x5, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x6, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x7, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x8, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x9, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0xa, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0xb, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0xc, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0xd, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0xe, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0xf, +} DCP_OUT_ROUND_TRUNC_MODE; +typedef enum DCP_KEY_MODE { + DCP_KEY_MODE_ALPHA0 = 0x0, + DCP_KEY_MODE_ALPHA1 = 0x1, + DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2, + DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x3, +} DCP_KEY_MODE; +typedef enum DCP_GRPH_DEGAMMA_MODE { + DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x0, + DCP_GRPH_DEGAMMA_MODE_ROMA = 0x1, + DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2, + DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x3, +} DCP_GRPH_DEGAMMA_MODE; +typedef enum DCP_CURSOR2_DEGAMMA_MODE { + DCP_CURSOR2_DEGAMMA_MODE_BYPASS = 0x0, + DCP_CURSOR2_DEGAMMA_MODE_ROMA = 0x1, + DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2, + DCP_CURSOR2_DEGAMMA_MODE_RESERVED = 0x3, +} DCP_CURSOR2_DEGAMMA_MODE; +typedef enum DCP_CURSOR_DEGAMMA_MODE { + DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x0, + DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x1, + DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2, + DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x3, +} DCP_CURSOR_DEGAMMA_MODE; +typedef enum DCP_GRPH_GAMUT_REMAP_MODE { + DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x0, + DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x1, + DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2, + DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x3, +} DCP_GRPH_GAMUT_REMAP_MODE; +typedef enum DCP_SPATIAL_DITHER_EN { + DCP_SPATIAL_DITHER_EN_FALSE = 0x0, + DCP_SPATIAL_DITHER_EN_TRUE = 0x1, +} DCP_SPATIAL_DITHER_EN; +typedef enum DCP_SPATIAL_DITHER_MODE { + DCP_SPATIAL_DITHER_MODE_BYPASS = 0x0, + DCP_SPATIAL_DITHER_MODE_ROMA = 0x1, + DCP_SPATIAL_DITHER_MODE_ROMB = 0x2, + DCP_SPATIAL_DITHER_MODE_RESERVED = 0x3, +} DCP_SPATIAL_DITHER_MODE; +typedef enum DCP_SPATIAL_DITHER_DEPTH { + DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x0, + DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x1, + DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2, + DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x3, +} DCP_SPATIAL_DITHER_DEPTH; +typedef enum DCP_FRAME_RANDOM_ENABLE { + DCP_FRAME_RANDOM_ENABLE_FALSE = 0x0, + DCP_FRAME_RANDOM_ENABLE_TRUE = 0x1, +} DCP_FRAME_RANDOM_ENABLE; +typedef enum DCP_RGB_RANDOM_ENABLE { + DCP_RGB_RANDOM_ENABLE_FALSE = 0x0, + DCP_RGB_RANDOM_ENABLE_TRUE = 0x1, +} DCP_RGB_RANDOM_ENABLE; +typedef enum DCP_HIGHPASS_RANDOM_ENABLE { + DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x0, + DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x1, +} DCP_HIGHPASS_RANDOM_ENABLE; +typedef enum DCP_CURSOR_EN { + DCP_CURSOR_EN_FALSE = 0x0, + DCP_CURSOR_EN_TRUE = 0x1, +} DCP_CURSOR_EN; +typedef enum DCP_CUR_INV_TRANS_CLAMP { + DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x0, + DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x1, +} DCP_CUR_INV_TRANS_CLAMP; +typedef enum DCP_CURSOR_MODE { + DCP_CURSOR_MODE_MONO_2BPP = 0x0, + DCP_CURSOR_MODE_24BPP_1BIT = 0x1, + DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2, + DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x3, +} DCP_CURSOR_MODE; +typedef enum DCP_CURSOR_2X_MAGNIFY { + DCP_CURSOR_2X_MAGNIFY_FALSE = 0x0, + DCP_CURSOR_2X_MAGNIFY_TRUE = 0x1, +} DCP_CURSOR_2X_MAGNIFY; +typedef enum DCP_CURSOR_FORCE_MC_ON { + DCP_CURSOR_FORCE_MC_ON_FALSE = 0x0, + DCP_CURSOR_FORCE_MC_ON_TRUE = 0x1, +} DCP_CURSOR_FORCE_MC_ON; +typedef enum DCP_CURSOR_URGENT_CONTROL { + DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x0, + DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x1, + DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2, + DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x3, + DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x4, +} DCP_CURSOR_URGENT_CONTROL; +typedef enum DCP_CURSOR_UPDATE_PENDING { + DCP_CURSOR_UPDATE_PENDING_FALSE = 0x0, + DCP_CURSOR_UPDATE_PENDING_TRUE = 0x1, +} DCP_CURSOR_UPDATE_PENDING; +typedef enum DCP_CURSOR_UPDATE_TAKEN { + DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x0, + DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x1, +} DCP_CURSOR_UPDATE_TAKEN; +typedef enum DCP_CURSOR_UPDATE_LOCK { + DCP_CURSOR_UPDATE_LOCK_FALSE = 0x0, + DCP_CURSOR_UPDATE_LOCK_TRUE = 0x1, +} DCP_CURSOR_UPDATE_LOCK; +typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE { + DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, + DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, +} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE; +typedef enum DCP_CURSOR_UPDATE_STEREO_MODE { + DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x0, + DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1, + DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2, + DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3, +} DCP_CURSOR_UPDATE_STEREO_MODE; +typedef enum DCP_CURSOR2_EN { + DCP_CURSOR2_EN_FALSE = 0x0, + DCP_CURSOR2_EN_TRUE = 0x1, +} DCP_CURSOR2_EN; +typedef enum DCP_CUR2_INV_TRANS_CLAMP { + DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x0, + DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x1, +} DCP_CUR2_INV_TRANS_CLAMP; +typedef enum DCP_CURSOR2_MODE { + DCP_CURSOR2_MODE_MONO_2BPP = 0x0, + DCP_CURSOR2_MODE_24BPP_1BIT = 0x1, + DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2, + DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI = 0x3, +} DCP_CURSOR2_MODE; +typedef enum DCP_CURSOR2_2X_MAGNIFY { + DCP_CURSOR2_2X_MAGNIFY_FALSE = 0x0, + DCP_CURSOR2_2X_MAGNIFY_TRUE = 0x1, +} DCP_CURSOR2_2X_MAGNIFY; +typedef enum DCP_CURSOR2_FORCE_MC_ON { + DCP_CURSOR2_FORCE_MC_ON_FALSE = 0x0, + DCP_CURSOR2_FORCE_MC_ON_TRUE = 0x1, +} DCP_CURSOR2_FORCE_MC_ON; +typedef enum DCP_CURSOR2_URGENT_CONTROL { + DCP_CURSOR2_URGENT_CONTROL_MODE_0 = 0x0, + DCP_CURSOR2_URGENT_CONTROL_MODE_1 = 0x1, + DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2, + DCP_CURSOR2_URGENT_CONTROL_MODE_3 = 0x3, + DCP_CURSOR2_URGENT_CONTROL_MODE_4 = 0x4, +} DCP_CURSOR2_URGENT_CONTROL; +typedef enum DCP_CURSOR2_UPDATE_PENDING { + DCP_CURSOR2_UPDATE_PENDING_FALSE = 0x0, + DCP_CURSOR2_UPDATE_PENDING_TRUE = 0x1, +} DCP_CURSOR2_UPDATE_PENDING; +typedef enum DCP_CURSOR2_UPDATE_TAKEN { + DCP_CURSOR2_UPDATE_TAKEN_FALSE = 0x0, + DCP_CURSOR2_UPDATE_TAKEN_TRUE = 0x1, +} DCP_CURSOR2_UPDATE_TAKEN; +typedef enum DCP_CURSOR2_UPDATE_LOCK { + DCP_CURSOR2_UPDATE_LOCK_FALSE = 0x0, + DCP_CURSOR2_UPDATE_LOCK_TRUE = 0x1, +} DCP_CURSOR2_UPDATE_LOCK; +typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE { + DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, + DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, +} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE; +typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE { + DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH = 0x0, + DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1, + DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2, + DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3, +} DCP_CURSOR2_UPDATE_STEREO_MODE; +typedef enum DCP_CUR_REQUEST_FILTER_DIS { + DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x0, + DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x1, +} DCP_CUR_REQUEST_FILTER_DIS; +typedef enum DCP_CURSOR_STEREO_EN { + DCP_CURSOR_STEREO_EN_FALSE = 0x0, + DCP_CURSOR_STEREO_EN_TRUE = 0x1, +} DCP_CURSOR_STEREO_EN; +typedef enum DCP_CURSOR_STEREO_OFFSET_YNX { + DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x0, + DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x1, +} DCP_CURSOR_STEREO_OFFSET_YNX; +typedef enum DCP_CURSOR2_STEREO_EN { + DCP_CURSOR2_STEREO_EN_FALSE = 0x0, + DCP_CURSOR2_STEREO_EN_TRUE = 0x1, +} DCP_CURSOR2_STEREO_EN; +typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX { + DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION = 0x0, + DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION = 0x1, +} DCP_CURSOR2_STEREO_OFFSET_YNX; +typedef enum DCP_DC_LUT_RW_MODE { + DCP_DC_LUT_RW_MODE_256_ENTRY = 0x0, + DCP_DC_LUT_RW_MODE_PWL = 0x1, +} DCP_DC_LUT_RW_MODE; +typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE { + DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x0, + DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x1, +} DCP_DC_LUT_VGA_ACCESS_ENABLE; +typedef enum DCP_DC_LUT_AUTOFILL { + DCP_DC_LUT_AUTOFILL_FALSE = 0x0, + DCP_DC_LUT_AUTOFILL_TRUE = 0x1, +} DCP_DC_LUT_AUTOFILL; +typedef enum DCP_DC_LUT_AUTOFILL_DONE { + DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x0, + DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x1, +} DCP_DC_LUT_AUTOFILL_DONE; +typedef enum DCP_DC_LUT_INC_B { + DCP_DC_LUT_INC_B_NA = 0x0, + DCP_DC_LUT_INC_B_2 = 0x1, + DCP_DC_LUT_INC_B_4 = 0x2, + DCP_DC_LUT_INC_B_8 = 0x3, + DCP_DC_LUT_INC_B_16 = 0x4, + DCP_DC_LUT_INC_B_32 = 0x5, + DCP_DC_LUT_INC_B_64 = 0x6, + DCP_DC_LUT_INC_B_128 = 0x7, + DCP_DC_LUT_INC_B_256 = 0x8, + DCP_DC_LUT_INC_B_512 = 0x9, +} DCP_DC_LUT_INC_B; +typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN { + DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_B_SIGNED_EN; +typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN { + DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN; +typedef enum DCP_DC_LUT_DATA_B_FORMAT { + DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x0, + DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x1, + DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2, + DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x3, +} DCP_DC_LUT_DATA_B_FORMAT; +typedef enum DCP_DC_LUT_INC_G { + DCP_DC_LUT_INC_G_NA = 0x0, + DCP_DC_LUT_INC_G_2 = 0x1, + DCP_DC_LUT_INC_G_4 = 0x2, + DCP_DC_LUT_INC_G_8 = 0x3, + DCP_DC_LUT_INC_G_16 = 0x4, + DCP_DC_LUT_INC_G_32 = 0x5, + DCP_DC_LUT_INC_G_64 = 0x6, + DCP_DC_LUT_INC_G_128 = 0x7, + DCP_DC_LUT_INC_G_256 = 0x8, + DCP_DC_LUT_INC_G_512 = 0x9, +} DCP_DC_LUT_INC_G; +typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN { + DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_G_SIGNED_EN; +typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN { + DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN; +typedef enum DCP_DC_LUT_DATA_G_FORMAT { + DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x0, + DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x1, + DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2, + DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x3, +} DCP_DC_LUT_DATA_G_FORMAT; +typedef enum DCP_DC_LUT_INC_R { + DCP_DC_LUT_INC_R_NA = 0x0, + DCP_DC_LUT_INC_R_2 = 0x1, + DCP_DC_LUT_INC_R_4 = 0x2, + DCP_DC_LUT_INC_R_8 = 0x3, + DCP_DC_LUT_INC_R_16 = 0x4, + DCP_DC_LUT_INC_R_32 = 0x5, + DCP_DC_LUT_INC_R_64 = 0x6, + DCP_DC_LUT_INC_R_128 = 0x7, + DCP_DC_LUT_INC_R_256 = 0x8, + DCP_DC_LUT_INC_R_512 = 0x9, +} DCP_DC_LUT_INC_R; +typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN { + DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_R_SIGNED_EN; +typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN { + DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN; +typedef enum DCP_DC_LUT_DATA_R_FORMAT { + DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x0, + DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x1, + DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2, + DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x3, +} DCP_DC_LUT_DATA_R_FORMAT; +typedef enum DCP_CRC_ENABLE { + DCP_CRC_ENABLE_FALSE = 0x0, + DCP_CRC_ENABLE_TRUE = 0x1, +} DCP_CRC_ENABLE; +typedef enum DCP_CRC_SOURCE_SEL { + DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x0, + DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x1, + DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2, + DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x4, +} DCP_CRC_SOURCE_SEL; +typedef enum DCP_CRC_LINE_SEL { + DCP_CRC_LINE_SEL_RESERVED = 0x0, + DCP_CRC_LINE_SEL_EVEN = 0x1, + DCP_CRC_LINE_SEL_ODD = 0x2, + DCP_CRC_LINE_SEL_BOTH = 0x3, +} DCP_CRC_LINE_SEL; +typedef enum DCP_GRPH_FLIP_RATE { + DCP_GRPH_FLIP_RATE_1FRAME = 0x0, + DCP_GRPH_FLIP_RATE_2FRAME = 0x1, + DCP_GRPH_FLIP_RATE_3FRAME = 0x2, + DCP_GRPH_FLIP_RATE_4FRAME = 0x3, + DCP_GRPH_FLIP_RATE_5FRAME = 0x4, + DCP_GRPH_FLIP_RATE_6FRAME = 0x5, + DCP_GRPH_FLIP_RATE_7FRAME = 0x6, + DCP_GRPH_FLIP_RATE_8FRAME = 0x7, +} DCP_GRPH_FLIP_RATE; +typedef enum DCP_GRPH_FLIP_RATE_ENABLE { + DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x0, + DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x1, +} DCP_GRPH_FLIP_RATE_ENABLE; +typedef enum DCP_GSL0_EN { + DCP_GSL0_EN_FALSE = 0x0, + DCP_GSL0_EN_TRUE = 0x1, +} DCP_GSL0_EN; +typedef enum DCP_GSL1_EN { + DCP_GSL1_EN_FALSE = 0x0, + DCP_GSL1_EN_TRUE = 0x1, +} DCP_GSL1_EN; +typedef enum DCP_GSL2_EN { + DCP_GSL2_EN_FALSE = 0x0, + DCP_GSL2_EN_TRUE = 0x1, +} DCP_GSL2_EN; +typedef enum DCP_GSL_MASTER_EN { + DCP_GSL_MASTER_EN_FALSE = 0x0, + DCP_GSL_MASTER_EN_TRUE = 0x1, +} DCP_GSL_MASTER_EN; +typedef enum DCP_GSL_XDMA_GROUP { + DCP_GSL_XDMA_GROUP_VSYNC = 0x0, + DCP_GSL_XDMA_GROUP_HSYNC0 = 0x1, + DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2, + DCP_GSL_XDMA_GROUP_HSYNC2 = 0x3, +} DCP_GSL_XDMA_GROUP; +typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN { + DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x0, + DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x1, +} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN; +typedef enum DCP_GSL_SYNC_SOURCE { + DCP_GSL_SYNC_SOURCE_FLIP = 0x0, + DCP_GSL_SYNC_SOURCE_PHASE0 = 0x1, + DCP_GSL_SYNC_SOURCE_RESET = 0x2, + DCP_GSL_SYNC_SOURCE_PHASE1 = 0x3, +} DCP_GSL_SYNC_SOURCE; +typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING { + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x0, + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x1, +} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING; +typedef enum DCP_TEST_DEBUG_WRITE_EN { + DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x0, + DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x1, +} DCP_TEST_DEBUG_WRITE_EN; +typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN { + DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x0, + DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x1, +} DCP_GRPH_STEREOSYNC_FLIP_EN; +typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE { + DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x0, + DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x1, + DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2, + DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x3, +} DCP_GRPH_STEREOSYNC_FLIP_MODE; +typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE { + DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x0, + DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x1, +} DCP_GRPH_STEREOSYNC_SELECT_DISABLE; +typedef enum DCP_GRPH_ROTATION_ANGLE { + DCP_GRPH_ROTATION_ANGLE_0 = 0x0, + DCP_GRPH_ROTATION_ANGLE_90 = 0x1, + DCP_GRPH_ROTATION_ANGLE_180 = 0x2, + DCP_GRPH_ROTATION_ANGLE_270 = 0x3, +} DCP_GRPH_ROTATION_ANGLE; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE; +typedef enum DCP_GRPH_REGAMMA_MODE { + DCP_GRPH_REGAMMA_MODE_BYPASS = 0x0, + DCP_GRPH_REGAMMA_MODE_SRGB = 0x1, + DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2, + DCP_GRPH_REGAMMA_MODE_PROGA = 0x3, + DCP_GRPH_REGAMMA_MODE_PROGB = 0x4, +} DCP_GRPH_REGAMMA_MODE; +typedef enum DCP_ALPHA_ROUND_TRUNC_MODE { + DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x0, + DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x1, +} DCP_ALPHA_ROUND_TRUNC_MODE; +typedef enum DCP_CURSOR_ALPHA_BLND_ENA { + DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x0, + DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x1, +} DCP_CURSOR_ALPHA_BLND_ENA; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK; +typedef enum DCP_GRPH_SURFACE_COUNTER_EN { + DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x0, + DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x1, +} DCP_GRPH_SURFACE_COUNTER_EN; +typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT { + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x0, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x1, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x3, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x4, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x5, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x6, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x7, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x8, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x9, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0xa, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0xb, +} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT; +typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED { + DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x0, + DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x1, +} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED; +typedef enum HDMI_KEEPOUT_MODE { + HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x0, + HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x1, +} HDMI_KEEPOUT_MODE; +typedef enum HDMI_CLOCK_CHANNEL_RATE { + HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x0, + HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x1, +} HDMI_CLOCK_CHANNEL_RATE; +typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { + HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x0, + HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x1, +} HDMI_NO_EXTRA_NULL_PACKET_FILLED; +typedef enum HDMI_PACKET_GEN_VERSION { + HDMI_PACKET_GEN_VERSION_OLD = 0x0, + HDMI_PACKET_GEN_VERSION_NEW = 0x1, +} HDMI_PACKET_GEN_VERSION; +typedef enum HDMI_ERROR_ACK { + HDMI_ERROR_ACK_INT = 0x0, + HDMI_ERROR_NOT_ACK = 0x1, +} HDMI_ERROR_ACK; +typedef enum HDMI_ERROR_MASK { + HDMI_ERROR_MASK_INT = 0x0, + HDMI_ERROR_NOT_MASK = 0x1, +} HDMI_ERROR_MASK; +typedef enum HDMI_DEEP_COLOR_DEPTH { + HDMI_DEEP_COLOR_DEPTH_24BPP = 0x0, + HDMI_DEEP_COLOR_DEPTH_30BPP = 0x1, + HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2, + HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x3, +} HDMI_DEEP_COLOR_DEPTH; +typedef enum HDMI_AUDIO_DELAY_EN { + HDMI_AUDIO_DELAY_DISABLE = 0x0, + HDMI_AUDIO_DELAY_58CLK = 0x1, + HDMI_AUDIO_DELAY_56CLK = 0x2, + HDMI_AUDIO_DELAY_RESERVED = 0x3, +} HDMI_AUDIO_DELAY_EN; +typedef enum HDMI_AUDIO_SEND_MAX_PACKETS { + HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x0, + HDMI_SEND_MAX_AUDIO_PACKETS = 0x1, +} HDMI_AUDIO_SEND_MAX_PACKETS; +typedef enum HDMI_ACR_SEND { + HDMI_ACR_NOT_SEND = 0x0, + HDMI_ACR_PKT_SEND = 0x1, +} HDMI_ACR_SEND; +typedef enum HDMI_ACR_CONT { + HDMI_ACR_CONT_DISABLE = 0x0, + HDMI_ACR_CONT_ENABLE = 0x1, +} HDMI_ACR_CONT; +typedef enum HDMI_ACR_SELECT { + HDMI_ACR_SELECT_HW = 0x0, + HDMI_ACR_SELECT_32K = 0x1, + HDMI_ACR_SELECT_44K = 0x2, + HDMI_ACR_SELECT_48K = 0x3, +} HDMI_ACR_SELECT; +typedef enum HDMI_ACR_SOURCE { + HDMI_ACR_SOURCE_HW = 0x0, + HDMI_ACR_SOURCE_SW = 0x1, +} HDMI_ACR_SOURCE; +typedef enum HDMI_ACR_N_MULTIPLE { + HDMI_ACR_0_MULTIPLE_RESERVED = 0x0, + HDMI_ACR_1_MULTIPLE = 0x1, + HDMI_ACR_2_MULTIPLE = 0x2, + HDMI_ACR_3_MULTIPLE_RESERVED = 0x3, + HDMI_ACR_4_MULTIPLE = 0x4, + HDMI_ACR_5_MULTIPLE_RESERVED = 0x5, + HDMI_ACR_6_MULTIPLE_RESERVED = 0x6, + HDMI_ACR_7_MULTIPLE_RESERVED = 0x7, +} HDMI_ACR_N_MULTIPLE; +typedef enum HDMI_ACR_AUDIO_PRIORITY { + HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x0, + HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x1, +} HDMI_ACR_AUDIO_PRIORITY; +typedef enum HDMI_NULL_SEND { + HDMI_NULL_NOT_SEND = 0x0, + HDMI_NULL_PKT_SEND = 0x1, +} HDMI_NULL_SEND; +typedef enum HDMI_GC_SEND { + HDMI_GC_NOT_SEND = 0x0, + HDMI_GC_PKT_SEND = 0x1, +} HDMI_GC_SEND; +typedef enum HDMI_GC_CONT { + HDMI_GC_CONT_DISABLE = 0x0, + HDMI_GC_CONT_ENABLE = 0x1, +} HDMI_GC_CONT; +typedef enum HDMI_ISRC_SEND { + HDMI_ISRC_NOT_SEND = 0x0, + HDMI_ISRC_PKT_SEND = 0x1, +} HDMI_ISRC_SEND; +typedef enum HDMI_ISRC_CONT { + HDMI_ISRC_CONT_DISABLE = 0x0, + HDMI_ISRC_CONT_ENABLE = 0x1, +} HDMI_ISRC_CONT; +typedef enum HDMI_AVI_INFO_SEND { + HDMI_AVI_INFO_NOT_SEND = 0x0, + HDMI_AVI_INFO_PKT_SEND = 0x1, +} HDMI_AVI_INFO_SEND; +typedef enum HDMI_AVI_INFO_CONT { + HDMI_AVI_INFO_CONT_DISABLE = 0x0, + HDMI_AVI_INFO_CONT_ENABLE = 0x1, +} HDMI_AVI_INFO_CONT; +typedef enum HDMI_AUDIO_INFO_SEND { + HDMI_AUDIO_INFO_NOT_SEND = 0x0, + HDMI_AUDIO_INFO_PKT_SEND = 0x1, +} HDMI_AUDIO_INFO_SEND; +typedef enum HDMI_AUDIO_INFO_CONT { + HDMI_AUDIO_INFO_CONT_DISABLE = 0x0, + HDMI_AUDIO_INFO_CONT_ENABLE = 0x1, +} HDMI_AUDIO_INFO_CONT; +typedef enum HDMI_MPEG_INFO_SEND { + HDMI_MPEG_INFO_NOT_SEND = 0x0, + HDMI_MPEG_INFO_PKT_SEND = 0x1, +} HDMI_MPEG_INFO_SEND; +typedef enum HDMI_MPEG_INFO_CONT { + HDMI_MPEG_INFO_CONT_DISABLE = 0x0, + HDMI_MPEG_INFO_CONT_ENABLE = 0x1, +} HDMI_MPEG_INFO_CONT; +typedef enum HDMI_GENERIC0_SEND { + HDMI_GENERIC0_NOT_SEND = 0x0, + HDMI_GENERIC0_PKT_SEND = 0x1, +} HDMI_GENERIC0_SEND; +typedef enum HDMI_GENERIC0_CONT { + HDMI_GENERIC0_CONT_DISABLE = 0x0, + HDMI_GENERIC0_CONT_ENABLE = 0x1, +} HDMI_GENERIC0_CONT; +typedef enum HDMI_GENERIC1_SEND { + HDMI_GENERIC1_NOT_SEND = 0x0, + HDMI_GENERIC1_PKT_SEND = 0x1, +} HDMI_GENERIC1_SEND; +typedef enum HDMI_GENERIC1_CONT { + HDMI_GENERIC1_CONT_DISABLE = 0x0, + HDMI_GENERIC1_CONT_ENABLE = 0x1, +} HDMI_GENERIC1_CONT; +typedef enum HDMI_GC_AVMUTE_CONT { + HDMI_GC_AVMUTE_CONT_DISABLE = 0x0, + HDMI_GC_AVMUTE_CONT_ENABLE = 0x1, +} HDMI_GC_AVMUTE_CONT; +typedef enum HDMI_PACKING_PHASE_OVERRIDE { + HDMI_PACKING_PHASE_SET_BY_HW = 0x0, + HDMI_PACKING_PHASE_SET_BY_SW = 0x1, +} HDMI_PACKING_PHASE_OVERRIDE; +typedef enum HDMI_GENERIC2_SEND { + HDMI_GENERIC2_NOT_SEND = 0x0, + HDMI_GENERIC2_PKT_SEND = 0x1, +} HDMI_GENERIC2_SEND; +typedef enum HDMI_GENERIC2_CONT { + HDMI_GENERIC2_CONT_DISABLE = 0x0, + HDMI_GENERIC2_CONT_ENABLE = 0x1, +} HDMI_GENERIC2_CONT; +typedef enum HDMI_GENERIC3_SEND { + HDMI_GENERIC3_NOT_SEND = 0x0, + HDMI_GENERIC3_PKT_SEND = 0x1, +} HDMI_GENERIC3_SEND; +typedef enum HDMI_GENERIC3_CONT { + HDMI_GENERIC3_CONT_DISABLE = 0x0, + HDMI_GENERIC3_CONT_ENABLE = 0x1, +} HDMI_GENERIC3_CONT; +typedef enum TMDS_PIXEL_ENCODING { + TMDS_PIXEL_ENCODING_444_OR_420 = 0x0, + TMDS_PIXEL_ENCODING_422 = 0x1, +} TMDS_PIXEL_ENCODING; +typedef enum TMDS_COLOR_FORMAT { + TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0, + TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x1, + TMDS_COLOR_FORMAT_DUAL30BPP = 0x2, + TMDS_COLOR_FORMAT_RESERVED = 0x3, +} TMDS_COLOR_FORMAT; +typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { + TMDS_STEREOSYNC_CTL0 = 0x0, + TMDS_STEREOSYNC_CTL1 = 0x1, + TMDS_STEREOSYNC_CTL2 = 0x2, + TMDS_STEREOSYNC_CTL3 = 0x3, +} TMDS_STEREOSYNC_CTL_SEL_REG; +typedef enum TMDS_CTL0_DATA_SEL { + TMDS_CTL0_DATA_SEL0_RESERVED = 0x0, + TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x1, + TMDS_CTL0_DATA_SEL2_VSYNC = 0x2, + TMDS_CTL0_DATA_SEL3_RESERVED = 0x3, + TMDS_CTL0_DATA_SEL4_HSYNC = 0x4, + TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x5, + TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x6, + TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x7, +} TMDS_CTL0_DATA_SEL; +typedef enum TMDS_CTL0_DATA_INVERT { + TMDS_CTL0_DATA_NORMAL = 0x0, + TMDS_CTL0_DATA_INVERT_EN = 0x1, +} TMDS_CTL0_DATA_INVERT; +typedef enum TMDS_CTL0_DATA_MODULATION { + TMDS_CTL0_DATA_MODULATION_DISABLE = 0x0, + TMDS_CTL0_DATA_MODULATION_BIT0 = 0x1, + TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2, + TMDS_CTL0_DATA_MODULATION_BIT2 = 0x3, +} TMDS_CTL0_DATA_MODULATION; +typedef enum TMDS_CTL0_PATTERN_OUT_EN { + TMDS_CTL0_PATTERN_OUT_DISABLE = 0x0, + TMDS_CTL0_PATTERN_OUT_ENABLE = 0x1, +} TMDS_CTL0_PATTERN_OUT_EN; +typedef enum TMDS_CTL1_DATA_SEL { + TMDS_CTL1_DATA_SEL0_RESERVED = 0x0, + TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x1, + TMDS_CTL1_DATA_SEL2_VSYNC = 0x2, + TMDS_CTL1_DATA_SEL3_RESERVED = 0x3, + TMDS_CTL1_DATA_SEL4_HSYNC = 0x4, + TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x5, + TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x6, + TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x7, +} TMDS_CTL1_DATA_SEL; +typedef enum TMDS_CTL1_DATA_INVERT { + TMDS_CTL1_DATA_NORMAL = 0x0, + TMDS_CTL1_DATA_INVERT_EN = 0x1, +} TMDS_CTL1_DATA_INVERT; +typedef enum TMDS_CTL1_DATA_MODULATION { + TMDS_CTL1_DATA_MODULATION_DISABLE = 0x0, + TMDS_CTL1_DATA_MODULATION_BIT0 = 0x1, + TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2, + TMDS_CTL1_DATA_MODULATION_BIT2 = 0x3, +} TMDS_CTL1_DATA_MODULATION; +typedef enum TMDS_CTL1_PATTERN_OUT_EN { + TMDS_CTL1_PATTERN_OUT_DISABLE = 0x0, + TMDS_CTL1_PATTERN_OUT_ENABLE = 0x1, +} TMDS_CTL1_PATTERN_OUT_EN; +typedef enum TMDS_CTL2_DATA_SEL { + TMDS_CTL2_DATA_SEL0_RESERVED = 0x0, + TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x1, + TMDS_CTL2_DATA_SEL2_VSYNC = 0x2, + TMDS_CTL2_DATA_SEL3_RESERVED = 0x3, + TMDS_CTL2_DATA_SEL4_HSYNC = 0x4, + TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x5, + TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x6, + TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x7, +} TMDS_CTL2_DATA_SEL; +typedef enum TMDS_CTL2_DATA_INVERT { + TMDS_CTL2_DATA_NORMAL = 0x0, + TMDS_CTL2_DATA_INVERT_EN = 0x1, +} TMDS_CTL2_DATA_INVERT; +typedef enum TMDS_CTL2_DATA_MODULATION { + TMDS_CTL2_DATA_MODULATION_DISABLE = 0x0, + TMDS_CTL2_DATA_MODULATION_BIT0 = 0x1, + TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2, + TMDS_CTL2_DATA_MODULATION_BIT2 = 0x3, +} TMDS_CTL2_DATA_MODULATION; +typedef enum TMDS_CTL2_PATTERN_OUT_EN { + TMDS_CTL2_PATTERN_OUT_DISABLE = 0x0, + TMDS_CTL2_PATTERN_OUT_ENABLE = 0x1, +} TMDS_CTL2_PATTERN_OUT_EN; +typedef enum TMDS_CTL3_DATA_INVERT { + TMDS_CTL3_DATA_NORMAL = 0x0, + TMDS_CTL3_DATA_INVERT_EN = 0x1, +} TMDS_CTL3_DATA_INVERT; +typedef enum TMDS_CTL3_DATA_MODULATION { + TMDS_CTL3_DATA_MODULATION_DISABLE = 0x0, + TMDS_CTL3_DATA_MODULATION_BIT0 = 0x1, + TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2, + TMDS_CTL3_DATA_MODULATION_BIT2 = 0x3, +} TMDS_CTL3_DATA_MODULATION; +typedef enum TMDS_CTL3_PATTERN_OUT_EN { + TMDS_CTL3_PATTERN_OUT_DISABLE = 0x0, + TMDS_CTL3_PATTERN_OUT_ENABLE = 0x1, +} TMDS_CTL3_PATTERN_OUT_EN; +typedef enum TMDS_CTL3_DATA_SEL { + TMDS_CTL3_DATA_SEL0_RESERVED = 0x0, + TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x1, + TMDS_CTL3_DATA_SEL2_VSYNC = 0x2, + TMDS_CTL3_DATA_SEL3_RESERVED = 0x3, + TMDS_CTL3_DATA_SEL4_HSYNC = 0x4, + TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x5, + TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x6, + TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x7, +} TMDS_CTL3_DATA_SEL; +typedef enum DIG_FE_CNTL_SOURCE_SELECT { + DIG_FE_SOURCE_FROM_FMT0 = 0x0, + DIG_FE_SOURCE_FROM_FMT1 = 0x1, + DIG_FE_SOURCE_FROM_FMT2 = 0x2, + DIG_FE_SOURCE_FROM_FMT3 = 0x3, + DIG_FE_SOURCE_FROM_FMT4 = 0x4, + DIG_FE_SOURCE_FROM_FMT5 = 0x5, +} DIG_FE_CNTL_SOURCE_SELECT; +typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { + DIG_FE_STEREOSYNC_FROM_FMT0 = 0x0, + DIG_FE_STEREOSYNC_FROM_FMT1 = 0x1, + DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2, + DIG_FE_STEREOSYNC_FROM_FMT3 = 0x3, + DIG_FE_STEREOSYNC_FROM_FMT4 = 0x4, + DIG_FE_STEREOSYNC_FROM_FMT5 = 0x5, +} DIG_FE_CNTL_STEREOSYNC_SELECT; +typedef enum DIG_FIFO_READ_CLOCK_SRC { + DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x0, + DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x1, +} DIG_FIFO_READ_CLOCK_SRC; +typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { + DIG_OUTPUT_CRC_ON_LINK0 = 0x0, + DIG_OUTPUT_CRC_ON_LINK1 = 0x1, +} DIG_OUTPUT_CRC_CNTL_LINK_SEL; +typedef enum DIG_OUTPUT_CRC_DATA_SEL { + DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x0, + DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x1, + DIG_OUTPUT_CRC_FOR_VBI = 0x2, + DIG_OUTPUT_CRC_FOR_AUDIO = 0x3, +} DIG_OUTPUT_CRC_DATA_SEL; +typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { + DIG_IN_NORMAL_OPERATION = 0x0, + DIG_IN_DEBUG_MODE = 0x1, +} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; +typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { + DIG_10BIT_TEST_PATTERN = 0x0, + DIG_ALTERNATING_TEST_PATTERN = 0x1, +} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; +typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { + DIG_TEST_PATTERN_NORMAL = 0x0, + DIG_TEST_PATTERN_RANDOM = 0x1, +} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; +typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { + DIG_RANDOM_PATTERN_ENABLED = 0x0, + DIG_RANDOM_PATTERN_RESETED = 0x1, +} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; +typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { + DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x0, + DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x1, +} DIG_TEST_PATTERN_EXTERNAL_RESET_EN; +typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { + DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x0, + DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x1, +} DIG_RANDOM_PATTERN_SEED_RAN_PAT; +typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL { + DIG_FIFO_USE_OVERWRITE_LEVEL = 0x0, + DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x1, +} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL; +typedef enum DIG_FIFO_ERROR_ACK { + DIG_FIFO_ERROR_ACK_INT = 0x0, + DIG_FIFO_ERROR_NOT_ACK = 0x1, +} DIG_FIFO_ERROR_ACK; +typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE { + DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x0, + DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x1, +} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE; +typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX { + DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x0, + DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1, +} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX; +typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT { + DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK = 0x0, + DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC = 0x1, +} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT; +typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK { + DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT = 0x0, + DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK = 0x1, +} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK; +typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK { + DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT = 0x0, + DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK = 0x1, +} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK; +typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { + AFMT_INTERRUPT_DISABLE = 0x0, + AFMT_INTERRUPT_ENABLE = 0x1, +} AFMT_INTERRUPT_STATUS_CHG_MASK; +typedef enum HDMI_GC_AVMUTE { + HDMI_GC_AVMUTE_SET = 0x0, + HDMI_GC_AVMUTE_UNSET = 0x1, +} HDMI_GC_AVMUTE; +typedef enum HDMI_DEFAULT_PAHSE { + HDMI_DEFAULT_PHASE_IS_0 = 0x0, + HDMI_DEFAULT_PHASE_IS_1 = 0x1, +} HDMI_DEFAULT_PAHSE; +typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { + AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0, + AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x1, +} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; +typedef enum AUDIO_LAYOUT_SELECT { + AUDIO_LAYOUT_0 = 0x0, + AUDIO_LAYOUT_1 = 0x1, +} AUDIO_LAYOUT_SELECT; +typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { + AFMT_AUDIO_CRC_ONESHOT = 0x0, + AFMT_AUDIO_CRC_AUTO_RESTART = 0x1, +} AFMT_AUDIO_CRC_CONTROL_CONT; +typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { + AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x0, + AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x1, +} AFMT_AUDIO_CRC_CONTROL_SOURCE; +typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { + AFMT_AUDIO_CRC_CH0_SIG = 0x0, + AFMT_AUDIO_CRC_CH1_SIG = 0x1, + AFMT_AUDIO_CRC_CH2_SIG = 0x2, + AFMT_AUDIO_CRC_CH3_SIG = 0x3, + AFMT_AUDIO_CRC_CH4_SIG = 0x4, + AFMT_AUDIO_CRC_CH5_SIG = 0x5, + AFMT_AUDIO_CRC_CH6_SIG = 0x6, + AFMT_AUDIO_CRC_CH7_SIG = 0x7, + AFMT_AUDIO_CRC_RESERVED = 0x8, + AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x9, +} AFMT_AUDIO_CRC_CONTROL_CH_SEL; +typedef enum AFMT_RAMP_CONTROL0_SIGN { + AFMT_RAMP_SIGNED = 0x0, + AFMT_RAMP_UNSIGNED = 0x1, +} AFMT_RAMP_CONTROL0_SIGN; +typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { + AFMT_AUDIO_PACKET_SENT_DISABLED = 0x0, + AFMT_AUDIO_PACKET_SENT_ENABLED = 0x1, +} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; +typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { + AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0, + AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x1, +} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; +typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { + AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x0, + AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x1, +} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; +typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { + AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x0, + AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x1, + AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2, + AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x3, + AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x4, + AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x5, + AFMT_AUDIO_SRC_RESERVED = 0x6, +} AFMT_AUDIO_SRC_CONTROL_SELECT; +typedef enum DIG_BE_CNTL_MODE { + DIG_BE_DP_SST_MODE = 0x0, + DIG_BE_RESERVED1 = 0x1, + DIG_BE_TMDS_DVI_MODE = 0x2, + DIG_BE_TMDS_HDMI_MODE = 0x3, + DIG_BE_SDVO_RESERVED = 0x4, + DIG_BE_DP_MST_MODE = 0x5, + DIG_BE_RESERVED2 = 0x6, + DIG_BE_RESERVED3 = 0x7, +} DIG_BE_CNTL_MODE; +typedef enum DIG_BE_CNTL_HPD_SELECT { + DIG_BE_CNTL_HPD1 = 0x0, + DIG_BE_CNTL_HPD2 = 0x1, + DIG_BE_CNTL_HPD3 = 0x2, + DIG_BE_CNTL_HPD4 = 0x3, + DIG_BE_CNTL_HPD5 = 0x4, + DIG_BE_CNTL_HPD6 = 0x5, +} DIG_BE_CNTL_HPD_SELECT; +typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { + LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x0, + LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x1, +} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; +typedef enum TMDS_SYNC_PHASE { + TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x0, + TMDS_SYNC_PHASE_ON_FRAME_START = 0x1, +} TMDS_SYNC_PHASE; +typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { + TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x0, + TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x1, +} TMDS_DATA_SYNCHRONIZATION_DSINTSEL; +typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { + TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x0, + TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x1, +} TMDS_TRANSMITTER_ENABLE_HPD_MASK; +typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { + TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x0, + TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x1, +} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; +typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { + TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x0, + TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x1, +} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { + TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x0, + TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1, + TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2, + TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x3, +} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; +typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { + TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x0, + TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x1, +} TMDS_TRANSMITTER_CONTROL_IDSCKSELA; +typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { + TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x0, + TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x1, +} TMDS_TRANSMITTER_CONTROL_IDSCKSELB; +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { + TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x0, + TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x1, +} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { + TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x0, + TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x1, +} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; +typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { + TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x0, + TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x1, +} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; +typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { + TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x0, + TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x1, +} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; +typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { + TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x0, + TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x1, +} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; +typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { + TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x0, + TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x1, +} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; +typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { + TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x0, + TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x1, +} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; +typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { + TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x0, + TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x1, + TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2, + TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x3, +} TMDS_REG_TEST_OUTPUTA_CNTLA; +typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { + TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x0, + TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x1, + TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2, + TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x3, +} TMDS_REG_TEST_OUTPUTB_CNTLB; +typedef enum DP_LINK_TRAINING_COMPLETE { + DP_LINK_TRAINING_NOT_COMPLETE = 0x0, + DP_LINK_TRAINING_ALREADY_COMPLETE = 0x1, +} DP_LINK_TRAINING_COMPLETE; +typedef enum DP_EMBEDDED_PANEL_MODE { + DP_EXTERNAL_PANEL = 0x0, + DP_EMBEDDED_PANEL = 0x1, +} DP_EMBEDDED_PANEL_MODE; +typedef enum DP_PIXEL_ENCODING { + DP_PIXEL_ENCODING_RGB444 = 0x0, + DP_PIXEL_ENCODING_YCBCR422 = 0x1, + DP_PIXEL_ENCODING_YCBCR444 = 0x2, + DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x3, + DP_PIXEL_ENCODING_Y_ONLY = 0x4, + DP_PIXEL_ENCODING_YCBCR420 = 0x5, + DP_PIXEL_ENCODING_RESERVED = 0x6, +} DP_PIXEL_ENCODING; +typedef enum DP_DYN_RANGE { + DP_DYN_VESA_RANGE = 0x0, + DP_DYN_CEA_RANGE = 0x1, +} DP_DYN_RANGE; +typedef enum DP_YCBCR_RANGE { + DP_YCBCR_RANGE_BT601_5 = 0x0, + DP_YCBCR_RANGE_BT709_5 = 0x1, +} DP_YCBCR_RANGE; +typedef enum DP_COMPONENT_DEPTH { + DP_COMPONENT_DEPTH_6BPC = 0x0, + DP_COMPONENT_DEPTH_8BPC = 0x1, + DP_COMPONENT_DEPTH_10BPC = 0x2, + DP_COMPONENT_DEPTH_12BPC = 0x3, + DP_COMPONENT_DEPTH_16BPC = 0x4, + DP_COMPONENT_DEPTH_RESERVED = 0x5, +} DP_COMPONENT_DEPTH; +typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE { + MSA_MISC0_OVERRIDE_DISABLE = 0x0, + MSA_MISC0_OVERRIDE_ENABLE = 0x1, +} DP_MSA_MISC0_OVERRIDE_ENABLE; +typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE { + MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0x0, + MSA_MISC1_BIT7_OVERRIDE_ENABLE = 0x1, +} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE; +typedef enum DP_UDI_LANES { + DP_UDI_1_LANE = 0x0, + DP_UDI_2_LANES = 0x1, + DP_UDI_LANES_RESERVED = 0x2, + DP_UDI_4_LANES = 0x3, +} DP_UDI_LANES; +typedef enum DP_VID_STREAM_DIS_DEFER { + DP_VID_STREAM_DIS_NO_DEFER = 0x0, + DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x1, + DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2, +} DP_VID_STREAM_DIS_DEFER; +typedef enum DP_STEER_OVERFLOW_ACK { + DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x0, + DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x1, +} DP_STEER_OVERFLOW_ACK; +typedef enum DP_STEER_OVERFLOW_MASK { + DP_STEER_OVERFLOW_MASKED = 0x0, + DP_STEER_OVERFLOW_UNMASK = 0x1, +} DP_STEER_OVERFLOW_MASK; +typedef enum DP_TU_OVERFLOW_ACK { + DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x0, + DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x1, +} DP_TU_OVERFLOW_ACK; +typedef enum DP_VID_TIMING_MODE { + DP_VID_TIMING_MODE_ASYNC = 0x0, + DP_VID_TIMING_MODE_SYNC = 0x1, +} DP_VID_TIMING_MODE; +typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { + DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x0, + DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x1, +} DP_VID_M_N_DOUBLE_BUFFER_MODE; +typedef enum DP_VID_M_N_GEN_EN { + DP_VID_M_N_PROGRAMMED_VIA_REG = 0x0, + DP_VID_M_N_CALC_AUTO = 0x1, +} DP_VID_M_N_GEN_EN; +typedef enum DP_VID_M_DOUBLE_VALUE_EN { + DP_VID_M_INPUT_PIXEL_RATE = 0x0, + DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 0x1, +} DP_VID_M_DOUBLE_VALUE_EN; +typedef enum DP_VID_ENHANCED_FRAME_MODE { + VID_NORMAL_FRAME_MODE = 0x0, + VID_ENHANCED_MODE = 0x1, +} DP_VID_ENHANCED_FRAME_MODE; +typedef enum DP_VID_MSA_TOP_FIELD_MODE { + DP_TOP_FIELD_ONLY = 0x0, + DP_TOP_PLUS_BOTTOM_FIELD = 0x1, +} DP_VID_MSA_TOP_FIELD_MODE; +typedef enum DP_VID_VBID_FIELD_POL { + DP_VID_VBID_FIELD_POL_NORMAL = 0x0, + DP_VID_VBID_FIELD_POL_INV = 0x1, +} DP_VID_VBID_FIELD_POL; +typedef enum DP_VID_STREAM_DISABLE_ACK { + ID_STREAM_DISABLE_NO_ACK = 0x0, + ID_STREAM_DISABLE_ACKED = 0x1, +} DP_VID_STREAM_DISABLE_ACK; +typedef enum DP_VID_STREAM_DISABLE_MASK { + VID_STREAM_DISABLE_MASKED = 0x0, + VID_STREAM_DISABLE_UNMASK = 0x1, +} DP_VID_STREAM_DISABLE_MASK; +typedef enum DPHY_ATEST_SEL_LANE0 { + DPHY_ATEST_LANE0_PRBS_PATTERN = 0x0, + DPHY_ATEST_LANE0_REG_PATTERN = 0x1, +} DPHY_ATEST_SEL_LANE0; +typedef enum DPHY_ATEST_SEL_LANE1 { + DPHY_ATEST_LANE1_PRBS_PATTERN = 0x0, + DPHY_ATEST_LANE1_REG_PATTERN = 0x1, +} DPHY_ATEST_SEL_LANE1; +typedef enum DPHY_ATEST_SEL_LANE2 { + DPHY_ATEST_LANE2_PRBS_PATTERN = 0x0, + DPHY_ATEST_LANE2_REG_PATTERN = 0x1, +} DPHY_ATEST_SEL_LANE2; +typedef enum DPHY_ATEST_SEL_LANE3 { + DPHY_ATEST_LANE3_PRBS_PATTERN = 0x0, + DPHY_ATEST_LANE3_REG_PATTERN = 0x1, +} DPHY_ATEST_SEL_LANE3; +typedef enum DPHY_BYPASS { + DPHY_8B10B_OUTPUT = 0x0, + DPHY_DBG_OUTPUT = 0x1, +} DPHY_BYPASS; +typedef enum DPHY_SKEW_BYPASS { + DPHY_WITH_SKEW = 0x0, + DPHY_NO_SKEW = 0x1, +} DPHY_SKEW_BYPASS; +typedef enum DPHY_TRAINING_PATTERN_SEL { + DPHY_TRAINING_PATTERN_1 = 0x0, + DPHY_TRAINING_PATTERN_2 = 0x1, + DPHY_TRAINING_PATTERN_3 = 0x2, + DPHY_TRAINING_PATTERN_4 = 0x3, +} DPHY_TRAINING_PATTERN_SEL; +typedef enum DPHY_8B10B_RESET { + DPHY_8B10B_NOT_RESET = 0x0, + DPHY_8B10B_RESETET = 0x1, +} DPHY_8B10B_RESET; +typedef enum DP_DPHY_8B10B_EXT_DISP { + DP_DPHY_8B10B_EXT_DISP_ZERO = 0x0, + DP_DPHY_8B10B_EXT_DISP_ONE = 0x1, +} DP_DPHY_8B10B_EXT_DISP; +typedef enum DPHY_8B10B_CUR_DISP { + DPHY_8B10B_CUR_DISP_ZERO = 0x0, + DPHY_8B10B_CUR_DISP_ONE = 0x1, +} DPHY_8B10B_CUR_DISP; +typedef enum DPHY_PRBS_EN { + DPHY_PRBS_DISABLE = 0x0, + DPHY_PRBS_ENABLE = 0x1, +} DPHY_PRBS_EN; +typedef enum DPHY_PRBS_SEL { + DPHY_PRBS7_SELECTED = 0x0, + DPHY_PRBS23_SELECTED = 0x1, + DPHY_PRBS11_SELECTED = 0x2, +} DPHY_PRBS_SEL; +typedef enum DPHY_LOAD_BS_COUNT_START { + DPHY_LOAD_BS_COUNT_STARTED = 0x0, + DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x1, +} DPHY_LOAD_BS_COUNT_START; +typedef enum DPHY_CRC_EN { + DPHY_CRC_DISABLED = 0x0, + DPHY_CRC_ENABLED = 0x1, +} DPHY_CRC_EN; +typedef enum DPHY_CRC_CONT_EN { + DPHY_CRC_ONE_SHOT = 0x0, + DPHY_CRC_CONTINUOUS = 0x1, +} DPHY_CRC_CONT_EN; +typedef enum DPHY_CRC_FIELD { + DPHY_CRC_START_FROM_TOP_FIELD = 0x0, + DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x1, +} DPHY_CRC_FIELD; +typedef enum DPHY_CRC_SEL { + DPHY_CRC_LANE0_SELECTED = 0x0, + DPHY_CRC_LANE1_SELECTED = 0x1, + DPHY_CRC_LANE2_SELECTED = 0x2, + DPHY_CRC_LANE3_SELECTED = 0x3, +} DPHY_CRC_SEL; +typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { + DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x0, + DPHY_FAST_TRAINING_CAPABLE = 0x1, +} DPHY_RX_FAST_TRAINING_CAPABLE; +typedef enum DP_SEC_COLLISION_ACK { + DP_SEC_COLLISION_ACK_NO_EFFECT = 0x0, + DP_SEC_COLLISION_ACK_CLR_FLAG = 0x1, +} DP_SEC_COLLISION_ACK; +typedef enum DP_SEC_AUDIO_MUTE { + DP_SEC_AUDIO_MUTE_HW_CTRL = 0x0, + DP_SEC_AUDIO_MUTE_SW_CTRL = 0x1, +} DP_SEC_AUDIO_MUTE; +typedef enum DP_SEC_TIMESTAMP_MODE { + DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x0, + DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x1, +} DP_SEC_TIMESTAMP_MODE; +typedef enum DP_SEC_ASP_PRIORITY { + DP_SEC_ASP_LOW_PRIORITY = 0x0, + DP_SEC_ASP_HIGH_PRIORITY = 0x1, +} DP_SEC_ASP_PRIORITY; +typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { + DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x0, + DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x1, +} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; +typedef enum DP_MSE_SAT_UPDATE_ACT { + DP_MSE_SAT_UPDATE_NO_ACTION = 0x0, + DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x1, + DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2, +} DP_MSE_SAT_UPDATE_ACT; +typedef enum DP_MSE_LINK_LINE { + DP_MSE_LINK_LINE_32_MTP_LONG = 0x0, + DP_MSE_LINK_LINE_64_MTP_LONG = 0x1, + DP_MSE_LINK_LINE_128_MTP_LONG = 0x2, + DP_MSE_LINK_LINE_256_MTP_LONG = 0x3, +} DP_MSE_LINK_LINE; +typedef enum DP_MSE_BLANK_CODE { + DP_MSE_BLANK_CODE_SF_FILLED = 0x0, + DP_MSE_BLANK_CODE_ZERO_FILLED = 0x1, +} DP_MSE_BLANK_CODE; +typedef enum DP_MSE_TIMESTAMP_MODE { + DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x0, + DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x1, +} DP_MSE_TIMESTAMP_MODE; +typedef enum DP_MSE_ZERO_ENCODER { + DP_MSE_NOT_ZERO_FE_ENCODER = 0x0, + DP_MSE_ZERO_FE_ENCODER = 0x1, +} DP_MSE_ZERO_ENCODER; +typedef enum DP_MSE_OUTPUT_DPDBG_DATA { + DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x0, + DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x1, +} DP_MSE_OUTPUT_DPDBG_DATA; +typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { + DP_DPHY_HBR2_PASS_THROUGH = 0x0, + DP_DPHY_HBR2_PATTERN_1 = 0x1, + DP_DPHY_HBR2_PATTERN_2_NEG = 0x2, + DP_DPHY_HBR2_PATTERN_3 = 0x3, + DP_DPHY_HBR2_PATTERN_2_POS = 0x6, +} DP_DPHY_HBR2_PATTERN_CONTROL_MODE; +typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { + DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x0, + DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x1, +} DPHY_CRC_MST_PHASE_ERROR_ACK; +typedef enum DPHY_SW_FAST_TRAINING_START { + DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x0, + DPHY_SW_FAST_TRAINING_STARTED = 0x1, +} DPHY_SW_FAST_TRAINING_START; +typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { + DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0, + DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1, +} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; +typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { + DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x0, + DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x1, +} DP_DPHY_FAST_TRAINING_COMPLETE_MASK; +typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { + DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x0, + DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x1, +} DP_DPHY_FAST_TRAINING_COMPLETE_ACK; +typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { + MSA_V_TIMING_OVERRIDE_DISABLED = 0x0, + MSA_V_TIMING_OVERRIDE_ENABLED = 0x1, +} DP_MSA_V_TIMING_OVERRIDE_EN; +typedef enum DP_SEC_GSP0_PRIORITY { + SEC_GSP0_PRIORITY_LOW = 0x0, + SEC_GSP0_PRIORITY_HIGH = 0x1, +} DP_SEC_GSP0_PRIORITY; +typedef enum DP_SEC_GSP0_SEND { + NOT_SENT = 0x0, + FORCE_SENT = 0x1, +} DP_SEC_GSP0_SEND; +typedef enum DP_AUX_CONTROL_HPD_SEL { + DP_AUX_CONTROL_HPD1_SELECTED = 0x0, + DP_AUX_CONTROL_HPD2_SELECTED = 0x1, + DP_AUX_CONTROL_HPD3_SELECTED = 0x2, + DP_AUX_CONTROL_HPD4_SELECTED = 0x3, + DP_AUX_CONTROL_HPD5_SELECTED = 0x4, + DP_AUX_CONTROL_HPD6_SELECTED = 0x5, +} DP_AUX_CONTROL_HPD_SEL; +typedef enum DP_AUX_CONTROL_TEST_MODE { + DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x0, + DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x1, +} DP_AUX_CONTROL_TEST_MODE; +typedef enum DP_AUX_SW_CONTROL_SW_GO { + DP_AUX_SW_CONTROL_SW__NOT_GO = 0x0, + DP_AUX_SW_CONTROL_SW__GO = 0x1, +} DP_AUX_SW_CONTROL_SW_GO; +typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { + DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x0, + DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x1, +} DP_AUX_SW_CONTROL_LS_READ_TRIG; +typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { + DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x0, + DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x1, + DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2, + DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x3, +} DP_AUX_ARB_CONTROL_ARB_PRIORITY; +typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { + DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x0, + DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x1, +} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; +typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { + DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x0, + DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x1, +} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; +typedef enum DP_AUX_INT_ACK { + DP_AUX_INT__NOT_ACK = 0x0, + DP_AUX_INT__ACK = 0x1, +} DP_AUX_INT_ACK; +typedef enum DP_AUX_LS_UPDATE_ACK { + DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x0, + DP_AUX_INT_LS_UPDATE_ACK = 0x1, +} DP_AUX_LS_UPDATE_ACK; +typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { + DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0, + DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1, +} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; +typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { + DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x0, + DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x1, + DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2, + DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x3, +} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; +typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN { + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x0, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x1, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x3, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x4, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x5, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x6, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x7, +} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN; +typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x0, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5, +} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; +typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7, +} DP_AUX_DPHY_RX_CONTROL_START_WINDOW; +typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7, +} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; +typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { + DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0, + DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1, + DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2, + DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3, +} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { + DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0, + DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { + DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0, + DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { + DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0, + DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; +typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { + DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0, + DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1, + DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2, + DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3, +} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; +typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN { + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x0, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x1, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x3, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x4, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x5, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x6, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x7, +} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN; +typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x0, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x1, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x3, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x4, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x5, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x6, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x7, +} DP_AUX_DPHY_RX_DETECTION_THRESHOLD; +typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { + DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0, + DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1, +} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; +typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { + DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0, + DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1, + DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2, + DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3, +} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; +typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { + DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0, + DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1, + DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2, + DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3, +} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; +typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { + DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0, + DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1, + DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2, + DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3, +} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; +typedef enum DP_AUX_ERR_OCCURRED_ACK { + DP_AUX_ERR_OCCURRED__NOT_ACK = 0x0, + DP_AUX_ERR_OCCURRED__ACK = 0x1, +} DP_AUX_ERR_OCCURRED_ACK; +typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { + DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x0, + DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x1, +} DP_AUX_POTENTIAL_ERR_REACHED_ACK; +typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { + ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x0, + ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x1, +} DP_AUX_DEFINITE_ERR_REACHED_ACK; +typedef enum DP_AUX_RESET { + DP_AUX_RESET_DEASSERTED = 0x0, + DP_AUX_RESET_ASSERTED = 0x1, +} DP_AUX_RESET; +typedef enum DP_AUX_RESET_DONE { + DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x0, + DP_AUX_RESET_SEQUENCE_DONE = 0x1, +} DP_AUX_RESET_DONE; +typedef enum FBC_IDLE_MASK_MASK_BITS { + FBC_IDLE_MASK_DISP_REG_UPDATE = 0x0, + FBC_IDLE_MASK_RESERVED1 = 0x1, + FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 0x2, + FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 0x3, + FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 0x4, + FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 0x5, + FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 0x6, + FBC_IDLE_MASK_RESERVED7 = 0x7, + FBC_IDLE_MASK_RESERVED8 = 0x8, + FBC_IDLE_MASK_RESERVED9 = 0x9, + FBC_IDLE_MASK_RESERVED10 = 0xa, + FBC_IDLE_MASK_RESERVED11 = 0xb, + FBC_IDLE_MASK_RESERVED12 = 0xc, + FBC_IDLE_MASK_RESERVED13 = 0xd, + FBC_IDLE_MASK_RESERVED14 = 0xe, + FBC_IDLE_MASK_RESERVED15 = 0xf, + FBC_IDLE_MASK_RESERVED16 = 0x10, + FBC_IDLE_MASK_RESERVED17 = 0x11, + FBC_IDLE_MASK_RESERVED18 = 0x12, + FBC_IDLE_MASK_RESERVED19 = 0x13, + FBC_IDLE_MASK_RESERVED20 = 0x14, + FBC_IDLE_MASK_RESERVED21 = 0x15, + FBC_IDLE_MASK_RESERVED22 = 0x16, + FBC_IDLE_MASK_RESERVED23 = 0x17, + FBC_IDLE_MASK_MC_HIT_REGION_0 = 0x18, + FBC_IDLE_MASK_MC_HIT_REGION_1 = 0x19, + FBC_IDLE_MASK_MC_HIT_REGION_2 = 0x1a, + FBC_IDLE_MASK_MC_HIT_REGION_3 = 0x1b, + FBC_IDLE_MASK_MC_WRITE = 0x1c, + FBC_IDLE_MASK_CG_STATIC_SCREEN = 0x1d, + FBC_IDLE_MASK_RESERVED30 = 0x1e, + FBC_IDLE_MASK_RESERVED31 = 0x1f, +} FBC_IDLE_MASK_MASK_BITS; +typedef enum FMT_CONTROL_PIXEL_ENCODING { + FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x0, + FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x1, + FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x2, + FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x3, +} FMT_CONTROL_PIXEL_ENCODING; +typedef enum FMT_CONTROL_SUBSAMPLING_MODE { + FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x0, + FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x1, + FMT_CONTROL_SUBSAMPLING_MODE_3_TAP = 0x2, + FMT_CONTROL_SUBSAMPLING_MODE_RESERVED = 0x3, +} FMT_CONTROL_SUBSAMPLING_MODE; +typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { + FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x0, + FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x1, +} FMT_CONTROL_SUBSAMPLING_ORDER; +typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS { + FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x0, + FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x1, +} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; +typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { + FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x0, + FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x1, +} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; +typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { + FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x0, + FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x1, + FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x2, +} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; +typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { + FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0, + FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1, + FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2, +} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; +typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { + FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0, + FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1, + FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2, +} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; +typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { + FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0, + FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1, +} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; +typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { + FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x0, + FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x1, + FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x2, + FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x3, +} FMT_BIT_DEPTH_CONTROL_25FRC_SEL; +typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { + FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x0, + FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x1, + FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x2, + FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x3, +} FMT_BIT_DEPTH_CONTROL_50FRC_SEL; +typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { + FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x0, + FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x1, + FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x2, + FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x3, +} FMT_BIT_DEPTH_CONTROL_75FRC_SEL; +typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT { + FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0, + FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1, +} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT; +typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { + FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0, + FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1, +} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; +typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { + FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x0, + FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x1, + FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x2, + FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x3, + FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x4, + FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x5, + FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x6, + FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x7, +} FMT_CLAMP_CNTL_COLOR_FORMAT; +typedef enum FMT_CRC_CNTL_CONT_EN { + FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x0, + FMT_CRC_CNTL_CONT_EN_CONT = 0x1, +} FMT_CRC_CNTL_CONT_EN; +typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN { + FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x0, + FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x1, +} FMT_CRC_CNTL_INCLUDE_OVERSCAN; +typedef enum FMT_CRC_CNTL_ONLY_BLANKB { + FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x0, + FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x1, +} FMT_CRC_CNTL_ONLY_BLANKB; +typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE { + FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x0, + FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x1, +} FMT_CRC_CNTL_PSR_MODE_ENABLE; +typedef enum FMT_CRC_CNTL_INTERLACE_MODE { + FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x0, + FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x1, + FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x2, + FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x3, +} FMT_CRC_CNTL_INTERLACE_MODE; +typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE { + FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x0, + FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x1, +} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE; +typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT { + FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x0, + FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x1, +} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT; +typedef enum FMT_DEBUG_CNTL_COLOR_SELECT { + FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x0, + FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x1, + FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x2, + FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x3, +} FMT_DEBUG_CNTL_COLOR_SELECT; +typedef enum FMT_SPATIAL_DITHER_MODE { + FMT_SPATIAL_DITHER_MODE_0 = 0x0, + FMT_SPATIAL_DITHER_MODE_1 = 0x1, + FMT_SPATIAL_DITHER_MODE_2 = 0x2, + FMT_SPATIAL_DITHER_MODE_3 = 0x3, +} FMT_SPATIAL_DITHER_MODE; +typedef enum FMT_STEREOSYNC_OVR_POL { + FMT_STEREOSYNC_OVR_POL_INVERTED = 0x0, + FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x1, +} FMT_STEREOSYNC_OVR_POL; +typedef enum FMT_DYNAMIC_EXP_MODE { + FMT_DYNAMIC_EXP_MODE_10to12 = 0x0, + FMT_DYNAMIC_EXP_MODE_8to12 = 0x1, +} FMT_DYNAMIC_EXP_MODE; +typedef enum LB_DATA_FORMAT_PIXEL_DEPTH { + LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x0, + LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x1, + LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x2, + LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x3, +} LB_DATA_FORMAT_PIXEL_DEPTH; +typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE { + LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0, + LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1, +} LB_DATA_FORMAT_PIXEL_EXPAN_MODE; +typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE { + LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x0, + LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x1, +} LB_DATA_FORMAT_PIXEL_REDUCE_MODE; +typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH { + LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x0, + LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x1, +} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH; +typedef enum LB_DATA_FORMAT_INTERLEAVE_EN { + LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x0, + LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x1, +} LB_DATA_FORMAT_INTERLEAVE_EN; +typedef enum LB_DATA_FORMAT_PREFILL_EN { + LB_DATA_FORMAT_PREFILL_DISABLE = 0x0, + LB_DATA_FORMAT_PREFILL_ENABLE = 0x1, +} LB_DATA_FORMAT_PREFILL_EN; +typedef enum LB_DATA_FORMAT_REQUEST_MODE { + LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x0, + LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x1, +} LB_DATA_FORMAT_REQUEST_MODE; +typedef enum LB_DATA_FORMAT_ALPHA_EN { + LB_DATA_FORMAT_ALPHA_DISABLE = 0x0, + LB_DATA_FORMAT_ALPHA_ENABLE = 0x1, +} LB_DATA_FORMAT_ALPHA_EN; +typedef enum LB_VLINE_START_END_VLINE_INV { + LB_VLINE_START_END_VLINE_NORMAL = 0x0, + LB_VLINE_START_END_VLINE_INVERSE = 0x1, +} LB_VLINE_START_END_VLINE_INV; +typedef enum LB_VLINE2_START_END_VLINE2_INV { + LB_VLINE2_START_END_VLINE2_NORMAL = 0x0, + LB_VLINE2_START_END_VLINE2_INVERSE = 0x1, +} LB_VLINE2_START_END_VLINE2_INV; +typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK { + LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x0, + LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x1, +} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK; +typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK { + LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x0, + LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x1, +} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK; +typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK { + LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x0, + LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x1, +} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK; +typedef enum LB_VLINE_STATUS_VLINE_ACK { + LB_VLINE_STATUS_VLINE_NORMAL = 0x0, + LB_VLINE_STATUS_VLINE_CLEAR = 0x1, +} LB_VLINE_STATUS_VLINE_ACK; +typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE { + LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0, + LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1, +} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE; +typedef enum LB_VLINE2_STATUS_VLINE2_ACK { + LB_VLINE2_STATUS_VLINE2_NORMAL = 0x0, + LB_VLINE2_STATUS_VLINE2_CLEAR = 0x1, +} LB_VLINE2_STATUS_VLINE2_ACK; +typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE { + LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0, + LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1, +} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE; +typedef enum LB_VBLANK_STATUS_VBLANK_ACK { + LB_VBLANK_STATUS_VBLANK_NORMAL = 0x0, + LB_VBLANK_STATUS_VBLANK_CLEAR = 0x1, +} LB_VBLANK_STATUS_VBLANK_ACK; +typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE { + LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0, + LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1, +} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE; +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL { + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x0, + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1, + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2, + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3, +} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL; +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 { + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x0, + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x1, +} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2; +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION { + LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x0, + LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x1, + LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x2, + LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x3, +} LB_SYNC_RESET_SEL_LB_SYNC_DURATION; +typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN { + LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x0, + LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x1, +} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN; +typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN { + LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0, + LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1, +} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN; +typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK { + LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x0, + LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x1, +} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK; +typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK { + LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x0, + LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x1, +} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK; +typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE { + LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2, + LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3, +} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE; +typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET { + LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0, + LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1, +} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET; +typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK { + LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0, + LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1, +} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK; +typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE { + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0, + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1, + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2, +} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE; +typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE { + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0, + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x1, +} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE; +typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE { + ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1, + ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2, +} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE; +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL { + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0, + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL; +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE { + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0, + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE; +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO { + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0, + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO; +typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN { + LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0, + LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1, +} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN; +typedef enum LBV_PIXEL_DEPTH { + PIXEL_DEPTH_30BPP = 0x0, + PIXEL_DEPTH_24BPP = 0x1, + PIXEL_DEPTH_18BPP = 0x2, + PIXEL_DEPTH_38BPP = 0x3, +} LBV_PIXEL_DEPTH; +typedef enum LBV_PIXEL_EXPAN_MODE { + PIXEL_EXPAN_MODE_ZERO_EXP = 0x0, + PIXEL_EXPAN_MODE_DYN_EXP = 0x1, +} LBV_PIXEL_EXPAN_MODE; +typedef enum LBV_INTERLEAVE_EN { + INTERLEAVE_DIS = 0x0, + INTERLEAVE_EN = 0x1, +} LBV_INTERLEAVE_EN; +typedef enum LBV_PIXEL_REDUCE_MODE { + PIXEL_REDUCE_MODE_TRUNCATION = 0x0, + PIXEL_REDUCE_MODE_ROUNDING = 0x1, +} LBV_PIXEL_REDUCE_MODE; +typedef enum LBV_DYNAMIC_PIXEL_DEPTH { + DYNAMIC_PIXEL_DEPTH_36BPP = 0x0, + DYNAMIC_PIXEL_DEPTH_30BPP = 0x1, +} LBV_DYNAMIC_PIXEL_DEPTH; +typedef enum LBV_DITHER_EN { + DITHER_DIS = 0x0, + DITHER_EN = 0x1, +} LBV_DITHER_EN; +typedef enum LBV_DOWNSCALE_PREFETCH_EN { + DOWNSCALE_PREFETCH_DIS = 0x0, + DOWNSCALE_PREFETCH_EN = 0x1, +} LBV_DOWNSCALE_PREFETCH_EN; +typedef enum LBV_MEMORY_CONFIG { + MEMORY_CONFIG_0 = 0x0, + MEMORY_CONFIG_1 = 0x1, + MEMORY_CONFIG_2 = 0x2, + MEMORY_CONFIG_3 = 0x3, +} LBV_MEMORY_CONFIG; +typedef enum LBV_SYNC_RESET_SEL2 { + SYNC_RESET_SEL2_VBLANK = 0x0, + SYNC_RESET_SEL2_VSYNC = 0x1, +} LBV_SYNC_RESET_SEL2; +typedef enum LBV_SYNC_DURATION { + SYNC_DURATION_16 = 0x0, + SYNC_DURATION_32 = 0x1, + SYNC_DURATION_64 = 0x2, + SYNC_DURATION_128 = 0x3, +} LBV_SYNC_DURATION; +typedef enum SCL_C_RAM_TAP_PAIR_IDX { + SCL_C_RAM_TAP_PAIR_ID0 = 0x0, + SCL_C_RAM_TAP_PAIR_ID1 = 0x1, + SCL_C_RAM_TAP_PAIR_ID2 = 0x2, + SCL_C_RAM_TAP_PAIR_ID3 = 0x3, + SCL_C_RAM_TAP_PAIR_ID4 = 0x4, +} SCL_C_RAM_TAP_PAIR_IDX; +typedef enum SCL_C_RAM_PHASE { + SCL_C_RAM_PHASE_0 = 0x0, + SCL_C_RAM_PHASE_1 = 0x1, + SCL_C_RAM_PHASE_2 = 0x2, + SCL_C_RAM_PHASE_3 = 0x3, + SCL_C_RAM_PHASE_4 = 0x4, + SCL_C_RAM_PHASE_5 = 0x5, + SCL_C_RAM_PHASE_6 = 0x6, + SCL_C_RAM_PHASE_7 = 0x7, + SCL_C_RAM_PHASE_8 = 0x8, +} SCL_C_RAM_PHASE; +typedef enum SCL_C_RAM_FILTER_TYPE { + SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x0, + SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x1, + SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x2, + SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x3, +} SCL_C_RAM_FILTER_TYPE; +typedef enum SCL_MODE_SEL { + SCL_MODE_RGB_BYPASS = 0x0, + SCL_MODE_RGB_SCALING = 0x1, + SCL_MODE_YCBCR_SCALING = 0x2, + SCL_MODE_YCBCR_BYPASS = 0x3, +} SCL_MODE_SEL; +typedef enum SCL_PSCL_EN { + SCL_PSCL_DISABLE = 0x0, + SCL_PSCL_ENANBLE = 0x1, +} SCL_PSCL_EN; +typedef enum SCL_V_NUM_OF_TAPS { + SCL_V_NUM_OF_TAPS_1 = 0x0, + SCL_V_NUM_OF_TAPS_2 = 0x1, + SCL_V_NUM_OF_TAPS_3 = 0x2, + SCL_V_NUM_OF_TAPS_4 = 0x3, + SCL_V_NUM_OF_TAPS_5 = 0x4, + SCL_V_NUM_OF_TAPS_6 = 0x5, +} SCL_V_NUM_OF_TAPS; +typedef enum SCL_H_NUM_OF_TAPS { + SCL_H_NUM_OF_TAPS_1 = 0x0, + SCL_H_NUM_OF_TAPS_2 = 0x1, + SCL_H_NUM_OF_TAPS_4 = 0x3, + SCL_H_NUM_OF_TAPS_6 = 0x5, + SCL_H_NUM_OF_TAPS_8 = 0x7, + SCL_H_NUM_OF_TAPS_10 = 0x9, +} SCL_H_NUM_OF_TAPS; +typedef enum SCL_BOUNDARY_MODE { + SCL_BOUNDARY_MODE_BLACK = 0x0, + SCL_BOUNDARY_MODE_EDGE = 0x1, +} SCL_BOUNDARY_MODE; +typedef enum SCL_EARLY_EOL_MOD { + SCL_EARLY_EOL_MODE_CRTC = 0x0, + SCL_EARLY_EOL_MODE_INTERNAL = 0x1, +} SCL_EARLY_EOL_MOD; +typedef enum SCL_BYPASS_MODE { + SCL_BYPASS_MODE_MC_MR = 0x0, + SCL_BYPASS_MODE_AC_NR = 0x1, + SCL_BYPASS_MODE_AC_AR = 0x2, + SCL_BYPASS_MODE_RESERVED = 0x3, +} SCL_BYPASS_MODE; +typedef enum SCL_V_MANUAL_REPLICATE_FACTOR { + SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x0, + SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x1, + SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x2, + SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x3, + SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x4, + SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x5, + SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x6, + SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x7, + SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x8, + SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x9, + SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0xa, + SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0xb, + SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0xc, + SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0xd, + SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0xe, + SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0xf, +} SCL_V_MANUAL_REPLICATE_FACTOR; +typedef enum SCL_H_MANUAL_REPLICATE_FACTOR { + SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x0, + SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x1, + SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x2, + SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x3, + SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x4, + SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x5, + SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x6, + SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x7, + SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x8, + SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x9, + SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0xa, + SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0xb, + SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0xc, + SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0xd, + SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0xe, + SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0xf, +} SCL_H_MANUAL_REPLICATE_FACTOR; +typedef enum SCL_V_CALC_AUTO_RATIO_EN { + SCL_V_CALC_AUTO_RATIO_DISABLE = 0x0, + SCL_V_CALC_AUTO_RATIO_ENABLE = 0x1, +} SCL_V_CALC_AUTO_RATIO_EN; +typedef enum SCL_H_CALC_AUTO_RATIO_EN { + SCL_H_CALC_AUTO_RATIO_DISABLE = 0x0, + SCL_H_CALC_AUTO_RATIO_ENABLE = 0x1, +} SCL_H_CALC_AUTO_RATIO_EN; +typedef enum SCL_H_FILTER_PICK_NEAREST { + SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x0, + SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x1, +} SCL_H_FILTER_PICK_NEAREST; +typedef enum SCL_H_2TAP_HARDCODE_COEF_EN { + SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x0, + SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x1, +} SCL_H_2TAP_HARDCODE_COEF_EN; +typedef enum SCL_V_FILTER_PICK_NEAREST { + SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x0, + SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x1, +} SCL_V_FILTER_PICK_NEAREST; +typedef enum SCL_V_2TAP_HARDCODE_COEF_EN { + SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x0, + SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x1, +} SCL_V_2TAP_HARDCODE_COEF_EN; +typedef enum SCL_UPDATE_TAKEN { + SCL_UPDATE_TAKEN_NO = 0x0, + SCL_UPDATE_TAKEN_YES = 0x1, +} SCL_UPDATE_TAKEN; +typedef enum SCL_UPDATE_LOCK { + SCL_UPDATE_UNLOCKED = 0x0, + SCL_UPDATE_LOCKED = 0x1, +} SCL_UPDATE_LOCK; +typedef enum SCL_COEF_UPDATE_COMPLETE { + SCL_COEF_UPDATE_NOT_COMPLETED = 0x0, + SCL_COEF_UPDATE_COMPLETED = 0x1, +} SCL_COEF_UPDATE_COMPLETE; +typedef enum SCL_HF_SHARP_SCALE_FACTOR { + SCL_HF_SHARP_SCALE_FACTOR_0 = 0x0, + SCL_HF_SHARP_SCALE_FACTOR_1 = 0x1, + SCL_HF_SHARP_SCALE_FACTOR_2 = 0x2, + SCL_HF_SHARP_SCALE_FACTOR_3 = 0x3, + SCL_HF_SHARP_SCALE_FACTOR_4 = 0x4, + SCL_HF_SHARP_SCALE_FACTOR_5 = 0x5, + SCL_HF_SHARP_SCALE_FACTOR_6 = 0x6, + SCL_HF_SHARP_SCALE_FACTOR_7 = 0x7, +} SCL_HF_SHARP_SCALE_FACTOR; +typedef enum SCL_HF_SHARP_EN { + SCL_HF_SHARP_DISABLE = 0x0, + SCL_HF_SHARP_ENABLE = 0x1, +} SCL_HF_SHARP_EN; +typedef enum SCL_VF_SHARP_SCALE_FACTOR { + SCL_VF_SHARP_SCALE_FACTOR_0 = 0x0, + SCL_VF_SHARP_SCALE_FACTOR_1 = 0x1, + SCL_VF_SHARP_SCALE_FACTOR_2 = 0x2, + SCL_VF_SHARP_SCALE_FACTOR_3 = 0x3, + SCL_VF_SHARP_SCALE_FACTOR_4 = 0x4, + SCL_VF_SHARP_SCALE_FACTOR_5 = 0x5, + SCL_VF_SHARP_SCALE_FACTOR_6 = 0x6, + SCL_VF_SHARP_SCALE_FACTOR_7 = 0x7, +} SCL_VF_SHARP_SCALE_FACTOR; +typedef enum SCL_VF_SHARP_EN { + SCL_VF_SHARP_DISABLE = 0x0, + SCL_VF_SHARP_ENABLE = 0x1, +} SCL_VF_SHARP_EN; +typedef enum SCL_ALU_DISABLE { + SCL_ALU_ENABLED = 0x0, + SCL_ALU_DISABLED = 0x1, +} SCL_ALU_DISABLE; +typedef enum SCL_HOST_CONFLICT_MASK { + SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x0, + SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x1, +} SCL_HOST_CONFLICT_MASK; +typedef enum SCL_SCL_MODE_CHANGE_MASK { + SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x0, + SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x1, +} SCL_SCL_MODE_CHANGE_MASK; +typedef enum SCLV_MODE_SEL { + SCLV_MODE_RGB_BYPASS = 0x0, + SCLV_MODE_RGB_SCALING = 0x1, + SCLV_MODE_YCBCR_SCALING = 0x2, + SCLV_MODE_YCBCR_BYPASS = 0x3, +} SCLV_MODE_SEL; +typedef enum SCLV_INTERLACE_SOURCE { + INTERLACE_SOURCE_PROGRESSIVE = 0x0, + INTERLACE_SOURCE_INTERLEAVE = 0x1, + INTERLACE_SOURCE_STACK = 0x2, +} SCLV_INTERLACE_SOURCE; +typedef enum SCLV_UPDATE_LOCK { + UPDATE_UNLOCKED = 0x0, + UPDATE_LOCKED = 0x1, +} SCLV_UPDATE_LOCK; +typedef enum SCLV_COEF_UPDATE_COMPLETE { + COEF_UPDATE_NOT_COMPLETE = 0x0, + COEF_UPDATE_COMPLETE = 0x1, +} SCLV_COEF_UPDATE_COMPLETE; +typedef enum COL_MAN_UPDATE_LOCK { + COL_MAN_UPDATE_UNLOCKED = 0x0, + COL_MAN_UPDATE_LOCKED = 0x1, +} COL_MAN_UPDATE_LOCK; +typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE { + COL_MAN_MULTIPLE_UPDATE = 0x0, + COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1, +} COL_MAN_DISABLE_MULTIPLE_UPDATE; +typedef enum COL_MAN_INPUTCSC_MODE { + INPUTCSC_MODE_BYPASS = 0x0, + INPUTCSC_MODE_A = 0x1, + INPUTCSC_MODE_B = 0x2, + INPUTCSC_MODE_UNITY = 0x3, +} COL_MAN_INPUTCSC_MODE; +typedef enum COL_MAN_INPUTCSC_TYPE { + INPUTCSC_TYPE_12_0 = 0x0, + INPUTCSC_TYPE_10_2 = 0x1, + INPUTCSC_TYPE_8_4 = 0x2, +} COL_MAN_INPUTCSC_TYPE; +typedef enum COL_MAN_INPUTCSC_CONVERT { + INPUTCSC_ROUND = 0x0, + INPUTCSC_TRUNCATE = 0x1, +} COL_MAN_INPUTCSC_CONVERT; +typedef enum COL_MAN_PRESCALE_MODE { + PRESCALE_MODE_BYPASS = 0x0, + PRESCALE_MODE_PROGRAM = 0x1, + PRESCALE_MODE_UNITY = 0x2, +} COL_MAN_PRESCALE_MODE; +typedef enum COL_MAN_INPUT_GAMMA_MODE { + INGAMMA_MODE_BYPASS = 0x0, + INGAMMA_MODE_FIX = 0x1, + INGAMMA_MODE_FLOAT = 0x2, +} COL_MAN_INPUT_GAMMA_MODE; +typedef enum COL_MAN_OUTPUT_CSC_MODE { + COL_MAN_OUTPUT_CSC_BYPASS = 0x0, + COL_MAN_OUTPUT_CSC_RGB = 0x1, + COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2, + COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3, + COL_MAN_OUTPUT_CSC_A = 0x4, + COL_MAN_OUTPUT_CSC_B = 0x5, + COL_MAN_OUTPUT_CSC_UNITY = 0x6, +} COL_MAN_OUTPUT_CSC_MODE; +typedef enum COL_MAN_DENORM_CLAMP_CONTROL { + DENORM_CLAMP_MODE_UNITY = 0x0, + DENORM_CLAMP_MODE_8 = 0x1, + DENORM_CLAMP_MODE_10 = 0x2, + DENORM_CLAMP_MODE_12 = 0x3, +} COL_MAN_DENORM_CLAMP_CONTROL; +typedef enum COL_MAN_GAMMA_CORR_CONTROL { + GAMMA_CORR_MODE_BYPASS = 0x0, + GAMMA_CORR_MODE_A = 0x1, + GAMMA_CORR_MODE_B = 0x2, +} COL_MAN_GAMMA_CORR_CONTROL; +typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE { + CM_GLOBAL_PASSTHROUGH_DISBALE = 0x0, + CM_GLOBAL_PASSTHROUGH_ENABLE = 0x1, +} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE; +typedef enum UNP_GRPH_EN { + UNP_GRPH_DISABLED = 0x0, + UNP_GRPH_ENABLED = 0x1, +} UNP_GRPH_EN; +typedef enum UNP_GRPH_DEPTH { + UNP_GRPH_8BPP = 0x0, + UNP_GRPH_16BPP = 0x1, + UNP_GRPH_32BPP = 0x2, +} UNP_GRPH_DEPTH; +typedef enum UNP_GRPH_NUM_BANKS { + UNP_GRPH_ADDR_SURF_2_BANK = 0x0, + UNP_GRPH_ADDR_SURF_4_BANK = 0x1, + UNP_GRPH_ADDR_SURF_8_BANK = 0x2, + UNP_GRPH_ADDR_SURF_16_BANK = 0x3, +} UNP_GRPH_NUM_BANKS; +typedef enum UNP_GRPH_BANK_WIDTH { + UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x0, + UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x1, + UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x2, + UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x3, +} UNP_GRPH_BANK_WIDTH; +typedef enum UNP_GRPH_BANK_HEIGHT { + UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x0, + UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x1, + UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x2, + UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} UNP_GRPH_BANK_HEIGHT; +typedef enum UNP_GRPH_TILE_SPLIT { + UNP_ADDR_SURF_TILE_SPLIT_64B = 0x0, + UNP_ADDR_SURF_TILE_SPLIT_128B = 0x1, + UNP_ADDR_SURF_TILE_SPLIT_256B = 0x2, + UNP_ADDR_SURF_TILE_SPLIT_512B = 0x3, + UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x4, + UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x5, + UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} UNP_GRPH_TILE_SPLIT; +typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE { + UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x0, + UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x1, +} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE; +typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE { + UNP_GRPH_PRIVILEGED_ACCESS_DIS = 0x0, + UNP_GRPH_PRIVILEGED_ACCESS_EN = 0x1, +} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE; +typedef enum UNP_GRPH_MACRO_TILE_ASPECT { + UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x0, + UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x1, + UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x2, + UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} UNP_GRPH_MACRO_TILE_ASPECT; +typedef enum UNP_GRPH_COLOR_EXPANSION_MODE { + UNP_GRPH_DYNAMIC_EXPANSION = 0x0, + UNP_GRPH_ZERO_EXPANSION = 0x1, +} UNP_GRPH_COLOR_EXPANSION_MODE; +typedef enum UNP_VIDEO_FORMAT { + UNP_VIDEO_FORMAT0 = 0x0, + UNP_VIDEO_FORMAT1 = 0x1, + UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x2, + UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x3, + UNP_VIDEO_FORMAT_YUV422_YCb = 0x4, + UNP_VIDEO_FORMAT_YUV422_YCr = 0x5, + UNP_VIDEO_FORMAT_YUV422_CbY = 0x6, + UNP_VIDEO_FORMAT_YUV422_CrY = 0x7, +} UNP_VIDEO_FORMAT; +typedef enum UNP_GRPH_ENDIAN_SWAP { + UNP_GRPH_ENDIAN_SWAP_NONE = 0x0, + UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x1, + UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x2, + UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x3, +} UNP_GRPH_ENDIAN_SWAP; +typedef enum UNP_GRPH_RED_CROSSBAR { + UNP_GRPH_RED_CROSSBAR_R_Cr = 0x0, + UNP_GRPH_RED_CROSSBAR_G_Y = 0x1, + UNP_GRPH_RED_CROSSBAR_B_Cb = 0x2, + UNP_GRPH_RED_CROSSBAR_A = 0x3, +} UNP_GRPH_RED_CROSSBAR; +typedef enum UNP_GRPH_GREEN_CROSSBAR { + UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x0, + UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x1, + UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x2, + UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x3, +} UNP_GRPH_GREEN_CROSSBAR; +typedef enum UNP_GRPH_BLUE_CROSSBAR { + UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x0, + UNP_GRPH_BLUE_CROSSBAR_A = 0x1, + UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x2, + UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x3, +} UNP_GRPH_BLUE_CROSSBAR; +typedef enum UNP_GRPH_MODE_UPDATE_LOCKG { + UNP_GRPH_UPDATE_LOCK_0 = 0x0, + UNP_GRPH_UPDATE_LOCK_1 = 0x1, +} UNP_GRPH_MODE_UPDATE_LOCKG; +typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { + UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x0, + UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x1, +} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; +typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { + UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x0, + UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x1, +} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; +typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { + UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x0, + UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x1, +} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; +typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN { + UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x0, + UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x1, +} UNP_GRPH_STEREOSYNC_FLIP_EN; +typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE { + UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x0, + UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x1, + UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x2, + UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x3, +} UNP_GRPH_STEREOSYNC_FLIP_MODE; +typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN { + UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x0, + UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x1, +} UNP_GRPH_STACK_INTERLACE_FLIP_EN; +typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE { + UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x0, + UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x1, + UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x2, + UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x3, +} UNP_GRPH_STACK_INTERLACE_FLIP_MODE; +typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE { + UNP_GRPH_STEREOSYNC_SELECT_EN = 0x0, + UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x1, +} UNP_GRPH_STEREOSYNC_SELECT_DISABLE; +typedef enum UNP_CRC_SOURCE_SEL { + UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x0, + UNP_CRC_SOURCE_SEL_LOWER32 = 0x1, + UNP_CRC_SOURCE_SEL_RESERVED = 0x2, + UNP_CRC_SOURCE_SEL_LOWER16 = 0x3, + UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x4, +} UNP_CRC_SOURCE_SEL; +typedef enum UNP_CRC_LINE_SEL { + UNP_CRC_LINE_SEL_RESERVED = 0x0, + UNP_CRC_LINE_SEL_EVEN_ONLY = 0x1, + UNP_CRC_LINE_SEL_ODD_ONLY = 0x2, + UNP_CRC_LINE_SEL_ODD_EVEN = 0x3, +} UNP_CRC_LINE_SEL; +typedef enum UNP_ROTATION_ANGLE { + UNP_ROTATION_ANGLE_0 = 0x0, + UNP_ROTATION_ANGLE_90 = 0x1, + UNP_ROTATION_ANGLE_180 = 0x2, + UNP_ROTATION_ANGLE_270 = 0x3, + UNP_ROTATION_ANGLE_0m = 0x4, + UNP_ROTATION_ANGLE_90m = 0x5, + UNP_ROTATION_ANGLE_180m = 0x6, + UNP_ROTATION_ANGLE_270m = 0x7, +} UNP_ROTATION_ANGLE; +typedef enum UNP_PIXEL_DROP { + UNP_PIXEL_NO_DROP = 0x0, + UNP_PIXEL_DROPPING = 0x1, +} UNP_PIXEL_DROP; +typedef enum UNP_BUFFER_MODE { + UNP_BUFFER_MODE_LUMA = 0x0, + UNP_BUFFER_MODE_LUMA_CHROMA = 0x1, +} UNP_BUFFER_MODE; +typedef enum WATERMARK_MASK_CONTROL { + WM_MASK_CONTROL_SET_A = 0x0, + WM_MASK_CONTROL_SET_B = 0x1, + WM_MASK_CONTROL_SET_C = 0x2, + WM_MASK_CONTROL_SET_D = 0x3, + WM_MASK_CONTROL_RESERVED1 = 0x4, + WM_MASK_CONTROL_RESERVED2 = 0x5, + WM_MASK_CONTROL_RESERVED3 = 0x6, + WM_MASK_CONTROL_ACTIVE_SET = 0x7, +} WATERMARK_MASK_CONTROL; +typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { + AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0, + AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1, +} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; +typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7, +} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; +typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7, +} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { + GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x0, + GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x1, +} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { + GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x0, + GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x1, +} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { + GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x0, + GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x1, +} GENERIC_AZ_CONTROLLER_REGISTER_STATUS; +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { + GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0, + GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1, +} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; +typedef enum AZ_GLOBAL_CAPABILITIES { + AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0, + AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1, +} AZ_GLOBAL_CAPABILITIES; +typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { + ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x0, + ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x1, +} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; +typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { + FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x0, + FLUSH_CONTROL_FLUSH_STARTED = 0x1, +} GLOBAL_CONTROL_FLUSH_CONTROL; +typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { + CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x0, + CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x1, +} GLOBAL_CONTROL_CONTROLLER_RESET; +typedef enum AZ_STATE_CHANGE_STATUS { + AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x0, + AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x1, +} AZ_STATE_CHANGE_STATUS; +typedef enum GLOBAL_STATUS_FLUSH_STATUS { + GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x0, + GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x1, +} GLOBAL_STATUS_FLUSH_STATUS; +typedef enum STREAM_0_SYNCHRONIZATION { + STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_0_SYNCHRONIZATION; +typedef enum STREAM_1_SYNCHRONIZATION { + STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_1_SYNCHRONIZATION; +typedef enum STREAM_2_SYNCHRONIZATION { + STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_2_SYNCHRONIZATION; +typedef enum STREAM_3_SYNCHRONIZATION { + STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_3_SYNCHRONIZATION; +typedef enum STREAM_4_SYNCHRONIZATION { + STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_4_SYNCHRONIZATION; +typedef enum STREAM_5_SYNCHRONIZATION { + STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_5_SYNCHRONIZATION; +typedef enum STREAM_6_SYNCHRONIZATION { + STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_6_SYNCHRONIZATION; +typedef enum STREAM_7_SYNCHRONIZATION { + STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_7_SYNCHRONIZATION; +typedef enum STREAM_8_SYNCHRONIZATION { + STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_8_SYNCHRONIZATION; +typedef enum STREAM_9_SYNCHRONIZATION { + STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_9_SYNCHRONIZATION; +typedef enum STREAM_10_SYNCHRONIZATION { + STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_10_SYNCHRONIZATION; +typedef enum STREAM_11_SYNCHRONIZATION { + STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_11_SYNCHRONIZATION; +typedef enum STREAM_12_SYNCHRONIZATION { + STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_12_SYNCHRONIZATION; +typedef enum STREAM_13_SYNCHRONIZATION { + STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_13_SYNCHRONIZATION; +typedef enum STREAM_14_SYNCHRONIZATION { + STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_14_SYNCHRONIZATION; +typedef enum STREAM_15_SYNCHRONIZATION { + STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_15_SYNCHRONIZATION; +typedef enum CORB_READ_POINTER_RESET { + CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x0, + CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x1, +} CORB_READ_POINTER_RESET; +typedef enum AZ_CORB_SIZE { + AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x0, + AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x1, + AZ_CORB_SIZE_256ENTRIES = 0x2, + AZ_CORB_SIZE_RESERVED = 0x3, +} AZ_CORB_SIZE; +typedef enum AZ_RIRB_WRITE_POINTER_RESET { + AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x0, + AZ_RIRB_WRITE_POINTER_DO_RESET = 0x1, +} AZ_RIRB_WRITE_POINTER_RESET; +typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { + RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0, + RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1, +} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; +typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { + RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0, + RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1, +} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; +typedef enum AZ_RIRB_SIZE { + AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x0, + AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x1, + AZ_RIRB_SIZE_256ENTRIES = 0x2, + AZ_RIRB_SIZE_UNDEFINED = 0x3, +} AZ_RIRB_SIZE; +typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { + IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0, + IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1, +} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; +typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { + IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0, + IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1, +} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; +typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { + DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0, + DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1, +} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { + AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { + AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { + AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; +typedef enum AZ_LATENCY_COUNTER_CONTROL { + AZ_LATENCY_COUNTER_NO_RESET = 0x0, + AZ_LATENCY_COUNTER_RESET_DONE = 0x1, +} AZ_LATENCY_COUNTER_CONTROL; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { + AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0, + AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1, +} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; +typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0, + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1, +} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; +typedef enum BLND_CONTROL_BLND_MODE { + BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0, + BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1, + BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2, + BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3, +} BLND_CONTROL_BLND_MODE; +typedef enum BLND_CONTROL_BLND_STEREO_TYPE { + BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0, + BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1, + BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2, + BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3, +} BLND_CONTROL_BLND_STEREO_TYPE; +typedef enum BLND_CONTROL_BLND_STEREO_POLARITY { + BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0, + BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1, +} BLND_CONTROL_BLND_STEREO_POLARITY; +typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN { + BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0, + BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1, +} BLND_CONTROL_BLND_FEEDTHROUGH_EN; +typedef enum BLND_CONTROL_BLND_ALPHA_MODE { + BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0, + BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1, + BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2, + BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3, +} BLND_CONTROL_BLND_ALPHA_MODE; +typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY { + BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0x0, + BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 0x1, +} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY; +typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE { + BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0, + BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1, +} BLND_CONTROL_BLND_MULTIPLIED_MODE; +typedef enum BLND_SM_CONTROL2_SM_MODE { + BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0, + BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2, + BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4, + BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6, +} BLND_SM_CONTROL2_SM_MODE; +typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE { + BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0, + BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1, +} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE; +typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE { + BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0, + BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1, +} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE; +typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { + BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0, + BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1, + BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2, + BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3, +} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; +typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { + BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0, + BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1, + BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2, + BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3, +} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; +typedef enum BLND_CONTROL2_PTI_ENABLE { + BLND_CONTROL2_PTI_ENABLE_FALSE = 0x0, + BLND_CONTROL2_PTI_ENABLE_TRUE = 0x1, +} BLND_CONTROL2_PTI_ENABLE; +typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { + BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0, + BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1, +} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; +typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN { + BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0, + BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1, +} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN; +typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { + BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0, + BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1, +} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; +typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { + BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0, + BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1, +} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0, + BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1, +} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0, + BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1, +} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0, + BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1, +} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0, + BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1, +} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0, + BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1, +} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0, + BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1, +} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { + BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0, + BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1, +} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; +typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT { + BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0, + BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1, +} BLND_DEBUG_BLND_CNV_MUX_SELECT; +typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { + BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0, + BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1, +} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_2 = 0xa, + DBG_CLIENT_BLKID_uvdf_3 = 0xb, + DBG_CLIENT_BLKID_uvdt_0 = 0xc, + DBG_CLIENT_BLKID_uvdi_0 = 0xd, + DBG_CLIENT_BLKID_bci0 = 0xe, + DBG_CLIENT_BLKID_vceb0_1 = 0xf, + DBG_CLIENT_BLKID_cb100 = 0x10, + DBG_CLIENT_BLKID_cb001 = 0x11, + DBG_CLIENT_BLKID_mcd4 = 0x12, + DBG_CLIENT_BLKID_tmonw00 = 0x13, + DBG_CLIENT_BLKID_cb101 = 0x14, + DBG_CLIENT_BLKID_sx10 = 0x15, + DBG_CLIENT_BLKID_cb301 = 0x16, + DBG_CLIENT_BLKID_tmonw01 = 0x17, + DBG_CLIENT_BLKID_vcea0_0 = 0x18, + DBG_CLIENT_BLKID_vcea0_1 = 0x19, + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, + DBG_CLIENT_BLKID_scf1 = 0x1c, + DBG_CLIENT_BLKID_sx20 = 0x1d, + DBG_CLIENT_BLKID_spim1 = 0x1e, + DBG_CLIENT_BLKID_pa10 = 0x1f, + DBG_CLIENT_BLKID_pa00 = 0x20, + DBG_CLIENT_BLKID_gmcon = 0x21, + DBG_CLIENT_BLKID_mcb = 0x22, + DBG_CLIENT_BLKID_vgt0 = 0x23, + DBG_CLIENT_BLKID_pc0 = 0x24, + DBG_CLIENT_BLKID_bci2 = 0x25, + DBG_CLIENT_BLKID_uvdb_0 = 0x26, + DBG_CLIENT_BLKID_spim3 = 0x27, + DBG_CLIENT_BLKID_cpc_0 = 0x28, + DBG_CLIENT_BLKID_cpc_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, + DBG_CLIENT_BLKID_cb000 = 0x2e, + DBG_CLIENT_BLKID_spim0 = 0x2f, + DBG_CLIENT_BLKID_mcc2 = 0x30, + DBG_CLIENT_BLKID_ds0 = 0x31, + DBG_CLIENT_BLKID_srbm = 0x32, + DBG_CLIENT_BLKID_ih = 0x33, + DBG_CLIENT_BLKID_sem = 0x34, + DBG_CLIENT_BLKID_sdma_0 = 0x35, + DBG_CLIENT_BLKID_sdma_1 = 0x36, + DBG_CLIENT_BLKID_hdp = 0x37, + DBG_CLIENT_BLKID_cb200 = 0x38, + DBG_CLIENT_BLKID_scf3 = 0x39, + DBG_CLIENT_BLKID_vceb1_0 = 0x3a, + DBG_CLIENT_BLKID_vcea1_0 = 0x3b, + DBG_CLIENT_BLKID_vcea1_1 = 0x3c, + DBG_CLIENT_BLKID_vcea1_2 = 0x3d, + DBG_CLIENT_BLKID_vcea1_3 = 0x3e, + DBG_CLIENT_BLKID_bci3 = 0x3f, + DBG_CLIENT_BLKID_mcd0 = 0x40, + DBG_CLIENT_BLKID_pa11 = 0x41, + DBG_CLIENT_BLKID_pa01 = 0x42, + DBG_CLIENT_BLKID_cb201 = 0x43, + DBG_CLIENT_BLKID_spim2 = 0x44, + DBG_CLIENT_BLKID_vgt2 = 0x45, + DBG_CLIENT_BLKID_pc2 = 0x46, + DBG_CLIENT_BLKID_smu_0 = 0x47, + DBG_CLIENT_BLKID_smu_1 = 0x48, + DBG_CLIENT_BLKID_smu_2 = 0x49, + DBG_CLIENT_BLKID_cb1 = 0x4a, + DBG_CLIENT_BLKID_ia0 = 0x4b, + DBG_CLIENT_BLKID_wd = 0x4c, + DBG_CLIENT_BLKID_ia1 = 0x4d, + DBG_CLIENT_BLKID_vcec1_0 = 0x4e, + DBG_CLIENT_BLKID_scf0 = 0x4f, + DBG_CLIENT_BLKID_vgt1 = 0x50, + DBG_CLIENT_BLKID_pc1 = 0x51, + DBG_CLIENT_BLKID_cb0 = 0x52, + DBG_CLIENT_BLKID_gdc_one_0 = 0x53, + DBG_CLIENT_BLKID_gdc_one_1 = 0x54, + DBG_CLIENT_BLKID_gdc_one_2 = 0x55, + DBG_CLIENT_BLKID_gdc_one_3 = 0x56, + DBG_CLIENT_BLKID_gdc_one_4 = 0x57, + DBG_CLIENT_BLKID_gdc_one_5 = 0x58, + DBG_CLIENT_BLKID_gdc_one_6 = 0x59, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_11 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_12 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_13 = 0x60, + DBG_CLIENT_BLKID_gdc_one_14 = 0x61, + DBG_CLIENT_BLKID_gdc_one_15 = 0x62, + DBG_CLIENT_BLKID_gdc_one_16 = 0x63, + DBG_CLIENT_BLKID_gdc_one_17 = 0x64, + DBG_CLIENT_BLKID_gdc_one_18 = 0x65, + DBG_CLIENT_BLKID_gdc_one_19 = 0x66, + DBG_CLIENT_BLKID_gdc_one_20 = 0x67, + DBG_CLIENT_BLKID_gdc_one_21 = 0x68, + DBG_CLIENT_BLKID_gdc_one_22 = 0x69, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_27 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_28 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_29 = 0x70, + DBG_CLIENT_BLKID_gdc_one_30 = 0x71, + DBG_CLIENT_BLKID_gdc_one_31 = 0x72, + DBG_CLIENT_BLKID_gdc_one_32 = 0x73, + DBG_CLIENT_BLKID_gdc_one_33 = 0x74, + DBG_CLIENT_BLKID_gdc_one_34 = 0x75, + DBG_CLIENT_BLKID_gdc_one_35 = 0x76, + DBG_CLIENT_BLKID_vceb0_0 = 0x77, + DBG_CLIENT_BLKID_vgt3 = 0x78, + DBG_CLIENT_BLKID_pc3 = 0x79, + DBG_CLIENT_BLKID_mcd3 = 0x7a, + DBG_CLIENT_BLKID_uvdu_0 = 0x7b, + DBG_CLIENT_BLKID_uvdu_1 = 0x7c, + DBG_CLIENT_BLKID_uvdu_2 = 0x7d, + DBG_CLIENT_BLKID_uvdu_3 = 0x7e, + DBG_CLIENT_BLKID_uvdu_4 = 0x7f, + DBG_CLIENT_BLKID_uvdu_5 = 0x80, + DBG_CLIENT_BLKID_uvdu_6 = 0x81, + DBG_CLIENT_BLKID_cb300 = 0x82, + DBG_CLIENT_BLKID_mcd1 = 0x83, + DBG_CLIENT_BLKID_sx00 = 0x84, + DBG_CLIENT_BLKID_uvdf_0 = 0x85, + DBG_CLIENT_BLKID_uvdf_1 = 0x86, + DBG_CLIENT_BLKID_mcc3 = 0x87, + DBG_CLIENT_BLKID_cpg_0 = 0x88, + DBG_CLIENT_BLKID_cpg_1 = 0x89, + DBG_CLIENT_BLKID_gck = 0x8a, + DBG_CLIENT_BLKID_mcc1 = 0x8b, + DBG_CLIENT_BLKID_cpf_0 = 0x8c, + DBG_CLIENT_BLKID_cpf_1 = 0x8d, + DBG_CLIENT_BLKID_rlc = 0x8e, + DBG_CLIENT_BLKID_grbm = 0x8f, + DBG_CLIENT_BLKID_sammsp = 0x90, + DBG_CLIENT_BLKID_dci_pg = 0x91, + DBG_CLIENT_BLKID_dci_0 = 0x92, + DBG_CLIENT_BLKID_dccg0_0 = 0x93, + DBG_CLIENT_BLKID_dccg0_1 = 0x94, + DBG_CLIENT_BLKID_dccg0_2 = 0x95, + DBG_CLIENT_BLKID_dccg0_3 = 0x96, + DBG_CLIENT_BLKID_dccg0_4 = 0x97, + DBG_CLIENT_BLKID_dccg0_5 = 0x98, + DBG_CLIENT_BLKID_dccg0_6 = 0x99, + DBG_CLIENT_BLKID_dccg0_7 = 0x9a, + DBG_CLIENT_BLKID_dccg0_8 = 0x9b, + DBG_CLIENT_BLKID_dcfe01_0 = 0x9c, + DBG_CLIENT_BLKID_dcfe02_0 = 0x9d, + DBG_CLIENT_BLKID_dcfe03_0 = 0x9e, + DBG_CLIENT_BLKID_dcfe04_0 = 0x9f, + DBG_CLIENT_BLKID_dcfe05_0 = 0xa0, + DBG_CLIENT_BLKID_dcfe06_0 = 0xa1, + DBG_CLIENT_BLKID_uvde_0 = 0xa2, + DBG_CLIENT_BLKID_RESERVED_LAST = 0xa3, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; +typedef enum HPD_INT_CONTROL_ACK { + HPD_INT_CONTROL_ACK_0 = 0x0, + HPD_INT_CONTROL_ACK_1 = 0x1, +} HPD_INT_CONTROL_ACK; +typedef enum HPD_INT_CONTROL_POLARITY { + HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x0, + HPD_INT_CONTROL_GEN_INT_ON_CON = 0x1, +} HPD_INT_CONTROL_POLARITY; +typedef enum HPD_INT_CONTROL_RX_INT_ACK { + HPD_INT_CONTROL_RX_INT_ACK_0 = 0x0, + HPD_INT_CONTROL_RX_INT_ACK_1 = 0x1, +} HPD_INT_CONTROL_RX_INT_ACK; +typedef enum DPDBG_EN { + DPDBG_DISABLE = 0x0, + DPDBG_ENABLE = 0x1, +} DPDBG_EN; +typedef enum DPDBG_INPUT_EN { + DPDBG_INPUT_DISABLE = 0x0, + DPDBG_INPUT_ENABLE = 0x1, +} DPDBG_INPUT_EN; +typedef enum DPDBG_ERROR_DETECTION_MODE { + DPDBG_ERROR_DETECTION_MODE_CSC = 0x0, + DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x1, +} DPDBG_ERROR_DETECTION_MODE; +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK { + DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x0, + DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x1, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK; +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE { + DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x0, + DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x1, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE; +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK { + DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x0, + DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x1, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK; +typedef enum PM_ASSERT_RESET { + PM_ASSERT_RESET_0 = 0x0, + PM_ASSERT_RESET_1 = 0x1, +} PM_ASSERT_RESET; +typedef enum DAC_MUX_SELECT { + DAC_MUX_SELECT_DACA = 0x0, + DAC_MUX_SELECT_DACB = 0x1, +} DAC_MUX_SELECT; +typedef enum TMDS_DVO_MUX_SELECT { + TMDS_DVO_MUX_SELECT_B = 0x0, + TMDS_DVO_MUX_SELECT_G = 0x1, + TMDS_DVO_MUX_SELECT_R = 0x2, + TMDS_DVO_MUX_SELECT_RESERVED = 0x3, +} TMDS_DVO_MUX_SELECT; +typedef enum DACA_SOFT_RESET { + DACA_SOFT_RESET_0 = 0x0, + DACA_SOFT_RESET_1 = 0x1, +} DACA_SOFT_RESET; +typedef enum I2S0_SPDIF0_SOFT_RESET { + I2S0_SPDIF0_SOFT_RESET_0 = 0x0, + I2S0_SPDIF0_SOFT_RESET_1 = 0x1, +} I2S0_SPDIF0_SOFT_RESET; +typedef enum I2S1_SOFT_RESET { + I2S1_SOFT_RESET_0 = 0x0, + I2S1_SOFT_RESET_1 = 0x1, +} I2S1_SOFT_RESET; +typedef enum SPDIF1_SOFT_RESET { + SPDIF1_SOFT_RESET_0 = 0x0, + SPDIF1_SOFT_RESET_1 = 0x1, +} SPDIF1_SOFT_RESET; +typedef enum DB_CLK_SOFT_RESET { + DB_CLK_SOFT_RESET_0 = 0x0, + DB_CLK_SOFT_RESET_1 = 0x1, +} DB_CLK_SOFT_RESET; +typedef enum FMT0_SOFT_RESET { + FMT0_SOFT_RESET_0 = 0x0, + FMT0_SOFT_RESET_1 = 0x1, +} FMT0_SOFT_RESET; +typedef enum FMT1_SOFT_RESET { + FMT1_SOFT_RESET_0 = 0x0, + FMT1_SOFT_RESET_1 = 0x1, +} FMT1_SOFT_RESET; +typedef enum FMT2_SOFT_RESET { + FMT2_SOFT_RESET_0 = 0x0, + FMT2_SOFT_RESET_1 = 0x1, +} FMT2_SOFT_RESET; +typedef enum FMT3_SOFT_RESET { + FMT3_SOFT_RESET_0 = 0x0, + FMT3_SOFT_RESET_1 = 0x1, +} FMT3_SOFT_RESET; +typedef enum FMT4_SOFT_RESET { + FMT4_SOFT_RESET_0 = 0x0, + FMT4_SOFT_RESET_1 = 0x1, +} FMT4_SOFT_RESET; +typedef enum FMT5_SOFT_RESET { + FMT5_SOFT_RESET_0 = 0x0, + FMT5_SOFT_RESET_1 = 0x1, +} FMT5_SOFT_RESET; +typedef enum MVP_SOFT_RESET { + MVP_SOFT_RESET_0 = 0x0, + MVP_SOFT_RESET_1 = 0x1, +} MVP_SOFT_RESET; +typedef enum ABM_SOFT_RESET { + ABM_SOFT_RESET_0 = 0x0, + ABM_SOFT_RESET_1 = 0x1, +} ABM_SOFT_RESET; +typedef enum DVO_SOFT_RESET { + DVO_SOFT_RESET_0 = 0x0, + DVO_SOFT_RESET_1 = 0x1, +} DVO_SOFT_RESET; +typedef enum DIGA_FE_SOFT_RESET { + DIGA_FE_SOFT_RESET_0 = 0x0, + DIGA_FE_SOFT_RESET_1 = 0x1, +} DIGA_FE_SOFT_RESET; +typedef enum DIGA_BE_SOFT_RESET { + DIGA_BE_SOFT_RESET_0 = 0x0, + DIGA_BE_SOFT_RESET_1 = 0x1, +} DIGA_BE_SOFT_RESET; +typedef enum DIGB_FE_SOFT_RESET { + DIGB_FE_SOFT_RESET_0 = 0x0, + DIGB_FE_SOFT_RESET_1 = 0x1, +} DIGB_FE_SOFT_RESET; +typedef enum DIGB_BE_SOFT_RESET { + DIGB_BE_SOFT_RESET_0 = 0x0, + DIGB_BE_SOFT_RESET_1 = 0x1, +} DIGB_BE_SOFT_RESET; +typedef enum DIGC_FE_SOFT_RESET { + DIGC_FE_SOFT_RESET_0 = 0x0, + DIGC_FE_SOFT_RESET_1 = 0x1, +} DIGC_FE_SOFT_RESET; +typedef enum DIGC_BE_SOFT_RESET { + DIGC_BE_SOFT_RESET_0 = 0x0, + DIGC_BE_SOFT_RESET_1 = 0x1, +} DIGC_BE_SOFT_RESET; +typedef enum DIGD_FE_SOFT_RESET { + DIGD_FE_SOFT_RESET_0 = 0x0, + DIGD_FE_SOFT_RESET_1 = 0x1, +} DIGD_FE_SOFT_RESET; +typedef enum DIGD_BE_SOFT_RESET { + DIGD_BE_SOFT_RESET_0 = 0x0, + DIGD_BE_SOFT_RESET_1 = 0x1, +} DIGD_BE_SOFT_RESET; +typedef enum DIGE_FE_SOFT_RESET { + DIGE_FE_SOFT_RESET_0 = 0x0, + DIGE_FE_SOFT_RESET_1 = 0x1, +} DIGE_FE_SOFT_RESET; +typedef enum DIGE_BE_SOFT_RESET { + DIGE_BE_SOFT_RESET_0 = 0x0, + DIGE_BE_SOFT_RESET_1 = 0x1, +} DIGE_BE_SOFT_RESET; +typedef enum DIGF_FE_SOFT_RESET { + DIGF_FE_SOFT_RESET_0 = 0x0, + DIGF_FE_SOFT_RESET_1 = 0x1, +} DIGF_FE_SOFT_RESET; +typedef enum DIGF_BE_SOFT_RESET { + DIGF_BE_SOFT_RESET_0 = 0x0, + DIGF_BE_SOFT_RESET_1 = 0x1, +} DIGF_BE_SOFT_RESET; +typedef enum DIGG_FE_SOFT_RESET { + DIGG_FE_SOFT_RESET_0 = 0x0, + DIGG_FE_SOFT_RESET_1 = 0x1, +} DIGG_FE_SOFT_RESET; +typedef enum DIGG_BE_SOFT_RESET { + DIGG_BE_SOFT_RESET_0 = 0x0, + DIGG_BE_SOFT_RESET_1 = 0x1, +} DIGG_BE_SOFT_RESET; +typedef enum DPDBG_SOFT_RESET { + DPDBG_SOFT_RESET_0 = 0x0, + DPDBG_SOFT_RESET_1 = 0x1, +} DPDBG_SOFT_RESET; +typedef enum DIGLPA_FE_SOFT_RESET { + DIGLPA_FE_SOFT_RESET_0 = 0x0, + DIGLPA_FE_SOFT_RESET_1 = 0x1, +} DIGLPA_FE_SOFT_RESET; +typedef enum DIGLPA_BE_SOFT_RESET { + DIGLPA_BE_SOFT_RESET_0 = 0x0, + DIGLPA_BE_SOFT_RESET_1 = 0x1, +} DIGLPA_BE_SOFT_RESET; +typedef enum DIGLPB_FE_SOFT_RESET { + DIGLPB_FE_SOFT_RESET_0 = 0x0, + DIGLPB_FE_SOFT_RESET_1 = 0x1, +} DIGLPB_FE_SOFT_RESET; +typedef enum DIGLPB_BE_SOFT_RESET { + DIGLPB_BE_SOFT_RESET_0 = 0x0, + DIGLPB_BE_SOFT_RESET_1 = 0x1, +} DIGLPB_BE_SOFT_RESET; +typedef enum GENERICA_STEREOSYNC_SEL { + GENERICA_STEREOSYNC_SEL_D1 = 0x0, + GENERICA_STEREOSYNC_SEL_D2 = 0x1, + GENERICA_STEREOSYNC_SEL_D3 = 0x2, + GENERICA_STEREOSYNC_SEL_D4 = 0x3, + GENERICA_STEREOSYNC_SEL_D5 = 0x4, + GENERICA_STEREOSYNC_SEL_D6 = 0x5, + GENERICA_STEREOSYNC_SEL_RESERVED = 0x6, +} GENERICA_STEREOSYNC_SEL; +typedef enum GENERICB_STEREOSYNC_SEL { + GENERICB_STEREOSYNC_SEL_D1 = 0x0, + GENERICB_STEREOSYNC_SEL_D2 = 0x1, + GENERICB_STEREOSYNC_SEL_D3 = 0x2, + GENERICB_STEREOSYNC_SEL_D4 = 0x3, + GENERICB_STEREOSYNC_SEL_D5 = 0x4, + GENERICB_STEREOSYNC_SEL_D6 = 0x5, + GENERICB_STEREOSYNC_SEL_RESERVED = 0x6, +} GENERICB_STEREOSYNC_SEL; +typedef enum DCO_DBG_BLOCK_SEL { + DCO_DBG_BLOCK_SEL_DCO = 0x0, + DCO_DBG_BLOCK_SEL_ABM = 0x1, + DCO_DBG_BLOCK_SEL_DVO = 0x2, + DCO_DBG_BLOCK_SEL_DAC = 0x3, + DCO_DBG_BLOCK_SEL_MVP = 0x4, + DCO_DBG_BLOCK_SEL_FMT0 = 0x5, + DCO_DBG_BLOCK_SEL_FMT1 = 0x6, + DCO_DBG_BLOCK_SEL_FMT2 = 0x7, + DCO_DBG_BLOCK_SEL_FMT3 = 0x8, + DCO_DBG_BLOCK_SEL_FMT4 = 0x9, + DCO_DBG_BLOCK_SEL_FMT5 = 0xa, + DCO_DBG_BLOCK_SEL_DIGFE_A = 0xb, + DCO_DBG_BLOCK_SEL_DIGFE_B = 0xc, + DCO_DBG_BLOCK_SEL_DIGFE_C = 0xd, + DCO_DBG_BLOCK_SEL_DIGFE_D = 0xe, + DCO_DBG_BLOCK_SEL_DIGFE_E = 0xf, + DCO_DBG_BLOCK_SEL_DIGFE_F = 0x10, + DCO_DBG_BLOCK_SEL_DIGFE_G = 0x11, + DCO_DBG_BLOCK_SEL_DIGA = 0x12, + DCO_DBG_BLOCK_SEL_DIGB = 0x13, + DCO_DBG_BLOCK_SEL_DIGC = 0x14, + DCO_DBG_BLOCK_SEL_DIGD = 0x15, + DCO_DBG_BLOCK_SEL_DIGE = 0x16, + DCO_DBG_BLOCK_SEL_DIGF = 0x17, + DCO_DBG_BLOCK_SEL_DIGG = 0x18, + DCO_DBG_BLOCK_SEL_DPFE_A = 0x19, + DCO_DBG_BLOCK_SEL_DPFE_B = 0x1a, + DCO_DBG_BLOCK_SEL_DPFE_C = 0x1b, + DCO_DBG_BLOCK_SEL_DPFE_D = 0x1c, + DCO_DBG_BLOCK_SEL_DPFE_E = 0x1d, + DCO_DBG_BLOCK_SEL_DPFE_F = 0x1e, + DCO_DBG_BLOCK_SEL_DPFE_G = 0x1f, + DCO_DBG_BLOCK_SEL_DPA = 0x20, + DCO_DBG_BLOCK_SEL_DPB = 0x21, + DCO_DBG_BLOCK_SEL_DPC = 0x22, + DCO_DBG_BLOCK_SEL_DPD = 0x23, + DCO_DBG_BLOCK_SEL_DPE = 0x24, + DCO_DBG_BLOCK_SEL_DPF = 0x25, + DCO_DBG_BLOCK_SEL_DPG = 0x26, + DCO_DBG_BLOCK_SEL_AUX0 = 0x27, + DCO_DBG_BLOCK_SEL_AUX1 = 0x28, + DCO_DBG_BLOCK_SEL_AUX2 = 0x29, + DCO_DBG_BLOCK_SEL_AUX3 = 0x2a, + DCO_DBG_BLOCK_SEL_AUX4 = 0x2b, + DCO_DBG_BLOCK_SEL_AUX5 = 0x2c, + DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x2d, + DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x2e, + DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x2f, + DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x30, + DCO_DBG_BLOCK_SEL_DIGLPA = 0x31, + DCO_DBG_BLOCK_SEL_DIGLPB = 0x32, + DCO_DBG_BLOCK_SEL_DPLPFEA = 0x33, + DCO_DBG_BLOCK_SEL_DPLPFEB = 0x34, + DCO_DBG_BLOCK_SEL_DPLPA = 0x35, + DCO_DBG_BLOCK_SEL_DPLPB = 0x36, +} DCO_DBG_BLOCK_SEL; +typedef enum DCO_DBG_CLOCK_SEL { + DCO_DBG_CLOCK_SEL_DISPCLK = 0x0, + DCO_DBG_CLOCK_SEL_SCLK = 0x1, + DCO_DBG_CLOCK_SEL_MVPCLK = 0x2, + DCO_DBG_CLOCK_SEL_DVOCLK = 0x3, + DCO_DBG_CLOCK_SEL_DACCLK = 0x4, + DCO_DBG_CLOCK_SEL_REFCLK = 0x5, + DCO_DBG_CLOCK_SEL_SYMCLKA = 0x6, + DCO_DBG_CLOCK_SEL_SYMCLKB = 0x7, + DCO_DBG_CLOCK_SEL_SYMCLKC = 0x8, + DCO_DBG_CLOCK_SEL_SYMCLKD = 0x9, + DCO_DBG_CLOCK_SEL_SYMCLKE = 0xa, + DCO_DBG_CLOCK_SEL_SYMCLKF = 0xb, + DCO_DBG_CLOCK_SEL_SYMCLKG = 0xc, + DCO_DBG_CLOCK_SEL_RESERVED = 0xd, + DCO_DBG_CLOCK_SEL_AM0CLK = 0xe, + DCO_DBG_CLOCK_SEL_AM1CLK = 0xf, + DCO_DBG_CLOCK_SEL_AM2CLK = 0x10, + DCO_DBG_CLOCK_SEL_SYMCLKLPA = 0x11, + DCO_DBG_CLOCK_SEL_SYMCLKLPB = 0x12, +} DCO_DBG_CLOCK_SEL; +typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE { + DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x0, + DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x1, +} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE; +typedef enum FMT420_MEMORY_SOURCE_SEL { + FMT420_MEMORY_SOURCE_SEL_FMT0 = 0x0, + FMT420_MEMORY_SOURCE_SEL_FMT1 = 0x1, + FMT420_MEMORY_SOURCE_SEL_FMT2 = 0x2, + FMT420_MEMORY_SOURCE_SEL_FMT3 = 0x3, + FMT420_MEMORY_SOURCE_SEL_FMT4 = 0x4, + FMT420_MEMORY_SOURCE_SEL_FMT5 = 0x5, + FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 0x6, +} FMT420_MEMORY_SOURCE_SEL; +typedef enum DOUT_I2C_CONTROL_GO { + DOUT_I2C_CONTROL_STOP_TRANSFER = 0x0, + DOUT_I2C_CONTROL_START_TRANSFER = 0x1, +} DOUT_I2C_CONTROL_GO; +typedef enum DOUT_I2C_CONTROL_SOFT_RESET { + DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x0, + DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x1, +} DOUT_I2C_CONTROL_SOFT_RESET; +typedef enum DOUT_I2C_CONTROL_SEND_RESET { + DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x0, + DOUT_I2C_CONTROL__SEND_RESET = 0x1, +} DOUT_I2C_CONTROL_SEND_RESET; +typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { + DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x0, + DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x1, +} DOUT_I2C_CONTROL_SW_STATUS_RESET; +typedef enum DOUT_I2C_CONTROL_DDC_SELECT { + DOUT_I2C_CONTROL_SELECT_DDC1 = 0x0, + DOUT_I2C_CONTROL_SELECT_DDC2 = 0x1, + DOUT_I2C_CONTROL_SELECT_DDC3 = 0x2, + DOUT_I2C_CONTROL_SELECT_DDC4 = 0x3, + DOUT_I2C_CONTROL_SELECT_DDC5 = 0x4, + DOUT_I2C_CONTROL_SELECT_DDC6 = 0x5, + DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x6, +} DOUT_I2C_CONTROL_DDC_SELECT; +typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { + DOUT_I2C_CONTROL_TRANS0 = 0x0, + DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x1, + DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x2, + DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x3, +} DOUT_I2C_CONTROL_TRANSACTION_COUNT; +typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL { + DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x0, + DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x1, +} DOUT_I2C_CONTROL_DBG_REF_SEL; +typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { + DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x0, + DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x1, + DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x2, + DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x3, +} DOUT_I2C_ARBITRATION_SW_PRIORITY; +typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { + DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x0, + DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x1, +} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; +typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { + DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x0, + DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x1, +} DOUT_I2C_ARBITRATION_ABORT_XFER; +typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { + DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x0, + DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x1, +} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; +typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { + DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x0, + DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x1, +} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; +typedef enum DOUT_I2C_ACK { + DOUT_I2C_NO_ACK = 0x0, + DOUT_I2C_ACK_TO_CLEAN = 0x1, +} DOUT_I2C_ACK; +typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { + DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x0, + DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1, + DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2, + DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3, +} DOUT_I2C_DDC_SPEED_THRESHOLD; +typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { + DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0, + DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x1, +} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; +typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { + DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x0, + DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x1, +} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; +typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { + DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x0, + DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x1, +} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; +typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { + DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0, + DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x1, +} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; +typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { + DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x0, + DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x1, +} DOUT_I2C_TRANSACTION_STOP_ON_NACK; +typedef enum DOUT_I2C_DATA_INDEX_WRITE { + DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x0, + DOUT_I2C_DATA__INDEX_WRITE = 0x1, +} DOUT_I2C_DATA_INDEX_WRITE; +typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { + DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0, + DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1, +} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; +typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { + DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x0, + DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x1, +} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; +typedef enum BLNDV_CONTROL_BLND_MODE { + BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0, + BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1, + BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2, + BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3, +} BLNDV_CONTROL_BLND_MODE; +typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE { + BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0, + BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1, + BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2, + BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3, +} BLNDV_CONTROL_BLND_STEREO_TYPE; +typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY { + BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0, + BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1, +} BLNDV_CONTROL_BLND_STEREO_POLARITY; +typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN { + BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0, + BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1, +} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN; +typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE { + BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0, + BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1, + BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2, + BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3, +} BLNDV_CONTROL_BLND_ALPHA_MODE; +typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY { + BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x0, + BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x1, +} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY; +typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE { + BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0, + BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1, +} BLNDV_CONTROL_BLND_MULTIPLIED_MODE; +typedef enum BLNDV_SM_CONTROL2_SM_MODE { + BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0, + BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2, + BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4, + BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6, +} BLNDV_SM_CONTROL2_SM_MODE; +typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE { + BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0, + BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1, +} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE; +typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE { + BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0, + BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1, +} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE; +typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3, +} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; +typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3, +} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; +typedef enum BLNDV_CONTROL2_PTI_ENABLE { + BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x0, + BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x1, +} BLNDV_CONTROL2_PTI_ENABLE; +typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { + BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0, + BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1, +} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; +typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN { + BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0, + BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1, +} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN; +typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { + BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0, + BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1, +} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; +typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { + BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0, + BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1, +} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0, + BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { + BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; +typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT { + BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0, + BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1, +} BLNDV_DEBUG_BLND_CNV_MUX_SELECT; +typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { + BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0, + BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1, +} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; +typedef enum DPCSTX_DBG_CFGCLK_SEL { + DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x0, + DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x1, + DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x2, + DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x3, +} DPCSTX_DBG_CFGCLK_SEL; +typedef enum DPCSTX_TX_SYMCLK_SEL { + DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0x0, + DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 0x1, + DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 0x2, +} DPCSTX_TX_SYMCLK_SEL; +typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL { + DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0x0, + DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 0x1, + DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 0x2, + DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 0x3, + DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 0x4, + DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 0x5, +} DPCSTX_TX_SYMCLK_DIV2_SEL; +typedef enum DPCSTX_DBG_CLOCK_SEL { + DPCSTX_DBG_CLOCK_SEL_DC_CFGCLK = 0x0, + DPCSTX_DBG_CLOCK_SEL_PHY_CFGCLK = 0x1, + DPCSTX_DBG_CLOCK_SEL_TXSYMCLK = 0x2, +} DPCSTX_DBG_CLOCK_SEL; +typedef enum DPCSTX_DVI_LINK_MODE { + DPCSTX_DVI_LINK_MODE_NORMAL = 0x0, + DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER = 0x1, + DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER = 0x2, +} DPCSTX_DVI_LINK_MODE; + +#endif /* DCE_11_2_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h new file mode 100755 index 000000000000..1ddc4183a1c9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h @@ -0,0 +1,18687 @@ +/* + * DCE_11_2 Register documentation + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_11_2_SH_MASK_H +#define DCE_11_2_SH_MASK_H + +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1 +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0 +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1 +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0 +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1 +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0 +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1 +#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x2 +#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x4 +#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x8 +#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10 +#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x20 +#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x40 +#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x80 +#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x100 +#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200 +#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x400 +#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa +#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800 +#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x1000 +#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x2000 +#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd +#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x4000 +#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x8000 +#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf +#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x10000 +#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x20000 +#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x1 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x2 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x4 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x8 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x20 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x40 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x100 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x400 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x800 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x1000 +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x2000 +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x4000 +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x8000 +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x10000 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x20000 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x40000 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x80000 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x100000 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x200000 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x400000 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x1000000 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x2000000 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x4000000 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x8000000 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000 +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000 +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000 +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000 +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f +#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK_MASK 0x1000000 +#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK__SHIFT 0x18 +#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR_MASK 0x2000000 +#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x19 +#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK_MASK 0x4000000 +#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK__SHIFT 0x1a +#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x8000000 +#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x1b +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 +#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 +#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff +#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 +#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff +#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 +#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000 +#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 +#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff +#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff +#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0 +#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 +#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 +#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 +#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d +#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 +#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 +#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff +#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 +#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 +#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 +#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 +#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 +#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 +#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 +#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 +#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 +#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 +#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 +#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1 +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4 +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2 +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100 +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 +#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 +#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 +#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 +#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 +#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000 +#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10 +#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 +#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 +#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 +#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 +#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 +#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 +#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 +#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 +#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 +#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 +#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 +#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 +#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc +#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 +#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 +#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 +#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff +#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 +#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff +#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff +#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 +#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff +#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x3fff +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3fff0000 +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x3fff +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3fff0000 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 +#define DAC_ENABLE__DAC_ENABLE_MASK 0x1 +#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 +#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 +#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 +#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 +#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18 +#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff +#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 +#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 +#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 +#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 +#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 +#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 +#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 +#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 +#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 +#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff +#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a +#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 +#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc +#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2 +#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 +#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1 +#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x2 +#define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define PERFMON_HI__PERFMON_HI_MASK 0xffff +#define PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 +#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff +#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1 +#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2 +#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 +#define DCCG_CBUS_ANTIGLITCH_RESETB__P0PLL_CBUS_ANTIGLITCH_RESETB_MASK 0x1 +#define DCCG_CBUS_ANTIGLITCH_RESETB__P0PLL_CBUS_ANTIGLITCH_RESETB__SHIFT 0x0 +#define DCCG_CBUS_ANTIGLITCH_RESETB__P1PLL_CBUS_ANTIGLITCH_RESETB_MASK 0x2 +#define DCCG_CBUS_ANTIGLITCH_RESETB__P1PLL_CBUS_ANTIGLITCH_RESETB__SHIFT 0x1 +#define DCCG_CBUS_ANTIGLITCH_RESETB__P2PLL_CBUS_ANTIGLITCH_RESETB_MASK 0x4 +#define DCCG_CBUS_ANTIGLITCH_RESETB__P2PLL_CBUS_ANTIGLITCH_RESETB__SHIFT 0x2 +#define DCCG_CBUS_ANTIGLITCH_RESETB__P3PLL_CBUS_ANTIGLITCH_RESETB_MASK 0x8 +#define DCCG_CBUS_ANTIGLITCH_RESETB__P3PLL_CBUS_ANTIGLITCH_RESETB__SHIFT 0x3 +#define DCCG_CBUS_SPARE__P0PLL_CBUS_SPARE_MASK 0xff +#define DCCG_CBUS_SPARE__P0PLL_CBUS_SPARE__SHIFT 0x0 +#define DCCG_CBUS_SPARE__P1PLL_CBUS_SPARE_MASK 0xff00 +#define DCCG_CBUS_SPARE__P1PLL_CBUS_SPARE__SHIFT 0x8 +#define DCCG_CBUS_SPARE__P2PLL_CBUS_SPARE_MASK 0xff0000 +#define DCCG_CBUS_SPARE__P2PLL_CBUS_SPARE__SHIFT 0x10 +#define DCCG_CBUS_SPARE__P3PLL_CBUS_SPARE_MASK 0xff000000 +#define DCCG_CBUS_SPARE__P3PLL_CBUS_SPARE__SHIFT 0x18 +#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf +#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100 +#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0xff +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION_MASK 0xff00 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff +#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0 +#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1 +#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0 +#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff +#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x30 +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 +#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 +#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 +#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 +#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 +#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 +#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 +#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 +#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 +#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 +#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 +#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 +#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 +#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40 +#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6 +#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI_MASK 0x80 +#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI__SHIFT 0x7 +#define SMU_CONTROL__MCIF_WB_FORCE_VBI_MASK 0x100 +#define SMU_CONTROL__MCIF_WB_FORCE_VBI__SHIFT 0x8 +#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 +#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80 +#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000 +#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000 +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000 +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000 +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x8 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x20 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x40 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x100 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x10000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x20000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x40000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x80000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x100000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x200000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x400000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x1000000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x2000000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 +#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0xf +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0xff0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x1 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x30 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x100 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x1 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x30 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x100 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x1 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x30 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x100 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x1 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x30 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x100 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x1 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x30 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x100 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x1 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x30 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x100 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x10 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x20 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x40 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x80 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x100 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN_MASK 0x800 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7 +#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE_MASK 0x10 +#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN_MASK 0x800 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7 +#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE_MASK 0x10 +#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN_MASK 0x800 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7 +#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE_MASK 0x10 +#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN_MASK 0x800 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7 +#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE_MASK 0x10 +#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN_MASK 0x800 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff +#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 +#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff +#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 +#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7 +#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE_MASK 0x10 +#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN_MASK 0x800 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff +#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 +#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff +#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 +#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7 +#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE_MASK 0x10 +#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000 +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000 +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000 +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c +#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17 +#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18 +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 +#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 +#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 +#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800 +#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x1f000 +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x7e0000 +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x11 +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d +#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE_MASK 0x80000000 +#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE__SHIFT 0x1f +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x3f +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x3f00 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0xf00000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0xf000000 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 +#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 +#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c +#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000 +#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d +#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000 +#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f +#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE_MASK 0xf +#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE__SHIFT 0x0 +#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE_MASK 0xf00 +#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf +#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0 +#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0 +#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4 +#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00 +#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8 +#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000 +#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc +#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000 +#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10 +#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000 +#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14 +#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000 +#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18 +#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000 +#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff +#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 +#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff +#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x1 +#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0 +#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xffffffff +#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0 +#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0xff +#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0 +#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0xff00 +#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8 +#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x3f0000 +#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10 +#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x3 +#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0 +#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE_MASK 0x30 +#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE__SHIFT 0x4 +#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x80 +#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7 +#define DVMM_CNTL__DBG_DCE_VMID_MASK 0xf00 +#define DVMM_CNTL__DBG_DCE_VMID__SHIFT 0x8 +#define DVMM_CNTL__FORCE_DBG_DCE_VMID_MASK 0x8000 +#define DVMM_CNTL__FORCE_DBG_DCE_VMID__SHIFT 0xf +#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x20000 +#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11 +#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x40000 +#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12 +#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xffffffff +#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0 +#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xffffffff +#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 +#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 +#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc +#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 +#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 +#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf +#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 +#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 +#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 +#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x3f0000 +#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xfff00000 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xffff +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800 +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000 +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000 +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000 +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x8000 +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x3 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10 +#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4 +#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40 +#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6 +#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100 +#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8 +#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600 +#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9 +#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800 +#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb +#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000 +#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000 +#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16 +#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000 +#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18 +#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000 +#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a +#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000 +#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM3_PWR_STATE_MASK 0xc0000000 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM3_PWR_STATE__SHIFT 0x1e +#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10 +#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4 +#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60 +#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5 +#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180 +#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7 +#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200 +#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9 +#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00 +#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa +#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000 +#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000 +#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf +#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000 +#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11 +#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000 +#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13 +#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000 +#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14 +#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000 +#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16 +#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000 +#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18 +#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE_MASK 0x30 +#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE_MASK 0xc0 +#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE_MASK 0x300 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x8 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE_MASK 0xc00 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE__SHIFT 0xa +#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE_MASK 0xc000 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE_MASK 0x30000 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE__SHIFT 0x10 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE_MASK 0xc0000 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE__SHIFT 0x12 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE_MASK 0x300000 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE__SHIFT 0x14 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE_MASK 0xc00000 +#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE__SHIFT 0x16 +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 +#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 +#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS_MASK 0x400 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS__SHIFT 0xa +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS_MASK 0x1000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS__SHIFT 0xc +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd +#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000 +#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 +#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 +#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS_MASK 0x2000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS__SHIFT 0x19 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS_MASK 0x4000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS__SHIFT 0x1a +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x1 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x2 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x4 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x8 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x10 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000 +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000 +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000 +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000 +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000 +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800 +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000 +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000 +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800 +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000 +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000 +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf +#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000 +#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000 +#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12 +#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000 +#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14 +#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000 +#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000 +#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b +#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000 +#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d +#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM_MASK 0x1 +#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM_MASK 0x2 +#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM__SHIFT 0x1 +#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM_MASK 0x4 +#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM_MASK 0x8 +#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM_MASK 0x10 +#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM__SHIFT 0x4 +#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM_MASK 0x20 +#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM__SHIFT 0x5 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x3 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x4 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x18 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x20 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0xc0 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x100 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x600 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x800 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x3000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x4000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x18000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x20000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0xc0000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x100000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x600000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x800000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x3000000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x3 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0xc +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x30 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0xc0 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x300 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0xc00 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x3000 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0xc000 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe +#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 +#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 +#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 +#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 +#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 +#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400 +#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa +#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800 +#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb +#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET_MASK 0x1000 +#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET__SHIFT 0xc +#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET_MASK 0x2000 +#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET__SHIFT 0xd +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x4000 +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xe +#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000 +#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10 +#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000 +#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11 +#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000 +#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12 +#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET_MASK 0x80000 +#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET__SHIFT 0x13 +#define DCI_MISC__MCIF_WB_URG_OVRD_MASK 0x1 +#define DCI_MISC__MCIF_WB_URG_OVRD__SHIFT 0x0 +#define DCI_MISC__MCIF_WB_URG_LVL_MASK 0x1e +#define DCI_MISC__MCIF_WB_URG_LVL__SHIFT 0x1 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1 +#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0 +#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0 +#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4 +#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00 +#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define DC_GENERICA__GENERICA_EN_MASK 0x1 +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL_MASK 0xf80 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x1 +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL_MASK 0xf00 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 +#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000 +#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000 +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_BIASENTST_MASK 0x380000 +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_BIASENTST__SHIFT 0x13 +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_RESBIASEN_MASK 0x400000 +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_RESBIASEN__SHIFT 0x16 +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_SPARE_CONTROL_MASK 0x1800000 +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_SPARE_CONTROL__SHIFT 0x17 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0 +#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0 +#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 +#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00 +#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc +#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0xf0000 +#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 +#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP_MASK 0x3800000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP__SHIFT 0x17 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP_MASK 0x1c000000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP__SHIFT 0x1a +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f +#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1 +#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0 +#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10 +#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4 +#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300 +#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8 +#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000 +#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1 +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0 +#define DCIO_DEBUG_CONFIG__DCIO_DBG_SEL_MASK 0xf00 +#define DCIO_DEBUG_CONFIG__DCIO_DBG_SEL__SHIFT 0x8 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800 +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000 +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000 +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000 +#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000 +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000 +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 +#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x4000000 +#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a +#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000 +#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c +#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000 +#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d +#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000 +#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e +#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000 +#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f +#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3 +#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 +#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc +#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2 +#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30 +#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4 +#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0 +#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE_MASK 0x1 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE__SHIFT 0x0 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK_MASK 0x2 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK__SHIFT 0x1 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR_MASK 0x4 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR__SHIFT 0x2 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE_MASK 0x8 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE__SHIFT 0x3 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK_MASK 0x10 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK__SHIFT 0x4 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR_MASK 0x20 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR__SHIFT 0x5 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE_MASK 0x40 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE__SHIFT 0x6 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK_MASK 0x80 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK__SHIFT 0x7 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR_MASK 0x100 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR__SHIFT 0x8 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE_MASK 0x200 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE__SHIFT 0x9 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK_MASK 0x400 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK__SHIFT 0xa +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR_MASK 0x800 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR__SHIFT 0xb +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE_MASK 0x1000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE__SHIFT 0xc +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK_MASK 0x2000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK__SHIFT 0xd +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR_MASK 0x4000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR__SHIFT 0xe +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE_MASK 0x8000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE__SHIFT 0xf +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK_MASK 0x10000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK__SHIFT 0x10 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR_MASK 0x20000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR__SHIFT 0x11 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE_MASK 0x40000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE__SHIFT 0x12 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK_MASK 0x80000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK__SHIFT 0x13 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR_MASK 0x100000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR__SHIFT 0x14 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE_MASK 0x1000000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE__SHIFT 0x18 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK_MASK 0x2000000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK__SHIFT 0x19 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR_MASK 0x4000000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR__SHIFT 0x1a +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE_MASK 0x8000000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE__SHIFT 0x1b +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK_MASK 0x10000000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK__SHIFT 0x1c +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR_MASK 0x20000000 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR__SHIFT 0x1d +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE_MASK 0x1 +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE__SHIFT 0x0 +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK_MASK 0x2 +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK__SHIFT 0x1 +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR_MASK 0x4 +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR__SHIFT 0x2 +#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ_MASK 0xffff +#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT_MASK 0xffff0000 +#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ_MASK 0xffff +#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT_MASK 0xffff0000 +#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ_MASK 0xffff +#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT_MASK 0xffff0000 +#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ_MASK 0xffff +#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT_MASK 0xffff0000 +#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ_MASK 0xffff +#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT_MASK 0xffff0000 +#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ_MASK 0xffff +#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT_MASK 0xffff0000 +#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ_MASK 0xffff +#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT_MASK 0xffff0000 +#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ_MASK 0xffff +#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT_MASK 0xffff0000 +#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT__SHIFT 0x10 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 +#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 +#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 +#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17 +#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 +#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b +#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff +#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 +#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff +#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 +#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff +#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 +#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff +#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 +#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff +#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 +#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff +#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 +#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff +#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 +#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff +#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 +#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff +#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 +#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff +#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 +#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff +#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 +#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff +#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff +#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 +#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff +#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0 +#define DCIO_DEBUG17__DCIO_DEBUG17_MASK 0xffffffff +#define DCIO_DEBUG17__DCIO_DEBUG17__SHIFT 0x0 +#define DCIO_DEBUG18__DCIO_DEBUG18_MASK 0xffffffff +#define DCIO_DEBUG18__DCIO_DEBUG18__SHIFT 0x0 +#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG1B__DCIO_DEBUGHPD_MASK 0xffffffff +#define DCIO_DEBUG1B__DCIO_DEBUGHPD__SHIFT 0x0 +#define DCIO_DEBUG1C__DCIO_DEBUG_UNIPHYA_CFG_MASK 0xffffffff +#define DCIO_DEBUG1C__DCIO_DEBUG_UNIPHYA_CFG__SHIFT 0x0 +#define DCIO_DEBUG1D__DCIO_DEBUG_UNIPHYB_CFG_MASK 0xffffffff +#define DCIO_DEBUG1D__DCIO_DEBUG_UNIPHYB_CFG__SHIFT 0x0 +#define DCIO_DEBUG1E__DCIO_DEBUG_UNIPHYC_CFG_MASK 0xffffffff +#define DCIO_DEBUG1E__DCIO_DEBUG_UNIPHYC_CFG__SHIFT 0x0 +#define DCIO_DEBUG1F__DCIO_DEBUG_UNIPHYD_CFG_MASK 0xffffffff +#define DCIO_DEBUG1F__DCIO_DEBUG_UNIPHYD_CFG__SHIFT 0x0 +#define DCIO_DEBUG20__DCIO_DEBUG_UNIPHYE_CFG_MASK 0xffffffff +#define DCIO_DEBUG20__DCIO_DEBUG_UNIPHYE_CFG__SHIFT 0x0 +#define DCIO_DEBUG21__DCIO_DEBUG_UNIPHYF_CFG_MASK 0xffffffff +#define DCIO_DEBUG21__DCIO_DEBUG_UNIPHYF_CFG__SHIFT 0x0 +#define DCIO_DEBUG22__DCIO_DEBUG_UNIPHYG_CFG_MASK 0xffffffff +#define DCIO_DEBUG22__DCIO_DEBUG_UNIPHYG_CFG__SHIFT 0x0 +#define DCIO_DEBUG23__DCIO_DEBUG_UNIPHYLPA_CFG_MASK 0xffffffff +#define DCIO_DEBUG23__DCIO_DEBUG_UNIPHYLPA_CFG__SHIFT 0x0 +#define DCIO_DEBUG24__DCIO_DEBUG_UNIPHYLPB_CFG_MASK 0xffffffff +#define DCIO_DEBUG24__DCIO_DEBUG_UNIPHYLPB_CFG__SHIFT 0x0 +#define DCIO_DEBUG25__DCIO_DEBUG_DCRXPHY_CFG_MASK 0xffffffff +#define DCIO_DEBUG25__DCIO_DEBUG_DCRXPHY_CFG__SHIFT 0x0 +#define DCIO_DEBUG26__DCIO_DEBUG_DPHY_CFG_MASK 0xffffffff +#define DCIO_DEBUG26__DCIO_DEBUG_DPHY_CFG__SHIFT 0x0 +#define DCIO_DEBUG27__DCIO_DEBUG_DACA_CFG_MASK 0xffffffff +#define DCIO_DEBUG27__DCIO_DEBUG_DACA_CFG__SHIFT 0x0 +#define DCIO_DEBUG28__DCIO_DEBUG_ZCAL_CFG_MASK 0xffffffff +#define DCIO_DEBUG28__DCIO_DEBUG_ZCAL_CFG__SHIFT 0x0 +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV1_MASK 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV1__SHIFT 0x3 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV1_MASK 0x80 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV1__SHIFT 0x7 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV1_MASK 0x800 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV1__SHIFT 0xb +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV1_MASK 0x8000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV1__SHIFT 0xf +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV1_MASK 0x80000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV1__SHIFT 0x13 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV1_MASK 0x800000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV1__SHIFT 0x17 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV1_MASK 0x8000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV1__SHIFT 0x1b +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV1_MASK 0x80 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV1__SHIFT 0x7 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV1_MASK 0x8000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV1__SHIFT 0xf +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV1_MASK 0x80 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV1__SHIFT 0x7 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV1_MASK 0x8000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV1__SHIFT 0xf +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV1_MASK 0x80 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV1__SHIFT 0x7 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV1_MASK 0x8000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV1__SHIFT 0xf +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV1_MASK 0x80 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV1__SHIFT 0x7 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV1_MASK 0x8000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV1__SHIFT 0xf +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV1_MASK 0x80 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV1__SHIFT 0x7 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV1_MASK 0x8000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV1__SHIFT 0xf +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV1_MASK 0x80 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV1__SHIFT 0x7 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV1_MASK 0x8000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV1__SHIFT 0xf +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 +#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 +#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV1_MASK 0x80 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV1__SHIFT 0x7 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV1_MASK 0x8000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV1__SHIFT 0xf +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RXSEL_MASK 0x30000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RXSEL__SHIFT 0x10 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPARE_MASK 0xc0000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPARE__SHIFT 0x12 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_BIASCRTEN_MASK 0x100000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL0P9_MASK 0x200000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL0P9__SHIFT 0x15 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL1P1_MASK 0x400000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL1P1__SHIFT 0x16 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_COMPSEL_MASK 0x800000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_COMPSEL__SHIFT 0x17 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL0P9_MASK 0x1000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL0P9__SHIFT 0x18 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL1P1_MASK 0x2000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL1P1__SHIFT 0x19 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCEN_MASK 0x4000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCEN__SHIFT 0x1a +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCSEL_MASK 0x8000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_FALLSLEWSEL_MASK 0x30000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_FALLSLEWSEL__SHIFT 0x1c +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RESBIASEN_MASK 0x40000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RESBIASEN__SHIFT 0x1e +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SLEWN_MASK 0x80000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SLEWN__SHIFT 0x1f +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV1_MASK 0x80 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV1__SHIFT 0x7 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV1_MASK 0x8000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV1__SHIFT 0xf +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV1_MASK 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV1__SHIFT 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV1_MASK 0x20 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV1__SHIFT 0x5 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV1_MASK 0x100000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV1__SHIFT 0x14 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV1_MASK 0x800000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV1__SHIFT 0x17 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV_MASK 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV__SHIFT 0x3 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV1_MASK 0x20 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV1__SHIFT 0x5 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV1_MASK 0x80 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV1__SHIFT 0x7 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV1_MASK 0x800 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV1__SHIFT 0xb +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV1_MASK 0x80000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV1__SHIFT 0x13 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV1_MASK 0x800000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV1__SHIFT 0x17 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV1_MASK 0x8000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV1__SHIFT 0x1b +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV1_MASK 0x80000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV1__SHIFT 0x1f +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x20 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x200 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x400 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x20000 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x40000 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x100000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x200000 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x400000 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x1000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x2000000 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x4000000 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000 +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000 +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV1_MASK 0x80 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV1__SHIFT 0x7 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV1_MASK 0x8000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV1__SHIFT 0xf +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV1_MASK 0x800000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV1__SHIFT 0x17 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV1_MASK 0x8000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV1__SHIFT 0x1b +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV1_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV1__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0xf0000 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0xf00000 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000 +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe +#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x30000 +#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX_PAD_RESBIASEN_MASK 0x40000 +#define PHY_AUX_CNTL__AUX_PAD_RESBIASEN__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX_PAD_COMPSEL_MASK 0x80000 +#define PHY_AUX_CNTL__AUX_PAD_COMPSEL__SHIFT 0x13 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_DATA_PD_EN_MASK 0x4 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_DATA_PD_EN__SHIFT 0x2 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RXSEL_MASK 0x30000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RXSEL__SHIFT 0x10 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPARE_MASK 0xc0000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPARE__SHIFT 0x12 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_BIASCRTEN_MASK 0x100000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL0P9_MASK 0x200000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL0P9__SHIFT 0x15 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL1P1_MASK 0x400000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL1P1__SHIFT 0x16 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_COMPSEL_MASK 0x800000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_COMPSEL__SHIFT 0x17 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL0P9_MASK 0x1000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL0P9__SHIFT 0x18 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL1P1_MASK 0x2000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL1P1__SHIFT 0x19 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCEN_MASK 0x4000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCEN__SHIFT 0x1a +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCSEL_MASK 0x8000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_FALLSLEWSEL_MASK 0x30000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_FALLSLEWSEL__SHIFT 0x1c +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RESBIASEN_MASK 0x40000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RESBIASEN__SHIFT 0x1e +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SLEWN_MASK 0x80000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SLEWN__SHIFT 0x1f +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 +#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1 +#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 +#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2 +#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 +#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0 +#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 +#define DC_GPIO_RECEIVER_EN0__VIPPAD_SCL_RECEN_MASK 0x1 +#define DC_GPIO_RECEIVER_EN0__VIPPAD_SCL_RECEN__SHIFT 0x0 +#define DC_GPIO_RECEIVER_EN0__VIPPAD_SDA_RECEN_MASK 0x2 +#define DC_GPIO_RECEIVER_EN0__VIPPAD_SDA_RECEN__SHIFT 0x1 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_RX_HPD_RECEN_MASK 0x10000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_RX_HPD_RECEN__SHIFT 0x10 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_HPD1_RECEN_MASK 0x20000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_HPD1_RECEN__SHIFT 0x11 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_VSYNC_RECEN_MASK 0x40000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_VSYNC_RECEN__SHIFT 0x12 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_CLK_RECEN_MASK 0x80000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_CLK_RECEN__SHIFT 0x13 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_VSYNCA_RECEN_MASK 0x100000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_VSYNCA_RECEN__SHIFT 0x14 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_HSYNCA_RECEN_MASK 0x200000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_HSYNCA_RECEN__SHIFT 0x15 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICG_RECEN_MASK 0x400000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICG_RECEN__SHIFT 0x16 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICF_RECEN_MASK 0x800000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICF_RECEN__SHIFT 0x17 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICE_RECEN_MASK 0x1000000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICE_RECEN__SHIFT 0x18 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICD_RECEN_MASK 0x2000000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICD_RECEN__SHIFT 0x19 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICC_RECEN_MASK 0x4000000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICC_RECEN__SHIFT 0x1a +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICB_RECEN_MASK 0x8000000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICB_RECEN__SHIFT 0x1b +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICA_RECEN_MASK 0x10000000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICA_RECEN__SHIFT 0x1c +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_BLON_RECEN_MASK 0x20000000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_BLON_RECEN__SHIFT 0x1d +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_DIGON_RECEN_MASK 0x40000000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_DIGON_RECEN__SHIFT 0x1e +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_DDC2DATA_RECEN_MASK 0x80000000 +#define DC_GPIO_RECEIVER_EN0__DC_GPIO_DDC2DATA_RECEN__SHIFT 0x1f +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC2CLK_RECEN_MASK 0x1 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC2CLK_RECEN__SHIFT 0x0 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1DATA_RECEN_MASK 0x2 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1DATA_RECEN__SHIFT 0x1 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1CLK_RECEN_MASK 0x4 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1CLK_RECEN__SHIFT 0x2 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3DATA_RECEN_MASK 0x8 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3DATA_RECEN__SHIFT 0x3 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3CLK_RECEN_MASK 0x10 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3CLK_RECEN__SHIFT 0x4 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4DATA_RECEN_MASK 0x20 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4DATA_RECEN__SHIFT 0x5 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4CLK_RECEN_MASK 0x40 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4CLK_RECEN__SHIFT 0x6 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5DATA_RECEN_MASK 0x80 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5DATA_RECEN__SHIFT 0x7 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5CLK_RECEN_MASK 0x100 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5CLK_RECEN__SHIFT 0x8 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6DATA_RECEN_MASK 0x200 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6DATA_RECEN__SHIFT 0x9 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6CLK_RECEN_MASK 0x400 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6CLK_RECEN__SHIFT 0xa +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD2_RECEN_MASK 0x800 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD2_RECEN__SHIFT 0xb +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD3_RECEN_MASK 0x1000 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD3_RECEN__SHIFT 0xc +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD4_RECEN_MASK 0x2000 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD4_RECEN__SHIFT 0xd +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD5_RECEN_MASK 0x4000 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD5_RECEN__SHIFT 0xe +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD6_RECEN_MASK 0x8000 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD6_RECEN__SHIFT 0xf +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_ENA_BL_RECEN_MASK 0x10000 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_ENA_BL_RECEN__SHIFT 0x10 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_A_RECEN_MASK 0x20000 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_A_RECEN__SHIFT 0x11 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_B_RECEN_MASK 0x40000 +#define DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_B_RECEN__SHIFT 0x12 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0xf +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x10 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x20 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x40 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x80 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x100 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x200 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x400 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x800 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x1000 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0xf +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x10 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x20 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x40 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x80 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x100 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x200 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x400 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x800 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x1000 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0xf +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x10 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x20 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x40 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x80 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x100 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x200 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x400 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x800 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x1000 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT_MASK 0x2000 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT__SHIFT 0xd +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU_MASK 0x4000 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU__SHIFT 0xe +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL_MASK 0x8000 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL__SHIFT 0xf +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN_MASK 0x10000 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN__SHIFT 0x10 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN_MASK 0x20000 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN__SHIFT 0x11 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE_MASK 0x40000 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE__SHIFT 0x12 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0xf +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x10 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x20 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x40 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x80 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x100 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x200 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x400 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x800 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x1000 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x7 +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK 0x700 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK 0x3800 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x70000 +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN_MASK 0x7000000 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP_MASK 0x38000000 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP__SHIFT 0x1b +#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x1 +#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0 +#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x2 +#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 +#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x10 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x20 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x40 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x80 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x100 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x200 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x3 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x30 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0xc0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x300 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0xc00 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x10000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x20000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x40000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x80000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x100000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x200000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x1000000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x2000000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x4000000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x8000000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_0P9_MASK 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_0P9__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_0P9_MASK 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_0P9__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_0P9_MASK 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_0P9__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_0P9_MASK 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_0P9__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_0P9_MASK 0x10 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_0P9_MASK 0x20 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_0P9__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_1P1_MASK 0x100 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_1P1__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_1P1_MASK 0x200 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_1P1__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_1P1_MASK 0x400 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_1P1__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_1P1_MASK 0x800 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_1P1__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_1P1_MASK 0x1000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_1P1__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_1P1_MASK 0x2000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_1P1__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_0P9_MASK 0x10000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_0P9__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_0P9_MASK 0x20000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_0P9__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_0P9_MASK 0x40000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_0P9__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_0P9_MASK 0x80000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_0P9__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_0P9_MASK 0x100000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_0P9__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_0P9_MASK 0x200000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_0P9__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_1P1_MASK 0x1000000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_1P1__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_1P1_MASK 0x2000000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_1P1__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_1P1_MASK 0x4000000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_1P1__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_1P1_MASK 0x8000000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_1P1__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_1P1_MASK 0x10000000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_1P1__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_1P1_MASK 0x20000000 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_1P1__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX1_BIASCRTEN_MASK 0x1 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX1_BIASCRTEN__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX2_BIASCRTEN_MASK 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX2_BIASCRTEN__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX3_BIASCRTEN_MASK 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX3_BIASCRTEN__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX4_BIASCRTEN_MASK 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX4_BIASCRTEN__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX5_BIASCRTEN_MASK 0x10 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX5_BIASCRTEN__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX6_BIASCRTEN_MASK 0x20 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX6_BIASCRTEN__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX1_SPARE_MASK 0xc0 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX1_SPARE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX2_SPARE_MASK 0x300 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX2_SPARE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX3_SPARE_MASK 0xc00 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX3_SPARE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX4_SPARE_MASK 0x3000 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX4_SPARE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX5_SPARE_MASK 0xc000 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX5_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX6_SPARE_MASK 0x30000 +#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX6_SPARE__SHIFT 0x10 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x3 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0xc +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x30 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCEN_MASK 0x100 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCEN_MASK 0x200 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCEN_MASK 0x400 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x1000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x2000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x4000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_0P9_MASK 0x10000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_0P9__SHIFT 0x10 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_0P9_MASK 0x20000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_0P9__SHIFT 0x11 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_0P9_MASK 0x40000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_0P9__SHIFT 0x12 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_1P1_MASK 0x100000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_1P1__SHIFT 0x14 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_1P1_MASK 0x200000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_1P1__SHIFT 0x15 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_1P1_MASK 0x400000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_1P1__SHIFT 0x16 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_0P9_MASK 0x1000000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_0P9__SHIFT 0x18 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_0P9_MASK 0x2000000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_0P9__SHIFT 0x19 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_0P9_MASK 0x4000000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_0P9__SHIFT 0x1a +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_1P1_MASK 0x10000000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_1P1__SHIFT 0x1c +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_1P1_MASK 0x20000000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_1P1__SHIFT 0x1d +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_1P1_MASK 0x40000000 +#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_1P1__SHIFT 0x1e +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_BIASCRTEN_MASK 0x1 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_BIASCRTEN__SHIFT 0x0 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_BIASCRTEN_MASK 0x2 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_BIASCRTEN__SHIFT 0x1 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_BIASCRTEN_MASK 0x4 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_BIASCRTEN__SHIFT 0x2 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_SLEWN_MASK 0x10 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_SLEWN__SHIFT 0x4 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_SLEWN_MASK 0x20 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_SLEWN__SHIFT 0x5 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_SLEWN_MASK 0x40 +#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_SLEWN__SHIFT 0x6 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 +#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 +#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x2 +#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1 +#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 +#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 +#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc +#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 +#define GRPH_CONTROL__GRPH_Z_MASK 0x30 +#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4 +#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 +#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 +#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 +#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb +#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 +#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 +#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 +#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 +#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 +#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff +#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0 +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0 +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0 +#define GRPH_X_START__GRPH_X_START_MASK 0x3fff +#define GRPH_X_START__GRPH_X_START__SHIFT 0x0 +#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff +#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0 +#define GRPH_X_END__GRPH_X_END_MASK 0x7fff +#define GRPH_X_END__GRPH_X_END__SHIFT 0x0 +#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff +#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x1 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 +#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 +#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0 +#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2 +#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x10 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x20 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6 +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0xff +#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0 +#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff +#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10 +#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff +#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10 +#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff +#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10 +#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff +#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10 +#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff +#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10 +#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff +#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10 +#define DENORM_CONTROL__DENORM_MODE_MASK 0x7 +#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0 +#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10 +#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4 +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10 +#define KEY_CONTROL__KEY_MODE_MASK 0x6 +#define KEY_CONTROL__KEY_MODE__SHIFT 0x1 +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10 +#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff +#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0 +#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000 +#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10 +#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff +#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10 +#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff +#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10 +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3 +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0 +#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300 +#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3 +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8 +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200 +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 +#define CUR_CONTROL__CURSOR_EN_MASK 0x1 +#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4 +#define CUR_CONTROL__CURSOR_MODE_MASK 0x300 +#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0xf000 +#define CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc +#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18 +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f +#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000 +#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff +#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000 +#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff +#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0 +#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00 +#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8 +#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000 +#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10 +#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff +#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0 +#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00 +#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8 +#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000 +#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000 +#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1 +#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0 +#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000 +#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000 +#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11 +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0 +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0 +#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff +#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1 +#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf +#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6 +#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00 +#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe +#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000 +#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16 +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0 +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8 +#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff +#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0 +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0 +#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1 +#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0 +#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e +#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1 +#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0 +#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5 +#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00 +#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9 +#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000 +#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14 +#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000 +#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15 +#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff +#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0 +#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff +#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 +#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1 +#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0 +#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2 +#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1 +#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4 +#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000 +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4 +#define DCP_DEBUG_SG__DCP_DEBUG_SG_MASK 0xffffffff +#define DCP_DEBUG_SG__DCP_DEBUG_SG__SHIFT 0x0 +#define DCP_DEBUG_SG2__DCP_DEBUG_SG2_MASK 0xffffffff +#define DCP_DEBUG_SG2__DCP_DEBUG_SG2__SHIFT 0x0 +#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG_MASK 0xffffffff +#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG__SHIFT 0x0 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff +#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0 +#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7 +#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0 +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0 +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1 +#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0 +#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2 +#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x1 +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0 +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x1e +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1 +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x200 +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9 +#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0xffff +#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0 +#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xffff0000 +#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100 +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG_FE_CNTL__DIG_START_MASK 0x400 +#define DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000 +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000 +#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000 +#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1 +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100 +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000 +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x4000000 +#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000 +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1 +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4 +#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8 +#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100 +#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200 +#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1 +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000 +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000 +#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1 +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1 +#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10 +#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00 +#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000 +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7 +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40 +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0xe000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0xff +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff +#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff +#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff +#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff +#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1 +#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2 +#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4 +#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38 +#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0 +#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000 +#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000 +#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100 +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7 +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x1 +#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x100 +#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1 +#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2 +#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4 +#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000 +#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000 +#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1 +#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1 +#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1 +#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11 +#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000 +#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19 +#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1 +#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100 +#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000 +#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000 +#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG_VERSION__DIG_TYPE_MASK 0x1 +#define DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1 +#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2 +#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4 +#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8 +#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100 +#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff +#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMCU_CTRL__RESET_UC_MASK 0x1 +#define DMCU_CTRL__RESET_UC__SHIFT 0x0 +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2 +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10 +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x100 +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x1 +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2 +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4 +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800 +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800 +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000 +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000 +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000 +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000 +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000 +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x1 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x1 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x2 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR_MASK 0x2 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x4 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x4 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x8 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x8 +#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x10 +#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR_MASK 0x10 +#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED_MASK 0x20 +#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR_MASK 0x20 +#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN_MASK 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN_MASK 0x20 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10 +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100 +#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x200 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x20000 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11 +#define DP_CONFIG__DP_UDI_LANES_MASK 0x3 +#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78 +#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3 +#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00 +#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000 +#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000 +#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1 +#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0 +#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x10 +#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x200 +#define DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9 +#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000 +#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP_VID_N__DP_VID_N_MASK 0xffffff +#define DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP_VID_M__DP_VID_M_MASK 0xffffff +#define DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1 +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000 +#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3 +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff +#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00 +#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000 +#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff +#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00 +#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000 +#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff +#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00 +#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000 +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x10000 +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x7 +#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10 +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1 +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10 +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000 +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1 +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x10 +#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x20 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x40 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x80 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xffff0000 +#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff +#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff +#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1 +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000 +#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10 +#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x7 +#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x3f00 +#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x70000 +#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3f000000 +#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x7 +#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x3f00 +#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x70000 +#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3f000000 +#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x7 +#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x3f00 +#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x70000 +#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3f000000 +#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff +#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0 +#define AUX_CONTROL__AUX_EN_MASK 0x1 +#define AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define AUX_CONTROL__AUX_RESET_MASK 0x10 +#define AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define AUX_CONTROL__AUX_RESET_DONE_MASK 0x20 +#define AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100 +#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000 +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000 +#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000 +#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000 +#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000 +#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define AUX_CONTROL__SPARE_0_MASK 0x40000000 +#define AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define AUX_CONTROL__SPARE_1_MASK 0x80000000 +#define AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1 +#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000 +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1 +#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2 +#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100 +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800 +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000 +#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1 +#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2 +#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100 +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800 +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000 +#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000 +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1 +#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00 +#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000 +#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00 +#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000 +#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000 +#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0 +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff +#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0 +#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff +#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff +#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff +#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff +#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff +#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff +#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff +#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff +#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff +#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff +#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff +#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0 +#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff +#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0 +#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff +#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0 +#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff +#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0 +#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff +#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0 +#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff +#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0 +#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff +#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0 +#define DVO_ENABLE__DVO_ENABLE_MASK 0x1 +#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0 +#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30 +#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0 +#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100 +#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8 +#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1 +#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0 +#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2 +#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1 +#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30 +#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4 +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100 +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8 +#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000 +#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10 +#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000 +#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11 +#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000 +#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12 +#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000 +#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14 +#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000 +#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15 +#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000 +#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16 +#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000 +#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18 +#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000 +#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f +#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000 +#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10 +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0 +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0 +#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1 +#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0 +#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe +#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1 +#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x100 +#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8 +#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN_MASK 0x400 +#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN__SHIFT 0xa +#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000 +#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19 +#define FBC_CNTL__FBC_EN_MASK 0x80000000 +#define FBC_CNTL__FBC_EN__SHIFT 0x1f +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0 +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8 +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14 +#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1 +#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8 +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200 +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800 +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb +#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000 +#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10 +#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff +#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0 +#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 +#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10 +#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000 +#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11 +#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000 +#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18 +#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff +#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0 +#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff +#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0 +#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffffff +#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0 +#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffffff +#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0 +#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffffff +#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0 +#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffffff +#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0 +#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffffff +#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0 +#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffffff +#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0 +#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffffff +#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0 +#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffffff +#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0 +#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffffff +#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0 +#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffffff +#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0 +#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffffff +#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0 +#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffffff +#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0 +#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffffff +#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0 +#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffffff +#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0 +#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffffff +#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0 +#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffffff +#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0xfff +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0xfff0000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0xfff +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0xfff0000 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0 +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8 +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3 +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0 +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800 +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0xfff +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0 +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0 +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0 +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3 +#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0 +#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4 +#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3 +#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0 +#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4 +#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300 +#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8 +#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400 +#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa +#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800 +#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000 +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc +#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x2000 +#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10 +#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000 +#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14 +#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000 +#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15 +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000 +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18 +#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000 +#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f +#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1 +#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0 +#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN_MASK 0x1 +#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN__SHIFT 0x0 +#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF_MASK 0x10 +#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF__SHIFT 0x4 +#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN_MASK 0x100 +#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN__SHIFT 0x8 +#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL_MASK 0xff +#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL__SHIFT 0x0 +#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL_MASK 0xff000 +#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL__SHIFT 0xc +#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL_MASK 0xff000000 +#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL__SHIFT 0x18 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x30000 +#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0xc0000 +#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x100000 +#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x200000 +#define FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000 +#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18 +#define FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000 +#define FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e +#define FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000 +#define FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000 +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000 +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000 +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000 +#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000 +#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000 +#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1 +#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0 +#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2 +#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4 +#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x20 +#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5 +#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x40 +#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6 +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100 +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8 +#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x200 +#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0 +#define FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x1fff +#define FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0xfff +#define FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0 +#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff +#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0 +#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff +#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0 +#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff +#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0 +#define FMT_DEBUG3__FMT_DEBUG3_MASK 0xffffffff +#define FMT_DEBUG3__FMT_DEBUG3__SHIFT 0x0 +#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff +#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0 +#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 +#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 +#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 +#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 +#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 +#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 +#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 +#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 +#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 +#define LB_DATA_FORMAT__PREFILL_EN_MASK 0x100 +#define LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8 +#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000 +#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc +#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 +#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 +#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 +#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x1fff +#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 +#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 +#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 +#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 +#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x1fff +#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 +#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff +#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 +#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff +#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0 +#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000 +#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10 +#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000 +#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f +#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff +#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0 +#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 +#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10 +#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 +#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f +#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff +#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff +#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 +#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 +#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 +#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 +#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 +#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 +#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 +#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 +#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 +#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10 +#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 +#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000 +#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc +#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 +#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 +#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 +#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 +#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 +#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 +#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 +#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 +#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 +#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 +#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 +#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 +#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 +#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 +#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 +#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 +#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 +#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 +#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 +#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 +#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 +#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 +#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 +#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 +#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 +#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 +#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa +#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 +#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 +#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 +#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3 +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f +#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff +#define LB_DEBUG__LB_DEBUG__SHIFT 0x0 +#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff +#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0 +#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff +#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 +#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 +#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 +#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 +#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 +#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 +#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 +#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 +#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 +#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 +#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40 +#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6 +#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80 +#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7 +#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000 +#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc +#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 +#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 +#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 +#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff +#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 +#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 +#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 +#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 +#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff +#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 +#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff +#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 +#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff +#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0 +#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000 +#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10 +#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000 +#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f +#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff +#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0 +#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 +#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10 +#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 +#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f +#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff +#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff +#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 +#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff +#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0 +#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff +#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0 +#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 +#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 +#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 +#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 +#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 +#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 +#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 +#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 +#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10 +#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 +#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000 +#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 +#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 +#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 +#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 +#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 +#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 +#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 +#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 +#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 +#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 +#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 +#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 +#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 +#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 +#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 +#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 +#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 +#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 +#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 +#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 +#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 +#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 +#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 +#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 +#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa +#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 +#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 +#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 +#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 +#define LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT_MASK 0x2000000 +#define LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT__SHIFT 0x19 +#define LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL_MASK 0x1c000000 +#define LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL__SHIFT 0x1a +#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 +#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 +#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff +#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0 +#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff +#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0 +#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff +#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff +#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MVP_CONTROL1__MVP_EN_MASK 0x1 +#define MVP_CONTROL1__MVP_EN__SHIFT 0x0 +#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70 +#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9 +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400 +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa +#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000 +#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000 +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18 +#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000 +#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000 +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000 +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc +#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000 +#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14 +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000 +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10 +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14 +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0 +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00 +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10 +#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000 +#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000 +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000 +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10 +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7 +#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00 +#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe +#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe +#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1 +#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000 +#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a +#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000 +#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b +#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7 +#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6 +#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200 +#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9 +#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400 +#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800 +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000 +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc +#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000 +#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13 +#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000 +#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define SCL_MODE__SCL_MODE_MASK 0x3 +#define SCL_MODE__SCL_MODE__SHIFT 0x0 +#define SCL_MODE__SCL_PSCL_EN_MASK 0x10 +#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4 +#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 +#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 +#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00 +#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8 +#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 +#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 +#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0 +#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 +#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 +#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 +#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 +#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 +#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 +#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 +#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff +#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 +#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 +#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 +#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff +#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 +#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 +#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 +#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 +#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 +#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 +#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 +#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 +#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3 +#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff +#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define SCLV_MODE__SCL_MODE_MASK 0x3 +#define SCLV_MODE__SCL_MODE__SHIFT 0x0 +#define SCLV_MODE__SCL_MODE_C_MASK 0xc +#define SCLV_MODE__SCL_MODE_C__SHIFT 0x2 +#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10 +#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4 +#define SCLV_MODE__SCL_PSCL_EN_C_MASK 0x20 +#define SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5 +#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300 +#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc +#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 +#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 +#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 +#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100 +#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 +#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff +#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff +#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff +#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff +#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 +#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 +#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 +#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 +#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 +#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 +#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 +#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 +#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 +#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff +#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 +#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff +#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 +#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff +#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0 +#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 +#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 +#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 +#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff +#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 +#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 +#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18 +#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18 +#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 +#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 +#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 +#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 +#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 +#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3 +#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff +#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff +#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10 +#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x300 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10000 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10 +#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3 +#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0 +#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff +#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0 +#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000 +#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10 +#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff +#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0 +#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000 +#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10 +#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff +#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0 +#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000 +#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10 +#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7 +#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10 +#define DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x3 +#define DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0 +#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x100 +#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000 +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 +#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3 +#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0 +#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0xff +#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0 +#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff +#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0 +#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7 +#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff +#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff +#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b +#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x1 +#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0 +#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x2 +#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1 +#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x100 +#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8 +#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x200 +#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9 +#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x10000 +#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10 +#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x20000 +#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11 +#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x1000000 +#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18 +#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x2000000 +#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x1 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x2 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x100 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x200 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9 +#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x1 +#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0 +#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x2 +#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1 +#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0xff +#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0 +#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0xffff +#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0 +#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0xffff +#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0 +#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xffff0000 +#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10 +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x3ff +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0 +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0xffc00 +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3ff00000 +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14 +#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x3 +#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0 +#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x4000000 +#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x1e +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x20 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0xc0 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0xf00 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x1000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x6000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x78000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x80000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x300000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x400000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x3800000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x4000000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x8000000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b +#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0xffff +#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0 +#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xffff0000 +#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10 +#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0xffff +#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0 +#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xffff0000 +#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10 +#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0xffff +#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0 +#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xffff0000 +#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10 +#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1 +#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0 +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0 +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff +#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0 +#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 +#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 +#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 +#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 +#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc +#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 +#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30 +#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4 +#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0xc0 +#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6 +#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 +#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 +#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x1800 +#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb +#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0xe000 +#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd +#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0xc0000 +#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12 +#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 +#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 +#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 +#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 +#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000 +#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d +#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 +#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f +#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0xc0 +#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6 +#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x1800 +#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb +#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0xe000 +#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd +#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0xc0000 +#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12 +#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000 +#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d +#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7 +#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0 +#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 +#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 +#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 +#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 +#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 +#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 +#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 +#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff +#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0 +#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff +#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0 +#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff +#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0 +#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff +#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0 +#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff +#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0 +#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff +#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0 +#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff +#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0 +#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff +#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0 +#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff +#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0 +#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff +#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 +#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 +#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 +#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c +#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0xff +#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0 +#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0xff00 +#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8 +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0 +#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1 +#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0 +#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e +#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1 +#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0 +#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5 +#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00 +#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9 +#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000 +#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14 +#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000 +#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x1 +#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0 +#define UNP_FLIP_CONTROL__UNP_DEBUG_SG_MASK 0xfffffffc +#define UNP_FLIP_CONTROL__UNP_DEBUG_SG__SHIFT 0x2 +#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1 +#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0 +#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c +#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2 +#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300 +#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8 +#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff +#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0 +#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff +#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0 +#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff +#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0 +#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0 +#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4 +#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7 +#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0 +#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10 +#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4 +#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100 +#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8 +#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff +#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0 +#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff +#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0 +#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG_MASK 0xffff +#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG__SHIFT 0x0 +#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG_MASK 0xffff0000 +#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG__SHIFT 0x10 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff +#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1 +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN_MASK 0x2 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL_MASK 0xc +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1 +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN_MASK 0x2 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL_MASK 0xc +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENENB__BLK_IO_BASE_MASK 0xff +#define GENENB__BLK_IO_BASE__SHIFT 0x0 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x8 +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x8 +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENS0__SENSE_SWITCH_MASK 0x10 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR_MASK 0x80 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS1__NO_DISPLAY_MASK 0x1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS_MASK 0x8 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK_MASK 0x30 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define DAC_DATA__DAC_DATA_MASK 0x3f +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xff +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x7 +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xff +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ00__SEQ_RST0B_MASK 0x1 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B_MASK 0x2 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ01__SEQ_DOT8_MASK 0x1 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2_MASK 0x4 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2_MASK 0x8 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4_MASK 0x10 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW_MASK 0x20 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ02__SEQ_MAP0_EN_MASK 0x1 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN_MASK 0x2 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN_MASK 0x4 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN_MASK 0x8 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B1_MASK 0x1 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2_MASK 0x2 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1_MASK 0x4 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2_MASK 0x8 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0_MASK 0x10 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0_MASK 0x20 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ04__SEQ_256K_MASK 0x2 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN_MASK 0x4 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN_MASK 0x8 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xff +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xff +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xff +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xff +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT03__H_BLANK_END_MASK 0x1f +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW_MASK 0x60 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT04__H_SYNC_START_MASK 0xff +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT05__H_SYNC_END_MASK 0x1f +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW_MASK 0x60 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5_MASK 0x80 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT06__V_TOTAL_MASK 0xff +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT07__V_TOTAL_B8_MASK 0x1 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8_MASK 0x2 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8_MASK 0x4 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8_MASK 0x8 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8_MASK 0x10 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9_MASK 0x20 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9_MASK 0x40 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9_MASK 0x80 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT08__ROW_SCAN_START_MASK 0x1f +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN_MASK 0x60 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT09__MAX_ROW_SCAN_MASK 0x1f +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9_MASK 0x20 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9_MASK 0x40 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT0A__CURSOR_START_MASK 0x1f +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE_MASK 0x20 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1f +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW_MASK 0x60 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0C__DISP_START_MASK 0xff +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xff +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xff +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xff +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xff +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT11__V_SYNC_END_MASK 0xf +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR_MASK 0x10 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN_MASK 0x20 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY_MASK 0x80 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT12__V_DISP_END_MASK 0xff +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xff +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT14__UNDRLN_LOC_MASK 0x1f +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4_MASK 0x20 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD_MASK 0x40 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT15__V_BLANK_START_MASK 0xff +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xff +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT17__RA0_AS_A13B_MASK 0x1 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B_MASK 0x2 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2_MASK 0x4 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2_MASK 0x8 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0_MASK 0x20 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE_MASK 0x40 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN_MASK 0x80 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT18__LINE_CMP_MASK 0xff +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT1E__GRPH_DEC_RD1_MASK 0x2 +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1F__GRPH_DEC_RD0_MASK 0xff +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xff +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0xf +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xff +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET0_MASK 0x1 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1_MASK 0x2 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2_MASK 0x4 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3_MASK 0x8 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA02__GRPH_CCOMP_MASK 0xf +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA03__GRPH_ROTATE_MASK 0x7 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL_MASK 0x18 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA04__GRPH_RMAP_MASK 0x3 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA05__GRPH_WRITE_MODE_MASK 0x3 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1_MASK 0x8 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN_MASK 0x10 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES_MASK 0x20 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK_MASK 0x40 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA06__GRPH_GRAPHICS_MASK 0x1 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN_MASK 0x2 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL_MASK 0xc +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA07__GRPH_XCARE0_MASK 0x1 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1_MASK 0x2 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2_MASK 0x4 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3_MASK 0x8 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA08__GRPH_BMSK_MASK 0xff +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define ATTRX__ATTR_IDX_MASK 0x1f +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20 +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 +#define ATTRDW__ATTR_DATA_MASK 0xff +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xff +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3f +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3f +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3f +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3f +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3f +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3f +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3f +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3f +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3f +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3f +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3f +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3f +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3f +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3f +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3f +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3f +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x1 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN_MASK 0x2 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN_MASK 0x4 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN_MASK 0x8 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2_MASK 0x40 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN_MASK 0x80 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR11__ATTR_OVSC_MASK 0xff +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR12__ATTR_MAP_EN_MASK 0xf +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX_MASK 0x30 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR13__ATTR_PPAN_MASK 0xf +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR14__ATTR_CSEL1_MASK 0x3 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2_MASK 0xc +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800 +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000 +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000 +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff +#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000 +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000 +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000 +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000 +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000 +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0 +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0 +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 +#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x7 +#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 +#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x700 +#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 +#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x70000 +#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 +#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 +#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff8000 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0xf +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb +#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 +#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 +#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 +#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 +#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff +#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 +#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff +#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 +#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 +#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 +#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 +#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 +#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x1 +#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0 +#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x2 +#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1 +#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x10 +#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4 +#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x20 +#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff +#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 +#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 +#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 +#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff +#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 +#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 +#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 +#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff +#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 +#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 +#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 +#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff +#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 +#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 +#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 +#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 +#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 +#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 +#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 +#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 +#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 +#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 +#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 +#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 +#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 +#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 +#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 +#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 +#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 +#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 +#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 +#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff +#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 +#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 +#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 +#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff +#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 +#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 +#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 +#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 +#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 +#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 +#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb +#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 +#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 +#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 +#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 +#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 +#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 +#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 +#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 +#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff +#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 +#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff +#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 +#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff +#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 +#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff +#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 +#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 +#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 +#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 +#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 +#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 +#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 +#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 +#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 +#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff +#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f +#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1 +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc +#define MINOR_VERSION__MINOR_VERSION_MASK 0xff +#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 +#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff +#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1 +#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 +#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2 +#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 +#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2 +#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1 +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2 +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4 +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8 +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10 +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20 +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40 +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80 +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100 +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200 +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400 +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800 +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000 +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000 +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000 +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000 +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000 +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1 +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2 +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4 +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8 +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10 +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20 +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40 +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80 +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100 +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200 +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400 +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800 +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000 +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000 +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000 +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000 +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000 +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000 +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40 +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80 +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100 +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200 +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400 +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800 +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000 +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000 +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000 +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000 +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff +#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_MASK 0x3 +#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 +#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1 +#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define RIRB_SIZE__RIRB_SIZE_MASK 0x3 +#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff +#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff +#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3 +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1 +#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1 +#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff +#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0 +#define BLND_CONTROL__BLND_MODE_MASK 0x300 +#define BLND_CONTROL__BLND_MODE__SHIFT 0x8 +#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00 +#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa +#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000 +#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc +#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000 +#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd +#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 +#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 +#define BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x40000 +#define BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12 +#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 +#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 +#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 +#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 +#define BLND_SM_CONTROL2__SM_MODE_MASK 0x7 +#define BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0 +#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 +#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 +#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 +#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 +#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 +#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 +#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 +#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1 +#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0 +#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30 +#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4 +#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40 +#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6 +#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80 +#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7 +#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100 +#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8 +#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 +#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 +#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 +#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 +#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 +#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 +#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 +#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c +#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000 +#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d +#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000 +#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa +#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb +#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 +#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 +#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe +#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff +#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 +#define WB_ENABLE__WB_ENABLE_MASK 0x1 +#define WB_ENABLE__WB_ENABLE__SHIFT 0x0 +#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1 +#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 +#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2 +#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 +#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x78 +#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3 +#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x80 +#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7 +#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x100 +#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8 +#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x200 +#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x3000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x4000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x18000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x60000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x180000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x600000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15 +#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000 +#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x3000000 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0xc000000 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a +#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c +#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000 +#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e +#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300 +#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 +#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000 +#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc +#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000 +#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd +#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000 +#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf +#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000 +#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 +#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000 +#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 +#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000 +#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 +#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000 +#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 +#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000 +#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 +#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000 +#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f +#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff +#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 +#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1 +#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 +#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100 +#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 +#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000 +#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 +#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1 +#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 +#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff +#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 +#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000 +#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 +#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff +#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 +#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000 +#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 +#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff +#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 +#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000 +#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 +#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff +#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 +#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000 +#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 +#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff +#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 +#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000 +#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 +#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff +#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 +#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000 +#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 +#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 +#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 +#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 +#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000 +#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1 +#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0 +#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0 +#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6 +#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1 +#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0 +#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2 +#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1 +#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4 +#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2 +#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8 +#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3 +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100 +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8 +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000 +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10 +#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff +#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0 +#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3 +#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 +#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c +#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 +#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1 +#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 +#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x7fff +#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0 +#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7fff0000 +#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10 +#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000 +#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f +#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0xff +#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0 +#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x100 +#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 +#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc +#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x8000 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf +#define DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x20000 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11 +#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18 +#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000 +#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f +#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2 +#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4 +#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8 +#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3 +#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 +#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 +#define DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x20 +#define DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5 +#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1 +#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0 +#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0 +#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000 +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000 +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000 +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000 +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000 +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000 +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d +#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3 +#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc +#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 +#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 +#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6 +#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300 +#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8 +#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00 +#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17 +#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3 +#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc +#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2 +#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30 +#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8 +#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00 +#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa +#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000 +#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc +#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000 +#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe +#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000 +#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10 +#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000 +#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12 +#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000 +#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14 +#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000 +#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16 +#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x1 +#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0 +#define DCFE_FLUSH__FLUSH_OCCURED_MASK 0x1 +#define DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0 +#define DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x2 +#define DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1 +#define DCFE_FLUSH__FLUSH_DEEP_MASK 0x4 +#define DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2 +#define DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x8 +#define DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3 +#define DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x10 +#define DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4 +#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8 +#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf +#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18 +#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000 +#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f +#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2 +#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4 +#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8 +#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3 +#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 +#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 +#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20 +#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5 +#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40 +#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f +#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE_MASK 0x3 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE__SHIFT 0x0 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS_MASK 0x4 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS__SHIFT 0x2 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x18 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x20 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5 +#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0xc0 +#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6 +#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x100 +#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8 +#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x600 +#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9 +#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x800 +#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb +#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x3000 +#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc +#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x4000 +#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe +#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x18000 +#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf +#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x20000 +#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11 +#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL_MASK 0x3 +#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0xc +#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 +#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 +#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 +#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0xc0 +#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6 +#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE_MASK 0x3 +#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE__SHIFT 0x0 +#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0xc +#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2 +#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x30 +#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4 +#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0xc0 +#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6 +#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x300 +#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8 +#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0xc00 +#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa +#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x3000 +#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc +#define DCFEV_L_FLUSH__FLUSH_OCCURED_MASK 0x1 +#define DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT 0x0 +#define DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x2 +#define DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1 +#define DCFEV_L_FLUSH__FLUSH_DEEP_MASK 0x4 +#define DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT 0x2 +#define DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x8 +#define DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3 +#define DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK 0x10 +#define DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4 +#define DCFEV_C_FLUSH__FLUSH_OCCURED_MASK 0x1 +#define DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT 0x0 +#define DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x2 +#define DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1 +#define DCFEV_C_FLUSH__FLUSH_DEEP_MASK 0x4 +#define DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT 0x2 +#define DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x8 +#define DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3 +#define DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK 0x10 +#define DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL_MASK 0xf +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL__SHIFT 0x0 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA_MASK 0x10 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA__SHIFT 0x4 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER_MASK 0x20 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER__SHIFT 0x5 +#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x1 +#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0 +#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1 +#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100 +#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000 +#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff +#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0 +#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff +#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0 +#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff +#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0 +#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff +#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0 +#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff +#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0 +#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff +#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0 +#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff +#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0 +#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff +#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0 +#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7 +#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0 +#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70 +#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT__SHIFT 0x14 +#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1 +#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4 +#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2 +#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8 +#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10 +#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20 +#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40 +#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80 +#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100 +#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200 +#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00 +#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa +#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000 +#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc +#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000 +#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe +#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000 +#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10 +#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000 +#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12 +#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000 +#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14 +#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000 +#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16 +#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x1 +#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0 +#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x2 +#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1 +#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0xc00 +#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa +#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x3000 +#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10 +#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20 +#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40 +#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80 +#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100 +#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200 +#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400 +#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800 +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000 +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000 +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000 +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000 +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000 +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f +#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3 +#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x4 +#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2 +#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x30000 +#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10 +#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x40000 +#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12 +#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x180000 +#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13 +#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x200000 +#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15 +#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL_MASK 0x7 +#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL__SHIFT 0x0 +#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE_MASK 0x30 +#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE__SHIFT 0x4 +#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS_MASK 0x100 +#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS__SHIFT 0x8 +#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE_MASK 0x3000 +#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE__SHIFT 0xc +#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL_MASK 0x7 +#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL__SHIFT 0x0 +#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE_MASK 0x30 +#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE__SHIFT 0x4 +#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS_MASK 0x100 +#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS__SHIFT 0x8 +#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE_MASK 0x3000 +#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE__SHIFT 0xc +#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL_MASK 0x7 +#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL__SHIFT 0x0 +#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE_MASK 0x30 +#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE__SHIFT 0x4 +#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS_MASK 0x100 +#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS__SHIFT 0x8 +#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE_MASK 0x3000 +#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE__SHIFT 0xc +#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL_MASK 0x7 +#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL__SHIFT 0x0 +#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE_MASK 0x30 +#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE__SHIFT 0x4 +#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS_MASK 0x100 +#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS__SHIFT 0x8 +#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE_MASK 0x3000 +#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE__SHIFT 0xc +#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL_MASK 0x7 +#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL__SHIFT 0x0 +#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE_MASK 0x30 +#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE__SHIFT 0x4 +#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS_MASK 0x100 +#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS__SHIFT 0x8 +#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE_MASK 0x3000 +#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE__SHIFT 0xc +#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL_MASK 0x7 +#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL__SHIFT 0x0 +#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE_MASK 0x30 +#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE__SHIFT 0x4 +#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS_MASK 0x100 +#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS__SHIFT 0x8 +#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE_MASK 0x3000 +#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE__SHIFT 0xc +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20 +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6 +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80 +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9 +#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400 +#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15 +#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x400000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16 +#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x800000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x7f +#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0 +#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x80 +#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 +#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x100 +#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 +#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x200 +#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 +#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x400 +#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa +#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x800 +#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb +#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x1000 +#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc +#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x2000 +#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd +#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x8000 +#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf +#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x10000 +#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10 +#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x20000 +#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 +#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x40000 +#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 +#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x80000 +#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 +#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x100000 +#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 +#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x200000 +#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 +#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x400000 +#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 +#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x800000 +#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 +#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x2000000 +#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19 +#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x4000000 +#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a +#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x1 +#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 +#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x2 +#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 +#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x4 +#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 +#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x8 +#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 +#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x10 +#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 +#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x20 +#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 +#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x40 +#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 +#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x100 +#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8 +#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x200 +#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9 +#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x400 +#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa +#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x800 +#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb +#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x1000 +#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc +#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x2000 +#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd +#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x4000 +#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe +#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x8000 +#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf +#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x10000 +#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 +#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x40000 +#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12 +#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x80000 +#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13 +#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1 +#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0 +#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2 +#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1 +#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10 +#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4 +#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100 +#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8 +#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000 +#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1 +#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 +#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10 +#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 +#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20 +#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 +#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40 +#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 +#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000 +#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc +#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000 +#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15 +#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000 +#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18 +#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000 +#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19 +#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000 +#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000 +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000 +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000 +#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f +#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x1 +#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x2 +#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x10 +#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x20 +#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5 +#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7 +#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 +#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000 +#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x1 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x10 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x100 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x1000 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0xfff0000 +#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS_MASK 0x1 +#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS__SHIFT 0x0 +#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE_MASK 0xfffffffe +#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR_MASK 0x1 +#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR__SHIFT 0x0 +#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS_MASK 0x1 +#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0 +#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE_MASK 0xfffffffe +#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR_MASK 0x1 +#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1 +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x3ff0000 +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x3ff0000 +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x3ff0000 +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x3ff0000 +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1 +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x3ff0000 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3 +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300 +#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6 +#define BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff +#define BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0 +#define BLNDV_CONTROL__BLND_MODE_MASK 0x300 +#define BLNDV_CONTROL__BLND_MODE__SHIFT 0x8 +#define BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0xc00 +#define BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa +#define BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000 +#define BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc +#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000 +#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd +#define BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 +#define BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 +#define BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x40000 +#define BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12 +#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 +#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 +#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 +#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 +#define BLNDV_SM_CONTROL2__SM_MODE_MASK 0x7 +#define BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0 +#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 +#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 +#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 +#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 +#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 +#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 +#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 +#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define BLNDV_CONTROL2__PTI_ENABLE_MASK 0x1 +#define BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0 +#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30 +#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4 +#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40 +#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6 +#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80 +#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7 +#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100 +#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8 +#define BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 +#define BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 +#define BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 +#define BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 +#define BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 +#define BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 +#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 +#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c +#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000 +#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d +#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000 +#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7 +#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100 +#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8 +#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200 +#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9 +#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400 +#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa +#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800 +#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb +#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 +#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 +#define BLNDV_DEBUG__BLND_DEBUG_MASK 0xfffffffe +#define BLNDV_DEBUG__BLND_DEBUG__SHIFT 0x1 +#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff +#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 +#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff +#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 +#define CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff +#define CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 +#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff +#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 +#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 +#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 +#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff +#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 +#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 +#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 +#define CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff +#define CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 +#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff +#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 +#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 +#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 +#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff +#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 +#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 +#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 +#define CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x1 +#define CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 +#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 +#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 +#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 +#define CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 +#define CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc +#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 +#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd +#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 +#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 +#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 +#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 +#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 +#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 +#define CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d +#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 +#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 +#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 +#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 +#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2 +#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1 +#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4 +#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2 +#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100 +#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8 +#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 +#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 +#define CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 +#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 +#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 +#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 +#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 +#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 +#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc +#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 +#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 +#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 +#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 +#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff +#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff +#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff +#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff +#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff +#define CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 +#define CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff +#define CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff +#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff +#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff +#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff +#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff +#define CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 +#define CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff +#define CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff +#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff +#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8 +#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff +#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0 +#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1 +#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf +#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff +#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0 +#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff +#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0 +#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff +#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0 +#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000 +#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18 +#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000 +#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19 +#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000 +#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa +#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff +#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14 +#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15 +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10 +#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0 +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10 +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 +#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff +#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0 +#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff +#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9 +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400 +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa +#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000 +#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000 +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14 +#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000 +#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18 +#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000 +#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18 +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18 +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0 +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 +#define CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7 +#define CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 +#define CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18 +#define CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 +#define CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x100 +#define CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 +#define CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7 +#define CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 +#define CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18 +#define CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 +#define CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x100 +#define CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 +#define CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7 +#define CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 +#define CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18 +#define CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 +#define CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x100 +#define CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 +#define CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7 +#define CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 +#define CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18 +#define CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 +#define CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x100 +#define CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 +#define MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x7 +#define MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 +#define MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x18 +#define MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 +#define MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x20 +#define MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 +#define MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x7 +#define MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 +#define MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x18 +#define MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 +#define MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x20 +#define MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 +#define MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x7 +#define MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 +#define MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x18 +#define MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 +#define MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x20 +#define MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 +#define MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x7 +#define MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 +#define MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x18 +#define MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 +#define MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x20 +#define MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x6 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x18 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x300 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0xc00 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x1000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x2000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x4000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x8000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0xf0000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x100000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0xc00000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x6 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x18 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x300 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0xc00 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x1000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x2000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x4000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x8000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0xf0000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x100000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0xc00000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x6 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x18 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x300 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0xc00 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x1000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x2000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x4000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x8000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0xf0000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x100000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0xc00000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x6 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x18 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x300 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0xc00 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x1000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x2000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x4000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x8000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0xf0000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x100000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0xc00000 +#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 +#define TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xffffffff +#define TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 +#define TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xffffffff +#define TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 +#define TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xffffffff +#define TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 +#define TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xffffffff +#define TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 +#define TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xffffffff +#define TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 +#define TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xffffffff +#define TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 +#define TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xffffffff +#define TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 +#define TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xffffffff +#define TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 +#define TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xffffffff +#define TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 +#define TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xffffffff +#define TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 +#define TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xffffffff +#define TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 +#define TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xffffffff +#define TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 +#define TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xffffffff +#define TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 +#define TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xffffffff +#define TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 +#define TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xffffffff +#define TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 +#define TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xffffffff +#define TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 +#define TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xffffffff +#define TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 +#define TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xffffffff +#define TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 +#define TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xffffffff +#define TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 +#define TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xffffffff +#define TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 +#define TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xffffffff +#define TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 +#define TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xffffffff +#define TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 +#define TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xffffffff +#define TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 +#define TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xffffffff +#define TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 +#define TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xffffffff +#define TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 +#define TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xffffffff +#define TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 +#define TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xffffffff +#define TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 +#define TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xffffffff +#define TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 +#define TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xffffffff +#define TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 +#define TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xffffffff +#define TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 +#define TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xffffffff +#define TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 +#define TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xffffffff +#define TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 +#define TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xffffffff +#define TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 +#define TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xffffffff +#define TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 +#define TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xffffffff +#define TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 +#define TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xffffffff +#define TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 +#define TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xffffffff +#define TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 +#define TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xffffffff +#define TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 +#define TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xffffffff +#define TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 +#define TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xffffffff +#define TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 +#define TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xffffffff +#define TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 +#define TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xffffffff +#define TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 +#define TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xffffffff +#define TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 +#define TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xffffffff +#define TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 +#define TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xffffffff +#define TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 +#define TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xffffffff +#define TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 +#define TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xffffffff +#define TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 +#define TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xffffffff +#define TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 +#define TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xffffffff +#define TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 +#define TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xffffffff +#define TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 +#define TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xffffffff +#define TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 +#define TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xffffffff +#define TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 +#define COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff +#define COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 +#define COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00 +#define COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 +#define COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000 +#define COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 +#define COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000 +#define COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 +#define COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf +#define COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 +#define COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0 +#define COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 +#define COMMON_LANE_PWRMGMT__vprot_en_MASK 0x800 +#define COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb +#define COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x1f +#define COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 +#define COMMON_TXCNTRL__clkgate_dis_MASK 0x20 +#define COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 +#define COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x1c0 +#define COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 +#define COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0xe00 +#define COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 +#define COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x7000 +#define COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc +#define COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x8000 +#define COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf +#define COMMON_TXCNTRL__dual_dvi_en_MASK 0x10000 +#define COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10 +#define COMMON_TMDP__tmdp_spare_MASK 0xffffffff +#define COMMON_TMDP__tmdp_spare__SHIFT 0x0 +#define COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x1 +#define COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 +#define COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x2 +#define COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 +#define COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x4 +#define COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 +#define COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x8 +#define COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 +#define COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x10 +#define COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 +#define COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x20 +#define COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 +#define COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x40 +#define COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 +#define COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x80 +#define COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 +#define COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x1 +#define COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 +#define COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x3e +#define COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 +#define COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x200000 +#define COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 +#define COMMON_DISP_RFU1__rfu_value1_MASK 0xffffffff +#define COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 +#define COMMON_DISP_RFU2__rfu_value2_MASK 0xffffffff +#define COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 +#define COMMON_DISP_RFU3__rfu_value3_MASK 0xffffffff +#define COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 +#define COMMON_DISP_RFU4__rfu_value4_MASK 0xffffffff +#define COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 +#define COMMON_DISP_RFU5__rfu_value5_MASK 0xffffffff +#define COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 +#define COMMON_DISP_RFU6__rfu_value6_MASK 0xffffffff +#define COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 +#define COMMON_DISP_RFU7__rfu_value7_MASK 0xffffffff +#define COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 +#define FREQ_CTRL0__fcw0_frac_MASK 0xffff +#define FREQ_CTRL0__fcw0_frac__SHIFT 0x0 +#define FREQ_CTRL0__fcw0_int_MASK 0x1ff0000 +#define FREQ_CTRL0__fcw0_int__SHIFT 0x10 +#define FREQ_CTRL1__fcw1_frac_MASK 0xffff +#define FREQ_CTRL1__fcw1_frac__SHIFT 0x0 +#define FREQ_CTRL1__fcw1_int_MASK 0x1ff0000 +#define FREQ_CTRL1__fcw1_int__SHIFT 0x10 +#define FREQ_CTRL2__fcw_denom_MASK 0xffff +#define FREQ_CTRL2__fcw_denom__SHIFT 0x0 +#define FREQ_CTRL2__fcw_slew_frac_MASK 0xffff0000 +#define FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 +#define FREQ_CTRL3__refclk_div_MASK 0x3 +#define FREQ_CTRL3__refclk_div__SHIFT 0x0 +#define FREQ_CTRL3__vco_pre_div_MASK 0x18 +#define FREQ_CTRL3__vco_pre_div__SHIFT 0x3 +#define FREQ_CTRL3__fracn_en_MASK 0x40 +#define FREQ_CTRL3__fracn_en__SHIFT 0x6 +#define FREQ_CTRL3__ssc_en_MASK 0x100 +#define FREQ_CTRL3__ssc_en__SHIFT 0x8 +#define FREQ_CTRL3__fcw_sel_MASK 0x400 +#define FREQ_CTRL3__fcw_sel__SHIFT 0xa +#define FREQ_CTRL3__freq_jump_en_MASK 0x1000 +#define FREQ_CTRL3__freq_jump_en__SHIFT 0xc +#define FREQ_CTRL3__tdc_resolution_MASK 0xff0000 +#define FREQ_CTRL3__tdc_resolution__SHIFT 0x10 +#define FREQ_CTRL3__dpll_cfg_1_MASK 0xff000000 +#define FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 +#define BW_CTRL_COARSE__gi_coarse_mant_MASK 0x3 +#define BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 +#define BW_CTRL_COARSE__gi_coarse_exp_MASK 0x3c +#define BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 +#define BW_CTRL_COARSE__gp_coarse_mant_MASK 0x780 +#define BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 +#define BW_CTRL_COARSE__gp_coarse_exp_MASK 0xf000 +#define BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc +#define BW_CTRL_COARSE__nctl_coarse_res_MASK 0x7e0000 +#define BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 +#define BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x3000000 +#define BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 +#define BW_CTRL_FINE__dpll_cfg_3_MASK 0x3ff +#define BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 +#define CAL_CTRL__bypass_freq_lock_MASK 0x1 +#define CAL_CTRL__bypass_freq_lock__SHIFT 0x0 +#define CAL_CTRL__tdc_cal_en_MASK 0x2 +#define CAL_CTRL__tdc_cal_en__SHIFT 0x1 +#define CAL_CTRL__tdc_cal_ctrl_MASK 0x1f8 +#define CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 +#define CAL_CTRL__meas_win_sel_MASK 0x600 +#define CAL_CTRL__meas_win_sel__SHIFT 0x9 +#define CAL_CTRL__kdco_cal_dis_MASK 0x800 +#define CAL_CTRL__kdco_cal_dis__SHIFT 0xb +#define CAL_CTRL__kdco_ratio_MASK 0x1fe000 +#define CAL_CTRL__kdco_ratio__SHIFT 0xd +#define CAL_CTRL__kdco_incr_cal_dis_MASK 0x400000 +#define CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 +#define CAL_CTRL__nctl_adj_dis_MASK 0x800000 +#define CAL_CTRL__nctl_adj_dis__SHIFT 0x17 +#define CAL_CTRL__refclk_rate_MASK 0xff000000 +#define CAL_CTRL__refclk_rate__SHIFT 0x18 +#define LOOP_CTRL__fbdiv_mask_en_MASK 0x1 +#define LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 +#define LOOP_CTRL__fb_slip_dis_MASK 0x4 +#define LOOP_CTRL__fb_slip_dis__SHIFT 0x2 +#define LOOP_CTRL__clk_tdc_sel_MASK 0x30 +#define LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 +#define LOOP_CTRL__clk_nctl_sel_MASK 0x180 +#define LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 +#define LOOP_CTRL__sig_del_patt_sel_MASK 0x400 +#define LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa +#define LOOP_CTRL__nctl_sig_del_dis_MASK 0x1000 +#define LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc +#define LOOP_CTRL__fbclk_track_refclk_MASK 0x4000 +#define LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe +#define LOOP_CTRL__prbs_en_MASK 0x10000 +#define LOOP_CTRL__prbs_en__SHIFT 0x10 +#define LOOP_CTRL__tdc_clk_gate_en_MASK 0x40000 +#define LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 +#define LOOP_CTRL__phase_offset_MASK 0x7f00000 +#define LOOP_CTRL__phase_offset__SHIFT 0x14 +#define VREG_CFG__bleeder_ac_MASK 0x1 +#define VREG_CFG__bleeder_ac__SHIFT 0x0 +#define VREG_CFG__bleeder_en_MASK 0x2 +#define VREG_CFG__bleeder_en__SHIFT 0x1 +#define VREG_CFG__is_1p2_MASK 0x4 +#define VREG_CFG__is_1p2__SHIFT 0x2 +#define VREG_CFG__reg_obs_sel_MASK 0x18 +#define VREG_CFG__reg_obs_sel__SHIFT 0x3 +#define VREG_CFG__reg_on_mode_MASK 0x60 +#define VREG_CFG__reg_on_mode__SHIFT 0x5 +#define VREG_CFG__rlad_tap_sel_MASK 0x780 +#define VREG_CFG__rlad_tap_sel__SHIFT 0x7 +#define VREG_CFG__reg_off_hi_MASK 0x800 +#define VREG_CFG__reg_off_hi__SHIFT 0xb +#define VREG_CFG__reg_off_lo_MASK 0x1000 +#define VREG_CFG__reg_off_lo__SHIFT 0xc +#define VREG_CFG__scale_driver_MASK 0x6000 +#define VREG_CFG__scale_driver__SHIFT 0xd +#define VREG_CFG__sel_bump_MASK 0x8000 +#define VREG_CFG__sel_bump__SHIFT 0xf +#define VREG_CFG__sel_rladder_x_MASK 0x10000 +#define VREG_CFG__sel_rladder_x__SHIFT 0x10 +#define VREG_CFG__short_rc_filt_x_MASK 0x20000 +#define VREG_CFG__short_rc_filt_x__SHIFT 0x11 +#define VREG_CFG__vref_pwr_on_MASK 0x40000 +#define VREG_CFG__vref_pwr_on__SHIFT 0x12 +#define VREG_CFG__dpll_cfg_2_MASK 0xff00000 +#define VREG_CFG__dpll_cfg_2__SHIFT 0x14 +#define OBSERVE0__lock_det_tdc_steps_MASK 0x1f +#define OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 +#define OBSERVE0__clear_sticky_lock_MASK 0x40 +#define OBSERVE0__clear_sticky_lock__SHIFT 0x6 +#define OBSERVE0__lock_det_dis_MASK 0x100 +#define OBSERVE0__lock_det_dis__SHIFT 0x8 +#define OBSERVE0__dco_cfg_MASK 0x3fc00 +#define OBSERVE0__dco_cfg__SHIFT 0xa +#define OBSERVE0__anaobs_sel_MASK 0xe00000 +#define OBSERVE0__anaobs_sel__SHIFT 0x15 +#define OBSERVE1__digobs_sel_MASK 0xf +#define OBSERVE1__digobs_sel__SHIFT 0x0 +#define OBSERVE1__digobs_trig_sel_MASK 0x1e0 +#define OBSERVE1__digobs_trig_sel__SHIFT 0x5 +#define OBSERVE1__digobs_div_MASK 0xc00 +#define OBSERVE1__digobs_div__SHIFT 0xa +#define OBSERVE1__digobs_trig_div_MASK 0x6000 +#define OBSERVE1__digobs_trig_div__SHIFT 0xd +#define OBSERVE1__lock_timer_MASK 0x3fff0000 +#define OBSERVE1__lock_timer__SHIFT 0x10 +#define DFT_OUT__dft_data_MASK 0xffffffff +#define DFT_OUT__dft_data__SHIFT 0x0 +#define PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x3 +#define PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x1 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x2 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0xc +#define PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 +#define PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0xe0 +#define PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 +#define PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x100 +#define PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 +#define PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x400 +#define PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa +#define PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x2000 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd +#define PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x4000 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe +#define PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x8000 +#define PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf +#define PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x10000 +#define PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0xe0000 +#define PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 +#define PPLL_VREG_CFG__pw_pc_bleeder_ac_MASK 0x1 +#define PPLL_VREG_CFG__pw_pc_bleeder_ac__SHIFT 0x0 +#define PPLL_VREG_CFG__pw_pc_bleeder_en_MASK 0x2 +#define PPLL_VREG_CFG__pw_pc_bleeder_en__SHIFT 0x1 +#define PPLL_VREG_CFG__pw_pc_is_1p2_MASK 0x4 +#define PPLL_VREG_CFG__pw_pc_is_1p2__SHIFT 0x2 +#define PPLL_VREG_CFG__pw_pc_reg_obs_sel_MASK 0x18 +#define PPLL_VREG_CFG__pw_pc_reg_obs_sel__SHIFT 0x3 +#define PPLL_VREG_CFG__pw_pc_reg_on_mode_MASK 0x60 +#define PPLL_VREG_CFG__pw_pc_reg_on_mode__SHIFT 0x5 +#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel_MASK 0x780 +#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel__SHIFT 0x7 +#define PPLL_VREG_CFG__pw_pc_reg_off_hi_MASK 0x800 +#define PPLL_VREG_CFG__pw_pc_reg_off_hi__SHIFT 0xb +#define PPLL_VREG_CFG__pw_pc_reg_off_lo_MASK 0x1000 +#define PPLL_VREG_CFG__pw_pc_reg_off_lo__SHIFT 0xc +#define PPLL_VREG_CFG__pw_pc_scale_driver_MASK 0x6000 +#define PPLL_VREG_CFG__pw_pc_scale_driver__SHIFT 0xd +#define PPLL_VREG_CFG__pw_pc_sel_bump_MASK 0x8000 +#define PPLL_VREG_CFG__pw_pc_sel_bump__SHIFT 0xf +#define PPLL_VREG_CFG__pw_pc_sel_rladder_x_MASK 0x10000 +#define PPLL_VREG_CFG__pw_pc_sel_rladder_x__SHIFT 0x10 +#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x_MASK 0x20000 +#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x__SHIFT 0x11 +#define PPLL_VREG_CFG__pw_pc_vref_pwr_on_MASK 0x40000 +#define PPLL_VREG_CFG__pw_pc_vref_pwr_on__SHIFT 0x12 +#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2_MASK 0xff00000 +#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2__SHIFT 0x14 +#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis_MASK 0x1 +#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis__SHIFT 0x0 +#define PPLL_MODE_CNTL__pw_pc_multi_phase_en_MASK 0xf00 +#define PPLL_MODE_CNTL__pw_pc_multi_phase_en__SHIFT 0x8 +#define PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK 0x30000 +#define PPLL_MODE_CNTL__reg_tmg_pwr_state__SHIFT 0x10 +#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK 0xffff +#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac__SHIFT 0x0 +#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int_MASK 0x1ff0000 +#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT 0x10 +#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK 0xffff +#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac__SHIFT 0x0 +#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int_MASK 0x1ff0000 +#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int__SHIFT 0x10 +#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom_MASK 0xffff +#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom__SHIFT 0x0 +#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac_MASK 0xffff0000 +#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac__SHIFT 0x10 +#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div_MASK 0x3 +#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div__SHIFT 0x0 +#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div_MASK 0x18 +#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div__SHIFT 0x3 +#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en_MASK 0x40 +#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en__SHIFT 0x6 +#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en_MASK 0x100 +#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en__SHIFT 0x8 +#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK 0x400 +#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel__SHIFT 0xa +#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en_MASK 0x1000 +#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en__SHIFT 0xc +#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol_MASK 0xff0000 +#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol__SHIFT 0x10 +#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1_MASK 0xff000000 +#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1__SHIFT 0x18 +#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant_MASK 0x3 +#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant__SHIFT 0x0 +#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp_MASK 0x3c +#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp__SHIFT 0x2 +#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant_MASK 0x780 +#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant__SHIFT 0x7 +#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp_MASK 0xf000 +#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp__SHIFT 0xc +#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res_MASK 0x7e0000 +#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res__SHIFT 0x11 +#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res_MASK 0x3000000 +#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res__SHIFT 0x18 +#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3_MASK 0x3ff +#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3__SHIFT 0x0 +#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock_MASK 0x1 +#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock__SHIFT 0x0 +#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en_MASK 0x2 +#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en__SHIFT 0x1 +#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl_MASK 0x1f8 +#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl__SHIFT 0x3 +#define PPLL_CAL_CTRL__pw_pc_meas_win_sel_MASK 0x600 +#define PPLL_CAL_CTRL__pw_pc_meas_win_sel__SHIFT 0x9 +#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis_MASK 0x800 +#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis__SHIFT 0xb +#define PPLL_CAL_CTRL__pw_pc_kdco_ratio_MASK 0x1fe000 +#define PPLL_CAL_CTRL__pw_pc_kdco_ratio__SHIFT 0xd +#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis_MASK 0x400000 +#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis__SHIFT 0x16 +#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis_MASK 0x800000 +#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis__SHIFT 0x17 +#define PPLL_CAL_CTRL__pw_pc_refclk_rate_MASK 0xff000000 +#define PPLL_CAL_CTRL__pw_pc_refclk_rate__SHIFT 0x18 +#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en_MASK 0x1 +#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en__SHIFT 0x0 +#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis_MASK 0x4 +#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis__SHIFT 0x2 +#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel_MASK 0x30 +#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel__SHIFT 0x4 +#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel_MASK 0x180 +#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel__SHIFT 0x7 +#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel_MASK 0x400 +#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel__SHIFT 0xa +#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis_MASK 0x1000 +#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis__SHIFT 0xc +#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk_MASK 0x4000 +#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk__SHIFT 0xe +#define PPLL_LOOP_CTRL__pw_pc_prbs_en_MASK 0x10000 +#define PPLL_LOOP_CTRL__pw_pc_prbs_en__SHIFT 0x10 +#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en_MASK 0x40000 +#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en__SHIFT 0x12 +#define PPLL_LOOP_CTRL__pw_pc_phase_offset_MASK 0x7f00000 +#define PPLL_LOOP_CTRL__pw_pc_phase_offset__SHIFT 0x14 +#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en_MASK 0x1 +#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en__SHIFT 0x0 +#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en_MASK 0x2 +#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en__SHIFT 0x1 +#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en_MASK 0x4 +#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en__SHIFT 0x2 +#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en_MASK 0x8 +#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en__SHIFT 0x3 +#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel_MASK 0x100 +#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel__SHIFT 0x8 +#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel_MASK 0x200 +#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel__SHIFT 0x9 +#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel_MASK 0x400 +#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel__SHIFT 0xa +#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel_MASK 0x800 +#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel__SHIFT 0xb +#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc_MASK 0xc000 +#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc__SHIFT 0xe +#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel_MASK 0x10000 +#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel__SHIFT 0x10 +#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel_MASK 0x100 +#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel__SHIFT 0x8 +#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel_MASK 0x200 +#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel__SHIFT 0x9 +#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel_MASK 0x400 +#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel__SHIFT 0xa +#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel_MASK 0x800 +#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel__SHIFT 0xb +#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en_MASK 0x1000 +#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en__SHIFT 0xc +#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel_MASK 0x2000 +#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel__SHIFT 0xd +#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel_MASK 0x4000 +#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel__SHIFT 0xe +#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel_MASK 0x8000 +#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel__SHIFT 0xf +#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel_MASK 0x30000 +#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel__SHIFT 0x10 +#define PPLL_CLKOUT_CNTL__regs_cc_resetb_MASK 0x100000 +#define PPLL_CLKOUT_CNTL__regs_cc_resetb__SHIFT 0x14 +#define PPLL_DFT_CNTL__regs_pw_obs_en_MASK 0x1 +#define PPLL_DFT_CNTL__regs_pw_obs_en__SHIFT 0x0 +#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1_MASK 0x6 +#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1__SHIFT 0x1 +#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK 0xf0 +#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1__SHIFT 0x4 +#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2_MASK 0xf00 +#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2__SHIFT 0x8 +#define PPLL_DFT_CNTL__regs_pw_obs_sel_MASK 0x3000 +#define PPLL_DFT_CNTL__regs_pw_obs_sel__SHIFT 0xc +#define PPLL_ANALOG_CNTL__regs_pw_spare_MASK 0xff +#define PPLL_ANALOG_CNTL__regs_pw_spare__SHIFT 0x0 +#define PPLL_POSTDIV__reg_tmg_postdiv_MASK 0xf00 +#define PPLL_POSTDIV__reg_tmg_postdiv__SHIFT 0x8 +#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2_MASK 0x1000 +#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2__SHIFT 0xc +#define PPLL_DEBUG0__pw_pc_phase_jump_trig_MASK 0x2 +#define PPLL_DEBUG0__pw_pc_phase_jump_trig__SHIFT 0x1 +#define PPLL_DEBUG0__pw_pc_fine_tdc_dis_MASK 0x4 +#define PPLL_DEBUG0__pw_pc_fine_tdc_dis__SHIFT 0x2 +#define PPLL_DEBUG0__pw_pc_coarse_tdc_dis_MASK 0x8 +#define PPLL_DEBUG0__pw_pc_coarse_tdc_dis__SHIFT 0x3 +#define PPLL_DEBUG0__pw_pc_alt_nctl_en_MASK 0x10 +#define PPLL_DEBUG0__pw_pc_alt_nctl_en__SHIFT 0x4 +#define PPLL_DEBUG0__pw_pc_alt_nctl_MASK 0x1ffffe0 +#define PPLL_DEBUG0__pw_pc_alt_nctl__SHIFT 0x5 +#define PPLL_DEBUG0__pw_pc_nctl_coarse_step_dis_MASK 0x2000000 +#define PPLL_DEBUG0__pw_pc_nctl_coarse_step_dis__SHIFT 0x19 +#define PPLL_DEBUG0__pw_pc_trig_coarse_step_MASK 0x4000000 +#define PPLL_DEBUG0__pw_pc_trig_coarse_step__SHIFT 0x1a +#define PPLL_DEBUG0__pw_pc_dft_sel_MASK 0x38000000 +#define PPLL_DEBUG0__pw_pc_dft_sel__SHIFT 0x1b +#define PPLL_DEBUG0__pw_pc_dft_capture_MASK 0x40000000 +#define PPLL_DEBUG0__pw_pc_dft_capture__SHIFT 0x1e +#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps_MASK 0x1f +#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps__SHIFT 0x0 +#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock_MASK 0x40 +#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock__SHIFT 0x6 +#define PPLL_OBSERVE0__pw_pc_lock_det_dis_MASK 0x100 +#define PPLL_OBSERVE0__pw_pc_lock_det_dis__SHIFT 0x8 +#define PPLL_OBSERVE0__pw_pc_dco_cfg_MASK 0x3fc00 +#define PPLL_OBSERVE0__pw_pc_dco_cfg__SHIFT 0xa +#define PPLL_OBSERVE0__pw_pc_anaobs_sel_MASK 0xe00000 +#define PPLL_OBSERVE0__pw_pc_anaobs_sel__SHIFT 0x15 +#define PPLL_OBSERVE1__pw_pc_digobs_sel_MASK 0xf +#define PPLL_OBSERVE1__pw_pc_digobs_sel__SHIFT 0x0 +#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel_MASK 0x1e0 +#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel__SHIFT 0x5 +#define PPLL_OBSERVE1__pw_pc_digobs_div_MASK 0xc00 +#define PPLL_OBSERVE1__pw_pc_digobs_div__SHIFT 0xa +#define PPLL_OBSERVE1__pw_pc_digobs_trig_div_MASK 0x3000 +#define PPLL_OBSERVE1__pw_pc_digobs_trig_div__SHIFT 0xc +#define PPLL_OBSERVE1__reg_tmg_lock_timer_MASK 0x3fff0000 +#define PPLL_OBSERVE1__reg_tmg_lock_timer__SHIFT 0x10 +#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK_MASK 0x4 +#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK__SHIFT 0x2 +#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT_MASK 0x8 +#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT__SHIFT 0x3 +#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING_MASK 0x100 +#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING__SHIFT 0x8 +#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy_MASK 0x200 +#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy__SHIFT 0x9 +#define PPLL_UPDATE_CNTL__TieLow1_MASK 0x10000 +#define PPLL_UPDATE_CNTL__TieLow1__SHIFT 0x10 +#define PPLL_OBSERVE0_OUT__disppll_core_obsout_MASK 0xffffffff +#define PPLL_OBSERVE0_OUT__disppll_core_obsout__SHIFT 0x0 +#define PPLL_STATUS_DEBUG1__dbg_pll_rdy_MASK 0x1 +#define PPLL_STATUS_DEBUG1__dbg_pll_rdy__SHIFT 0x0 +#define PPLL_STATUS_DEBUG1__core_disppll_pwr_ok_vddp_MASK 0x2 +#define PPLL_STATUS_DEBUG1__core_disppll_pwr_ok_vddp__SHIFT 0x1 +#define PPLL_STATUS_DEBUG1__core_disppll_rcu_dc_resetb_vddp_MASK 0x4 +#define PPLL_STATUS_DEBUG1__core_disppll_rcu_dc_resetb_vddp__SHIFT 0x2 +#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f +#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0 +#define PPLL_DIV_UPDATE_DEBUG__TieLow2_MASK 0x1 +#define PPLL_DIV_UPDATE_DEBUG__TieLow2__SHIFT 0x0 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_FB_DIV_CHANGED_MASK 0x2 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_FB_DIV_CHANGED__SHIFT 0x1 +#define PPLL_DIV_UPDATE_DEBUG__dbg_UPDATE_PENDING_MASK 0x4 +#define PPLL_DIV_UPDATE_DEBUG__dbg_UPDATE_PENDING__SHIFT 0x2 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_CURRENT_STATE_MASK 0x18 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_CURRENT_STATE__SHIFT 0x3 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ENABLE_MASK 0x20 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ENABLE__SHIFT 0x5 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_REQ_MASK 0x40 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_REQ__SHIFT 0x6 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ACK_MASK 0x80 +#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ACK__SHIFT 0x7 +#define PPLL_STATUS_DEBUG0__obsout_MASK 0xffffffff +#define PPLL_STATUS_DEBUG0__obsout__SHIFT 0x0 +#define COMP_EN_CTL__comp_en_MASK 0x1 +#define COMP_EN_CTL__comp_en__SHIFT 0x0 +#define COMP_EN_CTL__comp_en_override_MASK 0x4 +#define COMP_EN_CTL__comp_en_override__SHIFT 0x2 +#define COMP_EN_CTL__comp_done_MASK 0x10 +#define COMP_EN_CTL__comp_done__SHIFT 0x4 +#define COMP_EN_CTL__zcal_code_override_MASK 0x40 +#define COMP_EN_CTL__zcal_code_override__SHIFT 0x6 +#define COMP_EN_CTL__zcal_cal_rtt_MASK 0x80 +#define COMP_EN_CTL__zcal_cal_rtt__SHIFT 0x7 +#define COMP_EN_CTL__zcal_base_en_MASK 0x100 +#define COMP_EN_CTL__zcal_base_en__SHIFT 0x8 +#define COMP_EN_CTL__zcal_ht_rtt_sel_MASK 0x200 +#define COMP_EN_CTL__zcal_ht_rtt_sel__SHIFT 0x9 +#define COMP_EN_CTL__zcal_code_MASK 0x7c00 +#define COMP_EN_CTL__zcal_code__SHIFT 0xa +#define COMP_EN_CTL__zcal_ron_cal_mode_MASK 0x10000 +#define COMP_EN_CTL__zcal_ron_cal_mode__SHIFT 0x10 +#define COMP_EN_CTL__zcal_ana_dbg_sel_MASK 0x60000 +#define COMP_EN_CTL__zcal_ana_dbg_sel__SHIFT 0x11 +#define COMP_EN_CTL__cfg_cml_cmos_sel_MASK 0x80000 +#define COMP_EN_CTL__cfg_cml_cmos_sel__SHIFT 0x13 +#define COMP_EN_CTL__dsm_sel_MASK 0xf00000 +#define COMP_EN_CTL__dsm_sel__SHIFT 0x14 +#define DPCSTX_PHY_CNTL__DPCS_PHY_RESET_MASK 0x1 +#define DPCSTX_PHY_CNTL__DPCS_PHY_RESET__SHIFT 0x0 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x1 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x2 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x4 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x8 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX0_EN_MASK 0x10 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX1_EN_MASK 0x20 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX2_EN_MASK 0x40 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX3_EN_MASK 0x80 +#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7 +#define DPCSTX_TX_CNTL__DPCS_TX_RESYNC_MASK 0x1 +#define DPCSTX_TX_CNTL__DPCS_TX_RESYNC__SHIFT 0x0 +#define DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_EN_MASK 0x2 +#define DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_EN__SHIFT 0x1 +#define DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_OVERRIDE_EN_MASK 0x4 +#define DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_OVERRIDE_EN__SHIFT 0x2 +#define DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_MASK 0xf0 +#define DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE__SHIFT 0x4 +#define DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_DELAY_MASK 0x700 +#define DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_DELAY__SHIFT 0x8 +#define DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x1000 +#define DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc +#define DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x2000 +#define DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd +#define DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x4000 +#define DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe +#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x10000 +#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10 +#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x20000 +#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11 +#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_WR_START_DELAY_MASK 0xf00000 +#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_WR_START_DELAY__SHIFT 0x14 +#define DPCSTX_TX_CNTL__DPCS_TX_DVI_LINK_MODE_MASK 0x3000000 +#define DPCSTX_TX_CNTL__DPCS_TX_DVI_LINK_MODE__SHIFT 0x18 +#define DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000 +#define DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f +#define DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0xf +#define DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0 +#define DPCSTX_CBUS_CNTL__DPCS_PHY_MASTER_REQ_DELAY_MASK 0xff00 +#define DPCSTX_CBUS_CNTL__DPCS_PHY_MASTER_REQ_DELAY__SHIFT 0x8 +#define DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000 +#define DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f +#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_OVERFLOW_MASK 0x1 +#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_ERROR_CLR_MASK 0x2 +#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_ERROR_CLR__SHIFT 0x1 +#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_ERROR_MASK_MASK 0x10 +#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX0_FIFO_ERROR_MASK 0x1 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX0_FIFO_ERROR__SHIFT 0x0 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX1_FIFO_ERROR_MASK 0x2 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX1_FIFO_ERROR__SHIFT 0x1 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX2_FIFO_ERROR_MASK 0x4 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX2_FIFO_ERROR__SHIFT 0x2 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX3_FIFO_ERROR_MASK 0x8 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX3_FIFO_ERROR__SHIFT 0x3 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX_ERROR_CLR_MASK 0x100 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX_ERROR_CLR__SHIFT 0x8 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX_FIFO_ERROR_MASK_MASK 0x1000 +#define DPCSTX_TX_ERROR_STATUS__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0xc +#define DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x3ffff +#define DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0 +#define DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xffffffff +#define DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define DPCSTX_INDEX_MODE_ADDR__DPCS_INDEX_MODE_ADDR_MASK 0x3ffff +#define DPCSTX_INDEX_MODE_ADDR__DPCS_INDEX_MODE_ADDR__SHIFT 0x0 +#define DPCSTX_INDEX_MODE_DATA__DPCS_INDEX_MODE_DATA_MASK 0xffffffff +#define DPCSTX_INDEX_MODE_DATA__DPCS_INDEX_MODE_DATA__SHIFT 0x0 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK 0x1 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT 0x0 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK 0x6 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT 0x1 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK 0x38 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT 0x3 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CLOCK_SEL_MASK 0x700 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CLOCK_SEL__SHIFT 0x8 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_BLOCK_SEL_MASK 0x3800 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_BLOCK_SEL__SHIFT 0xb +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x4000 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe +#define DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK 0x10000 +#define DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT 0x10 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK 0xe0000 +#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT 0x11 +#define DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK 0xff000000 +#define DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT 0x18 +#define DPCSTX_TEST_DEBUG_DATA__DPCS_TEST_DEBUG_DATA_MASK 0xffffffff +#define DPCSTX_TEST_DEBUG_DATA__DPCS_TEST_DEBUG_DATA__SHIFT 0x0 + +#endif /* DCE_11_2_SH_MASK_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h index a9b6923192ee..ebaf67bb1589 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h @@ -1391,6 +1391,8 @@ #define mmRLC_CGTT_MGCG_OVERRIDE 0xec48 #define mmRLC_CGCG_CGLS_CTRL 0xec49 #define mmRLC_CGCG_RAMP_CTRL 0xec4a +#define mmRLC_CGCG_CGLS_CTRL_3D 0xec9d +#define mmRLC_CGCG_RAMP_CTRL_3D 0xec9e #define mmRLC_DYN_PG_STATUS 0xec4b #define mmRLC_DYN_PG_REQUEST 0xec4c #define mmRLC_PG_DELAY 0xec4d diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h index b2d4aaf045bc..6f6fb34742d2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h @@ -111,5 +111,6 @@ #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5 #define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4 #define mmUVD_JPEG_ADDR_CONFIG 0x3a1f +#define mmUVD_GP_SCRATCH4 0x3d38 #endif /* UVD_6_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h index eaf451e26643..32f3e345de08 100644 --- a/drivers/gpu/drm/amd/include/atombios.h +++ b/drivers/gpu/drm/amd/include/atombios.h @@ -79,9 +79,23 @@ #define ATOM_PPLL0 2 #define ATOM_PPLL3 3 +#define ATOM_PHY_PLL0 4 +#define ATOM_PHY_PLL1 5 + #define ATOM_EXT_PLL1 8 +#define ATOM_GCK_DFS 8 #define ATOM_EXT_PLL2 9 +#define ATOM_FCH_CLK 9 #define ATOM_EXT_CLOCK 10 +#define ATOM_DP_DTO 11 + +#define ATOM_COMBOPHY_PLL0 20 +#define ATOM_COMBOPHY_PLL1 21 +#define ATOM_COMBOPHY_PLL2 22 +#define ATOM_COMBOPHY_PLL3 23 +#define ATOM_COMBOPHY_PLL4 24 +#define ATOM_COMBOPHY_PLL5 25 + #define ATOM_PPLL_INVALID 0xFF #define ENCODER_REFCLK_SRC_P1PLL 0 @@ -224,6 +238,31 @@ typedef struct _ATOM_ROM_HEADER UCHAR ucReserved; }ATOM_ROM_HEADER; + +typedef struct _ATOM_ROM_HEADER_V2_1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, + //atombios should init it as "ATOM", don't change the position + USHORT usBiosRuntimeSegmentAddress; + USHORT usProtectedModeInfoOffset; + USHORT usConfigFilenameOffset; + USHORT usCRC_BlockOffset; + USHORT usBIOS_BootupMessageOffset; + USHORT usInt10Offset; + USHORT usPciBusDevInitCode; + USHORT usIoBaseAddress; + USHORT usSubsystemVendorID; + USHORT usSubsystemID; + USHORT usPCI_InfoOffset; + USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position + USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position + UCHAR ucExtendedFunctionCode; + UCHAR ucReserved; + ULONG ulPSPDirTableOffset; +}ATOM_ROM_HEADER_V2_1; + + //==============================Command Table Portion==================================== @@ -272,12 +311,12 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 - USHORT SetCRTC_Replication; //Atomic Table, used only by Bios + USHORT GetSMUClockInfo; //Atomic Table, used only by Bios USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios USHORT LUT_AutoFill; //Atomic Table, only used by Bios - USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios + USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 @@ -292,7 +331,7 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock - USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock + USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT MemoryTraining; //Atomic Table, used only by Bios @@ -333,6 +372,10 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ #define LCD1OutputControl HW_Misc_Operation #define TV1OutputControl Gfx_Harvesting #define TVEncoderControl SMC_Init +#define EnableHW_IconCursor SetDCEClock +#define SetCRTC_Replication GetSMUClockInfo + +#define MemoryRefreshConversion Gfx_Init typedef struct _ATOM_MASTER_COMMAND_TABLE { @@ -425,6 +468,9 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL #define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path +#define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only +#define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only +#define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only typedef struct _ATOM_COMPUTE_CLOCK_FREQ { @@ -518,6 +564,33 @@ typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 //ucPllCntlFlag #define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 +typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter + ULONG ulReserved[5]; +}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7; + +//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag +#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f +#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 +#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 + +typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 +{ + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider + USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 + USHORT usSclk_fcw_int; //integer divider of fcwc + UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv + UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved + UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 ) + UCHAR ucSscEnable; + USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable + USHORT usSsc_fcw1_int; //fcw1_int when SSC enable + USHORT usReserved; + USHORT usPcc_fcw_int; + USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable + USHORT usPcc_fcw_slew_frac; +}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7; // ucInputFlag #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode @@ -557,12 +630,16 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 ULONG ulReserved; }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2; +//Input parameter of DynamicMemorySettingsTable +//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER { ATOM_COMPUTE_CLOCK_FREQ ulClock; ULONG ulReserved[2]; }DYNAMICE_MEMORY_SETTINGS_PARAMETER; +//Input parameter of DynamicMemorySettingsTable +//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER { ATOM_COMPUTE_CLOCK_FREQ ulClock; @@ -570,6 +647,29 @@ typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER ULONG ulReserved; }DYNAMICE_ENGINE_SETTINGS_PARAMETER; +//Input parameter of DynamicMemorySettingsTable ver2.1 and above +//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM +typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; + UCHAR ucMclkDPMState; + UCHAR ucReserved[3]; + ULONG ulReserved; +}DYNAMICE_MC_DPM_SETTINGS_PARAMETER; + +//ucMclkDPMState +#define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0 +#define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1 +#define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2 + +typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 +{ + DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg; + DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg; + DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg; +}DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1; + + /****************************************************************************/ // Structures used by SetEngineClockTable /****************************************************************************/ @@ -584,6 +684,13 @@ typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; }SET_ENGINE_CLOCK_PS_ALLOCATION; +typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2 +{ + ULONG ulTargetEngineClock; //In 10Khz unit + COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved; +}SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2; + + /****************************************************************************/ // Structures used by SetMemoryClockTable /****************************************************************************/ @@ -827,6 +934,12 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 #define ATOM_ENCODER_CMD_SETUP 0x0f #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 +// New Command for DIGxEncoderControlTable v1.5 +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14 +#define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP +#define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table +#define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table + // ucStatus #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 @@ -955,6 +1068,69 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 + +typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5 +{ + UCHAR ucDigId; // 0~6 map to DIG0~DIG6 + UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP + UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI + UCHAR ucLaneNum; // Lane number + ULONG ulPixelClock; // Pixel Clock in 10Khz + UCHAR ucBitPerColor; + UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc + UCHAR ucReserved[2]; +}ENCODER_STREAM_SETUP_PARAMETERS_V5; + +typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5 +{ + UCHAR ucDigId; // 0~6 map to DIG0~DIG6 + UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP + UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI + UCHAR ucLaneNum; // Lane number + ULONG ulSymClock; // Symbol Clock in 10Khz + UCHAR ucHPDSel; + UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, + UCHAR ucReserved[2]; +}ENCODER_LINK_SETUP_PARAMETERS_V5; + +typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5 +{ + UCHAR ucDigId; // 0~6 map to DIG0~DIG6 + UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP + UCHAR ucPanelMode; // =0: external DP + // =0x1: internal DP2 + // =0x11: internal DP1 NutMeg/Travis DP Translator + UCHAR ucReserved; + ULONG ulReserved[2]; +}DP_PANEL_MODE_SETUP_PARAMETERS_V5; + +typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5 +{ + UCHAR ucDigId; // 0~6 map to DIG0~DIG6 + UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters + UCHAR ucReserved[2]; + ULONG ulReserved[2]; +}ENCODER_GENERIC_CMD_PARAMETERS_V5; + +//ucDigId +#define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x00 +#define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x01 +#define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x02 +#define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x03 +#define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x04 +#define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x05 +#define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06 + + +typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5 +{ + ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam; + ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam; + ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam; + DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam; +}DIG_ENCODER_CONTROL_PARAMETERS_V5; + + /****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable // LVTMATransmitterControlTable @@ -1371,6 +1547,49 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 +{ + UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx + union + { + UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI + UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" + }; + UCHAR ucLaneNum; // Lane number + ULONG ulSymClock; // Symbol Clock in 10Khz + UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned + UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, + UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h + UCHAR ucReserved; + ULONG ulReserved; +}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6; + + +// ucDigEncoderSel +#define ATOM_TRANMSITTER_V6__DIGA_SEL 0x01 +#define ATOM_TRANMSITTER_V6__DIGB_SEL 0x02 +#define ATOM_TRANMSITTER_V6__DIGC_SEL 0x04 +#define ATOM_TRANMSITTER_V6__DIGD_SEL 0x08 +#define ATOM_TRANMSITTER_V6__DIGE_SEL 0x10 +#define ATOM_TRANMSITTER_V6__DIGF_SEL 0x20 +#define ATOM_TRANMSITTER_V6__DIGG_SEL 0x40 + +// ucDigMode +#define ATOM_TRANSMITTER_DIGMODE_V6_DP 0 +#define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2 +#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3 +#define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5 + +//ucHPDSel +#define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x00 +#define ATOM_TRANSMITTER_V6_HPD1_SEL 0x01 +#define ATOM_TRANSMITTER_V6_HPD2_SEL 0x02 +#define ATOM_TRANSMITTER_V6_HPD3_SEL 0x03 +#define ATOM_TRANSMITTER_V6_HPD4_SEL 0x04 +#define ATOM_TRANSMITTER_V6_HPD5_SEL 0x05 +#define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06 + /****************************************************************************/ // Structures used by ExternalEncoderControlTable V1.3 @@ -1784,6 +2003,101 @@ typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; +typedef struct _PIXEL_CLOCK_PARAMETERS_V7 +{ + ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz. + + UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 + UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + UCHAR ucEncoderMode; // Encoder mode: + UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk + // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk ) + // bit[5:4]= RefClock source for PPLL. + // =0: XTLAIN( default mode ) + // =1: pcie + // =2: GENLK + UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to + UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp + UCHAR ucReserved[2]; + ULONG ulReserved; +}PIXEL_CLOCK_PARAMETERS_V7; + +//ucMiscInfo +#define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x01 +#define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x02 +#define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x04 +#define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x08 +#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x30 +#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x00 +#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x10 +#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x20 + +//ucDeepColorRatio +#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO +#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 +#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 +#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 + +// SetDCEClockTable input parameter for DCE11.1 +typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1 +{ + ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz. + UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS + UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1 + UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1 + UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1 +}SET_DCE_CLOCK_PARAMETERS_V1_1; + + +typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 +{ + SET_DCE_CLOCK_PARAMETERS_V1_1 asParam; + ULONG ulReserved[2]; +}SET_DCE_CLOCK_PS_ALLOCATION_V1_1; + +//SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag +#define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x01 +#define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01 +#define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02 + +// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above +typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1 +{ + ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. + UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK + UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx + UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) + UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK +}SET_DCE_CLOCK_PARAMETERS_V2_1; + +//ucDCEClkType +#define DCE_CLOCK_TYPE_DISPCLK 0 +#define DCE_CLOCK_TYPE_DPREFCLK 1 +#define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable + +//ucDCEClkFlag when ucDCEClkType == DPREFCLK +#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x03 +#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x00 +#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x01 +#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x02 +#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x03 + +//ucDCEClkFlag when ucDCEClkType == PIXCLK +#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03 +#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO +#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 +#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 +#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 +#define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04 + +typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1 +{ + SET_DCE_CLOCK_PARAMETERS_V2_1 asParam; + ULONG ulReserved[2]; +}SET_DCE_CLOCK_PS_ALLOCATION_V2_1; + + /****************************************************************************/ // Structures used by AdjustDisplayPllTable @@ -2300,6 +2614,11 @@ typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 #define VOLTAGE_TYPE_VDDCI 4 #define VOLTAGE_TYPE_VDDGFX 5 #define VOLTAGE_TYPE_PCC 6 +#define VOLTAGE_TYPE_MVPP 7 +#define VOLTAGE_TYPE_LEDDPM 8 +#define VOLTAGE_TYPE_PCC_MVDD 9 +#define VOLTAGE_TYPE_PCIE_VDDC 10 +#define VOLTAGE_TYPE_PCIE_VDDR 11 #define VOLTAGE_TYPE_GENERIC_I2C_1 0x11 #define VOLTAGE_TYPE_GENERIC_I2C_2 0x12 @@ -2396,6 +2715,39 @@ typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 USHORT usTDP_Power; // TDP_Current in unit of 0.1W }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; + +// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure +typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 +{ + UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI + UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info + USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id + ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table + ULONG ulReserved[3]; +}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3; + +// New Added from CI Hawaii for EVV feature +typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 +{ + ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv + ULONG ulReserved[4]; +}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3; + + +/****************************************************************************/ +// Structures used by GetSMUClockInfo +/****************************************************************************/ +typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1 +{ + ULONG ulDfsPllOutputFreq:24; + ULONG ucDfsDivider:8; +}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1; + +typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1 +{ + ULONG ulDfsOutputFreq; +}GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1; + /****************************************************************************/ // Structures used by TVEncoderControlTable /****************************************************************************/ @@ -2429,13 +2781,13 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES USHORT PaletteData; // Only used by BIOS USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 - USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 + USHORT SMU_Info; // Shared by various SW components,latest version 1.1 USHORT SupportedDevicesInfo; // Will be obsolete from R600 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 USHORT VESA_ToInternalModeLUT; // Only used by Bios - USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 + USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 USHORT GPUVirtualizationInfo; // Will be obsolete from R600 USHORT SaveRestoreInfo; // Only used by Bios @@ -2455,7 +2807,7 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 - USHORT ServiceInfo; + USHORT ServiceInfo; }ATOM_MASTER_LIST_OF_DATA_TABLES; typedef struct _ATOM_MASTER_DATA_TABLE @@ -2469,6 +2821,8 @@ typedef struct _ATOM_MASTER_DATA_TABLE #define DAC_Info PaletteData #define TMDS_Info DIGTransmitterInfo #define CompassionateData GPUVirtualizationInfo +#define AnalogTV_Info SMU_Info +#define ComponentVideoInfo GFX_Info /****************************************************************************/ // Structure used in MultimediaCapabilityInfoTable @@ -4278,10 +4632,15 @@ typedef struct _EXT_DISPLAY_PATH #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 //usCaps -#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 -#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02 -#define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 0x04 -#define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT 0x08 +#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x0001 +#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x0002 +#define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C +#define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip +#define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip +#define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip + + + typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO { @@ -4325,10 +4684,10 @@ typedef struct _ATOM_COMMON_RECORD_HEADER #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 - +#define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 22 //Must be updated when new record type is added,equal to that record definition! -#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE +#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE typedef struct _ATOM_I2C_RECORD { @@ -4458,10 +4817,12 @@ typedef struct _ATOM_ENCODER_DVO_CF_RECORD UCHAR ucPadding[2]; }ATOM_ENCODER_DVO_CF_RECORD; -// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap -#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder +// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap +#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN +#define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not. #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. +#define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board. typedef struct _ATOM_ENCODER_CAP_RECORD { @@ -4482,6 +4843,31 @@ typedef struct _ATOM_ENCODER_CAP_RECORD }; }ATOM_ENCODER_CAP_RECORD; +// Used after SI +typedef struct _ATOM_ENCODER_CAP_RECORD_V2 +{ + ATOM_COMMON_RECORD_HEADER sheader; + union { + USHORT usEncoderCap; + struct { +#if ATOM_BIG_ENDIAN + USHORT usReserved:12; // Bit4-15 may be defined for other capability in future + USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable + USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) + USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable + USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable +#else + USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable + USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable + USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) + USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable + USHORT usReserved:12; // Bit4-15 may be defined for other capability in future +#endif + }; + }; +}ATOM_ENCODER_CAP_RECORD_V2; + + // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 @@ -4554,6 +4940,16 @@ typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD USHORT usReserved; }ATOM_CONNECTOR_REMOTE_CAP_RECORD; + +typedef struct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 + UCHAR ucMaxTmdsClkRateIn2_5Mhz; + UCHAR ucReserved; +} ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD; + + typedef struct _ATOM_CONNECTOR_LAYOUT_INFO { USHORT usConnectorObjectId; @@ -4657,12 +5053,12 @@ typedef struct _ATOM_VOLTAGE_CONTROL #define VOLTAGE_CONTROL_ID_UP1801 0x0C #define VOLTAGE_CONTROL_ID_ST6788A 0x0D #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E -#define VOLTAGE_CONTROL_ID_AD527x 0x0F -#define VOLTAGE_CONTROL_ID_NCP81022 0x10 -#define VOLTAGE_CONTROL_ID_LTC2635 0x11 -#define VOLTAGE_CONTROL_ID_NCP4208 0x12 +#define VOLTAGE_CONTROL_ID_AD527x 0x0F +#define VOLTAGE_CONTROL_ID_NCP81022 0x10 +#define VOLTAGE_CONTROL_ID_LTC2635 0x11 +#define VOLTAGE_CONTROL_ID_NCP4208 0x12 #define VOLTAGE_CONTROL_ID_IR35xx 0x13 -#define VOLTAGE_CONTROL_ID_RT9403 0x14 +#define VOLTAGE_CONTROL_ID_RT9403 0x14 #define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40 @@ -4784,11 +5180,38 @@ typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 ULONG ulReserved; }ATOM_SVID2_VOLTAGE_OBJECT_V3; + + +typedef struct _ATOM_MERGED_VOLTAGE_OBJECT_V3 +{ + ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER + UCHAR ucMergedVType; // VDDC/VDCCI/.... + UCHAR ucReserved[3]; +}ATOM_MERGED_VOLTAGE_OBJECT_V3; + + +typedef struct _ATOM_EVV_DPM_INFO +{ + ULONG ulDPMSclk; // DPM state SCLK + USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv + UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable + UCHAR ucDPMState; // DPMState0~7 +} ATOM_EVV_DPM_INFO; + +// ucVoltageMode = VOLTAGE_OBJ_EVV +typedef struct _ATOM_EVV_VOLTAGE_OBJECT_V3 +{ + ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 + ATOM_EVV_DPM_INFO asEvvDpmList[8]; +}ATOM_EVV_VOLTAGE_OBJECT_V3; + + typedef union _ATOM_VOLTAGE_OBJECT_V3{ ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; + ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj; }ATOM_VOLTAGE_OBJECT_V3; typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 @@ -4963,7 +5386,11 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3 ULONG ulLkgEncodeMax; ULONG ulLkgEncodeMin; ULONG ulEfuseLogisticAlpha; + + union{ USHORT usPowerDpm0; + USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive + }; USHORT usPowerDpm1; USHORT usPowerDpm2; USHORT usPowerDpm3; @@ -5067,6 +5494,86 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4 ULONG ulReserved[8]; // Reserved for future ASIC }ATOM_ASIC_PROFILING_INFO_V3_4; +// for Polaris10/Polaris11 speed EVV algorithm +typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5 +{ + ATOM_COMMON_TABLE_HEADER asHeader; + ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv + ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv + USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address ) + UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD + UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length + ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 ) + ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) + ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) + EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1. + ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/> + ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/> + ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/> + ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/> + ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/> + ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/> + ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/> + ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/> + ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/> + ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/> + ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/> + UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/> + UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/> + UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/> + UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/> + UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/> + UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/> + UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/> + UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/> + ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1" + ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1" + ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1" + ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/> + ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/> + ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/> + ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/> + ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/> + ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/> + ULONG ulReserved[12]; +}ATOM_ASIC_PROFILING_INFO_V3_5; + + +typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{ + ULONG ulMaxSclkFreq; + UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz + UCHAR ucPostdiv; // divide by 2^n + USHORT ucFcw_pcc; + USHORT ucFcw_trans_upper; + USHORT ucRcw_trans_lower; +}ATOM_SCLK_FCW_RANGE_ENTRY_V1; + + +// SMU_InfoTable for Polaris10/Polaris11 +typedef struct _ATOM_SMU_INFO_V2_1 +{ + ATOM_COMMON_TABLE_HEADER asHeader; + UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1 + UCHAR ucReserved[3]; + ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8]; +}ATOM_SMU_INFO_V2_1; + + +// GFX_InfoTable for Polaris10/Polaris11 +typedef struct _ATOM_GFX_INFO_V2_1 +{ + ATOM_COMMON_TABLE_HEADER asHeader; + UCHAR GfxIpMinVer; + UCHAR GfxIpMajVer; + UCHAR max_shader_engines; + UCHAR max_tile_pipes; + UCHAR max_cu_per_sh; + UCHAR max_sh_per_se; + UCHAR max_backends_per_se; + UCHAR max_texture_channel_caches; +}ATOM_GFX_INFO_V2_1; + + typedef struct _ATOM_POWER_SOURCE_OBJECT { UCHAR ucPwrSrcId; // Power source @@ -5765,14 +6272,6 @@ sExtDispConnInfo: Display connector information table provided t **********************************************************************************************************************/ -// this Table is used for Kaveri/Kabini APU -typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 -{ - ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition - ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure -}ATOM_FUSION_SYSTEM_INFO_V2; - - typedef struct _ATOM_I2C_REG_INFO { UCHAR ucI2cRegIndex; @@ -5859,7 +6358,50 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 #define EDP_VS_VARIABLE_PREM_MODE 5 -// this IntegrateSystemInfoTable is used for Carrizo +// ulGPUCapInfo +#define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x08 +#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS 0x10 +//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML +#define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x00010000 +//ulGPUCapInfo[18]=1 indicate the IOMMU is not available +#define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x00040000 +//ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened. +#define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000 + + +typedef struct _DPHY_TIMING_PARA +{ + UCHAR ucProfileID; // SENSOR_PROFILES + ULONG ucPara; +} DPHY_TIMING_PARA; + +typedef struct _DPHY_ELEC_PARA +{ + USHORT usPara[3]; +} DPHY_ELEC_PARA; + +typedef struct _CAMERA_MODULE_INFO +{ + UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user + UCHAR strModuleName[8]; + DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor +} CAMERA_MODULE_INFO; + +typedef struct _FLASHLIGHT_INFO +{ + UCHAR ucID; // 0: Rear, 1: Front + UCHAR strName[8]; +} FLASHLIGHT_INFO; + +typedef struct _CAMERA_DATA +{ + ULONG ulVersionCode; + CAMERA_MODULE_INFO asCameraInfo[3]; // Assuming 3 camera sensors max + FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max + DPHY_ELEC_PARA asDphyElecPara; + ULONG ulCrcVal; // CRC +}CAMERA_DATA; + typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 { ATOM_COMMON_TABLE_HEADER sHeader; @@ -5883,7 +6425,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 USHORT usPanelRefreshRateRange; UCHAR ucMemoryType; UCHAR ucUMAChannelNumber; - UCHAR strVBIOSMsg[40]; + ULONG ulMsgReserved[10]; ATOM_TDP_CONFIG asTdpConfig; ULONG ulReserved[7]; ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; @@ -5925,8 +6467,27 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 UCHAR ucEDPv1_4VSMode; UCHAR ucReserved2; ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; + CAMERA_DATA asCameraInfo; + ULONG ulReserved8[29]; }ATOM_INTEGRATED_SYSTEM_INFO_V1_10; + +// this Table is used for Kaveri/Kabini APU +typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 +{ + ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition + ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure +}ATOM_FUSION_SYSTEM_INFO_V2; + + +typedef struct _ATOM_FUSION_SYSTEM_INFO_V3 +{ + ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition + ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable +}ATOM_FUSION_SYSTEM_INFO_V3; + +#define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800 + /**************************************************************************/ // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design //Memory SS Info Table @@ -6193,12 +6754,12 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S3_DFP1_ACTIVE 0x00000008L #define ATOM_S3_CRT2_ACTIVE 0x00000010L #define ATOM_S3_LCD2_ACTIVE 0x00000020L -#define ATOM_S3_DFP6_ACTIVE 0x00000040L +#define ATOM_S3_DFP6_ACTIVE 0x00000040L #define ATOM_S3_DFP2_ACTIVE 0x00000080L #define ATOM_S3_CV_ACTIVE 0x00000100L -#define ATOM_S3_DFP3_ACTIVE 0x00000200L -#define ATOM_S3_DFP4_ACTIVE 0x00000400L -#define ATOM_S3_DFP5_ACTIVE 0x00000800L +#define ATOM_S3_DFP3_ACTIVE 0x00000200L +#define ATOM_S3_DFP4_ACTIVE 0x00000400L +#define ATOM_S3_DFP5_ACTIVE 0x00000800L #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL @@ -6215,9 +6776,9 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L -#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L -#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L -#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L +#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L +#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L +#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L @@ -6238,9 +6799,9 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S3_DFP6_ACTIVEb0 0x40 #define ATOM_S3_DFP2_ACTIVEb0 0x80 #define ATOM_S3_CV_ACTIVEb1 0x01 -#define ATOM_S3_DFP3_ACTIVEb1 0x02 -#define ATOM_S3_DFP4_ACTIVEb1 0x04 -#define ATOM_S3_DFP5_ACTIVEb1 0x08 +#define ATOM_S3_DFP3_ACTIVEb1 0x02 +#define ATOM_S3_DFP4_ACTIVEb1 0x04 +#define ATOM_S3_DFP5_ACTIVEb1 0x08 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF @@ -6254,9 +6815,9 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 -#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 -#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 -#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 +#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 +#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 +#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF @@ -6878,15 +7439,18 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 #define _32Mx16 0x32 #define _32Mx32 0x33 #define _32Mx128 0x35 -#define _64Mx32 0x43 #define _64Mx8 0x41 #define _64Mx16 0x42 +#define _64Mx32 0x43 +#define _64Mx128 0x45 #define _128Mx8 0x51 #define _128Mx16 0x52 #define _128Mx32 0x53 #define _256Mx8 0x61 #define _256Mx16 0x62 +#define _256Mx32 0x63 #define _512Mx8 0x71 +#define _512Mx16 0x72 #define SAMSUNG 0x1 @@ -7407,6 +7971,17 @@ typedef struct _ATOM_MEMORY_TRAINING_INFO }ATOM_MEMORY_TRAINING_INFO; +typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulMCUcodeVersion; + USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array + USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array + USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array + USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array. +}ATOM_MEMORY_TRAINING_INFO_V3_1; + + typedef struct SW_I2C_CNTL_DATA_PARAMETERS { UCHAR ucControl; @@ -7623,7 +8198,7 @@ typedef struct _ASIC_TRANSMITTER_INFO { USHORT usTransmitterObjId; USHORT usSupportDevice; - UCHAR ucTransmitterCmdTblId; + UCHAR ucTransmitterCmdTblId; UCHAR ucConfig; UCHAR ucEncoderID; //available 1st encoder ( default ) UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h index ab84d4947247..a461e155a160 100644 --- a/drivers/gpu/drm/amd/include/cgs_common.h +++ b/drivers/gpu/drm/amd/include/cgs_common.h @@ -26,6 +26,8 @@ #include "amd_shared.h" +struct cgs_device; + /** * enum cgs_gpu_mem_type - GPU memory types */ @@ -92,6 +94,7 @@ enum cgs_voltage_planes { */ enum cgs_ucode_id { CGS_UCODE_ID_SMU = 0, + CGS_UCODE_ID_SMU_SK, CGS_UCODE_ID_SDMA0, CGS_UCODE_ID_SDMA1, CGS_UCODE_ID_CP_CE, @@ -111,6 +114,7 @@ enum cgs_system_info_id { CGS_SYSTEM_INFO_PCIE_MLW, CGS_SYSTEM_INFO_CG_FLAGS, CGS_SYSTEM_INFO_PG_FLAGS, + CGS_SYSTEM_INFO_GFX_CU_INFO, CGS_SYSTEM_INFO_ID_MAXIMUM, }; @@ -223,7 +227,7 @@ struct cgs_acpi_method_info { * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type, +typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, uint64_t *mc_start, uint64_t *mc_size, uint64_t *mem_size); @@ -239,7 +243,7 @@ typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size, +typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size, uint64_t min_offset, uint64_t max_offset, cgs_handle_t *kmem_handle, uint64_t *mcaddr); @@ -250,7 +254,7 @@ typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle); +typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle); /** * cgs_alloc_gpu_mem() - Allocate GPU memory @@ -279,7 +283,7 @@ typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle); * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type, +typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, uint64_t size, uint64_t align, uint64_t min_offset, uint64_t max_offset, cgs_handle_t *handle); @@ -291,7 +295,7 @@ typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); +typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); /** * cgs_gmap_gpu_mem() - GPU-map GPU memory @@ -303,7 +307,7 @@ typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, +typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, uint64_t *mcaddr); /** @@ -315,7 +319,7 @@ typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); +typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); /** * cgs_kmap_gpu_mem() - Kernel-map GPU memory @@ -326,7 +330,7 @@ typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, +typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, void **map); /** @@ -336,7 +340,7 @@ typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); +typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); /** * cgs_read_register() - Read an MMIO register @@ -345,7 +349,7 @@ typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); * * Return: register value */ -typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset); +typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); /** * cgs_write_register() - Write an MMIO register @@ -353,7 +357,7 @@ typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset); * @offset: register offset * @value: register value */ -typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset, +typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, uint32_t value); /** @@ -363,7 +367,7 @@ typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset, * * Return: register value */ -typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, +typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, unsigned index); /** @@ -372,7 +376,7 @@ typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg s * @offset: register offset * @value: register value */ -typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, +typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, unsigned index, uint32_t value); /** @@ -382,7 +386,7 @@ typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg spac * * Return: Value read */ -typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr); +typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr); /** * cgs_read_pci_config_word() - Read word from PCI configuration space @@ -391,7 +395,7 @@ typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr); * * Return: Value read */ -typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr); +typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr); /** * cgs_read_pci_config_dword() - Read dword from PCI configuration space @@ -400,7 +404,7 @@ typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr); * * Return: Value read */ -typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device, +typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr); /** @@ -409,7 +413,7 @@ typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device, * @addr: address * @value: value to write */ -typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr, +typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr, uint8_t value); /** @@ -418,7 +422,7 @@ typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr, * @addr: address, must be word-aligned * @value: value to write */ -typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, +typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr, uint16_t value); /** @@ -427,7 +431,7 @@ typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, * @addr: address, must be dword-aligned * @value: value to write */ -typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, +typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr, uint32_t value); @@ -441,7 +445,7 @@ typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_get_pci_resource_t)(void *cgs_device, +typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, enum cgs_resource_type resource_type, uint64_t size, uint64_t offset, @@ -458,7 +462,7 @@ typedef int (*cgs_get_pci_resource_t)(void *cgs_device, * Return: Pointer to start of the table, or NULL on failure */ typedef const void *(*cgs_atom_get_data_table_t)( - void *cgs_device, unsigned table, + struct cgs_device *cgs_device, unsigned table, uint16_t *size, uint8_t *frev, uint8_t *crev); /** @@ -470,7 +474,7 @@ typedef const void *(*cgs_atom_get_data_table_t)( * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table, +typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, uint8_t *frev, uint8_t *crev); /** @@ -481,7 +485,7 @@ typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device, +typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, unsigned table, void *args); /** @@ -491,7 +495,7 @@ typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request); +typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request); /** * cgs_destroy_pm_request() - Destroy a power management request @@ -500,7 +504,7 @@ typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request); * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request); +typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request); /** * cgs_set_pm_request() - Activate or deactiveate a PM request @@ -516,7 +520,7 @@ typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request); * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request, +typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request, int active); /** @@ -528,7 +532,7 @@ typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request, +typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request, enum cgs_clock clock, unsigned freq); /** @@ -540,7 +544,7 @@ typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request, +typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request, enum cgs_engine engine, int powered); /** @@ -551,7 +555,7 @@ typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device, +typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device, enum cgs_clock clock, struct cgs_clock_limits *limits); @@ -563,7 +567,7 @@ typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask, +typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask, const uint32_t *voltages); /** * cgs_get_firmware_info - Get the firmware information from core driver @@ -573,25 +577,25 @@ typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_get_firmware_info)(void *cgs_device, +typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, enum cgs_ucode_id type, struct cgs_firmware_info *info); -typedef int(*cgs_set_powergating_state)(void *cgs_device, +typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, enum amd_ip_block_type block_type, enum amd_powergating_state state); -typedef int(*cgs_set_clockgating_state)(void *cgs_device, +typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, enum amd_ip_block_type block_type, enum amd_clockgating_state state); typedef int(*cgs_get_active_displays_info)( - void *cgs_device, + struct cgs_device *cgs_device, struct cgs_display_info *info); -typedef int (*cgs_notify_dpm_enabled)(void *cgs_device, bool enabled); +typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); -typedef int (*cgs_call_acpi_method)(void *cgs_device, +typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device, uint32_t acpi_method, uint32_t acpi_function, void *pinput, void *poutput, @@ -599,7 +603,7 @@ typedef int (*cgs_call_acpi_method)(void *cgs_device, uint32_t input_size, uint32_t output_size); -typedef int (*cgs_query_system_info)(void *cgs_device, +typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, struct cgs_system_info *sys_info); struct cgs_ops { diff --git a/drivers/gpu/drm/amd/include/cgs_linux.h b/drivers/gpu/drm/amd/include/cgs_linux.h index 3b47ae313e36..ca4f6007a9b3 100644 --- a/drivers/gpu/drm/amd/include/cgs_linux.h +++ b/drivers/gpu/drm/amd/include/cgs_linux.h @@ -66,7 +66,7 @@ typedef int (*cgs_irq_handler_func_t)(void *private_data, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned src_id, +typedef int (*cgs_add_irq_source_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned num_types, cgs_irq_source_set_func_t set, cgs_irq_handler_func_t handler, @@ -83,7 +83,7 @@ typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned src_id, * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned src_id, unsigned type); +typedef int (*cgs_irq_get_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type); /** * cgs_irq_put() - Indicate IRQ source is no longer needed @@ -98,7 +98,7 @@ typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned src_id, unsigned type); * * Return: 0 on success, -errno otherwise */ -typedef int (*cgs_irq_put_t)(void *cgs_device, unsigned src_id, unsigned type); +typedef int (*cgs_irq_put_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type); struct cgs_os_ops { /* IRQ handling */ diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 9d2290044708..8e345bfddb69 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -37,6 +37,12 @@ return -EINVAL; \ } while (0) +#define PP_CHECK_HW(hwmgr) \ + do { \ + if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \ + return -EINVAL; \ + } while (0) + static int pp_early_init(void *handle) { return 0; @@ -54,22 +60,26 @@ static int pp_sw_init(void *handle) pp_handle = (struct pp_instance *)handle; hwmgr = pp_handle->hwmgr; - if (hwmgr == NULL || hwmgr->pptable_func == NULL || - hwmgr->hwmgr_func == NULL || + PP_CHECK_HW(hwmgr); + + if (hwmgr->pptable_func == NULL || hwmgr->pptable_func->pptable_init == NULL || hwmgr->hwmgr_func->backend_init == NULL) return -EINVAL; ret = hwmgr->pptable_func->pptable_init(hwmgr); - - if (ret == 0) - ret = hwmgr->hwmgr_func->backend_init(hwmgr); - if (ret) - printk("amdgpu: powerplay initialization failed\n"); - else - printk("amdgpu: powerplay initialized\n"); + goto err; + ret = hwmgr->hwmgr_func->backend_init(hwmgr); + if (ret) + goto err; + + pr_info("amdgpu: powerplay initialized\n"); + + return 0; +err: + pr_err("amdgpu: powerplay initialization failed\n"); return ret; } @@ -85,8 +95,9 @@ static int pp_sw_fini(void *handle) pp_handle = (struct pp_instance *)handle; hwmgr = pp_handle->hwmgr; - if (hwmgr != NULL || hwmgr->hwmgr_func != NULL || - hwmgr->hwmgr_func->backend_fini != NULL) + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->backend_fini != NULL) ret = hwmgr->hwmgr_func->backend_fini(hwmgr); return ret; @@ -172,21 +183,117 @@ static int pp_sw_reset(void *handle) return 0; } -static void pp_print_status(void *handle) -{ - -} static int pp_set_clockgating_state(void *handle, enum amd_clockgating_state state) { + struct pp_hwmgr *hwmgr; + uint32_t msg_id, pp_state; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } + + if (state == AMD_CG_STATE_UNGATE) + pp_state = 0; + else + pp_state = PP_STATE_CG | PP_STATE_LS; + + /* Enable/disable GFX blocks clock gating through SMU */ + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_CG, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_3D, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_RLC, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_CP, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_MG, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + + /* Enable/disable System blocks clock gating through SMU */ + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_BIF, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_BIF, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_MC, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_ROM, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_DRM, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_HDP, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_SDMA, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + return 0; } static int pp_set_powergating_state(void *handle, enum amd_powergating_state state) { - return 0; + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } + + /* Enable/disable GFX per cu powergating through SMU */ + return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr, + state == AMD_PG_STATE_GATE ? true : false); } static int pp_suspend(void *handle) @@ -236,6 +343,7 @@ static int pp_resume(void *handle) } const struct amd_ip_funcs pp_ip_funcs = { + .name = "powerplay", .early_init = pp_early_init, .late_init = NULL, .sw_init = pp_sw_init, @@ -247,7 +355,6 @@ const struct amd_ip_funcs pp_ip_funcs = { .is_idle = pp_is_idle, .wait_for_idle = pp_wait_for_idle, .soft_reset = pp_sw_reset, - .print_status = pp_print_status, .set_clockgating_state = pp_set_clockgating_state, .set_powergating_state = pp_set_powergating_state, }; @@ -275,9 +382,12 @@ static int pp_dpm_force_performance_level(void *handle, hwmgr = pp_handle->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->force_dpm_level == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->force_dpm_level == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); @@ -309,9 +419,12 @@ static int pp_dpm_get_sclk(void *handle, bool low) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->get_sclk == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_sclk == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->get_sclk(hwmgr, low); } @@ -325,9 +438,12 @@ static int pp_dpm_get_mclk(void *handle, bool low) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->get_mclk == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_mclk == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->get_mclk(hwmgr, low); } @@ -341,9 +457,12 @@ static int pp_dpm_powergate_vce(void *handle, bool gate) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->powergate_vce == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->powergate_vce == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); } @@ -357,9 +476,12 @@ static int pp_dpm_powergate_uvd(void *handle, bool gate) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->powergate_uvd == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->powergate_uvd == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); } @@ -455,10 +577,14 @@ pp_debugfs_print_current_performance_level(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->print_current_perforce_level == NULL) + if (hwmgr == NULL || hwmgr->hwmgr_func == NULL) return; + if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return; + } + hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m); } @@ -471,9 +597,12 @@ static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->set_fan_control_mode == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); } @@ -487,9 +616,12 @@ static int pp_dpm_get_fan_control_mode(void *handle) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->get_fan_control_mode == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); } @@ -503,9 +635,12 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->set_fan_speed_percent == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent); } @@ -519,9 +654,12 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->get_fan_speed_percent == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); } @@ -535,9 +673,12 @@ static int pp_dpm_get_temperature(void *handle) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->get_temperature == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_temperature == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->get_temperature(hwmgr); } @@ -591,9 +732,12 @@ static int pp_dpm_get_pp_table(void *handle, char **table) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->get_pp_table == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_pp_table == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->get_pp_table(hwmgr, table); } @@ -607,15 +751,18 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->set_pp_table == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->set_pp_table == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size); } static int pp_dpm_force_clock_level(void *handle, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { struct pp_hwmgr *hwmgr; @@ -624,11 +771,14 @@ static int pp_dpm_force_clock_level(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->force_clock_level == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); - return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level); + if (hwmgr->hwmgr_func->force_clock_level == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } + + return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); } static int pp_dpm_print_clock_levels(void *handle, @@ -641,10 +791,12 @@ static int pp_dpm_print_clock_levels(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || - hwmgr->hwmgr_func->print_clock_levels == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); + if (hwmgr->hwmgr_func->print_clock_levels == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); } diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c index 56856a2864d1..d6635cc4b0fc 100644 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c @@ -24,7 +24,7 @@ #include "eventactionchains.h" #include "eventsubchains.h" -static const pem_event_action *initialize_event[] = { +static const pem_event_action * const initialize_event[] = { block_adjust_power_state_tasks, power_budget_tasks, system_config_tasks, @@ -45,7 +45,7 @@ const struct action_chain initialize_action_chain = { initialize_event }; -static const pem_event_action *uninitialize_event[] = { +static const pem_event_action * const uninitialize_event[] = { ungate_all_display_phys_tasks, uninitialize_display_phy_access_tasks, disable_gfx_voltage_island_power_gating_tasks, @@ -64,7 +64,7 @@ const struct action_chain uninitialize_action_chain = { uninitialize_event }; -static const pem_event_action *power_source_change_event_pp_enabled[] = { +static const pem_event_action * const power_source_change_event_pp_enabled[] = { set_power_source_tasks, set_power_saving_state_tasks, adjust_power_state_tasks, @@ -79,7 +79,7 @@ const struct action_chain power_source_change_action_chain_pp_enabled = { power_source_change_event_pp_enabled }; -static const pem_event_action *power_source_change_event_pp_disabled[] = { +static const pem_event_action * const power_source_change_event_pp_disabled[] = { set_power_source_tasks, set_nbmcu_state_tasks, NULL @@ -90,7 +90,7 @@ const struct action_chain power_source_changes_action_chain_pp_disabled = { power_source_change_event_pp_disabled }; -static const pem_event_action *power_source_change_event_hardware_dc[] = { +static const pem_event_action * const power_source_change_event_hardware_dc[] = { set_power_source_tasks, set_power_saving_state_tasks, adjust_power_state_tasks, @@ -106,7 +106,7 @@ const struct action_chain power_source_change_action_chain_hardware_dc = { power_source_change_event_hardware_dc }; -static const pem_event_action *suspend_event[] = { +static const pem_event_action * const suspend_event[] = { reset_display_phy_access_tasks, unregister_interrupt_tasks, disable_gfx_voltage_island_power_gating_tasks, @@ -130,7 +130,7 @@ const struct action_chain suspend_action_chain = { suspend_event }; -static const pem_event_action *resume_event[] = { +static const pem_event_action * const resume_event[] = { unblock_hw_access_tasks, resume_connected_standby_tasks, notify_smu_resume_tasks, @@ -164,7 +164,7 @@ const struct action_chain resume_action_chain = { resume_event }; -static const pem_event_action *complete_init_event[] = { +static const pem_event_action * const complete_init_event[] = { unblock_adjust_power_state_tasks, adjust_power_state_tasks, enable_gfx_clock_gating_tasks, @@ -178,7 +178,7 @@ const struct action_chain complete_init_action_chain = { complete_init_event }; -static const pem_event_action *enable_gfx_clock_gating_event[] = { +static const pem_event_action * const enable_gfx_clock_gating_event[] = { enable_gfx_clock_gating_tasks, NULL }; @@ -188,7 +188,7 @@ const struct action_chain enable_gfx_clock_gating_action_chain = { enable_gfx_clock_gating_event }; -static const pem_event_action *disable_gfx_clock_gating_event[] = { +static const pem_event_action * const disable_gfx_clock_gating_event[] = { disable_gfx_clock_gating_tasks, NULL }; @@ -198,7 +198,7 @@ const struct action_chain disable_gfx_clock_gating_action_chain = { disable_gfx_clock_gating_event }; -static const pem_event_action *enable_cgpg_event[] = { +static const pem_event_action * const enable_cgpg_event[] = { enable_cgpg_tasks, NULL }; @@ -208,7 +208,7 @@ const struct action_chain enable_cgpg_action_chain = { enable_cgpg_event }; -static const pem_event_action *disable_cgpg_event[] = { +static const pem_event_action * const disable_cgpg_event[] = { disable_cgpg_tasks, NULL }; @@ -221,7 +221,7 @@ const struct action_chain disable_cgpg_action_chain = { /* Enable user _2d performance and activate */ -static const pem_event_action *enable_user_state_event[] = { +static const pem_event_action * const enable_user_state_event[] = { create_new_user_performance_state_tasks, adjust_power_state_tasks, NULL @@ -232,7 +232,7 @@ const struct action_chain enable_user_state_action_chain = { enable_user_state_event }; -static const pem_event_action *enable_user_2d_performance_event[] = { +static const pem_event_action * const enable_user_2d_performance_event[] = { enable_user_2d_performance_tasks, add_user_2d_performance_state_tasks, set_performance_state_tasks, @@ -247,7 +247,7 @@ const struct action_chain enable_user_2d_performance_action_chain = { }; -static const pem_event_action *disable_user_2d_performance_event[] = { +static const pem_event_action * const disable_user_2d_performance_event[] = { disable_user_2d_performance_tasks, delete_user_2d_performance_state_tasks, NULL @@ -259,7 +259,7 @@ const struct action_chain disable_user_2d_performance_action_chain = { }; -static const pem_event_action *display_config_change_event[] = { +static const pem_event_action * const display_config_change_event[] = { /* countDisplayConfigurationChangeEventTasks, */ unblock_adjust_power_state_tasks, set_cpu_power_state, @@ -278,7 +278,7 @@ const struct action_chain display_config_change_action_chain = { display_config_change_event }; -static const pem_event_action *readjust_power_state_event[] = { +static const pem_event_action * const readjust_power_state_event[] = { adjust_power_state_tasks, NULL }; diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c index 1e2ad5603080..cd1ca07ef7f7 100644 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c @@ -62,7 +62,7 @@ int pem_init_event_action_chains(struct pp_eventmgr *eventmgr) int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data) { - const pem_event_action **paction_chain; + const pem_event_action * const *paction_chain; const pem_event_action *psub_chain; int tmp_result = 0; int result = 0; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index b664e34dbcc0..f7ce4cb71346 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -8,7 +8,9 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ tonga_processpptables.o ppatomctrl.o \ tonga_hwmgr.o pppcielanes.o tonga_thermal.o\ fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \ - fiji_clockpowergating.o fiji_thermal.o + fiji_clockpowergating.o fiji_thermal.o \ + polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \ + polaris10_clockpowergating.o AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c index ff08ce41bde9..436fc16dabb6 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c @@ -237,7 +237,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) } -static struct phm_master_table_item cz_enable_clock_power_gatings_list[] = { +static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = { /*we don't need an exit table here, because there is only D3 cold on Kv*/ { phm_cf_want_uvd_power_gating, cz_tf_uvd_power_gating_initialize }, { phm_cf_want_vce_power_gating, cz_tf_vce_power_gating_initialize }, @@ -245,7 +245,7 @@ static struct phm_master_table_item cz_enable_clock_power_gatings_list[] = { { NULL, NULL } }; -struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = { +const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = { 0, PHM_MasterTableFlag_None, cz_enable_clock_power_gatings_list diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h index bbbc0571320e..1954ceaed439 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h @@ -28,8 +28,7 @@ #include "pp_asicblocks.h" extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating); -extern struct phm_master_table_header cz_phm_enable_clock_power_gatings_master; -extern struct phm_master_table_header cz_phm_disable_clock_power_gatings_master; +extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master; extern int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); extern int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c index 5682490337e3..1f14c477d15d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c @@ -915,7 +915,7 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr, return 0; } -static struct phm_master_table_item cz_set_power_state_list[] = { +static const struct phm_master_table_item cz_set_power_state_list[] = { {NULL, cz_tf_update_sclk_limit}, {NULL, cz_tf_set_deep_sleep_sclk_threshold}, {NULL, cz_tf_set_watermark_threshold}, @@ -925,13 +925,13 @@ static struct phm_master_table_item cz_set_power_state_list[] = { {NULL, NULL} }; -static struct phm_master_table_header cz_set_power_state_master = { +static const struct phm_master_table_header cz_set_power_state_master = { 0, PHM_MasterTableFlag_None, cz_set_power_state_list }; -static struct phm_master_table_item cz_setup_asic_list[] = { +static const struct phm_master_table_item cz_setup_asic_list[] = { {NULL, cz_tf_reset_active_process_mask}, {NULL, cz_tf_upload_pptable_to_smu}, {NULL, cz_tf_init_sclk_limit}, @@ -943,7 +943,7 @@ static struct phm_master_table_item cz_setup_asic_list[] = { {NULL, NULL} }; -static struct phm_master_table_header cz_setup_asic_master = { +static const struct phm_master_table_header cz_setup_asic_master = { 0, PHM_MasterTableFlag_None, cz_setup_asic_list @@ -984,14 +984,14 @@ static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr, return 0; } -static struct phm_master_table_item cz_power_down_asic_list[] = { +static const struct phm_master_table_item cz_power_down_asic_list[] = { {NULL, cz_tf_power_up_display_clock_sys_pll}, {NULL, cz_tf_clear_nb_dpm_flag}, {NULL, cz_tf_reset_cc6_data}, {NULL, NULL} }; -static struct phm_master_table_header cz_power_down_asic_master = { +static const struct phm_master_table_header cz_power_down_asic_master = { 0, PHM_MasterTableFlag_None, cz_power_down_asic_list @@ -1095,19 +1095,19 @@ static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr, return 0; } -static struct phm_master_table_item cz_disable_dpm_list[] = { +static const struct phm_master_table_item cz_disable_dpm_list[] = { { NULL, cz_tf_check_for_dpm_enabled}, {NULL, NULL}, }; -static struct phm_master_table_header cz_disable_dpm_master = { +static const struct phm_master_table_header cz_disable_dpm_master = { 0, PHM_MasterTableFlag_None, cz_disable_dpm_list }; -static struct phm_master_table_item cz_enable_dpm_list[] = { +static const struct phm_master_table_item cz_enable_dpm_list[] = { { NULL, cz_tf_check_for_dpm_disabled }, { NULL, cz_tf_program_voting_clients }, { NULL, cz_tf_start_dpm}, @@ -1117,7 +1117,7 @@ static struct phm_master_table_item cz_enable_dpm_list[] = { {NULL, NULL}, }; -static struct phm_master_table_header cz_enable_dpm_master = { +static const struct phm_master_table_header cz_enable_dpm_master = { 0, PHM_MasterTableFlag_None, cz_enable_dpm_list @@ -1729,7 +1729,7 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr, } static int cz_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) return -EINVAL; @@ -1738,10 +1738,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr, case PP_SCLK: smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSclkSoftMin, - (1 << level)); + mask); smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSclkSoftMax, - (1 << level)); + mask); break; default: break; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c index e68edf06ed73..e1b649bd5344 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c @@ -47,10 +47,17 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) data->uvd_power_gated = bgate; - if (bgate) + if (bgate) { + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_GATE); fiji_update_uvd_dpm(hwmgr, true); - else + } else { fiji_update_uvd_dpm(hwmgr, false); + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_UNGATE); + } return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c index 89f31bc5b68b..c94f9faa220a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c @@ -95,23 +95,23 @@ enum DPM_EVENT_SRC { /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */ -uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0}, - {600, 1050, 6, 1} }; +static const uint16_t fiji_clock_stretcher_lookup_table[2][4] = +{ {600, 1050, 3, 0}, {600, 1050, 6, 1} }; /* [FF, SS] type, [] 4 voltage ranges, and * [Floor Freq, Boundary Freq, VID min , VID max] */ -uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = +static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] * (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ -uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5}, - {0, 2, 4, 5, 6, 5} }; +static const uint8_t fiji_clock_stretch_amount_conversion[2][6] = +{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} }; -const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic); +static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic); struct fiji_power_state *cast_phw_fiji_power_state( struct pp_hw_power_state *hw_ps) @@ -465,14 +465,14 @@ static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) table_info->vdd_dep_on_mclk; PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, - "VDD dependency on SCLK table is missing. \ + "VDD dependency on SCLK table is missing. \ This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, - "VDD dependency on SCLK table has to have is missing. \ + "VDD dependency on SCLK table has to have is missing. \ This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, - "VDD dependency on MCLK table is missing. \ + "VDD dependency on MCLK table is missing. \ This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, "VDD dependency on MCLK table has to have is missing. \ @@ -579,6 +579,18 @@ static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr, return 0; } +static int fiji_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) +{ + struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); + + if (data->soft_pp_table) { + kfree(data->soft_pp_table); + data->soft_pp_table = NULL; + } + + return phm_hwmgr_backend_fini(hwmgr); +} + static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); @@ -734,7 +746,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr) data->pcie_lane_cap = (uint32_t)sys_info.value; } else { /* Ignore return value in here, we are cleaning up a mess. */ - tonga_hwmgr_backend_fini(hwmgr); + fiji_hwmgr_backend_fini(hwmgr); } return 0; @@ -1885,6 +1897,23 @@ static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, return 0; } + +static uint8_t fiji_get_sleep_divider_id_from_clock(uint32_t clock, + uint32_t clock_insr) +{ + uint8_t i; + uint32_t temp; + uint32_t min = max(clock_insr, (uint32_t)FIJI_MINIMUM_ENGINE_CLOCK); + + PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0); + for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { + temp = clock >> i; + + if (temp >= min || i == 0) + break; + } + return i; +} /** * Populates single SMC SCLK structure using the provided engine clock * @@ -1928,17 +1957,13 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr, threshold = clock * data->fast_watermark_threshold / 100; - /* - * TODO: get minimum clocks from dal configaration - * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks); - */ - /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */ - /* get level->DeepSleepDivId - if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) - { - level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR); - } */ + data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) + level->DeepSleepDivId = fiji_get_sleep_divider_id_from_clock(clock, + hwmgr->display_config.min_core_set_clock_in_sr); + /* Default to slow, highest DPM level will be * set to PPSMC_DISPLAY_WATERMARK_LOW later. @@ -3364,7 +3389,7 @@ static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr, DPM_EVENT_SRC, src); PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalController)); } else PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, @@ -4066,7 +4091,6 @@ static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); uint32_t mclk = fiji_ps->performance_levels [fiji_ps->performance_level_count - 1].memory_clock; - struct PP_Clocks min_clocks = {0}; uint32_t i; struct cgs_display_info info = {0}; @@ -4080,10 +4104,8 @@ static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons if (i >= sclk_table->count) data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; else { - /* TODO: Check SCLK in DAL's minimum clocks - * in case DeepSleep divider update is required. - */ - if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR) + if(data->display_timing.min_clock_in_sr != + hwmgr->display_config.min_core_set_clock_in_sr) data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; } @@ -5086,24 +5108,40 @@ static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); - *table = (char *)&data->smc_state_table; + if (!data->soft_pp_table) { + data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL); + if (!data->soft_pp_table) + return -ENOMEM; + memcpy(data->soft_pp_table, hwmgr->soft_pp_table, + hwmgr->soft_pp_table_size); + } - return sizeof(struct SMU73_Discrete_DpmTable); + *table = (char *)&data->soft_pp_table; + + return hwmgr->soft_pp_table_size; } static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); - void *table = (void *)&data->smc_state_table; + if (!data->soft_pp_table) { + data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL); + if (!data->soft_pp_table) + return -ENOMEM; + } - memcpy(table, buf, size); + memcpy(data->soft_pp_table, buf, size); + + hwmgr->soft_pp_table = data->soft_pp_table; + + /* TODO: re-init powerplay to implement modified pptable */ return 0; } static int fiji_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); @@ -5115,20 +5153,30 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr, if (!data->sclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); break; + case PP_MCLK: if (!data->mclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); break; + case PP_PCIE: + { + uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; + uint32_t level = 0; + + while (tmp >>= 1) + level++; + if (!data->pcie_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_PCIeDPM_ForceLevel, - (1 << level)); + level); break; + } default: break; } @@ -5252,19 +5300,19 @@ bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *h if (data->display_timing.num_existing_displays != info.display_count) is_update_required = true; -/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL - if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { - cgs_get_min_clock_settings(hwmgr->device, &min_clocks); - if(min_clocks.engineClockInSR != data->display_timing.minClockInSR) + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { + if(hwmgr->display_config.min_core_set_clock_in_sr != data->display_timing.min_clock_in_sr) is_update_required = true; -*/ + } + return is_update_required; } static const struct pp_hwmgr_func fiji_hwmgr_funcs = { .backend_init = &fiji_hwmgr_backend_init, - .backend_fini = &tonga_hwmgr_backend_fini, + .backend_fini = &fiji_hwmgr_backend_fini, .asic_setup = &fiji_setup_asic_task, .dynamic_state_management_enable = &fiji_enable_dpm_tasks, .force_dpm_level = &fiji_dpm_force_dpm_level, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h index a16f7cd4c238..170edf5a772d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h @@ -263,7 +263,7 @@ struct fiji_hwmgr { bool enable_tdc_limit_feature; bool enable_pkg_pwr_tracking_feature; bool disable_uvd_power_tune_feature; - struct fiji_pt_defaults *power_tune_defaults; + const struct fiji_pt_defaults *power_tune_defaults; struct SMU73_Discrete_PmFuses power_tune_table; uint32_t dte_tj_offset; uint32_t fast_watermark_threshold; @@ -302,6 +302,9 @@ struct fiji_hwmgr { bool pg_acp_init; bool frtc_enabled; bool frtc_status_changed; + + /* soft pptable for re-uploading into smu */ + void *soft_pp_table; }; /* To convert to Q8.8 format for firmware */ @@ -338,7 +341,6 @@ enum Fiji_I2CLineID { #define FIJI_UNUSED_GPIO_PIN 0x7F extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); -extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr); extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c index 6efcb2bac45f..db23a4068baf 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c @@ -32,7 +32,7 @@ #define VOLTAGE_SCALE 4 #define POWERTUNE_DEFAULT_SET_MAX 1 -struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { +const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { /*sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */ {1, 0xF, 0xFD, /* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */ @@ -143,7 +143,7 @@ static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda) int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); - struct fiji_pt_defaults *defaults = data->power_tune_defaults; + const struct fiji_pt_defaults *defaults = data->power_tune_defaults; SMU73_Discrete_DpmTable *dpm_table = &(data->smc_state_table); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -222,7 +222,7 @@ int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); - struct fiji_pt_defaults *defaults = data->power_tune_defaults; + const struct fiji_pt_defaults *defaults = data->power_tune_defaults; data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC; @@ -238,7 +238,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr) struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct fiji_pt_defaults *defaults = data->power_tune_defaults; + const struct fiji_pt_defaults *defaults = data->power_tune_defaults; /* TDC number of fraction bits are changed from 8 to 7 * for Fiji as requested by SMC team @@ -256,7 +256,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr) static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); - struct fiji_pt_defaults *defaults = data->power_tune_defaults; + const struct fiji_pt_defaults *defaults = data->power_tune_defaults; uint32_t temp; if (fiji_read_smc_sram_dword(hwmgr->smumgr, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c index e76a7de9aa32..92976b68d6fd 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c @@ -221,8 +221,8 @@ int fiji_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, if (duty100 == 0) return -EINVAL; - tmp64 = (uint64_t)speed * 100; - do_div(tmp64, duty100); + tmp64 = (uint64_t)speed * duty100; + do_div(tmp64, 100); duty = (uint32_t)tmp64; PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -615,7 +615,7 @@ static int tf_fiji_thermal_disable_alert(struct pp_hwmgr *hwmgr, return fiji_thermal_disable_alert(hwmgr); } -static struct phm_master_table_item +static const struct phm_master_table_item fiji_thermal_start_thermal_controller_master_list[] = { {NULL, tf_fiji_thermal_initialize}, {NULL, tf_fiji_thermal_set_temperature_range}, @@ -630,14 +630,14 @@ fiji_thermal_start_thermal_controller_master_list[] = { {NULL, NULL} }; -static struct phm_master_table_header +static const struct phm_master_table_header fiji_thermal_start_thermal_controller_master = { 0, PHM_MasterTableFlag_None, fiji_thermal_start_thermal_controller_master_list }; -static struct phm_master_table_item +static const struct phm_master_table_item fiji_thermal_set_temperature_range_master_list[] = { {NULL, tf_fiji_thermal_disable_alert}, {NULL, tf_fiji_thermal_set_temperature_range}, @@ -645,7 +645,7 @@ fiji_thermal_set_temperature_range_master_list[] = { {NULL, NULL} }; -struct phm_master_table_header +static const struct phm_master_table_header fiji_thermal_set_temperature_range_master = { 0, PHM_MasterTableFlag_None, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c index 72cfecc4f9f7..7a705cee0cc2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c @@ -84,7 +84,7 @@ int phm_dispatch_table(struct pp_hwmgr *hwmgr, } int phm_construct_table(struct pp_hwmgr *hwmgr, - struct phm_master_table_header *master_table, + const struct phm_master_table_header *master_table, struct phm_runtime_table_header *rt_table) { uint32_t function_count = 0; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 5fb98aa2e719..7d69ed635bc2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -34,6 +34,7 @@ extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr); extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr); extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr); +extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr); int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) { @@ -67,6 +68,10 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) case CHIP_FIJI: fiji_hwmgr_init(hwmgr); break; + case CHIP_POLARIS11: + case CHIP_POLARIS10: + polaris10_hwmgr_init(hwmgr); + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h index c9e6c2d80ea6..347fef127ce9 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h @@ -92,6 +92,8 @@ typedef struct phm_ppt_v1_voltage_lookup_table phm_ppt_v1_voltage_lookup_table; struct phm_ppt_v1_pcie_record { uint8_t gen_speed; uint8_t lane_width; + uint16_t usreserved; + uint32_t pcie_sclk; }; typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c new file mode 100644 index 000000000000..8f142a74ad08 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c @@ -0,0 +1,430 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "polaris10_clockpowergating.h" + +int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr) +{ + if (phm_cf_want_uvd_power_gating(hwmgr)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_UVDPowerOFF); + return 0; +} + +int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr) +{ + if (phm_cf_want_uvd_power_gating(hwmgr)) { + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDDynamicPowerGating)) { + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_UVDPowerON, 1); + } else { + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_UVDPowerON, 0); + } + } + + return 0; +} + +int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr) +{ + if (phm_cf_want_vce_power_gating(hwmgr)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_VCEPowerOFF); + return 0; +} + +int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr) +{ + if (phm_cf_want_vce_power_gating(hwmgr)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_VCEPowerON); + return 0; +} + +int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr) +{ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SamuPowerGating)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SAMPowerOFF); + return 0; +} + +int polaris10_phm_powerup_samu(struct pp_hwmgr *hwmgr) +{ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SamuPowerGating)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SAMPowerON); + return 0; +} + +int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + data->uvd_power_gated = false; + data->vce_power_gated = false; + data->samu_power_gated = false; + + polaris10_phm_powerup_uvd(hwmgr); + polaris10_phm_powerup_vce(hwmgr); + polaris10_phm_powerup_samu(hwmgr); + + return 0; +} + +int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->uvd_power_gated == bgate) + return 0; + + data->uvd_power_gated = bgate; + + if (bgate) { + polaris10_update_uvd_dpm(hwmgr, true); + polaris10_phm_powerdown_uvd(hwmgr); + } else { + polaris10_phm_powerup_uvd(hwmgr); + polaris10_update_uvd_dpm(hwmgr, false); + } + + return 0; +} + +int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->vce_power_gated == bgate) + return 0; + + data->vce_power_gated = bgate; + + if (bgate) + polaris10_phm_powerdown_vce(hwmgr); + else + polaris10_phm_powerup_vce(hwmgr); + + return 0; +} + +int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->samu_power_gated == bgate) + return 0; + + data->samu_power_gated = bgate; + + if (bgate) { + polaris10_update_samu_dpm(hwmgr, true); + polaris10_phm_powerdown_samu(hwmgr); + } else { + polaris10_phm_powerup_samu(hwmgr); + polaris10_update_samu_dpm(hwmgr, false); + } + + return 0; +} + +int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, + const uint32_t *msg_id) +{ + PPSMC_Msg msg; + uint32_t value; + + switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) { + case PP_GROUP_GFX: + switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { + case PP_BLOCK_GFX_CG: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_CGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS + ? PPSMC_MSG_EnableClockGatingFeature + : PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_CGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_GFX_3D: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_3DCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_3DLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_GFX_RLC: + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_RLC_LS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_GFX_CP: + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_CP_LS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_GFX_MG: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK | + CG_GFX_OTHERS_MGCG_MASK); + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + default: + return -1; + } + break; + + case PP_GROUP_SYS: + switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { + case PP_BLOCK_SYS_BIF: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_BIF_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_BIF_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_MC: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_MC_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_MC_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_DRM: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_DRM_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_DRM_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_HDP: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_HDP_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_HDP_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_SDMA: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_SDMA_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_SDMA_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_ROM: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_ROM_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + default: + return -1; + + } + break; + + default: + return -1; + + } + + return 0; +} + +/* This function is for Polaris11 only for now, + * Powerplay will only control the static per CU Power Gating. + * Dynamic per CU Power Gating will be done in gfx. + */ +int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) +{ + struct cgs_system_info sys_info = {0}; + uint32_t active_cus; + int result; + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO; + + result = cgs_query_system_info(hwmgr->device, &sys_info); + + if (result) + return -EINVAL; + else + active_cus = sys_info.value; + + if (enable) + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus); + else + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_GFX_CU_PG_DISABLE); +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h new file mode 100644 index 000000000000..88d68cb6e89d --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h @@ -0,0 +1,40 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _POLARIS10_CLOCK_POWER_GATING_H_ +#define _POLARIS10_CLOCK_POWER_GATING_H_ + +#include "polaris10_hwmgr.h" +#include "pp_asicblocks.h" + +int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr); +int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr); +int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, + const uint32_t *msg_id); +int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable); + +#endif /* _POLARIS10_CLOCK_POWER_GATING_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h new file mode 100644 index 000000000000..f78ffd935cee --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h @@ -0,0 +1,62 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef POLARIS10_DYN_DEFAULTS_H +#define POLARIS10_DYN_DEFAULTS_H + + +enum Polaris10dpm_TrendDetection { + Polaris10Adpm_TrendDetection_AUTO, + Polaris10Adpm_TrendDetection_UP, + Polaris10Adpm_TrendDetection_DOWN +}; +typedef enum Polaris10dpm_TrendDetection Polaris10dpm_TrendDetection; + +/* We need to fill in the default values */ + + +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1 0x000400 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000 + + +#define PPPOLARIS10_THERMALPROTECTCOUNTER_DFLT 0x200 +#define PPPOLARIS10_STATICSCREENTHRESHOLDUNIT_DFLT 0 +#define PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT 0x00C8 +#define PPPOLARIS10_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200 +#define PPPOLARIS10_REFERENCEDIVIDER_DFLT 4 + +#define PPPOLARIS10_ULVVOLTAGECHANGEDELAY_DFLT 1687 + +#define PPPOLARIS10_CGULVPARAMETER_DFLT 0x00040035 +#define PPPOLARIS10_CGULVCONTROL_DFLT 0x00007450 +#define PPPOLARIS10_TARGETACTIVITY_DFLT 50 +#define PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT 10 + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c new file mode 100644 index 000000000000..93768fa1dcdc --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c @@ -0,0 +1,4995 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include +#include +#include +#include "linux/delay.h" +#include "pp_acpi.h" +#include "hwmgr.h" +#include "polaris10_hwmgr.h" +#include "polaris10_powertune.h" +#include "polaris10_dyn_defaults.h" +#include "polaris10_smumgr.h" +#include "pp_debug.h" +#include "ppatomctrl.h" +#include "atombios.h" +#include "tonga_pptable.h" +#include "pppcielanes.h" +#include "amd_pcie_helpers.h" +#include "hardwaremanager.h" +#include "tonga_processpptables.h" +#include "cgs_common.h" +#include "smu74.h" +#include "smu_ucode_xfer_vi.h" +#include "smu74_discrete.h" +#include "smu/smu_7_1_3_d.h" +#include "smu/smu_7_1_3_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" +#include "oss/oss_3_0_d.h" +#include "gca/gfx_8_0_d.h" +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" +#include "dce/dce_10_0_d.h" +#include "dce/dce_10_0_sh_mask.h" + +#include "polaris10_thermal.h" +#include "polaris10_clockpowergating.h" + +#define MC_CG_ARB_FREQ_F0 0x0a +#define MC_CG_ARB_FREQ_F1 0x0b +#define MC_CG_ARB_FREQ_F2 0x0c +#define MC_CG_ARB_FREQ_F3 0x0d + +#define MC_CG_SEQ_DRAMCONF_S0 0x05 +#define MC_CG_SEQ_DRAMCONF_S1 0x06 +#define MC_CG_SEQ_YCLK_SUSPEND 0x04 +#define MC_CG_SEQ_YCLK_RESUME 0x0a + + +#define SMC_RAM_END 0x40000 + +#define SMC_CG_IND_START 0xc0030000 +#define SMC_CG_IND_END 0xc0040000 + +#define VOLTAGE_SCALE 4 +#define VOLTAGE_VID_OFFSET_SCALE1 625 +#define VOLTAGE_VID_OFFSET_SCALE2 100 + +#define VDDC_VDDCI_DELTA 200 + +#define MEM_FREQ_LOW_LATENCY 25000 +#define MEM_FREQ_HIGH_LATENCY 80000 + +#define MEM_LATENCY_HIGH 45 +#define MEM_LATENCY_LOW 35 +#define MEM_LATENCY_ERR 0xFFFF + +#define MC_SEQ_MISC0_GDDR5_SHIFT 28 +#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 +#define MC_SEQ_MISC0_GDDR5_VALUE 5 + + +#define PCIE_BUS_CLK 10000 +#define TCLK (PCIE_BUS_CLK / 10) + + +static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] = +{ {600, 1050, 3, 0}, {600, 1050, 6, 1} }; + +/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */ +static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = +{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, + { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; + +/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ +static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] = +{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} }; + +/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ +enum DPM_EVENT_SRC { + DPM_EVENT_SRC_ANALOG = 0, + DPM_EVENT_SRC_EXTERNAL = 1, + DPM_EVENT_SRC_DIGITAL = 2, + DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, + DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 +}; + +static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic); + +struct polaris10_power_state *cast_phw_polaris10_power_state( + struct pp_hw_power_state *hw_ps) +{ + PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic), + "Invalid Powerstate Type!", + return NULL); + + return (struct polaris10_power_state *)hw_ps; +} + +const struct polaris10_power_state *cast_const_phw_polaris10_power_state( + const struct pp_hw_power_state *hw_ps) +{ + PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic), + "Invalid Powerstate Type!", + return NULL); + + return (const struct polaris10_power_state *)hw_ps; +} + +static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr) +{ + return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) + ? true : false; +} + +/** + * Find the MC microcode version and store it in the HwMgr struct + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr) +{ + cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); + + hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); + + return 0; +} + +uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr) +{ + uint32_t speedCntl = 0; + + /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ + speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, + ixPCIE_LC_SPEED_CNTL); + return((uint16_t)PHM_GET_FIELD(speedCntl, + PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); +} + +int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) +{ + uint32_t link_width; + + /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ + link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, + PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); + + PP_ASSERT_WITH_CODE((7 >= link_width), + "Invalid PCIe lane width!", return 0); + + return decode_pcie_lane_width(link_width); +} + +void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) +{ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)hwmgr->pptable; + struct phm_clock_voltage_dependency_table *table = + table_info->vddc_dep_on_dal_pwrl; + struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table; + enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level; + uint32_t req_vddc = 0, req_volt, i; + + if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW && + dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE)) + return; + + for (i = 0; i < table->count; i++) { + if (dal_power_level == table->entries[i].clk) { + req_vddc = table->entries[i].v; + break; + } + } + + vddc_table = table_info->vdd_dep_on_sclk; + for (i = 0; i < vddc_table->count; i++) { + if (req_vddc <= vddc_table->entries[i].vddc) { + req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE) + << VDDC_SHIFT; + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_VddC_Request, req_volt); + return; + } + } + printk(KERN_ERR "DAL requested level can not" + " found a available voltage in VDDC DPM Table \n"); +} + +/** +* Enable voltage control +* +* @param pHwMgr the address of the powerplay hardware manager. +* @return always PP_Result_OK +*/ +int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) +{ + PP_ASSERT_WITH_CODE( + (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0), + "Failed to enable voltage DPM during DPM Start Function!", + return 1; + ); + + return 0; +} + +/** +* Checks if we want to support voltage control +* +* @param hwmgr the address of the powerplay hardware manager. +*/ +static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr) +{ + const struct polaris10_hwmgr *data = + (const struct polaris10_hwmgr *)(hwmgr->backend); + + return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control); +} + +/** +* Enable voltage control +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr) +{ + /* enable voltage control */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); + + return 0; +} + +/** +* Create Voltage Tables. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)hwmgr->pptable; + int result; + + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + result = atomctrl_get_voltage_table_v3(hwmgr, + VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, + &(data->mvdd_voltage_table)); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve MVDD table.", + return result); + } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { + result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), + table_info->vdd_dep_on_mclk); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve SVI2 MVDD table from dependancy table.", + return result;); + } + + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + result = atomctrl_get_voltage_table_v3(hwmgr, + VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, + &(data->vddci_voltage_table)); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve VDDCI table.", + return result); + } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { + result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), + table_info->vdd_dep_on_mclk); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve SVI2 VDDCI table from dependancy table.", + return result); + } + + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { + result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), + table_info->vddc_lookup_table); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve SVI2 VDDC table from lookup table.", + return result); + } + + PP_ASSERT_WITH_CODE( + (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)), + "Too many voltage values for VDDC. Trimming to fit state table.", + phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC, + &(data->vddc_voltage_table))); + + PP_ASSERT_WITH_CODE( + (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)), + "Too many voltage values for VDDCI. Trimming to fit state table.", + phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI, + &(data->vddci_voltage_table))); + + PP_ASSERT_WITH_CODE( + (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)), + "Too many voltage values for MVDD. Trimming to fit state table.", + phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD, + &(data->mvdd_voltage_table))); + + return 0; +} + +/** +* Programs static screed detection parameters +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_program_static_screen_threshold_parameters( + struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* Set static screen threshold unit */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, + data->static_screen_threshold_unit); + /* Set static screen threshold */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, + data->static_screen_threshold); + + return 0; +} + +/** +* Setup display gap for glitch free memory clock switching. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr) +{ + uint32_t display_gap = + cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_DISPLAY_GAP_CNTL); + + display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, + DISP_GAP, DISPLAY_GAP_IGNORE); + + display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, + DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_DISPLAY_GAP_CNTL, display_gap); + + return 0; +} + +/** +* Programs activity state transition voting clients +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* Clear reset for voting clients before enabling DPM */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); + + return 0; +} + +/** +* Get the location of various tables inside the FW image. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + uint32_t tmp; + int result; + bool error = false; + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, DpmTable), + &tmp, data->sram_end); + + if (0 == result) + data->dpm_table_start = tmp; + + error |= (0 != result); + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, SoftRegisters), + &tmp, data->sram_end); + + if (!result) { + data->soft_regs_start = tmp; + smu_data->soft_regs_start = tmp; + } + + error |= (0 != result); + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, mcRegisterTable), + &tmp, data->sram_end); + + if (!result) + data->mc_reg_table_start = tmp; + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, FanTable), + &tmp, data->sram_end); + + if (!result) + data->fan_table_start = tmp; + + error |= (0 != result); + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, mcArbDramTimingTable), + &tmp, data->sram_end); + + if (!result) + data->arb_table_start = tmp; + + error |= (0 != result); + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, Version), + &tmp, data->sram_end); + + if (!result) + hwmgr->microcode_version_info.SMC = tmp; + + error |= (0 != result); + + return error ? -1 : 0; +} + +/* Copy one arb setting to another and then switch the active set. + * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. + */ +static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, + uint32_t arb_src, uint32_t arb_dest) +{ + uint32_t mc_arb_dram_timing; + uint32_t mc_arb_dram_timing2; + uint32_t burst_time; + uint32_t mc_cg_config; + + switch (arb_src) { + case MC_CG_ARB_FREQ_F0: + mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); + mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); + burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); + break; + case MC_CG_ARB_FREQ_F1: + mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); + mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); + burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); + break; + default: + return -EINVAL; + } + + switch (arb_dest) { + case MC_CG_ARB_FREQ_F0: + cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); + cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); + PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); + break; + case MC_CG_ARB_FREQ_F1: + cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); + cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); + PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); + break; + default: + return -EINVAL; + } + + mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); + mc_cg_config |= 0x0000000F; + cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); + PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); + + return 0; +} + +/** +* Initial switch from ARB F0->F1 +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +* This function is to be called from the SetPowerState table. +*/ +static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) +{ + return polaris10_copy_and_switch_arb_sets(hwmgr, + MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); +} + +static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; + uint32_t i, max_entry; + + PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || + data->use_pcie_power_saving_levels), "No pcie performance levels!", + return -EINVAL); + + if (data->use_pcie_performance_levels && + !data->use_pcie_power_saving_levels) { + data->pcie_gen_power_saving = data->pcie_gen_performance; + data->pcie_lane_power_saving = data->pcie_lane_performance; + } else if (!data->use_pcie_performance_levels && + data->use_pcie_power_saving_levels) { + data->pcie_gen_performance = data->pcie_gen_power_saving; + data->pcie_lane_performance = data->pcie_lane_power_saving; + } + + phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, + SMU74_MAX_LEVELS_LINK, + MAX_REGULAR_DPM_NUMBER); + + if (pcie_table != NULL) { + /* max_entry is used to make sure we reserve one PCIE level + * for boot level (fix for A+A PSPP issue). + * If PCIE table from PPTable have ULV entry + 8 entries, + * then ignore the last entry.*/ + max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ? + SMU74_MAX_LEVELS_LINK : pcie_table->count; + for (i = 1; i < max_entry; i++) { + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, + get_pcie_gen_support(data->pcie_gen_cap, + pcie_table->entries[i].gen_speed), + get_pcie_lane_support(data->pcie_lane_cap, + pcie_table->entries[i].lane_width)); + } + data->dpm_table.pcie_speed_table.count = max_entry - 1; + + /* Setup BIF_SCLK levels */ + for (i = 0; i < max_entry; i++) + data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk; + } else { + /* Hardcode Pcie Table */ + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Min_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Min_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + + data->dpm_table.pcie_speed_table.count = 6; + } + /* Populate last level for boot PCIE level, but do not increment count. */ + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, + data->dpm_table.pcie_speed_table.count, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Min_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + + return 0; +} + +/* + * This function is to initalize all DPM state tables + * for SMU7 based on the dependency table. + * Dynamic state patching function will then trim these + * state tables to the allowed range based + * on the power policy or external client requests, + * such as UVD request, etc. + */ +int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint32_t i; + + struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = + table_info->vdd_dep_on_sclk; + struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = + table_info->vdd_dep_on_mclk; + + PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, + "SCLK dependency table is missing. This table is mandatory", + return -EINVAL); + PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, + "SCLK dependency table has to have is missing." + "This table is mandatory", + return -EINVAL); + + PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, + "MCLK dependency table is missing. This table is mandatory", + return -EINVAL); + PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, + "MCLK dependency table has to have is missing." + "This table is mandatory", + return -EINVAL); + + /* clear the state table to reset everything to default */ + phm_reset_single_dpm_table( + &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER); + phm_reset_single_dpm_table( + &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER); + + + /* Initialize Sclk DPM table based on allow Sclk values */ + data->dpm_table.sclk_table.count = 0; + for (i = 0; i < dep_sclk_table->count; i++) { + if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != + dep_sclk_table->entries[i].clk) { + + data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = + dep_sclk_table->entries[i].clk; + + data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = + (i == 0) ? true : false; + data->dpm_table.sclk_table.count++; + } + } + + /* Initialize Mclk DPM table based on allow Mclk values */ + data->dpm_table.mclk_table.count = 0; + for (i = 0; i < dep_mclk_table->count; i++) { + if (i == 0 || data->dpm_table.mclk_table.dpm_levels + [data->dpm_table.mclk_table.count - 1].value != + dep_mclk_table->entries[i].clk) { + data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = + dep_mclk_table->entries[i].clk; + data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = + (i == 0) ? true : false; + data->dpm_table.mclk_table.count++; + } + } + + /* setup PCIE gen speed levels */ + polaris10_setup_default_pcie_table(hwmgr); + + /* save a copy of the default DPM table */ + memcpy(&(data->golden_dpm_table), &(data->dpm_table), + sizeof(struct polaris10_dpm_table)); + + return 0; +} + +uint8_t convert_to_vid(uint16_t vddc) +{ + return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); +} + +/** + * Mvdd table preparation for SMC. + * + * @param *hwmgr The address of the hardware manager. + * @param *table The SMC DPM table structure to be populated. + * @return 0 + */ +static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t count, level; + + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + count = data->mvdd_voltage_table.count; + if (count > SMU_MAX_SMIO_LEVELS) + count = SMU_MAX_SMIO_LEVELS; + for (level = 0; level < count; level++) { + table->SmioTable2.Pattern[level].Voltage = + PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); + /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ + table->SmioTable2.Pattern[level].Smio = + (uint8_t) level; + table->Smio[level] |= + data->mvdd_voltage_table.entries[level].smio_low; + } + table->SmioMask2 = data->vddci_voltage_table.mask_low; + + table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); + } + + return 0; +} + +static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + uint32_t count, level; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + count = data->vddci_voltage_table.count; + + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + if (count > SMU_MAX_SMIO_LEVELS) + count = SMU_MAX_SMIO_LEVELS; + for (level = 0; level < count; ++level) { + table->SmioTable1.Pattern[level].Voltage = + PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE); + table->SmioTable1.Pattern[level].Smio = (uint8_t) level; + + table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low; + } + } + + table->SmioMask1 = data->vddci_voltage_table.mask_low; + + return 0; +} + +/** +* Preparation of vddc and vddgfx CAC tables for SMC. +* +* @param hwmgr the address of the hardware manager +* @param table the SMC DPM table structure to be populated +* @return always 0 +*/ +static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + uint32_t count; + uint8_t index; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_voltage_lookup_table *lookup_table = + table_info->vddc_lookup_table; + /* tables is already swapped, so in order to use the value from it, + * we need to swap it back. + * We are populating vddc CAC data to BapmVddc table + * in split and merged mode + */ + for (count = 0; count < lookup_table->count; count++) { + index = phm_get_voltage_index(lookup_table, + data->vddc_voltage_table.entries[count].value); + table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low); + table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid); + table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high); + } + + return 0; +} + +/** +* Preparation of voltage tables for SMC. +* +* @param hwmgr the address of the hardware manager +* @param table the SMC DPM table structure to be populated +* @return always 0 +*/ + +int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + polaris10_populate_smc_vddci_table(hwmgr, table); + polaris10_populate_smc_mvdd_table(hwmgr, table); + polaris10_populate_cac_table(hwmgr, table); + + return 0; +} + +static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_Ulv *state) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + state->CcPwrDynRm = 0; + state->CcPwrDynRm1 = 0; + + state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset; + state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * + VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); + + state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; + + CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); + CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); + + return 0; +} + +static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + return polaris10_populate_ulv_level(hwmgr, &table->Ulv); +} + +static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + int i; + + /* Index (dpm_table->pcie_speed_table.count) + * is reserved for PCIE boot level. */ + for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { + table->LinkLevel[i].PcieGenSpeed = + (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; + table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( + dpm_table->pcie_speed_table.dpm_levels[i].param1); + table->LinkLevel[i].EnabledForActivity = 1; + table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); + table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); + table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); + } + + data->smc_state_table.LinkLevelCount = + (uint8_t)dpm_table->pcie_speed_table.count; + data->dpm_level_enable_mask.pcie_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); + + return 0; +} + +static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr) +{ + uint32_t reference_clock, tmp; + struct cgs_display_info info = {0}; + struct cgs_mode_info mode_info; + + info.mode_info = &mode_info; + + tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK); + + if (tmp) + return TCLK; + + cgs_get_active_displays_info(hwmgr->device, &info); + reference_clock = mode_info.ref_clock; + + tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); + + if (0 != tmp) + return reference_clock / 4; + + return reference_clock; +} + +/** +* Calculates the SCLK dividers using the provided engine clock +* +* @param hwmgr the address of the hardware manager +* @param clock the engine clock to use to populate the structure +* @param sclk the SMC SCLK structure to be populated +*/ +static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, + uint32_t clock, SMU_SclkSetting *sclk_setting) +{ + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const SMU74_Discrete_DpmTable *table = &(data->smc_state_table); + struct pp_atomctrl_clock_dividers_ai dividers; + + uint32_t ref_clock; + uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq; + uint8_t i; + int result; + uint64_t temp; + + sclk_setting->SclkFrequency = clock; + /* get the engine clock dividers for this clock value */ + result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); + if (result == 0) { + sclk_setting->Fcw_int = dividers.usSclk_fcw_int; + sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; + sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; + sclk_setting->PllRange = dividers.ucSclkPllRange; + sclk_setting->Sclk_slew_rate = 0x400; + sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; + sclk_setting->Pcc_down_slew_rate = 0xffff; + sclk_setting->SSc_En = dividers.ucSscEnable; + sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; + sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; + sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac; + return result; + } + + ref_clock = polaris10_get_xclk(hwmgr); + + for (i = 0; i < NUM_SCLK_RANGE; i++) { + if (clock > data->range_table[i].trans_lower_frequency + && clock <= data->range_table[i].trans_upper_frequency) { + sclk_setting->PllRange = i; + break; + } + } + + sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); + temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; + temp <<= 0x10; + do_div(temp, ref_clock); + sclk_setting->Fcw_frac = temp & 0xffff; + + pcc_target_percent = 10; /* Hardcode 10% for now. */ + pcc_target_freq = clock - (clock * pcc_target_percent / 100); + sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); + + ss_target_percent = 2; /* Hardcode 2% for now. */ + sclk_setting->SSc_En = 0; + if (ss_target_percent) { + sclk_setting->SSc_En = 1; + ss_target_freq = clock - (clock * ss_target_percent / 100); + sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); + temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; + temp <<= 0x10; + do_div(temp, ref_clock); + sclk_setting->Fcw1_frac = temp & 0xffff; + } + + return 0; +} + +static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, + struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, + uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) +{ + uint32_t i; + uint16_t vddci; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + *voltage = *mvdd = 0; + + /* clock - voltage dependency table is empty table */ + if (dep_table->count == 0) + return -EINVAL; + + for (i = 0; i < dep_table->count; i++) { + /* find first sclk bigger than request */ + if (dep_table->entries[i].clk >= clock) { + *voltage |= (dep_table->entries[i].vddc * + VOLTAGE_SCALE) << VDDC_SHIFT; + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control) + *voltage |= (data->vbios_boot_state.vddci_bootup_value * + VOLTAGE_SCALE) << VDDCI_SHIFT; + else if (dep_table->entries[i].vddci) + *voltage |= (dep_table->entries[i].vddci * + VOLTAGE_SCALE) << VDDCI_SHIFT; + else { + vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), + (dep_table->entries[i].vddc - + (uint16_t)data->vddc_vddci_delta)); + *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; + } + + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) + *mvdd = data->vbios_boot_state.mvdd_bootup_value * + VOLTAGE_SCALE; + else if (dep_table->entries[i].mvdd) + *mvdd = (uint32_t) dep_table->entries[i].mvdd * + VOLTAGE_SCALE; + + *voltage |= 1 << PHASES_SHIFT; + return 0; + } + } + + /* sclk is bigger than max sclk in the dependence table */ + *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; + + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control) + *voltage |= (data->vbios_boot_state.vddci_bootup_value * + VOLTAGE_SCALE) << VDDCI_SHIFT; + else if (dep_table->entries[i-1].vddci) { + vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), + (dep_table->entries[i].vddc - + (uint16_t)data->vddc_vddci_delta)); + *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; + } + + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) + *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE; + else if (dep_table->entries[i].mvdd) + *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; + + return 0; +} + +static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = +{ {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112}, + {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160}, + {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112}, + {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160}, + {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112}, + {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160}, + {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108}, + {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} }; + +static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr) +{ + uint32_t i, ref_clk; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + SMU74_Discrete_DpmTable *table = &(data->smc_state_table); + struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; + + ref_clk = polaris10_get_xclk(hwmgr); + + if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { + for (i = 0; i < NUM_SCLK_RANGE; i++) { + table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting; + table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; + table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc; + + table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper; + table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower; + + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); + } + return; + } + + for (i = 0; i < NUM_SCLK_RANGE; i++) { + + data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; + data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; + + table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting; + table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; + table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc; + + table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper; + table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower; + + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); + } +} + +/** +* Populates single SMC SCLK structure using the provided engine clock +* +* @param hwmgr the address of the hardware manager +* @param clock the engine clock to use to populate the structure +* @param sclk the SMC SCLK structure to be populated +*/ + +static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, + uint32_t clock, uint16_t sclk_al_threshold, + struct SMU74_Discrete_GraphicsLevel *level) +{ + int result, i, temp; + /* PP_Clocks minClocks; */ + uint32_t mvdd; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + SMU_SclkSetting curr_sclk_setting = { 0 }; + + result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting); + + /* populate graphics levels */ + result = polaris10_get_dependency_volt_by_clk(hwmgr, + table_info->vdd_dep_on_sclk, clock, + &level->MinVoltage, &mvdd); + + PP_ASSERT_WITH_CODE((0 == result), + "can not find VDDC voltage value for " + "VDDC engine clock dependency table", + return result); + level->ActivityLevel = sclk_al_threshold; + + level->CcPwrDynRm = 0; + level->CcPwrDynRm1 = 0; + level->EnabledForActivity = 0; + level->EnabledForThrottle = 1; + level->UpHyst = 10; + level->DownHyst = 0; + level->VoltageDownHyst = 0; + level->PowerThrottle = 0; + + /* + * TODO: get minimum clocks from dal configaration + * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks); + */ + /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */ + + /* get level->DeepSleepDivId + if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) + level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR); + */ + PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0); + for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { + temp = clock >> i; + + if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0) + break; + } + + level->DeepSleepDivId = i; + + /* Default to slow, highest DPM level will be + * set to PPSMC_DISPLAY_WATERMARK_LOW later. + */ + if (data->update_up_hyst) + level->UpHyst = (uint8_t)data->up_hyst; + if (data->update_down_hyst) + level->DownHyst = (uint8_t)data->down_hyst; + + level->SclkSetting = curr_sclk_setting; + + CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage); + CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1); + CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel); + CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate); + return 0; +} + +/** +* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states +* +* @param hwmgr the address of the hardware manager +*/ +static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; + uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count; + int result = 0; + uint32_t array = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); + uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) * + SMU74_MAX_LEVELS_GRAPHICS; + struct SMU74_Discrete_GraphicsLevel *levels = + data->smc_state_table.GraphicsLevel; + uint32_t i, max_entry; + uint8_t hightest_pcie_level_enabled = 0, + lowest_pcie_level_enabled = 0, + mid_pcie_level_enabled = 0, + count = 0; + + polaris10_get_sclk_range_table(hwmgr); + + for (i = 0; i < dpm_table->sclk_table.count; i++) { + + result = polaris10_populate_single_graphic_level(hwmgr, + dpm_table->sclk_table.dpm_levels[i].value, + (uint16_t)data->activity_target[i], + &(data->smc_state_table.GraphicsLevel[i])); + if (result) + return result; + + /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ + if (i > 1) + levels[i].DeepSleepDivId = 0; + } + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SPLLShutdownSupport)) + data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; + + data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; + data->smc_state_table.GraphicsDpmLevelCount = + (uint8_t)dpm_table->sclk_table.count; + data->dpm_level_enable_mask.sclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); + + + if (pcie_table != NULL) { + PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), + "There must be 1 or more PCIE levels defined in PPTable.", + return -EINVAL); + max_entry = pcie_entry_cnt - 1; + for (i = 0; i < dpm_table->sclk_table.count; i++) + levels[i].pcieDpmLevel = + (uint8_t) ((i < max_entry) ? i : max_entry); + } else { + while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && + ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & + (1 << (hightest_pcie_level_enabled + 1))) != 0)) + hightest_pcie_level_enabled++; + + while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && + ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & + (1 << lowest_pcie_level_enabled)) == 0)) + lowest_pcie_level_enabled++; + + while ((count < hightest_pcie_level_enabled) && + ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & + (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) + count++; + + mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) < + hightest_pcie_level_enabled ? + (lowest_pcie_level_enabled + 1 + count) : + hightest_pcie_level_enabled; + + /* set pcieDpmLevel to hightest_pcie_level_enabled */ + for (i = 2; i < dpm_table->sclk_table.count; i++) + levels[i].pcieDpmLevel = hightest_pcie_level_enabled; + + /* set pcieDpmLevel to lowest_pcie_level_enabled */ + levels[0].pcieDpmLevel = lowest_pcie_level_enabled; + + /* set pcieDpmLevel to mid_pcie_level_enabled */ + levels[1].pcieDpmLevel = mid_pcie_level_enabled; + } + /* level count will send to smc once at init smc table and never change */ + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + (uint32_t)array_size, data->sram_end); + + return result; +} + +static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr, + uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + int result = 0; + struct cgs_display_info info = {0, 0, NULL}; + + cgs_get_active_displays_info(hwmgr->device, &info); + + if (table_info->vdd_dep_on_mclk) { + result = polaris10_get_dependency_volt_by_clk(hwmgr, + table_info->vdd_dep_on_mclk, clock, + &mem_level->MinVoltage, &mem_level->MinMvdd); + PP_ASSERT_WITH_CODE((0 == result), + "can not find MinVddc voltage value from memory " + "VDDC voltage dependency table", return result); + } + + mem_level->MclkFrequency = clock; + mem_level->StutterEnable = 0; + mem_level->EnabledForThrottle = 1; + mem_level->EnabledForActivity = 0; + mem_level->UpHyst = 0; + mem_level->DownHyst = 100; + mem_level->VoltageDownHyst = 0; + mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target; + mem_level->StutterEnable = false; + + mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; + + data->display_timing.num_existing_displays = info.display_count; + + if ((data->mclk_stutter_mode_threshold) && + (clock <= data->mclk_stutter_mode_threshold) && + (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, + STUTTER_ENABLE) & 0x1)) + mem_level->StutterEnable = true; + + if (!result) { + CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd); + CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency); + CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel); + CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage); + } + return result; +} + +/** +* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states +* +* @param hwmgr the address of the hardware manager +*/ +static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + int result; + /* populate MCLK dpm table to SMU7 */ + uint32_t array = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); + uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) * + SMU74_MAX_LEVELS_MEMORY; + struct SMU74_Discrete_MemoryLevel *levels = + data->smc_state_table.MemoryLevel; + uint32_t i; + + for (i = 0; i < dpm_table->mclk_table.count; i++) { + PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), + "can not populate memory level as memory clock is zero", + return -EINVAL); + result = polaris10_populate_single_memory_level(hwmgr, + dpm_table->mclk_table.dpm_levels[i].value, + &levels[i]); + if (i == dpm_table->mclk_table.count - 1) { + levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; + levels[i].EnabledForActivity = 1; + } + if (result) + return result; + } + + /* in order to prevent MC activity from stutter mode to push DPM up. + * the UVD change complements this by putting the MCLK in + * a higher state by default such that we are not effected by + * up threshold or and MCLK DPM latency. + */ + levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target; + CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel); + + data->smc_state_table.MemoryDpmLevelCount = + (uint8_t)dpm_table->mclk_table.count; + data->dpm_level_enable_mask.mclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); + + /* level count will send to smc once at init smc table and never change */ + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + (uint32_t)array_size, data->sram_end); + + return result; +} + +/** +* Populates the SMC MVDD structure using the provided memory clock. +* +* @param hwmgr the address of the hardware manager +* @param mclk the MCLK value to be used in the decision if MVDD should be high or low. +* @param voltage the SMC VOLTAGE structure to be populated +*/ +int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr, + uint32_t mclk, SMIO_Pattern *smio_pat) +{ + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint32_t i = 0; + + if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) { + /* find mvdd value which clock is more than request */ + for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { + if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { + smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value; + break; + } + } + PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, + "MVDD Voltage is outside the supported range.", + return -EINVAL); + } else + return -EINVAL; + + return 0; +} + +static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) +{ + int result = 0; + uint32_t sclk_frequency; + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + SMIO_Pattern vol_level; + uint32_t mvdd; + uint16_t us_mvdd; + + table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; + + if (!data->sclk_dpm_key_disabled) { + /* Get MinVoltage and Frequency from DPM0, + * already converted to SMC_UL */ + sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value; + result = polaris10_get_dependency_volt_by_clk(hwmgr, + table_info->vdd_dep_on_sclk, + table->ACPILevel.SclkFrequency, + &table->ACPILevel.MinVoltage, &mvdd); + PP_ASSERT_WITH_CODE((0 == result), + "Cannot find ACPI VDDC voltage value " + "in Clock Dependency Table", ); + } else { + sclk_frequency = data->vbios_boot_state.sclk_bootup_value; + table->ACPILevel.MinVoltage = + data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE; + } + + result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting)); + PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result); + + table->ACPILevel.DeepSleepDivId = 0; + table->ACPILevel.CcPwrDynRm = 0; + table->ACPILevel.CcPwrDynRm1 = 0; + + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); + + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate); + + if (!data->mclk_dpm_key_disabled) { + /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */ + table->MemoryACPILevel.MclkFrequency = + data->dpm_table.mclk_table.dpm_levels[0].value; + result = polaris10_get_dependency_volt_by_clk(hwmgr, + table_info->vdd_dep_on_mclk, + table->MemoryACPILevel.MclkFrequency, + &table->MemoryACPILevel.MinVoltage, &mvdd); + PP_ASSERT_WITH_CODE((0 == result), + "Cannot find ACPI VDDCI voltage value " + "in Clock Dependency Table", + ); + } else { + table->MemoryACPILevel.MclkFrequency = + data->vbios_boot_state.mclk_bootup_value; + table->MemoryACPILevel.MinVoltage = + data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE; + } + + us_mvdd = 0; + if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) || + (data->mclk_dpm_key_disabled)) + us_mvdd = data->vbios_boot_state.mvdd_bootup_value; + else { + if (!polaris10_populate_mvdd_value(hwmgr, + data->dpm_table.mclk_table.dpm_levels[0].value, + &vol_level)) + us_mvdd = vol_level.Voltage; + } + + if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level)) + table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage); + else + table->MemoryACPILevel.MinMvdd = 0; + + table->MemoryACPILevel.StutterEnable = false; + + table->MemoryACPILevel.EnabledForThrottle = 0; + table->MemoryACPILevel.EnabledForActivity = 0; + table->MemoryACPILevel.UpHyst = 0; + table->MemoryACPILevel.DownHyst = 100; + table->MemoryACPILevel.VoltageDownHyst = 0; + table->MemoryACPILevel.ActivityLevel = + PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); + + CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage); + + return result; +} + +static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = + table_info->mm_dep_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + table->VceLevelCount = (uint8_t)(mm_table->count); + table->VceBootLevel = 0; + + for (count = 0; count < table->VceLevelCount; count++) { + table->VceLevel[count].Frequency = mm_table->entries[count].eclk; + table->VceLevel[count].MinVoltage = 0; + table->VceLevel[count].MinVoltage |= + (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; + table->VceLevel[count].MinVoltage |= + ((mm_table->entries[count].vddc - data->vddc_vddci_delta) * + VOLTAGE_SCALE) << VDDCI_SHIFT; + table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; + + /*retrieve divider value for VBIOS */ + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->VceLevel[count].Frequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for VCE engine clock", + return result); + + table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); + } + return result; +} + +static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = + table_info->mm_dep_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + table->SamuBootLevel = 0; + table->SamuLevelCount = (uint8_t)(mm_table->count); + + for (count = 0; count < table->SamuLevelCount; count++) { + /* not sure whether we need evclk or not */ + table->SamuLevel[count].MinVoltage = 0; + table->SamuLevel[count].Frequency = mm_table->entries[count].samclock; + table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc * + VOLTAGE_SCALE) << VDDC_SHIFT; + table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - + data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; + table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT; + + /* retrieve divider value for VBIOS */ + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->SamuLevel[count].Frequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for samu clock", return result); + + table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage); + } + return result; +} + +static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, + int32_t eng_clock, int32_t mem_clock, + SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs) +{ + uint32_t dram_timing; + uint32_t dram_timing2; + uint32_t burst_time; + int result; + + result = atomctrl_set_engine_dram_timings_rv770(hwmgr, + eng_clock, mem_clock); + PP_ASSERT_WITH_CODE(result == 0, + "Error calling VBIOS to set DRAM_TIMING.", return result); + + dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); + dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); + burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); + + + arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); + arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); + arb_regs->McArbBurstTime = (uint8_t)burst_time; + + return 0; +} + +static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct SMU74_Discrete_MCArbDramTimingTable arb_regs; + uint32_t i, j; + int result = 0; + + for (i = 0; i < data->dpm_table.sclk_table.count; i++) { + for (j = 0; j < data->dpm_table.mclk_table.count; j++) { + result = polaris10_populate_memory_timing_parameters(hwmgr, + data->dpm_table.sclk_table.dpm_levels[i].value, + data->dpm_table.mclk_table.dpm_levels[j].value, + &arb_regs.entries[i][j]); + if (result == 0) + result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j); + if (result != 0) + return result; + } + } + + result = polaris10_copy_bytes_to_smc( + hwmgr->smumgr, + data->arb_table_start, + (uint8_t *)&arb_regs, + sizeof(SMU74_Discrete_MCArbDramTimingTable), + data->sram_end); + return result; +} + +static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = + table_info->mm_dep_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + table->UvdLevelCount = (uint8_t)(mm_table->count); + table->UvdBootLevel = 0; + + for (count = 0; count < table->UvdLevelCount; count++) { + table->UvdLevel[count].MinVoltage = 0; + table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; + table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; + table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * + VOLTAGE_SCALE) << VDDC_SHIFT; + table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - + data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; + table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; + + /* retrieve divider value for VBIOS */ + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->UvdLevel[count].VclkFrequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for Vclk clock", return result); + + table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; + + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->UvdLevel[count].DclkFrequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for Dclk clock", return result); + + table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage); + + } + return result; +} + +static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + int result = 0; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + table->GraphicsBootLevel = 0; + table->MemoryBootLevel = 0; + + /* find boot level from dpm table */ + result = phm_find_boot_level(&(data->dpm_table.sclk_table), + data->vbios_boot_state.sclk_bootup_value, + (uint32_t *)&(table->GraphicsBootLevel)); + + result = phm_find_boot_level(&(data->dpm_table.mclk_table), + data->vbios_boot_state.mclk_bootup_value, + (uint32_t *)&(table->MemoryBootLevel)); + + table->BootVddc = data->vbios_boot_state.vddc_bootup_value * + VOLTAGE_SCALE; + table->BootVddci = data->vbios_boot_state.vddci_bootup_value * + VOLTAGE_SCALE; + table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value * + VOLTAGE_SCALE; + + CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc); + CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci); + CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); + + return 0; +} + + +static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint8_t count, level; + + count = (uint8_t)(table_info->vdd_dep_on_sclk->count); + + for (level = 0; level < count; level++) { + if (table_info->vdd_dep_on_sclk->entries[level].clk >= + data->vbios_boot_state.sclk_bootup_value) { + data->smc_state_table.GraphicsBootLevel = level; + break; + } + } + + count = (uint8_t)(table_info->vdd_dep_on_mclk->count); + for (level = 0; level < count; level++) { + if (table_info->vdd_dep_on_mclk->entries[level].clk >= + data->vbios_boot_state.mclk_bootup_value) { + data->smc_state_table.MemoryBootLevel = level; + break; + } + } + + return 0; +} + +static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) +{ + uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, + volt_with_cks, value; + uint16_t clock_freq_u16; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, + volt_offset = 0; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = + table_info->vdd_dep_on_sclk; + + stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount; + + /* Read SMU_Eefuse to read and calculate RO and determine + * if the part is SS or FF. if RO >= 1660MHz, part is FF. + */ + efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixSMU_EFUSE_0 + (146 * 4)); + efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixSMU_EFUSE_0 + (148 * 4)); + efuse &= 0xFF000000; + efuse = efuse >> 24; + efuse2 &= 0xF; + + if (efuse2 == 1) + ro = (2300 - 1350) * efuse / 255 + 1350; + else + ro = (2500 - 1000) * efuse / 255 + 1000; + + if (ro >= 1660) + type = 0; + else + type = 1; + + /* Populate Stretch amount */ + data->smc_state_table.ClockStretcherAmount = stretch_amount; + + /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ + for (i = 0; i < sclk_table->count; i++) { + data->smc_state_table.Sclk_CKS_masterEn0_7 |= + sclk_table->entries[i].cks_enable << i; + volt_without_cks = (uint32_t)((14041 * + (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 / + (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000))); + volt_with_cks = (uint32_t)((13946 * + (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 / + (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000))); + if (volt_without_cks >= volt_with_cks) + volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + + sclk_table->entries[i].cks_voffset) * 100 / 625) + 1); + data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; + } + + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, + STRETCH_ENABLE, 0x0); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, + masterReset, 0x1); + /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, + masterReset, 0x0); + + /* Populate CKS Lookup Table */ + if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5) + stretch_amount2 = 0; + else if (stretch_amount == 3 || stretch_amount == 4) + stretch_amount2 = 1; + else { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ClockStretcher); + PP_ASSERT_WITH_CODE(false, + "Stretch Amount in PPTable not supported\n", + return -EINVAL); + } + + value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixPWR_CKS_CNTL); + value &= 0xFFC2FF87; + data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = + polaris10_clock_stretcher_lookup_table[stretch_amount2][0]; + data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = + polaris10_clock_stretcher_lookup_table[stretch_amount2][1]; + clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table. + GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100); + if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16 + && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) { + /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */ + value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16; + /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */ + value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18; + /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */ + value |= (polaris10_clock_stretch_amount_conversion + [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]] + [stretch_amount]) << 3; + } + CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq); + CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq); + data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = + polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; + data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= + (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7; + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixPWR_CKS_CNTL, value); + + /* Populate DDT Lookup Table */ + for (i = 0; i < 4; i++) { + /* Assign the minimum and maximum VID stored + * in the last row of Clock Stretcher Voltage Table. + */ + data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID = + (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2]; + data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID = + (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3]; + /* Loop through each SCLK and check the frequency + * to see if it lies within the frequency for clock stretcher. + */ + for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) { + cks_setting = 0; + clock_freq = PP_SMC_TO_HOST_UL( + data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency); + /* Check the allowed frequency against the sclk level[j]. + * Sclk's endianness has already been converted, + * and it's in 10Khz unit, + * as opposed to Data table, which is in Mhz unit. + */ + if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) { + cks_setting |= 0x2; + if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100) + cks_setting |= 0x1; + } + data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting + |= cks_setting << (j * 2); + } + CONVERT_FROM_HOST_TO_SMC_US( + data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting); + } + + value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); + value &= 0xFFFFFFFE; + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); + + return 0; +} + +/** +* Populates the SMC VRConfig field in DPM table. +* +* @param hwmgr the address of the hardware manager +* @param table the SMC DPM table structure to be populated +* @return always 0 +*/ +static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint16_t config; + + config = VR_MERGED_WITH_VDDC; + table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT); + + /* Set Vddc Voltage Controller */ + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { + config = VR_SVI2_PLANE_1; + table->VRConfig |= config; + } else { + PP_ASSERT_WITH_CODE(false, + "VDDC should be on SVI2 control in merged mode!", + ); + } + /* Set Vddci Voltage Controller */ + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { + config = VR_SVI2_PLANE_2; /* only in merged mode */ + table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); + } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + config = VR_SMIO_PATTERN_1; + table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); + } else { + config = VR_STATIC_VOLTAGE; + table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); + } + /* Set Mvdd Voltage Controller */ + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { + config = VR_SVI2_PLANE_2; + table->VRConfig |= (config << VRCONF_MVDD_SHIFT); + } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + config = VR_SMIO_PATTERN_2; + table->VRConfig |= (config << VRCONF_MVDD_SHIFT); + } else { + config = VR_STATIC_VOLTAGE; + table->VRConfig |= (config << VRCONF_MVDD_SHIFT); + } + + return 0; +} + +/** +* Initializes the SMC table and uploads it +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) +{ + int result; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table); + const struct polaris10_ulv_parm *ulv = &(data->ulv); + uint8_t i; + struct pp_atomctrl_gpio_pin_assignment gpio_pin; + pp_atomctrl_clock_dividers_vi dividers; + + result = polaris10_setup_default_dpm_tables(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to setup default DPM tables!", return result); + + if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control) + polaris10_populate_smc_voltage_tables(hwmgr, table); + + table->SystemFlags = 0; + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition)) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StepVddc)) + table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; + + if (data->is_memory_gddr5) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; + + if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) { + result = polaris10_populate_ulv_state(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize ULV state!", return result); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT); + } + + result = polaris10_populate_smc_link_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Link Level!", return result); + + result = polaris10_populate_all_graphic_levels(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Graphics Level!", return result); + + result = polaris10_populate_all_memory_levels(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Memory Level!", return result); + + result = polaris10_populate_smc_acpi_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize ACPI Level!", return result); + + result = polaris10_populate_smc_vce_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize VCE Level!", return result); + + result = polaris10_populate_smc_samu_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize SAMU Level!", return result); + + /* Since only the initial state is completely set up at this point + * (the other states are just copies of the boot state) we only + * need to populate the ARB settings for the initial state. + */ + result = polaris10_program_memory_timing_parameters(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to Write ARB settings for the initial state.", return result); + + result = polaris10_populate_smc_uvd_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize UVD Level!", return result); + + result = polaris10_populate_smc_boot_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Boot Level!", return result); + + result = polaris10_populate_smc_initailial_state(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Boot State!", return result); + + result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to populate BAPM Parameters!", return result); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ClockStretcher)) { + result = polaris10_populate_clock_stretcher_data_table(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to populate Clock Stretcher Data Table!", + return result); + } + + table->GraphicsVoltageChangeEnable = 1; + table->GraphicsThermThrottleEnable = 1; + table->GraphicsInterval = 1; + table->VoltageInterval = 1; + table->ThermalInterval = 1; + table->TemperatureLimitHigh = + table_info->cac_dtp_table->usTargetOperatingTemp * + POLARIS10_Q88_FORMAT_CONVERSION_UNIT; + table->TemperatureLimitLow = + (table_info->cac_dtp_table->usTargetOperatingTemp - 1) * + POLARIS10_Q88_FORMAT_CONVERSION_UNIT; + table->MemoryVoltageChangeEnable = 1; + table->MemoryInterval = 1; + table->VoltageResponseTime = 0; + table->PhaseResponseTime = 0; + table->MemoryThermThrottleEnable = 1; + table->PCIeBootLinkLevel = 0; + table->PCIeGenInterval = 1; + table->VRConfig = 0; + + result = polaris10_populate_vr_config(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to populate VRConfig setting!", return result); + + table->ThermGpio = 17; + table->SclkStepSize = 0x4000; + + if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { + table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; + } else { + table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN; + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_RegulatorHot); + } + + if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, + &gpio_pin)) { + table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift; + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition); + } else { + table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN; + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition); + } + + /* Thermal Output GPIO */ + if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID, + &gpio_pin)) { + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ThermalOutGPIO); + + table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift; + + /* For porlarity read GPIOPAD_A with assigned Gpio pin + * since VBIOS will program this register to set 'inactive state', + * driver can then determine 'active state' from this and + * program SMU with correct polarity + */ + table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) + & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; + table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; + + /* if required, combine VRHot/PCC with thermal out GPIO */ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot) + && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal)) + table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; + } else { + table->ThermOutGpio = 17; + table->ThermOutPolarity = 1; + table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; + } + + /* Populate BIF_SCLK levels into SMC DPM table */ + for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) { + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], ÷rs); + PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result); + + if (i == 0) + table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); + else + table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); + } + + for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++) + table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); + + CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); + CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); + CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); + CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); + CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); + CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); + CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); + CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); + CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); + + /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, + data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, SystemFlags), + (uint8_t *)&(table->SystemFlags), + sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController), + data->sram_end); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to upload dpm data to SMC memory!", return result); + + return 0; +} + +/** +* Initialize the ARB DRAM timing table's index field. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr) +{ + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t tmp; + int result; + + /* This is a read-modify-write on the first byte of the ARB table. + * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure + * is the field 'current'. + * This solution is ugly, but we never write the whole table only + * individual fields in it. + * In reality this field should not be in that structure + * but in a soft register. + */ + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + data->arb_table_start, &tmp, data->sram_end); + + if (result) + return result; + + tmp &= 0x00FFFFFF; + tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; + + return polaris10_write_smc_sram_dword(hwmgr->smumgr, + data->arb_table_start, tmp, data->sram_end); +} + +static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) +{ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_RegulatorHot)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_EnableVRHotGPIOInterrupt); + + return 0; +} + +static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr) +{ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, + SCLK_PWRMGT_OFF, 0); + return 0; +} + +static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_ulv_parm *ulv = &(data->ulv); + + if (ulv->ulv_supported) + return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); + + return 0; +} + +static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) +{ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep)) { + if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON)) + PP_ASSERT_WITH_CODE(false, + "Attempt to enable Master Deep Sleep switch failed!", + return -1); + } else { + if (smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_MASTER_DeepSleep_OFF)) { + PP_ASSERT_WITH_CODE(false, + "Attempt to disable Master Deep Sleep switch failed!", + return -1); + } + } + + return 0; +} + +static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* enable SCLK dpm */ + if (!data->sclk_dpm_key_disabled) + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), + "Failed to enable SCLK DPM during DPM Start Function!", + return -1); + + /* enable MCLK dpm */ + if (0 == data->mclk_dpm_key_disabled) { + + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_Enable)), + "Failed to enable MCLK DPM during DPM Start Function!", + return -1); + + + PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); + udelay(10); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); + } + + return 0; +} + +static int polaris10_start_dpm(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /*enable general power management */ + + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, + GLOBAL_PWRMGT_EN, 1); + + /* enable sclk deep sleep */ + + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, + DYNAMIC_PM_EN, 1); + + /* prepare for PCIE DPM */ + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + data->soft_regs_start + offsetof(SMU74_SoftRegisters, + VoltageChangeTimeout), 0x1000); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, + SWRST_COMMAND_1, RESETLC, 0x0); +/* + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_Voltage_Cntl_Enable)), + "Failed to enable voltage DPM during DPM Start Function!", + return -1); +*/ + + if (polaris10_enable_sclk_mclk_dpm(hwmgr)) { + printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); + return -1; + } + + /* enable PCIE dpm */ + if (0 == data->pcie_dpm_key_disabled) { + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_Enable)), + "Failed to enable pcie DPM during DPM Start Function!", + return -1); + } + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_Falcon_QuickTransition)) { + PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_EnableACDCGPIOInterrupt)), + "Failed to enable AC DC GPIO Interrupt!", + ); + } + + return 0; +} + +static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) +{ + bool protection; + enum DPM_EVENT_SRC src; + + switch (sources) { + default: + printk(KERN_ERR "Unknown throttling event sources."); + /* fall through */ + case 0: + protection = false; + /* src is unused */ + break; + case (1 << PHM_AutoThrottleSource_Thermal): + protection = true; + src = DPM_EVENT_SRC_DIGITAL; + break; + case (1 << PHM_AutoThrottleSource_External): + protection = true; + src = DPM_EVENT_SRC_EXTERNAL; + break; + case (1 << PHM_AutoThrottleSource_External) | + (1 << PHM_AutoThrottleSource_Thermal): + protection = true; + src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; + break; + } + /* Order matters - don't enable thermal protection for the wrong source. */ + if (protection) { + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, + DPM_EVENT_SRC, src); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, + THERMAL_PROTECTION_DIS, + !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ThermalController)); + } else + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, + THERMAL_PROTECTION_DIS, 1); +} + +static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, + PHM_AutoThrottleSource source) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (!(data->active_auto_throttle_sources & (1 << source))) { + data->active_auto_throttle_sources |= 1 << source; + polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); + } + return 0; +} + +static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) +{ + return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); +} + +int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + data->pcie_performance_request = true; + + return 0; +} + +int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) +{ + int tmp_result, result = 0; + tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1; + PP_ASSERT_WITH_CODE(result == 0, + "DPM is already running right now, no need to enable DPM!", + return 0); + + if (polaris10_voltage_control(hwmgr)) { + tmp_result = polaris10_enable_voltage_control(hwmgr); + PP_ASSERT_WITH_CODE(tmp_result == 0, + "Failed to enable voltage control!", + result = tmp_result); + + tmp_result = polaris10_construct_voltage_tables(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to contruct voltage tables!", + result = tmp_result); + } + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EngineSpreadSpectrumSupport)) + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ThermalController)) + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); + + tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to program static screen threshold parameters!", + result = tmp_result); + + tmp_result = polaris10_enable_display_gap(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable display gap!", result = tmp_result); + + tmp_result = polaris10_program_voting_clients(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to program voting clients!", result = tmp_result); + + tmp_result = polaris10_process_firmware_header(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to process firmware header!", result = tmp_result); + + tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to initialize switch from ArbF0 to F1!", + result = tmp_result); + + tmp_result = polaris10_init_smc_table(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to initialize SMC table!", result = tmp_result); + + tmp_result = polaris10_init_arb_table_index(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to initialize ARB table index!", result = tmp_result); + + tmp_result = polaris10_populate_pm_fuses(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to populate PM fuses!", result = tmp_result); + + tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable VR hot GPIO interrupt!", result = tmp_result); + + tmp_result = polaris10_enable_sclk_control(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable SCLK control!", result = tmp_result); + + tmp_result = polaris10_enable_smc_voltage_controller(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable voltage control!", result = tmp_result); + + tmp_result = polaris10_enable_ulv(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable ULV!", result = tmp_result); + + tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable deep sleep master switch!", result = tmp_result); + + tmp_result = polaris10_start_dpm(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to start DPM!", result = tmp_result); + + tmp_result = polaris10_enable_smc_cac(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable SMC CAC!", result = tmp_result); + + tmp_result = polaris10_enable_power_containment(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable power containment!", result = tmp_result); + + tmp_result = polaris10_power_control_set_level(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to power control set level!", result = tmp_result); + + tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable thermal auto throttle!", result = tmp_result); + + tmp_result = polaris10_pcie_performance_request(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "pcie performance request failed!", result = tmp_result); + + return result; +} + +int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) +{ + + return 0; +} + +int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr) +{ + + return 0; +} + +int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->soft_pp_table) { + kfree(data->soft_pp_table); + data->soft_pp_table = NULL; + } + + return phm_hwmgr_backend_fini(hwmgr); +} + +int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicPatchPowerState); + + if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EnableMVDDControl); + + if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ControlVDDCI); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TablelessHardwareInterface); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EnableSMU7ThermalManagement); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicPowerManagement); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UnTabledHardwareInterface); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TablelessHardwareInterface); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SMC); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_NonABMSupportInPPLib); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicUVDState); + + /* power tune caps Assume disabled */ + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SQRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DBRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TDRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TCPRamping); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment); + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_RegulatorHot); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ODFuzzyFanControlSupport); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_FanSpeedInTableIsRPM); + if (hwmgr->chip_id == CHIP_POLARIS11) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SPLLShutdownSupport); + return 0; +} + +static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + polaris10_initialize_power_tune_defaults(hwmgr); + + data->pcie_gen_performance.max = PP_PCIEGen1; + data->pcie_gen_performance.min = PP_PCIEGen3; + data->pcie_gen_power_saving.max = PP_PCIEGen1; + data->pcie_gen_power_saving.min = PP_PCIEGen3; + data->pcie_lane_performance.max = 0; + data->pcie_lane_performance.min = 16; + data->pcie_lane_power_saving.max = 0; + data->pcie_lane_power_saving.min = 16; +} + +/** +* Get Leakage VDDC based on leakage ID. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint16_t vv_id; + uint16_t vddc = 0; + uint16_t i, j; + uint32_t sclk = 0; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)hwmgr->pptable; + struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = + table_info->vdd_dep_on_sclk; + int result; + + for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) { + vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; + if (!phm_get_sclk_for_voltage_evv(hwmgr, + table_info->vddc_lookup_table, vv_id, &sclk)) { + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ClockStretcher)) { + for (j = 1; j < sclk_table->count; j++) { + if (sclk_table->entries[j].clk == sclk && + sclk_table->entries[j].cks_enable == 0) { + sclk += 5000; + break; + } + } + } + + + PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, + VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), + "Error retrieving EVV voltage value!", + continue); + + + /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ + PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), + "Invalid VDDC value", result = -EINVAL;); + + /* the voltage should not be zero nor equal to leakage ID */ + if (vddc != 0 && vddc != vv_id) { + data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100); + data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; + data->vddc_leakage.count++; + } + } + } + + return 0; +} + +/** + * Change virtual leakage voltage to actual value. + * + * @param hwmgr the address of the powerplay hardware manager. + * @param pointer to changing voltage + * @param pointer to leakage table + */ +static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, + uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table) +{ + uint32_t index; + + /* search for leakage voltage ID 0xff01 ~ 0xff08 */ + for (index = 0; index < leakage_table->count; index++) { + /* if this voltage matches a leakage voltage ID */ + /* patch with actual leakage voltage */ + if (leakage_table->leakage_id[index] == *voltage) { + *voltage = leakage_table->actual_voltage[index]; + break; + } + } + + if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) + printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n"); +} + +/** +* Patch voltage lookup table by EVV leakages. +* +* @param hwmgr the address of the powerplay hardware manager. +* @param pointer to voltage lookup table +* @param pointer to leakage table +* @return always 0 +*/ +static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, + phm_ppt_v1_voltage_lookup_table *lookup_table, + struct polaris10_leakage_voltage *leakage_table) +{ + uint32_t i; + + for (i = 0; i < lookup_table->count; i++) + polaris10_patch_with_vdd_leakage(hwmgr, + &lookup_table->entries[i].us_vdd, leakage_table); + + return 0; +} + +static int polaris10_patch_clock_voltage_limits_with_vddc_leakage( + struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table, + uint16_t *vddc) +{ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); + hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = + table_info->max_clock_voltage_on_dc.vddc; + return 0; +} + +static int polaris10_patch_voltage_dependency_tables_with_lookup_table( + struct pp_hwmgr *hwmgr) +{ + uint8_t entryId; + uint8_t voltageId; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = + table_info->vdd_dep_on_sclk; + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = + table_info->vdd_dep_on_mclk; + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = + table_info->mm_dep_table; + + for (entryId = 0; entryId < sclk_table->count; ++entryId) { + voltageId = sclk_table->entries[entryId].vddInd; + sclk_table->entries[entryId].vddc = + table_info->vddc_lookup_table->entries[voltageId].us_vdd; + } + + for (entryId = 0; entryId < mclk_table->count; ++entryId) { + voltageId = mclk_table->entries[entryId].vddInd; + mclk_table->entries[entryId].vddc = + table_info->vddc_lookup_table->entries[voltageId].us_vdd; + } + + for (entryId = 0; entryId < mm_table->count; ++entryId) { + voltageId = mm_table->entries[entryId].vddcInd; + mm_table->entries[entryId].vddc = + table_info->vddc_lookup_table->entries[voltageId].us_vdd; + } + + return 0; + +} + +static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) +{ + /* Need to determine if we need calculated voltage. */ + return 0; +} + +static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) +{ + /* Need to determine if we need calculated voltage from mm table. */ + return 0; +} + +static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr, + struct phm_ppt_v1_voltage_lookup_table *lookup_table) +{ + uint32_t table_size, i, j; + struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; + table_size = lookup_table->count; + + PP_ASSERT_WITH_CODE(0 != lookup_table->count, + "Lookup table is empty", return -EINVAL); + + /* Sorting voltages */ + for (i = 0; i < table_size - 1; i++) { + for (j = i + 1; j > 0; j--) { + if (lookup_table->entries[j].us_vdd < + lookup_table->entries[j - 1].us_vdd) { + tmp_voltage_lookup_record = lookup_table->entries[j - 1]; + lookup_table->entries[j - 1] = lookup_table->entries[j]; + lookup_table->entries[j] = tmp_voltage_lookup_record; + } + } + } + + return 0; +} + +static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr) +{ + int result = 0; + int tmp_result; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr, + table_info->vddc_lookup_table, &(data->vddc_leakage)); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, + &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); + if (tmp_result) + result = tmp_result; + + return result; +} + +static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) +{ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = + table_info->vdd_dep_on_sclk; + struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = + table_info->vdd_dep_on_mclk; + + PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, + "VDD dependency on SCLK table is missing. \ + This table is mandatory", return -EINVAL); + PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, + "VDD dependency on SCLK table has to have is missing. \ + This table is mandatory", return -EINVAL); + + PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, + "VDD dependency on MCLK table is missing. \ + This table is mandatory", return -EINVAL); + PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, + "VDD dependency on MCLK table has to have is missing. \ + This table is mandatory", return -EINVAL); + + table_info->max_clock_voltage_on_ac.sclk = + allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; + table_info->max_clock_voltage_on_ac.mclk = + allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; + table_info->max_clock_voltage_on_ac.vddc = + allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; + table_info->max_clock_voltage_on_ac.vddci = + allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; + + hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; + hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; + hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc; + hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci; + + return 0; +} + +int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; + uint32_t temp_reg; + int result; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + data->dll_default_on = false; + data->sram_end = SMC_RAM_END; + data->mclk_dpm0_activity_target = 0xa; + data->disable_dpm_mask = 0xFF; + data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT; + data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT; + data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT; + + data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0; + data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1; + data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2; + data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3; + data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4; + data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5; + data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6; + data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7; + + data->vddc_vddci_delta = VDDC_VDDCI_DELTA; + + data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT; + + /* need to set voltage control types before EVV patching */ + data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE; + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE; + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE; + + if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) + data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EnableMVDDControl)) { + if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO; + else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; + } + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ControlVDDCI)) { + if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO; + else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; + } + + polaris10_set_features_platform_caps(hwmgr); + + polaris10_init_dpm_defaults(hwmgr); + + /* Get leakage voltage based on leakage ID. */ + result = polaris10_get_evv_voltages(hwmgr); + + if (result) { + printk("Get EVV Voltage Failed. Abort Driver loading!\n"); + return -1; + } + + polaris10_complete_dependency_tables(hwmgr); + polaris10_set_private_data_based_on_pptable(hwmgr); + + /* Initalize Dynamic State Adjustment Rule Settings */ + result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); + + if (0 == result) { + struct cgs_system_info sys_info = {0}; + + data->is_tlu_enabled = 0; + + hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = + POLARIS10_MAX_HARDWARE_POWERLEVELS; + hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; + hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; + + + if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { + temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); + switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { + case 0: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); + break; + case 1: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); + break; + case 2: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); + break; + case 3: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); + break; + case 4: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); + break; + default: + PP_ASSERT_WITH_CODE(0, + "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!", + ); + break; + } + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); + } + + if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 && + hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) { + hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit = + (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; + + hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit = + (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; + + hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1; + + hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100; + + hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit = + (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; + + hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1; + + table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ? + (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0; + + table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp; + table_info->cac_dtp_table->usOperatingTempStep = 1; + table_info->cac_dtp_table->usOperatingTempHyst = 1; + + hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = + hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; + + hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = + hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM; + + hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit = + table_info->cac_dtp_table->usOperatingTempMinLimit; + + hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit = + table_info->cac_dtp_table->usOperatingTempMaxLimit; + + hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = + table_info->cac_dtp_table->usDefaultTargetOperatingTemp; + + hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep = + table_info->cac_dtp_table->usOperatingTempStep; + + hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = + table_info->cac_dtp_table->usTargetOperatingTemp; + } + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; + result = cgs_query_system_info(hwmgr->device, &sys_info); + if (result) + data->pcie_gen_cap = 0x30007; + else + data->pcie_gen_cap = (uint32_t)sys_info.value; + if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) + data->pcie_spc_cap = 20; + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; + result = cgs_query_system_info(hwmgr->device, &sys_info); + if (result) + data->pcie_lane_cap = 0x2f0000; + else + data->pcie_lane_cap = (uint32_t)sys_info.value; + + hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ +/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ + hwmgr->platform_descriptor.clockStep.engineClock = 500; + hwmgr->platform_descriptor.clockStep.memoryClock = 500; + } else { + /* Ignore return value in here, we are cleaning up a mess. */ + polaris10_hwmgr_backend_fini(hwmgr); + } + + return 0; +} + +static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t level, tmp; + + if (!data->pcie_dpm_key_disabled) { + if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { + level = 0; + tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; + while (tmp >>= 1) + level++; + + if (level) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_ForceLevel, level); + } + } + + if (!data->sclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { + level = 0; + tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; + while (tmp >>= 1) + level++; + + if (level) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + (1 << level)); + } + } + + if (!data->mclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { + level = 0; + tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; + while (tmp >>= 1) + level++; + + if (level) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + (1 << level)); + } + } + + return 0; +} + +static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + phm_apply_dal_min_voltage_request(hwmgr); + + if (!data->sclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + data->dpm_level_enable_mask.sclk_dpm_enable_mask); + } + + if (!data->mclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + data->dpm_level_enable_mask.mclk_dpm_enable_mask); + } + + return 0; +} + +static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (!polaris10_is_dpm_running(hwmgr)) + return -EINVAL; + + if (!data->pcie_dpm_key_disabled) { + smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_UnForceLevel); + } + + return polaris10_upload_dpm_level_enable_mask(hwmgr); +} + +static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = + (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t level; + + if (!data->sclk_dpm_key_disabled) + if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { + level = phm_get_lowest_enabled_level(hwmgr, + data->dpm_level_enable_mask.sclk_dpm_enable_mask); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + (1 << level)); + + } + + if (!data->mclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { + level = phm_get_lowest_enabled_level(hwmgr, + data->dpm_level_enable_mask.mclk_dpm_enable_mask); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + (1 << level)); + } + } + + if (!data->pcie_dpm_key_disabled) { + if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { + level = phm_get_lowest_enabled_level(hwmgr, + data->dpm_level_enable_mask.pcie_dpm_enable_mask); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_ForceLevel, + (level)); + } + } + + return 0; + +} +static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr, + enum amd_dpm_forced_level level) +{ + int ret = 0; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_HIGH: + ret = polaris10_force_dpm_highest(hwmgr); + if (ret) + return ret; + break; + case AMD_DPM_FORCED_LEVEL_LOW: + ret = polaris10_force_dpm_lowest(hwmgr); + if (ret) + return ret; + break; + case AMD_DPM_FORCED_LEVEL_AUTO: + ret = polaris10_unforce_dpm_levels(hwmgr); + if (ret) + return ret; + break; + default: + break; + } + + hwmgr->dpm_level = level; + + return ret; +} + +static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr) +{ + return sizeof(struct polaris10_power_state); +} + + +static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + struct pp_power_state *request_ps, + const struct pp_power_state *current_ps) +{ + + struct polaris10_power_state *polaris10_ps = + cast_phw_polaris10_power_state(&request_ps->hardware); + uint32_t sclk; + uint32_t mclk; + struct PP_Clocks minimum_clocks = {0}; + bool disable_mclk_switching; + bool disable_mclk_switching_for_frame_lock; + struct cgs_display_info info = {0}; + const struct phm_clock_and_voltage_limits *max_limits; + uint32_t i; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + int32_t count; + int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; + + data->battery_state = (PP_StateUILabel_Battery == + request_ps->classification.ui_label); + + PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2, + "VI should always have 2 performance levels", + ); + + max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? + &(hwmgr->dyn_state.max_clock_voltage_on_ac) : + &(hwmgr->dyn_state.max_clock_voltage_on_dc); + + /* Cap clock DPM tables at DC MAX if it is in DC. */ + if (PP_PowerSource_DC == hwmgr->power_source) { + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk) + polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk; + if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk) + polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk; + } + } + + polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; + polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; + + cgs_get_active_displays_info(hwmgr->device, &info); + + /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ + + /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */ + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StablePState)) { + max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); + stable_pstate_sclk = (max_limits->sclk * 75) / 100; + + for (count = table_info->vdd_dep_on_sclk->count - 1; + count >= 0; count--) { + if (stable_pstate_sclk >= + table_info->vdd_dep_on_sclk->entries[count].clk) { + stable_pstate_sclk = + table_info->vdd_dep_on_sclk->entries[count].clk; + break; + } + } + + if (count < 0) + stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; + + stable_pstate_mclk = max_limits->mclk; + + minimum_clocks.engineClock = stable_pstate_sclk; + minimum_clocks.memoryClock = stable_pstate_mclk; + } + + if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) + minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; + + if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) + minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; + + polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; + + if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { + PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= + hwmgr->platform_descriptor.overdriveLimit.engineClock), + "Overdrive sclk exceeds limit", + hwmgr->gfx_arbiter.sclk_over_drive = + hwmgr->platform_descriptor.overdriveLimit.engineClock); + + if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) + polaris10_ps->performance_levels[1].engine_clock = + hwmgr->gfx_arbiter.sclk_over_drive; + } + + if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { + PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= + hwmgr->platform_descriptor.overdriveLimit.memoryClock), + "Overdrive mclk exceeds limit", + hwmgr->gfx_arbiter.mclk_over_drive = + hwmgr->platform_descriptor.overdriveLimit.memoryClock); + + if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) + polaris10_ps->performance_levels[1].memory_clock = + hwmgr->gfx_arbiter.mclk_over_drive; + } + + disable_mclk_switching_for_frame_lock = phm_cap_enabled( + hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); + + disable_mclk_switching = (1 < info.display_count) || + disable_mclk_switching_for_frame_lock; + + sclk = polaris10_ps->performance_levels[0].engine_clock; + mclk = polaris10_ps->performance_levels[0].memory_clock; + + if (disable_mclk_switching) + mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; + + if (sclk < minimum_clocks.engineClock) + sclk = (minimum_clocks.engineClock > max_limits->sclk) ? + max_limits->sclk : minimum_clocks.engineClock; + + if (mclk < minimum_clocks.memoryClock) + mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? + max_limits->mclk : minimum_clocks.memoryClock; + + polaris10_ps->performance_levels[0].engine_clock = sclk; + polaris10_ps->performance_levels[0].memory_clock = mclk; + + polaris10_ps->performance_levels[1].engine_clock = + (polaris10_ps->performance_levels[1].engine_clock >= + polaris10_ps->performance_levels[0].engine_clock) ? + polaris10_ps->performance_levels[1].engine_clock : + polaris10_ps->performance_levels[0].engine_clock; + + if (disable_mclk_switching) { + if (mclk < polaris10_ps->performance_levels[1].memory_clock) + mclk = polaris10_ps->performance_levels[1].memory_clock; + + polaris10_ps->performance_levels[0].memory_clock = mclk; + polaris10_ps->performance_levels[1].memory_clock = mclk; + } else { + if (polaris10_ps->performance_levels[1].memory_clock < + polaris10_ps->performance_levels[0].memory_clock) + polaris10_ps->performance_levels[1].memory_clock = + polaris10_ps->performance_levels[0].memory_clock; + } + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StablePState)) { + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk; + polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk; + polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; + polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; + } + } + return 0; +} + + +static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +{ + struct pp_power_state *ps; + struct polaris10_power_state *polaris10_ps; + + if (hwmgr == NULL) + return -EINVAL; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware); + + if (low) + return polaris10_ps->performance_levels[0].memory_clock; + else + return polaris10_ps->performance_levels + [polaris10_ps->performance_level_count-1].memory_clock; +} + +static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +{ + struct pp_power_state *ps; + struct polaris10_power_state *polaris10_ps; + + if (hwmgr == NULL) + return -EINVAL; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware); + + if (low) + return polaris10_ps->performance_levels[0].engine_clock; + else + return polaris10_ps->performance_levels + [polaris10_ps->performance_level_count-1].engine_clock; +} + +static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, + struct pp_hw_power_state *hw_ps) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps; + ATOM_FIRMWARE_INFO_V2_2 *fw_info; + uint16_t size; + uint8_t frev, crev; + int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); + + /* First retrieve the Boot clocks and VDDC from the firmware info table. + * We assume here that fw_info is unchanged if this call fails. + */ + fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( + hwmgr->device, index, + &size, &frev, &crev); + if (!fw_info) + /* During a test, there is no firmware info table. */ + return 0; + + /* Patch the state. */ + data->vbios_boot_state.sclk_bootup_value = + le32_to_cpu(fw_info->ulDefaultEngineClock); + data->vbios_boot_state.mclk_bootup_value = + le32_to_cpu(fw_info->ulDefaultMemoryClock); + data->vbios_boot_state.mvdd_bootup_value = + le16_to_cpu(fw_info->usBootUpMVDDCVoltage); + data->vbios_boot_state.vddc_bootup_value = + le16_to_cpu(fw_info->usBootUpVDDCVoltage); + data->vbios_boot_state.vddci_bootup_value = + le16_to_cpu(fw_info->usBootUpVDDCIVoltage); + data->vbios_boot_state.pcie_gen_bootup_value = + phm_get_current_pcie_speed(hwmgr); + + data->vbios_boot_state.pcie_lane_bootup_value = + (uint16_t)phm_get_current_pcie_lane_number(hwmgr); + + /* set boot power state */ + ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; + ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; + ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; + ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; + + return 0; +} + +static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, + void *state, struct pp_power_state *power_state, + void *pp_table, uint32_t classification_flag) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_power_state *polaris10_power_state = + (struct polaris10_power_state *)(&(power_state->hardware)); + struct polaris10_performance_level *performance_level; + ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; + ATOM_Tonga_POWERPLAYTABLE *powerplay_table = + (ATOM_Tonga_POWERPLAYTABLE *)pp_table; + ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = + (ATOM_Tonga_SCLK_Dependency_Table *) + (((unsigned long)powerplay_table) + + le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); + ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = + (ATOM_Tonga_MCLK_Dependency_Table *) + (((unsigned long)powerplay_table) + + le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); + + /* The following fields are not initialized here: id orderedList allStatesList */ + power_state->classification.ui_label = + (le16_to_cpu(state_entry->usClassification) & + ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> + ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; + power_state->classification.flags = classification_flag; + /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ + + power_state->classification.temporary_state = false; + power_state->classification.to_be_deleted = false; + + power_state->validation.disallowOnDC = + (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & + ATOM_Tonga_DISALLOW_ON_DC)); + + power_state->pcie.lanes = 0; + + power_state->display.disableFrameModulation = false; + power_state->display.limitRefreshrate = false; + power_state->display.enableVariBright = + (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & + ATOM_Tonga_ENABLE_VARIBRIGHT)); + + power_state->validation.supportedPowerLevels = 0; + power_state->uvd_clocks.VCLK = 0; + power_state->uvd_clocks.DCLK = 0; + power_state->temperatures.min = 0; + power_state->temperatures.max = 0; + + performance_level = &(polaris10_power_state->performance_levels + [polaris10_power_state->performance_level_count++]); + + PP_ASSERT_WITH_CODE( + (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS), + "Performance levels exceeds SMC limit!", + return -1); + + PP_ASSERT_WITH_CODE( + (polaris10_power_state->performance_level_count <= + hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), + "Performance levels exceeds Driver limit!", + return -1); + + /* Performance levels are arranged from low to high. */ + performance_level->memory_clock = mclk_dep_table->entries + [state_entry->ucMemoryClockIndexLow].ulMclk; + performance_level->engine_clock = sclk_dep_table->entries + [state_entry->ucEngineClockIndexLow].ulSclk; + performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, + state_entry->ucPCIEGenLow); + performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, + state_entry->ucPCIELaneHigh); + + performance_level = &(polaris10_power_state->performance_levels + [polaris10_power_state->performance_level_count++]); + performance_level->memory_clock = mclk_dep_table->entries + [state_entry->ucMemoryClockIndexHigh].ulMclk; + performance_level->engine_clock = sclk_dep_table->entries + [state_entry->ucEngineClockIndexHigh].ulSclk; + performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, + state_entry->ucPCIEGenHigh); + performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, + state_entry->ucPCIELaneHigh); + + return 0; +} + +static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr, + unsigned long entry_index, struct pp_power_state *state) +{ + int result; + struct polaris10_power_state *ps; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = + table_info->vdd_dep_on_mclk; + + state->hardware.magic = PHM_VIslands_Magic; + + ps = (struct polaris10_power_state *)(&state->hardware); + + result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state, + polaris10_get_pp_table_entry_callback_func); + + /* This is the earliest time we have all the dependency table and the VBIOS boot state + * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state + * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state + */ + if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { + if (dep_mclk_table->entries[0].clk != + data->vbios_boot_state.mclk_bootup_value) + printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " + "does not match VBIOS boot MCLK level"); + if (dep_mclk_table->entries[0].vddci != + data->vbios_boot_state.vddci_bootup_value) + printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " + "does not match VBIOS boot VDDCI level"); + } + + /* set DC compatible flag if this state supports DC */ + if (!state->validation.disallowOnDC) + ps->dc_compatible = true; + + if (state->classification.flags & PP_StateClassificationFlag_ACPI) + data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; + + ps->uvd_clks.vclk = state->uvd_clocks.VCLK; + ps->uvd_clks.dclk = state->uvd_clocks.DCLK; + + if (!result) { + uint32_t i; + + switch (state->classification.ui_label) { + case PP_StateUILabel_Performance: + data->use_pcie_performance_levels = true; + + for (i = 0; i < ps->performance_level_count; i++) { + if (data->pcie_gen_performance.max < + ps->performance_levels[i].pcie_gen) + data->pcie_gen_performance.max = + ps->performance_levels[i].pcie_gen; + + if (data->pcie_gen_performance.min > + ps->performance_levels[i].pcie_gen) + data->pcie_gen_performance.min = + ps->performance_levels[i].pcie_gen; + + if (data->pcie_lane_performance.max < + ps->performance_levels[i].pcie_lane) + data->pcie_lane_performance.max = + ps->performance_levels[i].pcie_lane; + + if (data->pcie_lane_performance.min > + ps->performance_levels[i].pcie_lane) + data->pcie_lane_performance.min = + ps->performance_levels[i].pcie_lane; + } + break; + case PP_StateUILabel_Battery: + data->use_pcie_power_saving_levels = true; + + for (i = 0; i < ps->performance_level_count; i++) { + if (data->pcie_gen_power_saving.max < + ps->performance_levels[i].pcie_gen) + data->pcie_gen_power_saving.max = + ps->performance_levels[i].pcie_gen; + + if (data->pcie_gen_power_saving.min > + ps->performance_levels[i].pcie_gen) + data->pcie_gen_power_saving.min = + ps->performance_levels[i].pcie_gen; + + if (data->pcie_lane_power_saving.max < + ps->performance_levels[i].pcie_lane) + data->pcie_lane_power_saving.max = + ps->performance_levels[i].pcie_lane; + + if (data->pcie_lane_power_saving.min > + ps->performance_levels[i].pcie_lane) + data->pcie_lane_power_saving.min = + ps->performance_levels[i].pcie_lane; + } + break; + default: + break; + } + } + return 0; +} + +static void +polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) +{ + uint32_t sclk, mclk, activity_percent; + uint32_t offset; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); + + sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); + + mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", + mclk / 100, sclk / 100); + + offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity); + activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); + activity_percent += 0x80; + activity_percent >>= 8; + + seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent); + + seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en"); + + seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en"); +} + +static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) +{ + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); + uint32_t sclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].engine_clock; + struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + uint32_t mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; + struct PP_Clocks min_clocks = {0}; + uint32_t i; + struct cgs_display_info info = {0}; + + data->need_update_smu7_dpm_table = 0; + + for (i = 0; i < sclk_table->count; i++) { + if (sclk == sclk_table->dpm_levels[i].value) + break; + } + + if (i >= sclk_table->count) + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; + else { + /* TODO: Check SCLK in DAL's minimum clocks + * in case DeepSleep divider update is required. + */ + if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && + (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK || + data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK)) + data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; + } + + for (i = 0; i < mclk_table->count; i++) { + if (mclk == mclk_table->dpm_levels[i].value) + break; + } + + if (i >= mclk_table->count) + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; + + cgs_get_active_displays_info(hwmgr->device, &info); + + if (data->display_timing.num_existing_displays != info.display_count) + data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; + + return 0; +} + +static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr, + const struct polaris10_power_state *polaris10_ps) +{ + uint32_t i; + uint32_t sclk, max_sclk = 0; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + sclk = polaris10_ps->performance_levels[i].engine_clock; + if (max_sclk < sclk) + max_sclk = sclk; + } + + for (i = 0; i < dpm_table->sclk_table.count; i++) { + if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) + return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? + dpm_table->pcie_speed_table.dpm_levels + [dpm_table->pcie_speed_table.count - 1].value : + dpm_table->pcie_speed_table.dpm_levels[i].value); + } + + return 0; +} + +static int polaris10_request_link_speed_change_before_state_change( + struct pp_hwmgr *hwmgr, const void *input) +{ + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_nps = + cast_const_phw_polaris10_power_state(states->pnew_state); + const struct polaris10_power_state *polaris10_cps = + cast_const_phw_polaris10_power_state(states->pcurrent_state); + + uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps); + uint16_t current_link_speed; + + if (data->force_pcie_gen == PP_PCIEGenInvalid) + current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps); + else + current_link_speed = data->force_pcie_gen; + + data->force_pcie_gen = PP_PCIEGenInvalid; + data->pspp_notify_required = false; + + if (target_link_speed > current_link_speed) { + switch (target_link_speed) { + case PP_PCIEGen3: + if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) + break; + data->force_pcie_gen = PP_PCIEGen2; + if (current_link_speed == PP_PCIEGen2) + break; + case PP_PCIEGen2: + if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) + break; + default: + data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr); + break; + } + } else { + if (target_link_speed < current_link_speed) + data->pspp_notify_required = true; + } + + return 0; +} + +static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (0 == data->need_update_smu7_dpm_table) + return 0; + + if ((0 == data->sclk_dpm_key_disabled) && + (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), + "Trying to freeze SCLK DPM when DPM is disabled", + ); + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_FreezeLevel), + "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", + return -1); + } + + if ((0 == data->mclk_dpm_key_disabled) && + (data->need_update_smu7_dpm_table & + DPMTABLE_OD_UPDATE_MCLK)) { + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), + "Trying to freeze MCLK DPM when DPM is disabled", + ); + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_FreezeLevel), + "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", + return -1); + } + + return 0; +} + +static int polaris10_populate_and_upload_sclk_mclk_dpm_levels( + struct pp_hwmgr *hwmgr, const void *input) +{ + int result = 0; + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t sclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].engine_clock; + uint32_t mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + + struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table; + uint32_t dpm_count, clock_percent; + uint32_t i; + + if (0 == data->need_update_smu7_dpm_table) + return 0; + + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { + dpm_table->sclk_table.dpm_levels + [dpm_table->sclk_table.count - 1].value = sclk; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { + /* Need to do calculation based on the golden DPM table + * as the Heatmap GPU Clock axis is also based on the default values + */ + PP_ASSERT_WITH_CODE( + (golden_dpm_table->sclk_table.dpm_levels + [golden_dpm_table->sclk_table.count - 1].value != 0), + "Divide by 0!", + return -1); + dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2; + + for (i = dpm_count; i > 1; i--) { + if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) { + clock_percent = + ((sclk + - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value + ) * 100) + / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value; + + dpm_table->sclk_table.dpm_levels[i].value = + golden_dpm_table->sclk_table.dpm_levels[i].value + + (golden_dpm_table->sclk_table.dpm_levels[i].value * + clock_percent)/100; + + } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) { + clock_percent = + ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value + - sclk) * 100) + / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value; + + dpm_table->sclk_table.dpm_levels[i].value = + golden_dpm_table->sclk_table.dpm_levels[i].value - + (golden_dpm_table->sclk_table.dpm_levels[i].value * + clock_percent) / 100; + } else + dpm_table->sclk_table.dpm_levels[i].value = + golden_dpm_table->sclk_table.dpm_levels[i].value; + } + } + } + + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { + dpm_table->mclk_table.dpm_levels + [dpm_table->mclk_table.count - 1].value = mclk; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { + + PP_ASSERT_WITH_CODE( + (golden_dpm_table->mclk_table.dpm_levels + [golden_dpm_table->mclk_table.count-1].value != 0), + "Divide by 0!", + return -1); + dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2; + for (i = dpm_count; i > 1; i--) { + if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) { + clock_percent = ((mclk - + golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100) + / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value; + + dpm_table->mclk_table.dpm_levels[i].value = + golden_dpm_table->mclk_table.dpm_levels[i].value + + (golden_dpm_table->mclk_table.dpm_levels[i].value * + clock_percent) / 100; + + } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) { + clock_percent = ( + (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk) + * 100) + / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value; + + dpm_table->mclk_table.dpm_levels[i].value = + golden_dpm_table->mclk_table.dpm_levels[i].value - + (golden_dpm_table->mclk_table.dpm_levels[i].value * + clock_percent) / 100; + } else + dpm_table->mclk_table.dpm_levels[i].value = + golden_dpm_table->mclk_table.dpm_levels[i].value; + } + } + } + + if (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { + result = polaris10_populate_all_graphic_levels(hwmgr); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", + return result); + } + + if (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { + /*populate MCLK dpm table to SMU7 */ + result = polaris10_populate_all_memory_levels(hwmgr); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", + return result); + } + + return result; +} + +static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, + struct polaris10_single_dpm_table *dpm_table, + uint32_t low_limit, uint32_t high_limit) +{ + uint32_t i; + + for (i = 0; i < dpm_table->count; i++) { + if ((dpm_table->dpm_levels[i].value < low_limit) + || (dpm_table->dpm_levels[i].value > high_limit)) + dpm_table->dpm_levels[i].enabled = false; + else + dpm_table->dpm_levels[i].enabled = true; + } + + return 0; +} + +static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr, + const struct polaris10_power_state *polaris10_ps) +{ + int result = 0; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t high_limit_count; + + PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1), + "power state did not have any performance level", + return -1); + + high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1; + + polaris10_trim_single_dpm_states(hwmgr, + &(data->dpm_table.sclk_table), + polaris10_ps->performance_levels[0].engine_clock, + polaris10_ps->performance_levels[high_limit_count].engine_clock); + + polaris10_trim_single_dpm_states(hwmgr, + &(data->dpm_table.mclk_table), + polaris10_ps->performance_levels[0].memory_clock, + polaris10_ps->performance_levels[high_limit_count].memory_clock); + + return result; +} + +static int polaris10_generate_dpm_level_enable_mask( + struct pp_hwmgr *hwmgr, const void *input) +{ + int result; + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + + result = polaris10_trim_dpm_states(hwmgr, polaris10_ps); + if (result) + return result; + + data->dpm_level_enable_mask.sclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); + data->dpm_level_enable_mask.mclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); + data->dpm_level_enable_mask.pcie_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); + + return 0; +} + +int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) +{ + return smum_send_msg_to_smc(hwmgr->smumgr, enable ? + PPSMC_MSG_UVDDPM_Enable : + PPSMC_MSG_UVDDPM_Disable); +} + +int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) +{ + return smum_send_msg_to_smc(hwmgr->smumgr, enable? + PPSMC_MSG_VCEDPM_Enable : + PPSMC_MSG_VCEDPM_Disable); +} + +int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) +{ + return smum_send_msg_to_smc(hwmgr->smumgr, enable? + PPSMC_MSG_SAMUDPM_Enable : + PPSMC_MSG_SAMUDPM_Disable); +} + +int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + if (!bgate) { + data->smc_state_table.UvdBootLevel = 0; + if (table_info->mm_dep_table->count > 0) + data->smc_state_table.UvdBootLevel = + (uint8_t) (table_info->mm_dep_table->count - 1); + mm_boot_level_offset = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, UvdBootLevel); + mm_boot_level_offset /= 4; + mm_boot_level_offset *= 4; + mm_boot_level_value = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset); + mm_boot_level_value &= 0x00FFFFFF; + mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24; + cgs_write_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); + + if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDDPM) || + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StablePState)) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_UVDDPM_SetEnabledMask, + (uint32_t)(1 << data->smc_state_table.UvdBootLevel)); + } + + return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate); +} + +static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) +{ + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_nps = + cast_const_phw_polaris10_power_state(states->pnew_state); + const struct polaris10_power_state *polaris10_cps = + cast_const_phw_polaris10_power_state(states->pcurrent_state); + + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + if (polaris10_nps->vce_clks.evclk > 0 && + (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) { + + data->smc_state_table.VceBootLevel = + (uint8_t) (table_info->mm_dep_table->count - 1); + + mm_boot_level_offset = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, VceBootLevel); + mm_boot_level_offset /= 4; + mm_boot_level_offset *= 4; + mm_boot_level_value = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset); + mm_boot_level_value &= 0xFF00FFFF; + mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16; + cgs_write_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_VCEDPM_SetEnabledMask, + (uint32_t)1 << data->smc_state_table.VceBootLevel); + + polaris10_enable_disable_vce_dpm(hwmgr, true); + } else if (polaris10_nps->vce_clks.evclk == 0 && + polaris10_cps != NULL && + polaris10_cps->vce_clks.evclk > 0) + polaris10_enable_disable_vce_dpm(hwmgr, false); + } + + return 0; +} + +int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + if (!bgate) { + data->smc_state_table.SamuBootLevel = + (uint8_t) (table_info->mm_dep_table->count - 1); + mm_boot_level_offset = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, SamuBootLevel); + mm_boot_level_offset /= 4; + mm_boot_level_offset *= 4; + mm_boot_level_value = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset); + mm_boot_level_value &= 0xFFFFFF00; + mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0; + cgs_write_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StablePState)) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SAMUDPM_SetEnabledMask, + (uint32_t)(1 << data->smc_state_table.SamuBootLevel)); + } + + return polaris10_enable_disable_samu_dpm(hwmgr, !bgate); +} + +static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification) + && (hwmgr->gfx_arbiter.sclk_threshold != + data->low_sclk_interrupt_threshold)) { + data->low_sclk_interrupt_threshold = + hwmgr->gfx_arbiter.sclk_threshold; + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + + CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); + + result = polaris10_copy_bytes_to_smc( + hwmgr->smumgr, + data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, + LowSclkInterruptThreshold), + (uint8_t *)&low_sclk_interrupt_threshold, + sizeof(uint32_t), + data->sram_end); + } + + return result; +} + +static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) + return polaris10_program_memory_timing_parameters(hwmgr); + + return 0; +} + +static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (0 == data->need_update_smu7_dpm_table) + return 0; + + if ((0 == data->sclk_dpm_key_disabled) && + (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { + + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), + "Trying to Unfreeze SCLK DPM when DPM is disabled", + ); + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_UnfreezeLevel), + "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", + return -1); + } + + if ((0 == data->mclk_dpm_key_disabled) && + (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { + + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), + "Trying to Unfreeze MCLK DPM when DPM is disabled", + ); + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_UnfreezeLevel), + "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", + return -1); + } + + data->need_update_smu7_dpm_table = 0; + + return 0; +} + +static int polaris10_notify_link_speed_change_after_state_change( + struct pp_hwmgr *hwmgr, const void *input) +{ + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps); + uint8_t request; + + if (data->pspp_notify_required) { + if (target_link_speed == PP_PCIEGen3) + request = PCIE_PERF_REQ_GEN3; + else if (target_link_speed == PP_PCIEGen2) + request = PCIE_PERF_REQ_GEN2; + else + request = PCIE_PERF_REQ_GEN1; + + if (request == PCIE_PERF_REQ_GEN1 && + phm_get_current_pcie_speed(hwmgr) > 0) + return 0; + + if (acpi_pcie_perf_request(hwmgr->device, request, false)) { + if (PP_PCIEGen2 == target_link_speed) + printk("PSPP request to switch to Gen2 from Gen3 Failed!"); + else + printk("PSPP request to switch to Gen1 from Gen2 Failed!"); + } + } + + return 0; +} + +static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) +{ + int tmp_result, result = 0; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to find DPM states clocks in DPM table!", + result = tmp_result); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PCIEPerformanceRequest)) { + tmp_result = + polaris10_request_link_speed_change_before_state_change(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to request link speed change before state change!", + result = tmp_result); + } + + tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to freeze SCLK MCLK DPM!", result = tmp_result); + + tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to populate and upload SCLK MCLK DPM levels!", + result = tmp_result); + + tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to generate DPM level enabled mask!", + result = tmp_result); + + tmp_result = polaris10_update_vce_dpm(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to update VCE DPM!", + result = tmp_result); + + tmp_result = polaris10_update_sclk_threshold(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to update SCLK threshold!", + result = tmp_result); + + tmp_result = polaris10_program_mem_timing_parameters(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to program memory timing parameters!", + result = tmp_result); + + tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to unfreeze SCLK MCLK DPM!", + result = tmp_result); + + tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to upload DPM level enabled mask!", + result = tmp_result); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PCIEPerformanceRequest)) { + tmp_result = + polaris10_notify_link_speed_change_after_state_change(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to notify link speed change after state change!", + result = tmp_result); + } + data->apply_optimized_settings = false; + return result; +} + +static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) +{ + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; + + if (phm_is_hw_access_blocked(hwmgr)) + return 0; + + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); +} + +int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) +{ + PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; + + return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; +} + +int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) +{ + uint32_t num_active_displays = 0; + struct cgs_display_info info = {0}; + info.mode_info = NULL; + + cgs_get_active_displays_info(hwmgr->device, &info); + + num_active_displays = info.display_count; + + if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */ + polaris10_notify_smc_display_change(hwmgr, false); + else + polaris10_notify_smc_display_change(hwmgr, true); + + return 0; +} + +/** +* Programs the display gap +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always OK +*/ +int polaris10_program_display_gap(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t num_active_displays = 0; + uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); + uint32_t display_gap2; + uint32_t pre_vbi_time_in_us; + uint32_t frame_time_in_us; + uint32_t ref_clock; + uint32_t refresh_rate = 0; + struct cgs_display_info info = {0}; + struct cgs_mode_info mode_info; + + info.mode_info = &mode_info; + + cgs_get_active_displays_info(hwmgr->device, &info); + num_active_displays = info.display_count; + + display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); + + ref_clock = mode_info.ref_clock; + refresh_rate = mode_info.refresh_rate; + + if (0 == refresh_rate) + refresh_rate = 60; + + frame_time_in_us = 1000000 / refresh_rate; + + pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us; + display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); + + polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0); + + return 0; +} + + +int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) +{ + return polaris10_program_display_gap(hwmgr); +} + +/** +* Set maximum target operating fan output RPM +* +* @param hwmgr: the address of the powerplay hardware manager. +* @param usMaxFanRpm: max operating fan RPM value. +* @return The response that came from the SMC. +*/ +static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) +{ + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; + + if (phm_is_hw_access_blocked(hwmgr)) + return 0; + + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); +} + +int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, + const void *thermal_interrupt_info) +{ + return 0; +} + +bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + bool is_update_required = false; + struct cgs_display_info info = {0, 0, NULL}; + + cgs_get_active_displays_info(hwmgr->device, &info); + + if (data->display_timing.num_existing_displays != info.display_count) + is_update_required = true; +/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL + if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { + cgs_get_min_clock_settings(hwmgr->device, &min_clocks); + if (min_clocks.engineClockInSR != data->display_timing.minClockInSR && + (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK || + data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK)) + is_update_required = true; +*/ + return is_update_required; +} + +static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1, + const struct polaris10_performance_level *pl2) +{ + return ((pl1->memory_clock == pl2->memory_clock) && + (pl1->engine_clock == pl2->engine_clock) && + (pl1->pcie_gen == pl2->pcie_gen) && + (pl1->pcie_lane == pl2->pcie_lane)); +} + +int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) +{ + const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1); + const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2); + int i; + + if (pstate1 == NULL || pstate2 == NULL || equal == NULL) + return -EINVAL; + + /* If the two states don't even have the same number of performance levels they cannot be the same state. */ + if (psa->performance_level_count != psb->performance_level_count) { + *equal = false; + return 0; + } + + for (i = 0; i < psa->performance_level_count; i++) { + if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { + /* If we have found even one performance level pair that is different the states are different. */ + *equal = false; + return 0; + } + } + + /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ + *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); + *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); + *equal &= (psa->sclk_threshold == psb->sclk_threshold); + + return 0; +} + +int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + uint32_t vbios_version; + + /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/ + + phm_get_mc_microcode_version(hwmgr); + vbios_version = hwmgr->microcode_version_info.MC & 0xf; + /* Full version of MC ucode has already been loaded. */ + if (vbios_version == 0) { + data->need_long_memory_training = false; + return 0; + } + + data->need_long_memory_training = true; + +/* + * PPMCME_FirmwareDescriptorEntry *pfd = NULL; + pfd = &tonga_mcmeFirmware; + if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN)) + polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold, + pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray, + pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize); +*/ + return 0; +} + +/** + * Read clock related registers. + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL) + & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK; + + data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2) + & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; + + data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4) + & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK; + + return 0; +} + +/** + * Find out if memory is GDDR5. + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t temp; + + temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); + + data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == + ((temp & MC_SEQ_MISC0_GDDR5_MASK) >> + MC_SEQ_MISC0_GDDR5_SHIFT)); + + return 0; +} + +/** + * Enables Dynamic Power Management by SMC + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr) +{ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + GENERAL_PWRMGT, STATIC_PM_EN, 1); + + return 0; +} + +/** + * Initialize PowerGating States for different engines + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + data->uvd_power_gated = false; + data->vce_power_gated = false; + data->samu_power_gated = false; + + return 0; +} + +static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + data->low_sclk_interrupt_threshold = 0; + + return 0; +} + +int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr) +{ + int tmp_result, result = 0; + + polaris10_upload_mc_firmware(hwmgr); + + tmp_result = polaris10_read_clock_registers(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to read clock registers!", result = tmp_result); + + tmp_result = polaris10_get_memory_type(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to get memory type!", result = tmp_result); + + tmp_result = polaris10_enable_acpi_power_management(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable ACPI power management!", result = tmp_result); + + tmp_result = polaris10_init_power_gate_state(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to init power gate state!", result = tmp_result); + + tmp_result = phm_get_mc_microcode_version(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to get MC microcode version!", result = tmp_result); + + tmp_result = polaris10_init_sclk_threshold(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to init sclk threshold!", result = tmp_result); + + return result; +} + +static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (!data->soft_pp_table) { + data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL); + if (!data->soft_pp_table) + return -ENOMEM; + memcpy(data->soft_pp_table, hwmgr->soft_pp_table, + hwmgr->soft_pp_table_size); + } + + *table = (char *)&data->soft_pp_table; + + return hwmgr->soft_pp_table_size; +} + +static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (!data->soft_pp_table) { + data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL); + if (!data->soft_pp_table) + return -ENOMEM; + } + + memcpy(data->soft_pp_table, buf, size); + + hwmgr->soft_pp_table = data->soft_pp_table; + + /* TODO: re-init powerplay to implement modified pptable */ + + return 0; +} + +static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, uint32_t mask) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + switch (type) { + case PP_SCLK: + if (!data->sclk_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); + break; + case PP_MCLK: + if (!data->mclk_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); + break; + case PP_PCIE: + { + uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; + uint32_t level = 0; + + while (tmp >>= 1) + level++; + + if (!data->pcie_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_ForceLevel, + level); + break; + } + default: + break; + } + + return 0; +} + +static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr) +{ + uint32_t speedCntl = 0; + + /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ + speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, + ixPCIE_LC_SPEED_CNTL); + return((uint16_t)PHM_GET_FIELD(speedCntl, + PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); +} + +static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); + struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); + int i, now, size = 0; + uint32_t clock, pcie_speed; + + switch (type) { + case PP_SCLK: + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); + clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + + for (i = 0; i < sclk_table->count; i++) { + if (clock > sclk_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < sclk_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, sclk_table->dpm_levels[i].value / 100, + (i == now) ? "*" : ""); + break; + case PP_MCLK: + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); + clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + + for (i = 0; i < mclk_table->count; i++) { + if (clock > mclk_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < mclk_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, mclk_table->dpm_levels[i].value / 100, + (i == now) ? "*" : ""); + break; + case PP_PCIE: + pcie_speed = polaris10_get_current_pcie_speed(hwmgr); + for (i = 0; i < pcie_table->count; i++) { + if (pcie_speed != pcie_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < pcie_table->count; i++) + size += sprintf(buf + size, "%d: %s %s\n", i, + (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : + (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : + (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", + (i == now) ? "*" : ""); + break; + default: + break; + } + return size; +} + +static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) +{ + if (mode) { + /* stop auto-manage */ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) + polaris10_fan_ctrl_stop_smc_fan_control(hwmgr); + polaris10_fan_ctrl_set_static_mode(hwmgr, mode); + } else + /* restart auto-manage */ + polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr); + + return 0; +} + +static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr) +{ + if (hwmgr->fan_ctrl_is_in_default_mode) + return hwmgr->fan_ctrl_default_mode; + else + return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, FDO_PWM_MODE); +} + +static const struct pp_hwmgr_func polaris10_hwmgr_funcs = { + .backend_init = &polaris10_hwmgr_backend_init, + .backend_fini = &polaris10_hwmgr_backend_fini, + .asic_setup = &polaris10_setup_asic_task, + .dynamic_state_management_enable = &polaris10_enable_dpm_tasks, + .apply_state_adjust_rules = polaris10_apply_state_adjust_rules, + .force_dpm_level = &polaris10_force_dpm_level, + .power_state_set = polaris10_set_power_state_tasks, + .get_power_state_size = polaris10_get_power_state_size, + .get_mclk = polaris10_dpm_get_mclk, + .get_sclk = polaris10_dpm_get_sclk, + .patch_boot_state = polaris10_dpm_patch_boot_state, + .get_pp_table_entry = polaris10_get_pp_table_entry, + .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries, + .print_current_perforce_level = polaris10_print_current_perforce_level, + .powerdown_uvd = polaris10_phm_powerdown_uvd, + .powergate_uvd = polaris10_phm_powergate_uvd, + .powergate_vce = polaris10_phm_powergate_vce, + .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating, + .update_clock_gatings = polaris10_phm_update_clock_gatings, + .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment, + .display_config_changed = polaris10_display_configuration_changed_task, + .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output, + .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output, + .get_temperature = polaris10_thermal_get_temperature, + .stop_thermal_controller = polaris10_thermal_stop_thermal_controller, + .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info, + .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent, + .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent, + .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default, + .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm, + .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm, + .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller, + .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt, + .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration, + .check_states_equal = polaris10_check_states_equal, + .set_fan_control_mode = polaris10_set_fan_control_mode, + .get_fan_control_mode = polaris10_get_fan_control_mode, + .get_pp_table = polaris10_get_pp_table, + .set_pp_table = polaris10_set_pp_table, + .force_clock_level = polaris10_force_clock_level, + .print_clock_levels = polaris10_print_clock_levels, + .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating, +}; + +int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data; + + data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + hwmgr->backend = data; + hwmgr->hwmgr_func = &polaris10_hwmgr_funcs; + hwmgr->pptable_func = &tonga_pptable_funcs; + pp_polaris10_thermal_initialize(hwmgr); + + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h new file mode 100644 index 000000000000..beedf35cbfa6 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h @@ -0,0 +1,357 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef POLARIS10_HWMGR_H +#define POLARIS10_HWMGR_H + +#include "hwmgr.h" +#include "smu74.h" +#include "smu74_discrete.h" +#include "ppatomctrl.h" +#include "polaris10_ppsmc.h" +#include "polaris10_powertune.h" + +#define POLARIS10_MAX_HARDWARE_POWERLEVELS 2 + +#define POLARIS10_VOLTAGE_CONTROL_NONE 0x0 +#define POLARIS10_VOLTAGE_CONTROL_BY_GPIO 0x1 +#define POLARIS10_VOLTAGE_CONTROL_BY_SVID2 0x2 +#define POLARIS10_VOLTAGE_CONTROL_MERGED 0x3 + +#define DPMTABLE_OD_UPDATE_SCLK 0x00000001 +#define DPMTABLE_OD_UPDATE_MCLK 0x00000002 +#define DPMTABLE_UPDATE_SCLK 0x00000004 +#define DPMTABLE_UPDATE_MCLK 0x00000008 + +struct polaris10_performance_level { + uint32_t memory_clock; + uint32_t engine_clock; + uint16_t pcie_gen; + uint16_t pcie_lane; +}; + +struct polaris10_uvd_clocks { + uint32_t vclk; + uint32_t dclk; +}; + +struct polaris10_vce_clocks { + uint32_t evclk; + uint32_t ecclk; +}; + +struct polaris10_power_state { + uint32_t magic; + struct polaris10_uvd_clocks uvd_clks; + struct polaris10_vce_clocks vce_clks; + uint32_t sam_clk; + uint16_t performance_level_count; + bool dc_compatible; + uint32_t sclk_threshold; + struct polaris10_performance_level performance_levels[POLARIS10_MAX_HARDWARE_POWERLEVELS]; +}; + +struct polaris10_dpm_level { + bool enabled; + uint32_t value; + uint32_t param1; +}; + +#define POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID 5 +#define MAX_REGULAR_DPM_NUMBER 8 +#define POLARIS10_MINIMUM_ENGINE_CLOCK 2500 + +struct polaris10_single_dpm_table { + uint32_t count; + struct polaris10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; +}; + +struct polaris10_dpm_table { + struct polaris10_single_dpm_table sclk_table; + struct polaris10_single_dpm_table mclk_table; + struct polaris10_single_dpm_table pcie_speed_table; + struct polaris10_single_dpm_table vddc_table; + struct polaris10_single_dpm_table vddci_table; + struct polaris10_single_dpm_table mvdd_table; +}; + +struct polaris10_clock_registers { + uint32_t vCG_SPLL_FUNC_CNTL; + uint32_t vCG_SPLL_FUNC_CNTL_2; + uint32_t vCG_SPLL_FUNC_CNTL_3; + uint32_t vCG_SPLL_FUNC_CNTL_4; + uint32_t vCG_SPLL_SPREAD_SPECTRUM; + uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; + uint32_t vDLL_CNTL; + uint32_t vMCLK_PWRMGT_CNTL; + uint32_t vMPLL_AD_FUNC_CNTL; + uint32_t vMPLL_DQ_FUNC_CNTL; + uint32_t vMPLL_FUNC_CNTL; + uint32_t vMPLL_FUNC_CNTL_1; + uint32_t vMPLL_FUNC_CNTL_2; + uint32_t vMPLL_SS1; + uint32_t vMPLL_SS2; +}; + +#define DISABLE_MC_LOADMICROCODE 1 +#define DISABLE_MC_CFGPROGRAMMING 2 + +struct polaris10_voltage_smio_registers { + uint32_t vS0_VID_LOWER_SMIO_CNTL; +}; + +#define POLARIS10_MAX_LEAKAGE_COUNT 8 + +struct polaris10_leakage_voltage { + uint16_t count; + uint16_t leakage_id[POLARIS10_MAX_LEAKAGE_COUNT]; + uint16_t actual_voltage[POLARIS10_MAX_LEAKAGE_COUNT]; +}; + +struct polaris10_vbios_boot_state { + uint16_t mvdd_bootup_value; + uint16_t vddc_bootup_value; + uint16_t vddci_bootup_value; + uint32_t sclk_bootup_value; + uint32_t mclk_bootup_value; + uint16_t pcie_gen_bootup_value; + uint16_t pcie_lane_bootup_value; +}; + +/* Ultra Low Voltage parameter structure */ +struct polaris10_ulv_parm { + bool ulv_supported; + uint32_t cg_ulv_parameter; + uint32_t ulv_volt_change_delay; + struct polaris10_performance_level ulv_power_level; +}; + +struct polaris10_display_timing { + uint32_t min_clock_in_sr; + uint32_t num_existing_displays; +}; + +struct polaris10_dpmlevel_enable_mask { + uint32_t uvd_dpm_enable_mask; + uint32_t vce_dpm_enable_mask; + uint32_t acp_dpm_enable_mask; + uint32_t samu_dpm_enable_mask; + uint32_t sclk_dpm_enable_mask; + uint32_t mclk_dpm_enable_mask; + uint32_t pcie_dpm_enable_mask; +}; + +struct polaris10_pcie_perf_range { + uint16_t max; + uint16_t min; +}; +struct polaris10_range_table { + uint32_t trans_lower_frequency; /* in 10khz */ + uint32_t trans_upper_frequency; +}; + +struct polaris10_hwmgr { + struct polaris10_dpm_table dpm_table; + struct polaris10_dpm_table golden_dpm_table; + SMU74_Discrete_DpmTable smc_state_table; + struct SMU74_Discrete_Ulv ulv_setting; + + struct polaris10_range_table range_table[NUM_SCLK_RANGE]; + uint32_t voting_rights_clients0; + uint32_t voting_rights_clients1; + uint32_t voting_rights_clients2; + uint32_t voting_rights_clients3; + uint32_t voting_rights_clients4; + uint32_t voting_rights_clients5; + uint32_t voting_rights_clients6; + uint32_t voting_rights_clients7; + uint32_t static_screen_threshold_unit; + uint32_t static_screen_threshold; + uint32_t voltage_control; + uint32_t vddc_vddci_delta; + + uint32_t active_auto_throttle_sources; + + struct polaris10_clock_registers clock_registers; + struct polaris10_voltage_smio_registers voltage_smio_registers; + + bool is_memory_gddr5; + uint16_t acpi_vddc; + bool pspp_notify_required; + uint16_t force_pcie_gen; + uint16_t acpi_pcie_gen; + uint32_t pcie_gen_cap; + uint32_t pcie_lane_cap; + uint32_t pcie_spc_cap; + struct polaris10_leakage_voltage vddc_leakage; + struct polaris10_leakage_voltage Vddci_leakage; + + uint32_t mvdd_control; + uint32_t vddc_mask_low; + uint32_t mvdd_mask_low; + uint16_t max_vddc_in_pptable; + uint16_t min_vddc_in_pptable; + uint16_t max_vddci_in_pptable; + uint16_t min_vddci_in_pptable; + uint32_t mclk_strobe_mode_threshold; + uint32_t mclk_stutter_mode_threshold; + uint32_t mclk_edc_enable_threshold; + uint32_t mclk_edcwr_enable_threshold; + bool is_uvd_enabled; + struct polaris10_vbios_boot_state vbios_boot_state; + + bool pcie_performance_request; + bool battery_state; + bool is_tlu_enabled; + + /* ---- SMC SRAM Address of firmware header tables ---- */ + uint32_t sram_end; + uint32_t dpm_table_start; + uint32_t soft_regs_start; + uint32_t mc_reg_table_start; + uint32_t fan_table_start; + uint32_t arb_table_start; + + /* ---- Stuff originally coming from Evergreen ---- */ + uint32_t vddci_control; + struct pp_atomctrl_voltage_table vddc_voltage_table; + struct pp_atomctrl_voltage_table vddci_voltage_table; + struct pp_atomctrl_voltage_table mvdd_voltage_table; + + uint32_t mgcg_cgtt_local2; + uint32_t mgcg_cgtt_local3; + uint32_t gpio_debug; + uint32_t mc_micro_code_feature; + uint32_t highest_mclk; + uint16_t acpi_vddci; + uint8_t mvdd_high_index; + uint8_t mvdd_low_index; + bool dll_default_on; + bool performance_request_registered; + + /* ---- Low Power Features ---- */ + struct polaris10_ulv_parm ulv; + + /* ---- CAC Stuff ---- */ + uint32_t cac_table_start; + bool cac_configuration_required; + bool driver_calculate_cac_leakage; + bool cac_enabled; + + /* ---- DPM2 Parameters ---- */ + uint32_t power_containment_features; + bool enable_dte_feature; + bool enable_tdc_limit_feature; + bool enable_pkg_pwr_tracking_feature; + bool disable_uvd_power_tune_feature; + const struct polaris10_pt_defaults *power_tune_defaults; + struct SMU74_Discrete_PmFuses power_tune_table; + uint32_t dte_tj_offset; + uint32_t fast_watermark_threshold; + + /* ---- Phase Shedding ---- */ + bool vddc_phase_shed_control; + + /* ---- DI/DT ---- */ + struct polaris10_display_timing display_timing; + uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK]; + + /* ---- Thermal Temperature Setting ---- */ + struct polaris10_dpmlevel_enable_mask dpm_level_enable_mask; + uint32_t need_update_smu7_dpm_table; + uint32_t sclk_dpm_key_disabled; + uint32_t mclk_dpm_key_disabled; + uint32_t pcie_dpm_key_disabled; + uint32_t min_engine_clocks; + struct polaris10_pcie_perf_range pcie_gen_performance; + struct polaris10_pcie_perf_range pcie_lane_performance; + struct polaris10_pcie_perf_range pcie_gen_power_saving; + struct polaris10_pcie_perf_range pcie_lane_power_saving; + bool use_pcie_performance_levels; + bool use_pcie_power_saving_levels; + uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS]; + uint32_t mclk_activity_target; + uint32_t mclk_dpm0_activity_target; + uint32_t low_sclk_interrupt_threshold; + uint32_t last_mclk_dpm_enable_mask; + bool uvd_enabled; + + /* ---- Power Gating States ---- */ + bool uvd_power_gated; + bool vce_power_gated; + bool samu_power_gated; + bool need_long_memory_training; + + /* Application power optimization parameters */ + bool update_up_hyst; + bool update_down_hyst; + uint32_t down_hyst; + uint32_t up_hyst; + uint32_t disable_dpm_mask; + bool apply_optimized_settings; + + /* soft pptable for re-uploading into smu */ + void *soft_pp_table; +}; + +/* To convert to Q8.8 format for firmware */ +#define POLARIS10_Q88_FORMAT_CONVERSION_UNIT 256 + +enum Polaris10_I2CLineID { + Polaris10_I2CLineID_DDC1 = 0x90, + Polaris10_I2CLineID_DDC2 = 0x91, + Polaris10_I2CLineID_DDC3 = 0x92, + Polaris10_I2CLineID_DDC4 = 0x93, + Polaris10_I2CLineID_DDC5 = 0x94, + Polaris10_I2CLineID_DDC6 = 0x95, + Polaris10_I2CLineID_SCLSDA = 0x96, + Polaris10_I2CLineID_DDCVGA = 0x97 +}; + +#define POLARIS10_I2C_DDC1DATA 0 +#define POLARIS10_I2C_DDC1CLK 1 +#define POLARIS10_I2C_DDC2DATA 2 +#define POLARIS10_I2C_DDC2CLK 3 +#define POLARIS10_I2C_DDC3DATA 4 +#define POLARIS10_I2C_DDC3CLK 5 +#define POLARIS10_I2C_SDA 40 +#define POLARIS10_I2C_SCL 41 +#define POLARIS10_I2C_DDC4DATA 65 +#define POLARIS10_I2C_DDC4CLK 66 +#define POLARIS10_I2C_DDC5DATA 0x48 +#define POLARIS10_I2C_DDC5CLK 0x49 +#define POLARIS10_I2C_DDC6DATA 0x4a +#define POLARIS10_I2C_DDC6CLK 0x4b +#define POLARIS10_I2C_DDCVGADATA 0x4c +#define POLARIS10_I2C_DDCVGACLK 0x4d + +#define POLARIS10_UNUSED_GPIO_PIN 0x7F + +int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr); + +int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c new file mode 100644 index 000000000000..0b99ab3ba0c5 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c @@ -0,0 +1,398 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "hwmgr.h" +#include "smumgr.h" +#include "polaris10_hwmgr.h" +#include "polaris10_powertune.h" +#include "polaris10_smumgr.h" +#include "smu74_discrete.h" +#include "pp_debug.h" + +#define VOLTAGE_SCALE 4 +#define POWERTUNE_DEFAULT_SET_MAX 1 + +static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { + /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, + * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */ + { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, + { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, + { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } }, +}; + +void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *polaris10_hwmgr = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + if (table_info && + table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX && + table_info->cac_dtp_table->usPowerTuneDataSetID) + polaris10_hwmgr->power_tune_defaults = + &polaris10_power_tune_data_set_array + [table_info->cac_dtp_table->usPowerTuneDataSetID - 1]; + else + polaris10_hwmgr->power_tune_defaults = &polaris10_power_tune_data_set_array[0]; + +} + +static uint16_t scale_fan_gain_settings(uint16_t raw_setting) +{ + uint32_t tmp; + tmp = raw_setting * 4096 / 100; + return (uint16_t)tmp; +} + +int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_pt_defaults *defaults = data->power_tune_defaults; + SMU74_Discrete_DpmTable *dpm_table = &(data->smc_state_table); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table; + struct pp_advance_fan_control_parameters *fan_table= + &hwmgr->thermal_controller.advanceFanControlParameters; + int i, j, k; + const uint16_t *pdef1; + const uint16_t *pdef2; + + dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); + dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); + + PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, + "Target Operating Temp is out of Range!", + ); + + dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( + cac_dtp_table->usTargetOperatingTemp * 256); + dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( + cac_dtp_table->usTemperatureLimitHotspot * 256); + dpm_table->FanGainEdge = PP_HOST_TO_SMC_US( + scale_fan_gain_settings(fan_table->usFanGainEdge)); + dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US( + scale_fan_gain_settings(fan_table->usFanGainHotspot)); + + pdef1 = defaults->BAPMTI_R; + pdef2 = defaults->BAPMTI_RC; + + for (i = 0; i < SMU74_DTE_ITERATIONS; i++) { + for (j = 0; j < SMU74_DTE_SOURCES; j++) { + for (k = 0; k < SMU74_DTE_SINKS; k++) { + dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1); + dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2); + pdef1++; + pdef2++; + } + } + } + + return 0; +} + +static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_pt_defaults *defaults = data->power_tune_defaults; + + data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; + data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC; + data->power_tune_table.SviLoadLineTrimVddC = 3; + data->power_tune_table.SviLoadLineOffsetVddC = 0; + + return 0; +} + +static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) +{ + uint16_t tdc_limit; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + const struct polaris10_pt_defaults *defaults = data->power_tune_defaults; + + tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128); + data->power_tune_table.TDC_VDDC_PkgLimit = + CONVERT_FROM_HOST_TO_SMC_US(tdc_limit); + data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc = + defaults->TDC_VDDC_ThrottleReleaseLimitPerc; + data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt; + + return 0; +} + +static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_pt_defaults *defaults = data->power_tune_defaults; + uint32_t temp; + + if (polaris10_read_smc_sram_dword(hwmgr->smumgr, + fuse_table_offset + + offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl), + (uint32_t *)&temp, data->sram_end)) + PP_ASSERT_WITH_CODE(false, + "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!", + return -EINVAL); + else { + data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl; + data->power_tune_table.LPMLTemperatureMin = + (uint8_t)((temp >> 16) & 0xff); + data->power_tune_table.LPMLTemperatureMax = + (uint8_t)((temp >> 8) & 0xff); + data->power_tune_table.Reserved = (uint8_t)(temp & 0xff); + } + return 0; +} + +static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) +{ + int i; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) + data->power_tune_table.LPMLTemperatureScaler[i] = 0; + + return 0; +} + +static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) + || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) + hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = + hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity; + + data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US( + hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity); + return 0; +} + +static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) +{ + int i; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) + data->power_tune_table.GnbLPML[i] = 0; + + return 0; +} + +static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) +{ + return 0; +} + +static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd; + uint16_t lo_sidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd; + struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; + + hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256); + lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256); + + data->power_tune_table.BapmVddCBaseLeakageHiSidd = + CONVERT_FROM_HOST_TO_SMC_US(hi_sidd); + data->power_tune_table.BapmVddCBaseLeakageLoSidd = + CONVERT_FROM_HOST_TO_SMC_US(lo_sidd); + + return 0; +} + +int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t pm_fuse_table_offset; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment)) { + if (polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, PmFuseTable), + &pm_fuse_table_offset, data->sram_end)) + PP_ASSERT_WITH_CODE(false, + "Attempt to get pm_fuse_table_offset Failed!", + return -EINVAL); + + if (polaris10_populate_svi_load_line(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate SviLoadLine Failed!", + return -EINVAL); + + if (polaris10_populate_tdc_limit(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate TDCLimit Failed!", return -EINVAL); + + if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate TdcWaterfallCtl, " + "LPMLTemperature Min and Max Failed!", + return -EINVAL); + + if (0 != polaris10_populate_temperature_scaler(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate LPMLTemperatureScaler Failed!", + return -EINVAL); + + if (polaris10_populate_fuzzy_fan(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate Fuzzy Fan Control parameters Failed!", + return -EINVAL); + + if (polaris10_populate_gnb_lpml(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate GnbLPML Failed!", + return -EINVAL); + + if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate GnbLPML Min and Max Vid Failed!", + return -EINVAL); + + if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate BapmVddCBaseLeakage Hi and Lo " + "Sidd Failed!", return -EINVAL); + + if (polaris10_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, + (uint8_t *)&data->power_tune_table, + sizeof(struct SMU74_Discrete_PmFuses), data->sram_end)) + PP_ASSERT_WITH_CODE(false, + "Attempt to download PmFuseTable Failed!", + return -EINVAL); + } + return 0; +} + +int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + int result = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC)) { + int smc_result; + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_EnableCac)); + PP_ASSERT_WITH_CODE((0 == smc_result), + "Failed to enable CAC in SMC.", result = -1); + + data->cac_enabled = (0 == smc_result) ? true : false; + } + return result; +} + +int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->power_containment_features & + POWERCONTAINMENT_FEATURE_PkgPwrLimit) + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PkgPwrSetLimit, n); + return 0; +} + +static int polaris10_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) +{ + return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, + PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); +} + +int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + int smc_result; + int result = 0; + + data->power_containment_features = 0; + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment)) { + + if (data->enable_tdc_limit_feature) { + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_TDCLimitEnable)); + PP_ASSERT_WITH_CODE((0 == smc_result), + "Failed to enable TDCLimit in SMC.", result = -1;); + if (0 == smc_result) + data->power_containment_features |= + POWERCONTAINMENT_FEATURE_TDCLimit; + } + + if (data->enable_pkg_pwr_tracking_feature) { + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable)); + PP_ASSERT_WITH_CODE((0 == smc_result), + "Failed to enable PkgPwrTracking in SMC.", result = -1;); + if (0 == smc_result) { + struct phm_cac_tdp_table *cac_table = + table_info->cac_dtp_table; + uint32_t default_limit = + (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256); + + data->power_containment_features |= + POWERCONTAINMENT_FEATURE_PkgPwrLimit; + + if (polaris10_set_power_limit(hwmgr, default_limit)) + printk(KERN_ERR "Failed to set Default Power Limit in SMC!"); + } + } + } + return result; +} + +int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr) +{ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; + int adjust_percent, target_tdp; + int result = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment)) { + /* adjustment percentage has already been validated */ + adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? + hwmgr->platform_descriptor.TDPAdjustment : + (-1 * hwmgr->platform_descriptor.TDPAdjustment); + /* SMC requested that target_tdp to be 7 bit fraction in DPM table + * but message to be 8 bit fraction for messages + */ + target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100; + result = polaris10_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp); + } + + return result; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h new file mode 100644 index 000000000000..68bc1cb6d40c --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h @@ -0,0 +1,70 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef POLARIS10_POWERTUNE_H +#define POLARIS10_POWERTUNE_H + +enum polaris10_pt_config_reg_type { + POLARIS10_CONFIGREG_MMR = 0, + POLARIS10_CONFIGREG_SMC_IND, + POLARIS10_CONFIGREG_DIDT_IND, + POLARIS10_CONFIGREG_CACHE, + POLARIS10_CONFIGREG_MAX +}; + +/* PowerContainment Features */ +#define POWERCONTAINMENT_FEATURE_DTE 0x00000001 +#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 +#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 + +struct polaris10_pt_config_reg { + uint32_t offset; + uint32_t mask; + uint32_t shift; + uint32_t value; + enum polaris10_pt_config_reg_type type; +}; + +struct polaris10_pt_defaults { + uint8_t SviLoadLineEn; + uint8_t SviLoadLineVddC; + uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; + uint8_t TDC_MAWt; + uint8_t TdcWaterfallCtl; + uint8_t DTEAmbientTempBase; + + uint32_t DisplayCac; + uint32_t BAPM_TEMP_GRADIENT; + uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; + uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; +}; + +void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr); +int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr); +int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr); +int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr); +int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr); +int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); +int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr); + +#endif /* POLARIS10_POWERTUNE_H */ + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c new file mode 100644 index 000000000000..aba167f7d167 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c @@ -0,0 +1,712 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "polaris10_thermal.h" +#include "polaris10_hwmgr.h" +#include "polaris10_smumgr.h" +#include "polaris10_ppsmc.h" +#include "smu/smu_7_1_3_d.h" +#include "smu/smu_7_1_3_sh_mask.h" + +int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, + struct phm_fan_speed_info *fan_speed_info) +{ + if (hwmgr->thermal_controller.fanInfo.bNoFan) + return 0; + + fan_speed_info->supports_percent_read = true; + fan_speed_info->supports_percent_write = true; + fan_speed_info->min_percent = 0; + fan_speed_info->max_percent = 100; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_FanSpeedInTableIsRPM) && + hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { + fan_speed_info->supports_rpm_read = true; + fan_speed_info->supports_rpm_write = true; + fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; + fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM; + } else { + fan_speed_info->min_rpm = 0; + fan_speed_info->max_rpm = 0; + } + + return 0; +} + +int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, + uint32_t *speed) +{ + uint32_t duty100; + uint32_t duty; + uint64_t tmp64; + + if (hwmgr->thermal_controller.fanInfo.bNoFan) + return 0; + + duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL1, FMAX_DUTY100); + duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_STATUS, FDO_PWM_DUTY); + + if (duty100 == 0) + return -EINVAL; + + + tmp64 = (uint64_t)duty * 100; + do_div(tmp64, duty100); + *speed = (uint32_t)tmp64; + + if (*speed > 100) + *speed = 100; + + return 0; +} + +int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) +{ + uint32_t tach_period; + uint32_t crystal_clock_freq; + + if (hwmgr->thermal_controller.fanInfo.bNoFan || + (hwmgr->thermal_controller.fanInfo. + ucTachometerPulsesPerRevolution == 0)) + return 0; + + tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_TACH_STATUS, TACH_PERIOD); + + if (tach_period == 0) + return -EINVAL; + + crystal_clock_freq = tonga_get_xclk(hwmgr); + + *speed = 60 * crystal_clock_freq * 10000 / tach_period; + + return 0; +} + +/** +* Set Fan Speed Control to static mode, so that the user can decide what speed to use. +* @param hwmgr the address of the powerplay hardware manager. +* mode the fan control mode, 0 default, 1 by percent, 5, by RPM +* @exception Should always succeed. +*/ +int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) +{ + + if (hwmgr->fan_ctrl_is_in_default_mode) { + hwmgr->fan_ctrl_default_mode = + PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, FDO_PWM_MODE); + hwmgr->tmin = + PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, TMIN); + hwmgr->fan_ctrl_is_in_default_mode = false; + } + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, TMIN, 0); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, FDO_PWM_MODE, mode); + + return 0; +} + +/** +* Reset Fan Speed Control to default mode. +* @param hwmgr the address of the powerplay hardware manager. +* @exception Should always succeed. +*/ +int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) +{ + if (!hwmgr->fan_ctrl_is_in_default_mode) { + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, TMIN, hwmgr->tmin); + hwmgr->fan_ctrl_is_in_default_mode = true; + } + + return 0; +} + +int polaris10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) +{ + int result; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ODFuzzyFanControlSupport)) { + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY); + result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_FanSpeedInTableIsRPM)) + hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanRPM); + else + hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr, + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanPWM); + + } else { + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE); + result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); + } + + if (!result && hwmgr->thermal_controller. + advanceFanControlParameters.ucTargetTemperature) + result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanTemperatureTarget, + hwmgr->thermal_controller. + advanceFanControlParameters.ucTargetTemperature); + + return result; +} + + +int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) +{ + return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl); +} + +/** +* Set Fan Speed in percent. +* @param hwmgr the address of the powerplay hardware manager. +* @param speed is the percentage value (0% - 100%) to be set. +* @exception Fails is the 100% setting appears to be 0. +*/ +int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, + uint32_t speed) +{ + uint32_t duty100; + uint32_t duty; + uint64_t tmp64; + + if (hwmgr->thermal_controller.fanInfo.bNoFan) + return 0; + + if (speed > 100) + speed = 100; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) + polaris10_fan_ctrl_stop_smc_fan_control(hwmgr); + + duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL1, FMAX_DUTY100); + + if (duty100 == 0) + return -EINVAL; + + tmp64 = (uint64_t)speed * duty100; + do_div(tmp64, 100); + duty = (uint32_t)tmp64; + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty); + + return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); +} + +/** +* Reset Fan Speed to default. +* @param hwmgr the address of the powerplay hardware manager. +* @exception Always succeeds. +*/ +int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) +{ + int result; + + if (hwmgr->thermal_controller.fanInfo.bNoFan) + return 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) { + result = polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); + if (!result) + result = polaris10_fan_ctrl_start_smc_fan_control(hwmgr); + } else + result = polaris10_fan_ctrl_set_default_mode(hwmgr); + + return result; +} + +/** +* Set Fan Speed in RPM. +* @param hwmgr the address of the powerplay hardware manager. +* @param speed is the percentage value (min - max) to be set. +* @exception Fails is the speed not lie between min and max. +*/ +int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) +{ + uint32_t tach_period; + uint32_t crystal_clock_freq; + + if (hwmgr->thermal_controller.fanInfo.bNoFan || + (hwmgr->thermal_controller.fanInfo. + ucTachometerPulsesPerRevolution == 0) || + (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || + (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) + return 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) + polaris10_fan_ctrl_stop_smc_fan_control(hwmgr); + + crystal_clock_freq = tonga_get_xclk(hwmgr); + + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_TACH_STATUS, TACH_PERIOD, tach_period); + + return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); +} + +/** +* Reads the remote temperature from the SIslands thermal controller. +* +* @param hwmgr The address of the hardware manager. +*/ +int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr) +{ + int temp; + + temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_MULT_THERMAL_STATUS, CTF_TEMP); + + /* Bit 9 means the reading is lower than the lowest usable value. */ + if (temp & 0x200) + temp = POLARIS10_THERMAL_MAXIMUM_TEMP_READING; + else + temp = temp & 0x1ff; + + temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + + return temp; +} + +/** +* Set the requested temperature range for high and low alert signals +* +* @param hwmgr The address of the hardware manager. +* @param range Temperature range to be programmed for high and low alert signals +* @exception PP_Result_BadInput if the input data is not valid. +*/ +static int polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, + uint32_t low_temp, uint32_t high_temp) +{ + uint32_t low = POLARIS10_THERMAL_MINIMUM_ALERT_TEMP * + PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + uint32_t high = POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP * + PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + + if (low < low_temp) + low = low_temp; + if (high > high_temp) + high = high_temp; + + if (low > high) + return -EINVAL; + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, DIG_THERM_INTH, + (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, DIG_THERM_INTL, + (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_CTRL, DIG_THERM_DPM, + (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + + return 0; +} + +/** +* Programs thermal controller one-time setting registers +* +* @param hwmgr The address of the hardware manager. +*/ +static int polaris10_thermal_initialize(struct pp_hwmgr *hwmgr) +{ + if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_TACH_CTRL, EDGE_PER_REV, + hwmgr->thermal_controller.fanInfo. + ucTachometerPulsesPerRevolution - 1); + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28); + + return 0; +} + +/** +* Enable thermal alerts on the RV770 thermal controller. +* +* @param hwmgr The address of the hardware manager. +*/ +static int polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr) +{ + uint32_t alert; + + alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, THERM_INT_MASK); + alert &= ~(POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, THERM_INT_MASK, alert); + + /* send message to SMU to enable internal thermal interrupts */ + return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable); +} + +/** +* Disable thermal alerts on the RV770 thermal controller. +* @param hwmgr The address of the hardware manager. +*/ +static int polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr) +{ + uint32_t alert; + + alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, THERM_INT_MASK); + alert |= (POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, THERM_INT_MASK, alert); + + /* send message to SMU to disable internal thermal interrupts */ + return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable); +} + +/** +* Uninitialize the thermal controller. +* Currently just disables alerts. +* @param hwmgr The address of the hardware manager. +*/ +int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) +{ + int result = polaris10_thermal_disable_alert(hwmgr); + + if (!hwmgr->thermal_controller.fanInfo.bNoFan) + polaris10_fan_ctrl_set_default_mode(hwmgr); + + return result; +} + +/** +* Set up the fan table to control the fan using the SMC. +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from set temperature range routine +*/ +int tf_polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + uint32_t duty100; + uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; + uint16_t fdo_min, slope1, slope2; + uint32_t reference_clock; + int res; + uint64_t tmp64; + + if (data->fan_table_start == 0) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + + duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL1, FMAX_DUTY100); + + if (duty100 == 0) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + + tmp64 = hwmgr->thermal_controller.advanceFanControlParameters. + usPWMMin * duty100; + do_div(tmp64, 10000); + fdo_min = (uint16_t)tmp64; + + t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - + hwmgr->thermal_controller.advanceFanControlParameters.usTMin; + t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - + hwmgr->thermal_controller.advanceFanControlParameters.usTMed; + + pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - + hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin; + pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - + hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed; + + slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); + slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); + + fan_table.TempMin = cpu_to_be16((50 + hwmgr-> + thermal_controller.advanceFanControlParameters.usTMin) / 100); + fan_table.TempMed = cpu_to_be16((50 + hwmgr-> + thermal_controller.advanceFanControlParameters.usTMed) / 100); + fan_table.TempMax = cpu_to_be16((50 + hwmgr-> + thermal_controller.advanceFanControlParameters.usTMax) / 100); + + fan_table.Slope1 = cpu_to_be16(slope1); + fan_table.Slope2 = cpu_to_be16(slope2); + + fan_table.FdoMin = cpu_to_be16(fdo_min); + + fan_table.HystDown = cpu_to_be16(hwmgr-> + thermal_controller.advanceFanControlParameters.ucTHyst); + + fan_table.HystUp = cpu_to_be16(1); + + fan_table.HystSlope = cpu_to_be16(1); + + fan_table.TempRespLim = cpu_to_be16(5); + + reference_clock = tonga_get_xclk(hwmgr); + + fan_table.RefreshPeriod = cpu_to_be32((hwmgr-> + thermal_controller.advanceFanControlParameters.ulCycleDelay * + reference_clock) / 1600); + + fan_table.FdoMax = cpu_to_be16((uint16_t)duty100); + + fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD( + hwmgr->device, CGS_IND_REG__SMC, + CG_MULT_THERMAL_CTRL, TEMP_SEL); + + res = polaris10_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start, + (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), + data->sram_end); + + if (!res && hwmgr->thermal_controller. + advanceFanControlParameters.ucMinimumPWMLimit) + res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanMinPwm, + hwmgr->thermal_controller. + advanceFanControlParameters.ucMinimumPWMLimit); + + if (!res && hwmgr->thermal_controller. + advanceFanControlParameters.ulMinFanSCLKAcousticLimit) + res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanSclkTarget, + hwmgr->thermal_controller. + advanceFanControlParameters.ulMinFanSCLKAcousticLimit); + + if (res) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + + return 0; +} + +/** +* Start the fan control on the SMC. +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from set temperature range routine +*/ +int tf_polaris10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ +/* If the fantable setup has failed we could have disabled + * PHM_PlatformCaps_MicrocodeFanControl even after + * this function was included in the table. + * Make sure that we still think controlling the fan is OK. +*/ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) { + polaris10_fan_ctrl_start_smc_fan_control(hwmgr); + polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); + } + + return 0; +} + +/** +* Set temperature range for high and low alerts +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from set temperature range routine +*/ +int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input; + + if (range == NULL) + return -EINVAL; + + return polaris10_thermal_set_temperature_range(hwmgr, range->min, range->max); +} + +/** +* Programs one-time setting registers +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from initialize thermal controller routine +*/ +int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + return polaris10_thermal_initialize(hwmgr); +} + +/** +* Enable high and low alerts +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from enable alert routine +*/ +int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + return polaris10_thermal_enable_alert(hwmgr); +} + +/** +* Disable high and low alerts +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from disable alert routine +*/ +static int tf_polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + return polaris10_thermal_disable_alert(hwmgr); +} + +static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + int ret; + struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) + return 0; + + ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ? + 0 : -1; + + if (!ret) + /* If this param is not changed, this function could fire unnecessarily */ + smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY; + + return ret; +} + +static const struct phm_master_table_item +polaris10_thermal_start_thermal_controller_master_list[] = { + {NULL, tf_polaris10_thermal_initialize}, + {NULL, tf_polaris10_thermal_set_temperature_range}, + {NULL, tf_polaris10_thermal_enable_alert}, + {NULL, tf_polaris10_thermal_avfs_enable}, +/* We should restrict performance levels to low before we halt the SMC. + * On the other hand we are still in boot state when we do this + * so it would be pointless. + * If this assumption changes we have to revisit this table. + */ + {NULL, tf_polaris10_thermal_setup_fan_table}, + {NULL, tf_polaris10_thermal_start_smc_fan_control}, + {NULL, NULL} +}; + +static const struct phm_master_table_header +polaris10_thermal_start_thermal_controller_master = { + 0, + PHM_MasterTableFlag_None, + polaris10_thermal_start_thermal_controller_master_list +}; + +static const struct phm_master_table_item +polaris10_thermal_set_temperature_range_master_list[] = { + {NULL, tf_polaris10_thermal_disable_alert}, + {NULL, tf_polaris10_thermal_set_temperature_range}, + {NULL, tf_polaris10_thermal_enable_alert}, + {NULL, NULL} +}; + +static const struct phm_master_table_header +polaris10_thermal_set_temperature_range_master = { + 0, + PHM_MasterTableFlag_None, + polaris10_thermal_set_temperature_range_master_list +}; + +int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) +{ + if (!hwmgr->thermal_controller.fanInfo.bNoFan) + polaris10_fan_ctrl_set_default_mode(hwmgr); + return 0; +} + +/** +* Initializes the thermal controller related functions in the Hardware Manager structure. +* @param hwmgr The address of the hardware manager. +* @exception Any error code from the low-level communication. +*/ +int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr) +{ + int result; + + result = phm_construct_table(hwmgr, + &polaris10_thermal_set_temperature_range_master, + &(hwmgr->set_temperature_range)); + + if (!result) { + result = phm_construct_table(hwmgr, + &polaris10_thermal_start_thermal_controller_master, + &(hwmgr->start_thermal_controller)); + if (result) + phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range)); + } + + if (!result) + hwmgr->fan_ctrl_is_in_default_mode = true; + return result; +} + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h new file mode 100644 index 000000000000..62f8cbc2d590 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h @@ -0,0 +1,62 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _POLARIS10_THERMAL_H_ +#define _POLARIS10_THERMAL_H_ + +#include "hwmgr.h" + +#define POLARIS10_THERMAL_HIGH_ALERT_MASK 0x1 +#define POLARIS10_THERMAL_LOW_ALERT_MASK 0x2 + +#define POLARIS10_THERMAL_MINIMUM_TEMP_READING -256 +#define POLARIS10_THERMAL_MAXIMUM_TEMP_READING 255 + +#define POLARIS10_THERMAL_MINIMUM_ALERT_TEMP 0 +#define POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP 255 + +#define FDO_PWM_MODE_STATIC 1 +#define FDO_PWM_MODE_STATIC_RPM 5 + + +extern int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); +extern int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); +extern int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); + +extern int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr); +extern int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); +extern int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed); +extern int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode); +extern int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); +extern int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); +extern int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr); +extern int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed); +extern int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); +extern int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); +extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr); + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c index 7b2d5000292d..58742e0d1492 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c @@ -1,3 +1,26 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include #include "linux/delay.h" #include "hwmgr.h" diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c index 2a83a4af2904..da9f5f1b6dc2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c @@ -373,6 +373,37 @@ int atomctrl_get_engine_pll_dividers_vi( return result; } +int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, + uint32_t clock_value, + pp_atomctrl_clock_dividers_ai *dividers) +{ + COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters; + int result; + + pll_patameters.ulClock.ulClock = clock_value; + pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK; + + result = cgs_atom_exec_cmd_table + (hwmgr->device, + GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), + &pll_patameters); + + if (0 == result) { + dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac); + dividers->usSclk_fcw_int = le16_to_cpu(pll_patameters.usSclk_fcw_int); + dividers->ucSclkPostDiv = pll_patameters.ucSclkPostDiv; + dividers->ucSclkVcoMode = pll_patameters.ucSclkVcoMode; + dividers->ucSclkPllRange = pll_patameters.ucSclkPllRange; + dividers->ucSscEnable = pll_patameters.ucSscEnable; + dividers->usSsc_fcw1_frac = le16_to_cpu(pll_patameters.usSsc_fcw1_frac); + dividers->usSsc_fcw1_int = le16_to_cpu(pll_patameters.usSsc_fcw1_int); + dividers->usPcc_fcw_int = le16_to_cpu(pll_patameters.usPcc_fcw_int); + dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac); + dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac); + } + return result; +} + int atomctrl_get_dfs_pll_dividers_vi( struct pp_hwmgr *hwmgr, uint32_t clock_value, @@ -618,7 +649,7 @@ int atomctrl_calculate_voltage_evv_on_sclk( if (!getASICProfilingInfo) return -1; - if(getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 || + if (getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 || (getASICProfilingInfo->asHeader.ucTableFormatRevision == 3 && getASICProfilingInfo->asHeader.ucTableContentRevision < 4)) return -1; @@ -891,18 +922,18 @@ int atomctrl_calculate_voltage_evv_on_sclk( *----------------------- */ - fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4,fSclk), fSM_A5)); + fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4, fSclk), fSM_A5)); fB_Term = fAdd(fAdd(fMultiply(fSM_A2, fSclk), fSM_A6), fMargin_RO_b); fC_Term = fAdd(fMargin_RO_c, fAdd(fMultiply(fSM_A0,fLkg_FT), - fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT,fSclk)), + fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT, fSclk)), fAdd(fMultiply(fSM_A3, fSclk), - fSubtract(fSM_A7,fRO_fused))))); + fSubtract(fSM_A7, fRO_fused))))); fVDDC_base = fSubtract(fRO_fused, fSubtract(fMargin_RO_c, fSubtract(fSM_A3, fMultiply(fSM_A1, fSclk)))); - fVDDC_base = fDivide(fVDDC_base, fAdd(fMultiply(fSM_A0,fSclk), fSM_A2)); + fVDDC_base = fDivide(fVDDC_base, fAdd(fMultiply(fSM_A0, fSclk), fSM_A2)); repeat = fSubtract(fVDDC_base, fDivide(fMargin_DC_sigma, ConvertToFraction(1000))); @@ -916,7 +947,7 @@ int atomctrl_calculate_voltage_evv_on_sclk( fSubtract(fRO_DC_margin, fSubtract(fSM_A3, fMultiply(fSM_A2, repeat)))); - fDC_SCLK = fDivide(fDC_SCLK, fAdd(fMultiply(fSM_A0,repeat), fSM_A1)); + fDC_SCLK = fDivide(fDC_SCLK, fAdd(fMultiply(fSM_A0, repeat), fSM_A1)); fSigma_DC = fSubtract(fSclk, fDC_SCLK); @@ -996,7 +1027,7 @@ int atomctrl_calculate_voltage_evv_on_sclk( fV_NL = fRoundUpByStepSize(fV_NL, fStepSize, 0); if (GreaterThan(fV_max, fV_NL) && - (GreaterThan(fV_NL,fEVV_V) || + (GreaterThan(fV_NL, fEVV_V) || Equal(fV_NL, fEVV_V))) { fV_NL = fMultiply(fV_NL, ConvertToFraction(1000)); @@ -1010,10 +1041,10 @@ int atomctrl_calculate_voltage_evv_on_sclk( } /** atomctrl_get_voltage_evv_on_sclk gets voltage via call to ATOM COMMAND table. - * @param hwmgr input: pointer to hwManager + * @param hwmgr input: pointer to hwManager * @param voltage_type input: type of EVV voltage VDDC or VDDGFX * @param sclk input: in 10Khz unit. DPM state SCLK frequency - * which is define in PPTable SCLK/VDDC dependence + * which is define in PPTable SCLK/VDDC dependence * table associated with this virtual_voltage_Id * @param virtual_voltage_Id input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08 * @param voltage output: real voltage level in unit of mv @@ -1205,3 +1236,69 @@ int atomctrl_read_efuse(void *device, uint16_t start_index, return result; } + +int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, + uint8_t level) +{ + DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters; + int result; + + memory_clock_parameters.asDPMMCReg.ulClock.ulClockFreq = memory_clock & SET_CLOCK_FREQ_MASK; + memory_clock_parameters.asDPMMCReg.ulClock.ulComputeClockFlag = ADJUST_MC_SETTING_PARAM; + memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level; + + result = cgs_atom_exec_cmd_table + (hwmgr->device, + GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings), + &memory_clock_parameters); + + return result; +} + +int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, + uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage) +{ + + int result; + GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space; + + get_voltage_info_param_space.ucVoltageType = voltage_type; + get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; + get_voltage_info_param_space.usVoltageLevel = virtual_voltage_Id; + get_voltage_info_param_space.ulSCLKFreq = sclk; + + result = cgs_atom_exec_cmd_table(hwmgr->device, + GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), + &get_voltage_info_param_space); + + if (0 != result) + return result; + + *voltage = get_voltage_info_param_space.usVoltageLevel; + + return result; +} + +int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table) +{ + + int i; + u8 frev, crev; + u16 size; + + ATOM_SMU_INFO_V2_1 *psmu_info = + (ATOM_SMU_INFO_V2_1 *)cgs_atom_get_data_table(hwmgr->device, + GetIndexIntoMasterTable(DATA, SMU_Info), + &size, &frev, &crev); + + + for (i = 0; i < psmu_info->ucSclkEntryNum; i++) { + table->entry[i].ucVco_setting = psmu_info->asSclkFcwRangeEntry[i].ucVco_setting; + table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv; + table->entry[i].usFcw_pcc = psmu_info->asSclkFcwRangeEntry[i].ucFcw_pcc; + table->entry[i].usFcw_trans_upper = psmu_info->asSclkFcwRangeEntry[i].ucFcw_trans_upper; + table->entry[i].usRcw_trans_lower = psmu_info->asSclkFcwRangeEntry[i].ucRcw_trans_lower; + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h index 627420b80a5f..d24ebb566905 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h @@ -101,6 +101,23 @@ struct pp_atomctrl_clock_dividers_vi { }; typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi; +struct pp_atomctrl_clock_dividers_ai { + u16 usSclk_fcw_frac; + u16 usSclk_fcw_int; + u8 ucSclkPostDiv; + u8 ucSclkVcoMode; + u8 ucSclkPllRange; + u8 ucSscEnable; + u16 usSsc_fcw1_frac; + u16 usSsc_fcw1_int; + u16 usReserved; + u16 usPcc_fcw_int; + u16 usSsc_fcw_slew_frac; + u16 usPcc_fcw_slew_frac; +}; +typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai; + + union pp_atomctrl_s_mpll_fb_divider { struct { uint32_t cl_kf : 12; @@ -204,6 +221,21 @@ struct pp_atomctrl_mc_register_address { typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address; +#define MAX_SCLK_RANGE 8 + +struct pp_atom_ctrl_sclk_range_table_entry{ + uint8_t ucVco_setting; + uint8_t ucPostdiv; + uint16_t usFcw_pcc; + uint16_t usFcw_trans_upper; + uint16_t usRcw_trans_lower; +}; + + +struct pp_atom_ctrl_sclk_range_table{ + struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE]; +}; + struct pp_atomctrl_mc_reg_table { uint8_t last; /* number of registers */ uint8_t num_entries; /* number of AC timing entries */ @@ -240,7 +272,11 @@ extern int atomctrl_read_efuse(void *device, uint16_t start_index, uint16_t end_index, uint32_t mask, uint32_t *efuse); extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug); - - +extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers); +extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, + uint8_t level); +extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, + uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); +extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); #endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h index b10df328d58c..009bd5963ed8 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h @@ -127,8 +127,8 @@ fInt fExponential(fInt exponent) /*Can be used to calculate e^exponent*/ fInt solution = fPositiveOne; /*Starting off with baseline of 1 */ fInt error_term; - uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78}; - uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078}; + static const uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78}; + static const uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078}; if (GreaterThan(fZERO, exponent)) { exponent = fNegate(exponent); @@ -162,8 +162,8 @@ fInt fNaturalLog(fInt value) fInt solution = ConvertToFraction(0); /*Starting off with baseline of 0 */ fInt error_term; - uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078}; - uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78}; + static const uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078}; + static const uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78}; while (GreaterThan(fAdd(value, fNegativeOne), upper_bound)) { for (i = 0; i < 10; i++) { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 0d5d8372953e..1faad92b50d3 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c @@ -51,6 +51,9 @@ #include "bif/bif_5_0_d.h" #include "bif/bif_5_0_sh_mask.h" +#include "dce/dce_10_0_d.h" +#include "dce/dce_10_0_sh_mask.h" + #include "cgs_linux.h" #include "eventmgr.h" #include "amd_pcie_helpers.h" @@ -86,17 +89,17 @@ typedef uint32_t PECI_RegistryValue; /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */ -uint16_t PP_ClockStretcherLookupTable[2][4] = { +static const uint16_t PP_ClockStretcherLookupTable[2][4] = { {600, 1050, 3, 0}, {600, 1050, 6, 1} }; /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */ -uint32_t PP_ClockStretcherDDTTable[2][4][4] = { +static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ -uint8_t PP_ClockStretchAmountConversion[2][6] = { +static const uint8_t PP_ClockStretchAmountConversion[2][6] = { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} }; @@ -110,7 +113,7 @@ enum DPM_EVENT_SRC { }; typedef enum DPM_EVENT_SRC DPM_EVENT_SRC; -const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic); +static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic); struct tonga_power_state *cast_phw_tonga_power_state( struct pp_hw_power_state *hw_ps) @@ -429,19 +432,20 @@ int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr) } } } - PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk - (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, - virtual_voltage_id, &vddgfx), - "Error retrieving EVV voltage value!", continue); + if (0 == atomctrl_get_voltage_evv_on_sclk + (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, + virtual_voltage_id, &vddgfx)) { + /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ + PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1); - /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ - PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1); - - /* the voltage should not be zero nor equal to leakage ID */ - if (vddgfx != 0 && vddgfx != virtual_voltage_id) { - data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; - data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id; - data->vddcgfx_leakage.count++; + /* the voltage should not be zero nor equal to leakage ID */ + if (vddgfx != 0 && vddgfx != virtual_voltage_id) { + data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; + data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id; + data->vddcgfx_leakage.count++; + } + } else { + printk("Error retrieving EVV voltage value!\n"); } } } else { @@ -449,20 +453,20 @@ int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr) if (0 == tonga_get_sclk_for_voltage_evv(hwmgr, pptable_info->vddc_lookup_table, virtual_voltage_id, &sclk)) { - PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk - (hwmgr, VOLTAGE_TYPE_VDDC, sclk, - virtual_voltage_id, &vddc), - "Error retrieving EVV voltage value!", continue); + if (0 == atomctrl_get_voltage_evv_on_sclk + (hwmgr, VOLTAGE_TYPE_VDDC, sclk, + virtual_voltage_id, &vddc)) { + /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ + PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1); - /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ - if (vddc > 2000) - printk(KERN_ERR "[ powerplay ] Invalid VDDC value! \n"); - - /* the voltage should not be zero nor equal to leakage ID */ - if (vddc != 0 && vddc != virtual_voltage_id) { - data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; - data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; - data->vddc_leakage.count++; + /* the voltage should not be zero nor equal to leakage ID */ + if (vddc != 0 && vddc != virtual_voltage_id) { + data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; + data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; + data->vddc_leakage.count++; + } + } else { + printk("Error retrieving EVV voltage value!\n"); } } } @@ -2037,14 +2041,11 @@ static int tonga_populate_single_memory_level( data->display_timing.num_existing_displays = info.display_count; if ((data->mclk_stutter_mode_threshold != 0) && - (memory_clock <= data->mclk_stutter_mode_threshold) && - (data->is_uvd_enabled == 0) -#if defined(LINUX) - && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) - && (data->display_timing.num_existing_displays <= 2) - && (data->display_timing.num_existing_displays != 0) -#endif - ) + (memory_clock <= data->mclk_stutter_mode_threshold) && + (data->is_uvd_enabled == 0) + && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) + && (data->display_timing.num_existing_displays <= 2) + && (data->display_timing.num_existing_displays != 0)) memory_level->StutterEnable = 1; /* decide strobe mode*/ @@ -2415,6 +2416,24 @@ int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, return 0; } +static uint8_t tonga_get_sleep_divider_id_from_clock(uint32_t engine_clock, + uint32_t min_engine_clock_in_sr) +{ + uint32_t i, temp; + uint32_t min = max(min_engine_clock_in_sr, (uint32_t)TONGA_MINIMUM_ENGINE_CLOCK); + + PP_ASSERT_WITH_CODE((engine_clock >= min), + "Engine clock can't satisfy stutter requirement!", return 0); + + for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) { + temp = engine_clock >> i; + + if(temp >= min || i == 0) + break; + } + return (uint8_t)i; +} + /** * Populates single SMC SCLK structure using the provided engine clock * @@ -2463,12 +2482,12 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t *get the DAL clock. do it in funture. PECI_GetMinClockSettings(hwmgr->peci, &minClocks); data->display_timing.min_clock_insr = minClocks.engineClockInSR; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) - { - graphic_level->DeepSleepDivId = PhwTonga_GetSleepDividerIdFromClock(hwmgr, engine_clock, minClocks.engineClockInSR); - } */ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep)) + graphic_level->DeepSleepDivId = + tonga_get_sleep_divider_id_from_clock(engine_clock, + data->display_timing.min_clock_insr); /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/ graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; @@ -2663,7 +2682,7 @@ static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) struct TONGA_DLL_SPEED_SETTING { uint16_t Min; /* Minimum Data Rate*/ uint16_t Max; /* Maximum Data Rate*/ - uint32_t dll_speed; /* The desired DLL_SPEED setting*/ + uint32_t dll_speed; /* The desired DLL_SPEED setting*/ }; static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) @@ -3296,14 +3315,14 @@ static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr) pptable_info->vdd_dep_on_mclk; PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, - "VDD dependency on SCLK table is missing. \ + "VDD dependency on SCLK table is missing. \ This table is mandatory", return -1); PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, - "VDD dependency on SCLK table has to have is missing. \ + "VDD dependency on SCLK table has to have is missing. \ This table is mandatory", return -1); PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, - "VDD dependency on MCLK table is missing. \ + "VDD dependency on MCLK table is missing. \ This table is mandatory", return -1); PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, "VDD dependency on MCLK table has to have is missing. \ @@ -4424,17 +4443,14 @@ int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr) int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; + struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); + + if (data->soft_pp_table) { + kfree(data->soft_pp_table); + data->soft_pp_table = NULL; } - if (NULL != hwmgr->backend) { - kfree(hwmgr->backend); - hwmgr->backend = NULL; - } - - return 0; + return phm_hwmgr_backend_fini(hwmgr); } /** @@ -5874,7 +5890,7 @@ uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr) if (!fw_info) return 0; - reference_clock = le16_to_cpu(fw_info->usMinPixelClockPLL_Output); + reference_clock = le16_to_cpu(fw_info->usReferenceClock); divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); @@ -6039,24 +6055,40 @@ static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table) { struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); - *table = (char *)&data->smc_state_table; + if (!data->soft_pp_table) { + data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL); + if (!data->soft_pp_table) + return -ENOMEM; + memcpy(data->soft_pp_table, hwmgr->soft_pp_table, + hwmgr->soft_pp_table_size); + } - return sizeof(struct SMU72_Discrete_DpmTable); + *table = (char *)&data->soft_pp_table; + + return hwmgr->soft_pp_table_size; } static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size) { struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); - void *table = (void *)&data->smc_state_table; + if (!data->soft_pp_table) { + data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL); + if (!data->soft_pp_table) + return -ENOMEM; + } - memcpy(table, buf, size); + memcpy(data->soft_pp_table, buf, size); + + hwmgr->soft_pp_table = data->soft_pp_table; + + /* TODO: re-init powerplay to implement modified pptable */ return 0; } static int tonga_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); @@ -6068,20 +6100,28 @@ static int tonga_force_clock_level(struct pp_hwmgr *hwmgr, if (!data->sclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); break; case PP_MCLK: if (!data->mclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); break; case PP_PCIE: + { + uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; + uint32_t level = 0; + + while (tmp >>= 1) + level++; + if (!data->pcie_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_PCIeDPM_ForceLevel, - (1 << level)); + level); break; + } default: break; } @@ -6173,6 +6213,7 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = { .powergate_uvd = tonga_phm_powergate_uvd, .powergate_vce = tonga_phm_powergate_vce, .disable_clock_power_gating = tonga_phm_disable_clock_power_gating, + .update_clock_gatings = tonga_phm_update_clock_gatings, .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment, .display_config_changed = tonga_display_configuration_changed_task, .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h index f88d3bbe6671..573cd39fe78d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h @@ -74,7 +74,7 @@ struct tonga_power_state { }; struct _phw_tonga_dpm_level { - bool enabled; + bool enabled; uint32_t value; uint32_t param1; }; @@ -237,20 +237,20 @@ struct tonga_hwmgr { irq_handler_func_t ctf_callback; void *ctf_context; - phw_tonga_clock_registers clock_registers; + phw_tonga_clock_registers clock_registers; phw_tonga_voltage_smio_registers voltage_smio_registers; - bool is_memory_GDDR5; + bool is_memory_GDDR5; uint16_t acpi_vddc; - bool pspp_notify_required; /* Flag to indicate if PSPP notification to SBIOS is required */ + bool pspp_notify_required; /* Flag to indicate if PSPP notification to SBIOS is required */ uint16_t force_pcie_gen; /* The forced PCI-E speed if not 0xffff */ uint16_t acpi_pcie_gen; /* The PCI-E speed at ACPI time */ uint32_t pcie_gen_cap; /* The PCI-E speed capabilities bitmap from CAIL */ uint32_t pcie_lane_cap; /* The PCI-E lane capabilities bitmap from CAIL */ uint32_t pcie_spc_cap; /* Symbol Per Clock Capabilities from registry */ - phw_tonga_leakage_voltage vddc_leakage; /* The Leakage VDDC supported (based on leakage ID).*/ - phw_tonga_leakage_voltage vddcgfx_leakage; /* The Leakage VDDC supported (based on leakage ID). */ - phw_tonga_leakage_voltage vddci_leakage; /* The Leakage VDDCI supported (based on leakage ID). */ + phw_tonga_leakage_voltage vddc_leakage; /* The Leakage VDDC supported (based on leakage ID).*/ + phw_tonga_leakage_voltage vddcgfx_leakage; /* The Leakage VDDC supported (based on leakage ID). */ + phw_tonga_leakage_voltage vddci_leakage; /* The Leakage VDDCI supported (based on leakage ID). */ uint32_t mvdd_control; uint32_t vddc_mask_low; @@ -263,8 +263,8 @@ struct tonga_hwmgr { uint32_t mclk_stutter_mode_threshold; uint32_t mclk_edc_enable_threshold; uint32_t mclk_edc_wr_enable_threshold; - bool is_uvd_enabled; - bool is_xdma_enabled; + bool is_uvd_enabled; + bool is_xdma_enabled; phw_tonga_vbios_boot_state vbios_boot_state; bool battery_state; @@ -353,6 +353,8 @@ struct tonga_hwmgr { bool acp_power_gated; /* 1: gated, 0:not gated */ bool pg_acp_init; + /* soft pptable for re-uploading into smu */ + void *soft_pp_table; }; typedef struct tonga_hwmgr tonga_hwmgr; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h index 9a4456e6521b..1b44f4e9b8f5 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h @@ -209,6 +209,20 @@ typedef struct _ATOM_Tonga_PCIE_Table { ATOM_Tonga_PCIE_Record entries[1]; /* Dynamically allocate entries. */ } ATOM_Tonga_PCIE_Table; +typedef struct _ATOM_Polaris10_PCIE_Record { + UCHAR ucPCIEGenSpeed; + UCHAR usPCIELaneWidth; + UCHAR ucReserved[2]; + ULONG ulPCIE_Sclk; +} ATOM_Polaris10_PCIE_Record; + +typedef struct _ATOM_Polaris10_PCIE_Table { + UCHAR ucRevId; + UCHAR ucNumEntries; /* Number of entries. */ + ATOM_Polaris10_PCIE_Record entries[1]; /* Dynamically allocate entries. */ +} ATOM_Polaris10_PCIE_Table; + + typedef struct _ATOM_Tonga_MM_Dependency_Record { UCHAR ucVddcInd; /* VDDC voltage */ USHORT usVddgfxOffset; /* Offset relative to VDDC voltage */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c index b156481b50e8..10e3630ee39d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c @@ -138,12 +138,15 @@ const void *get_powerplay_table(struct pp_hwmgr *hwmgr) u16 size; u8 frev, crev; - void *table_address; + void *table_address = (void *)hwmgr->soft_pp_table; - table_address = (ATOM_Tonga_POWERPLAYTABLE *) - cgs_atom_get_data_table(hwmgr->device, index, &size, &frev, &crev); - - hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ + if (!table_address) { + table_address = (ATOM_Tonga_POWERPLAYTABLE *) + cgs_atom_get_data_table(hwmgr->device, + index, &size, &frev, &crev); + hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ + hwmgr->soft_pp_table_size = size; + } return table_address; } @@ -448,48 +451,91 @@ static int get_sclk_voltage_dependency_table( static int get_pcie_table( struct pp_hwmgr *hwmgr, phm_ppt_v1_pcie_table **pp_tonga_pcie_table, - const ATOM_Tonga_PCIE_Table * atom_pcie_table + const PPTable_Generic_SubTable_Header * pTable ) { uint32_t table_size, i, pcie_count; phm_ppt_v1_pcie_table *pcie_table; struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable); - PP_ASSERT_WITH_CODE((0 != atom_pcie_table->ucNumEntries), - "Invalid PowerPlay Table!", return -1); - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries; + if (pTable->ucRevId < 1) { + const ATOM_Tonga_PCIE_Table *atom_pcie_table = (ATOM_Tonga_PCIE_Table *)pTable; + PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), + "Invalid PowerPlay Table!", return -1); - pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL); + table_size = sizeof(uint32_t) + + sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries; - if (NULL == pcie_table) - return -ENOMEM; + pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL); - memset(pcie_table, 0x00, table_size); + if (pcie_table == NULL) + return -ENOMEM; - /* - * Make sure the number of pcie entries are less than or equal to sclk dpm levels. - * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1. - */ - pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1; - if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) - pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; - else - printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ - Disregarding the excess entries... \n"); + memset(pcie_table, 0x00, table_size); - pcie_table->count = pcie_count; + /* + * Make sure the number of pcie entries are less than or equal to sclk dpm levels. + * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1. + */ + pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1; + if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) + pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; + else + printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ + Disregarding the excess entries... \n"); - for (i = 0; i < pcie_count; i++) { - pcie_table->entries[i].gen_speed = - atom_pcie_table->entries[i].ucPCIEGenSpeed; - pcie_table->entries[i].lane_width = - atom_pcie_table->entries[i].usPCIELaneWidth; + pcie_table->count = pcie_count; + + for (i = 0; i < pcie_count; i++) { + pcie_table->entries[i].gen_speed = + atom_pcie_table->entries[i].ucPCIEGenSpeed; + pcie_table->entries[i].lane_width = + atom_pcie_table->entries[i].usPCIELaneWidth; + } + + *pp_tonga_pcie_table = pcie_table; + } else { + /* Polaris10/Polaris11 and newer. */ + const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)pTable; + PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), + "Invalid PowerPlay Table!", return -1); + + table_size = sizeof(uint32_t) + + sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries; + + pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL); + + if (pcie_table == NULL) + return -ENOMEM; + + memset(pcie_table, 0x00, table_size); + + /* + * Make sure the number of pcie entries are less than or equal to sclk dpm levels. + * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1. + */ + pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1; + if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) + pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; + else + printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ + Disregarding the excess entries... \n"); + + pcie_table->count = pcie_count; + + for (i = 0; i < pcie_count; i++) { + pcie_table->entries[i].gen_speed = + atom_pcie_table->entries[i].ucPCIEGenSpeed; + pcie_table->entries[i].lane_width = + atom_pcie_table->entries[i].usPCIELaneWidth; + pcie_table->entries[i].pcie_sclk = + atom_pcie_table->entries[i].ulPCIE_Sclk; + } + + *pp_tonga_pcie_table = pcie_table; } - *pp_tonga_pcie_table = pcie_table; - return 0; } @@ -668,8 +714,8 @@ static int init_clock_voltage_dependency( const ATOM_Tonga_Hard_Limit_Table *pHardLimits = (const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) + le16_to_cpu(powerplay_table->usHardLimitTableOffset)); - const ATOM_Tonga_PCIE_Table *pcie_table = - (const ATOM_Tonga_PCIE_Table *)(((unsigned long) powerplay_table) + + const PPTable_Generic_SubTable_Header *pcie_table = + (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) + le16_to_cpu(powerplay_table->usPCIETableOffset)); pp_table_information->vdd_dep_on_sclk = NULL; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c index a188174747c9..47ef1ca2d78b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c @@ -195,8 +195,8 @@ int tonga_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed) if (0 == duty100) return -EINVAL; - tmp64 = (uint64_t)speed * 100; - do_div(tmp64, duty100); + tmp64 = (uint64_t)speed * duty100; + do_div(tmp64, 100); duty = (uint32_t)tmp64; PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL0, FDO_STATIC_DUTY, duty); @@ -525,7 +525,7 @@ static int tf_tonga_thermal_disable_alert(struct pp_hwmgr *hwmgr, void *input, v return tonga_thermal_disable_alert(hwmgr); } -static struct phm_master_table_item tonga_thermal_start_thermal_controller_master_list[] = { +static const struct phm_master_table_item tonga_thermal_start_thermal_controller_master_list[] = { { NULL, tf_tonga_thermal_initialize }, { NULL, tf_tonga_thermal_set_temperature_range }, { NULL, tf_tonga_thermal_enable_alert }, @@ -538,20 +538,20 @@ static struct phm_master_table_item tonga_thermal_start_thermal_controller_maste { NULL, NULL } }; -static struct phm_master_table_header tonga_thermal_start_thermal_controller_master = { +static const struct phm_master_table_header tonga_thermal_start_thermal_controller_master = { 0, PHM_MasterTableFlag_None, tonga_thermal_start_thermal_controller_master_list }; -static struct phm_master_table_item tonga_thermal_set_temperature_range_master_list[] = { +static const struct phm_master_table_item tonga_thermal_set_temperature_range_master_list[] = { { NULL, tf_tonga_thermal_disable_alert}, { NULL, tf_tonga_thermal_set_temperature_range}, { NULL, tf_tonga_thermal_enable_alert}, { NULL, NULL } }; -struct phm_master_table_header tonga_thermal_set_temperature_range_master = { +static const struct phm_master_table_header tonga_thermal_set_temperature_range_master = { 0, PHM_MasterTableFlag_None, tonga_thermal_set_temperature_range_master_list diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 7255f7ddf93a..50b367d44307 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -289,6 +289,9 @@ struct pp_states_info { #define PP_BLOCK_GFX_CG 0x01 #define PP_BLOCK_GFX_MG 0x02 +#define PP_BLOCK_GFX_3D 0x04 +#define PP_BLOCK_GFX_RLC 0x08 +#define PP_BLOCK_GFX_CP 0x10 #define PP_BLOCK_SYS_BIF 0x01 #define PP_BLOCK_SYS_MC 0x02 #define PP_BLOCK_SYS_ROM 0x04 @@ -337,7 +340,7 @@ struct amd_powerplay_funcs { int (*get_pp_num_states)(void *handle, struct pp_states_info *data); int (*get_pp_table)(void *handle, char **table); int (*set_pp_table)(void *handle, const char *buf, size_t size); - int (*force_clock_level)(void *handle, enum pp_clock_type type, int level); + int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); }; diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h index 10437dcfd365..d63ef83b2628 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h @@ -37,7 +37,7 @@ typedef int (*pem_event_action)(struct pp_eventmgr *eventmgr, struct action_chain { const char *description; /* action chain description for debugging purpose */ - const pem_event_action **action_chain; /* pointer to chain of event actions */ + const pem_event_action * const *action_chain; /* pointer to chain of event actions */ }; struct pem_power_source_ui_state_info { diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h index 0262ad35502a..8a31665321a8 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h +++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h @@ -46,7 +46,7 @@ struct PWR_Command_Table typedef struct PWR_Command_Table PWR_Command_Table; #define PWR_VIRUS_TABLE_SIZE 10243 -static PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] = +static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] = { { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX }, { PwrCmdWrite, 0x00000000, mmPCIE_DATA }, diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h index 040d3f7cbf49..56f712c7d07a 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h @@ -211,6 +211,7 @@ enum phm_platform_caps { PHM_PlatformCaps_ClockStretcher, PHM_PlatformCaps_TablelessHardwareInterface, PHM_PlatformCaps_EnableDriverEVV, + PHM_PlatformCaps_SPLLShutdownSupport, PHM_PlatformCaps_Max }; diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 928f5a740cba..fd4ce7aaeee9 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -141,7 +141,7 @@ enum phm_master_table_flag { struct phm_master_table_header { uint32_t storage_size; uint32_t flags; - struct phm_master_table_item *master_list; + const struct phm_master_table_item *master_list; }; struct phm_runtime_table_header { @@ -199,7 +199,7 @@ extern int phm_dispatch_table(struct pp_hwmgr *hwmgr, void *input, void *output); extern int phm_construct_table(struct pp_hwmgr *hwmgr, - struct phm_master_table_header *master_table, + const struct phm_master_table_header *master_table, struct phm_runtime_table_header *rt_table); extern int phm_destroy_table(struct pp_hwmgr *hwmgr, @@ -335,8 +335,9 @@ struct pp_hwmgr_func { int (*power_off_asic)(struct pp_hwmgr *hwmgr); int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table); int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size); - int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, int level); + int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); + int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable); }; struct pp_table_func { @@ -499,7 +500,7 @@ struct phm_dynamic_state_info { struct phm_ppm_table *ppm_parameter_table; struct phm_cac_tdp_table *cac_dtp_table; struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; - struct phm_vq_budgeting_table *vq_budgeting_table; + struct phm_vq_budgeting_table *vq_budgeting_table; }; struct pp_fan_info { @@ -576,6 +577,7 @@ struct pp_hwmgr { void *device; struct pp_smumgr *smumgr; const void *soft_pp_table; + uint32_t soft_pp_table_size; bool need_pp_table_upload; enum amd_dpm_forced_level dpm_level; bool block_hw_access; diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h new file mode 100644 index 000000000000..0c6a413eaa5b --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h @@ -0,0 +1,409 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef POLARIS10_PP_SMC_H +#define POLARIS10_PP_SMC_H + + +#pragma pack(push, 1) + + +#define PPSMC_SWSTATE_FLAG_DC 0x01 +#define PPSMC_SWSTATE_FLAG_UVD 0x02 +#define PPSMC_SWSTATE_FLAG_VCE 0x04 + +#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 +#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 +#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff + +#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 +#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 +#define PPSMC_SYSTEMFLAG_GDDR5 0x04 + +#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 + +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 +#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 + + +#define PPSMC_DPM2FLAGS_TDPCLMP 0x01 +#define PPSMC_DPM2FLAGS_PWRSHFT 0x02 +#define PPSMC_DPM2FLAGS_OCP 0x04 + + +#define PPSMC_DISPLAY_WATERMARK_LOW 0 +#define PPSMC_DISPLAY_WATERMARK_HIGH 1 + + +#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 +#define PPSMC_STATEFLAG_POWERBOOST 0x02 +#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 +#define PPSMC_STATEFLAG_POWERSHIFT 0x08 +#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 +#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 +#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 + + +#define FDO_MODE_HARDWARE 0 +#define FDO_MODE_PIECE_WISE_LINEAR 1 + +enum FAN_CONTROL { + FAN_CONTROL_FUZZY, + FAN_CONTROL_TABLE +}; + + +#define PPSMC_Result_OK ((uint16_t)0x01) +#define PPSMC_Result_NoMore ((uint16_t)0x02) + +#define PPSMC_Result_NotNow ((uint16_t)0x03) +#define PPSMC_Result_Failed ((uint16_t)0xFF) +#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) +#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) + +typedef uint16_t PPSMC_Result; + +#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) + + +#define PPSMC_MSG_Halt ((uint16_t)0x10) +#define PPSMC_MSG_Resume ((uint16_t)0x11) +#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) +#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) +#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) +#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) +#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) +#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) +#define PPSMC_MSG_LevelUp ((uint16_t)0x18) +#define PPSMC_MSG_LevelDown ((uint16_t)0x19) +#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) +#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) +#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) +#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) +#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) +#define PPSMC_MSG_ForceHigh ((uint16_t)0x42) +#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) +#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) +#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) +#define PPSMC_MSG_EnableCac ((uint16_t)0x53) +#define PPSMC_MSG_DisableCac ((uint16_t)0x54) +#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) +#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) +#define PPSMC_CACHistoryStart ((uint16_t)0x57) +#define PPSMC_CACHistoryStop ((uint16_t)0x58) +#define PPSMC_TDPClampingActive ((uint16_t)0x59) +#define PPSMC_TDPClampingInactive ((uint16_t)0x5A) +#define PPSMC_StartFanControl ((uint16_t)0x5B) +#define PPSMC_StopFanControl ((uint16_t)0x5C) +#define PPSMC_NoDisplay ((uint16_t)0x5D) +#define PPSMC_HasDisplay ((uint16_t)0x5E) +#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) +#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) +#define PPSMC_MSG_EnableULV ((uint16_t)0x62) +#define PPSMC_MSG_DisableULV ((uint16_t)0x63) +#define PPSMC_MSG_EnterULV ((uint16_t)0x64) +#define PPSMC_MSG_ExitULV ((uint16_t)0x65) +#define PPSMC_PowerShiftActive ((uint16_t)0x6A) +#define PPSMC_PowerShiftInactive ((uint16_t)0x6B) +#define PPSMC_OCPActive ((uint16_t)0x6C) +#define PPSMC_OCPInactive ((uint16_t)0x6D) +#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) +#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) +#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) +#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) +#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) +#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) +#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) +#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) +#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) +#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) +#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) +#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) +#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) +#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) +#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) +#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) + +#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) +#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) +#define PPSMC_FlushDataCache ((uint16_t)0x80) +#define PPSMC_FlushInstrCache ((uint16_t)0x81) + +#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) +#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) + +#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) + +#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) +#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) +#define PPSMC_MSG_EnableDTE ((uint16_t)0x87) +#define PPSMC_MSG_DisableDTE ((uint16_t)0x88) + +#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) +#define PPSM_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A) +#define PPSM_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B) +#define PPSM_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C) + +#define PPSMC_MSG_BREAK ((uint16_t)0xF8) + +#define PPSMC_MSG_Test ((uint16_t) 0x100) +#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) +#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) +#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) +#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) +#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) +#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) +#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) +#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) +#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) +#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) +#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) +#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) +#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) +#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) +#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) +#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) +#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) +#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) +#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) +#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) +#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) +#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) +#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) +#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) +#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) +#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) +#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) +#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) +#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) +#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) +#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) +#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) +#define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125) +#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) +#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) +#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) + +#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) +#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) +#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) +#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) +#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) +#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) +#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) +#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) +#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) +#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) +#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) +#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) +#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) +#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) +#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) +#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) +#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) +#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) +#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) +#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) +#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) +#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) +#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) +#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) +#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) +#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) +#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) +#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) +#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) +#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) +#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) +#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) +#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) +#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) +#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) +#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) +#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) + +#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) +#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) +#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) +#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) +#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152) +#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153) +#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) +#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) +#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) +#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) +#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) +#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) +#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) +#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) +#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c) +#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) +#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) +#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) +#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) +#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) +#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) +#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) +#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) +#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) +#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) +#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) +#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) +#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) +#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) +#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) +#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c) +#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d) +#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e) +#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f) +#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) +#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) +#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) +#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) +#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) +#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) +#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) +#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) +#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) +#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) +#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) +#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) +#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) +#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) +#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) +#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) +#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) +#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) +#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) +#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) +#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) +#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) +#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) +#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) +#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) +#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) +#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) +#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) +#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) +#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) +#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) +#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) +#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) +#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) +#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) +#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) +#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) +#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) +#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) +#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) +#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) +#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) +#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) +#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) +#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) +#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) +#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) + +#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) +#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) +#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) +#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) +#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) +#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) +#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) +#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) +#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) + +#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) +#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) +#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) +#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) +#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) +#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) +#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) + +#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) +#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) +#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) +#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) +#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) +#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) +#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) +#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) +#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) +#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) +#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) +#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) +#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) +#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) +#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) +#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) +#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) +#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) +#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) +#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) +#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) +#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) +#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) +#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) +#define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A) +#define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B) + +#define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C) +#define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x275) +#define PPSMC_MSG_UseNewGPIOScheme ((uint16_t) 0x277) +#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400) +#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401) +#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402) +#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403) +#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404) + +#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280) +#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281) +#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282) + +#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300) +#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301) + +#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600) +#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601) +#define PPSMC_MSG_SetAddress ((uint16_t) 0x800) +#define PPSMC_MSG_GetData ((uint16_t) 0x801) +#define PPSMC_MSG_SetData ((uint16_t) 0x802) + +typedef uint16_t PPSMC_Msg; + +#define PPSMC_EVENT_STATUS_THERMAL 0x00000001 +#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 +#define PPSMC_EVENT_STATUS_DC 0x00000004 + +#pragma pack(pop) + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h new file mode 100644 index 000000000000..f497e7d98e6d --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h @@ -0,0 +1,10088 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _POLARIS10_PWRVIRUS_H +#define _POLARIS10_PWRVIRUS_H + +#define mmSMC_IND_INDEX_11 0x01AC +#define mmSMC_IND_DATA_11 0x01AD +#define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a +#define mmCP_HYP_MEC1_UCODE_DATA 0xf81b +#define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c +#define mmCP_HYP_MEC2_UCODE_DATA 0xf81d + +enum PWR_Command { + PwrCmdNull = 0, + PwrCmdWrite, + PwrCmdEnd, + PwrCmdMax +}; + +typedef enum PWR_Command PWR_Command; + +struct PWR_Command_Table { + PWR_Command command; + uint32_t data; + uint32_t reg; +}; + +typedef struct PWR_Command_Table PWR_Command_Table; + + +#define PWR_VIRUS_TABLE_SIZE 10031 + +static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = { + { PwrCmdWrite, 0x00000000, mmRLC_CNTL }, + { PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL }, + { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL }, + { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL }, + { PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL }, + { PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE }, + { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG }, + { PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO }, + { PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI }, + { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR }, + { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR }, + { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdEnd, 0x00000000, 0x00000000 }, +}; + + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74.h b/drivers/gpu/drm/amd/powerplay/inc/smu74.h new file mode 100644 index 000000000000..1a12d85b8e97 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu74.h @@ -0,0 +1,774 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#ifndef SMU74_H +#define SMU74_H + +#pragma pack(push, 1) + +#define SMU__DGPU_ONLY + +#define SMU__NUM_SCLK_DPM_STATE 8 +#define SMU__NUM_MCLK_DPM_LEVELS 4 +#define SMU__NUM_LCLK_DPM_LEVELS 8 +#define SMU__NUM_PCIE_DPM_LEVELS 8 + +enum SID_OPTION { + SID_OPTION_HI, + SID_OPTION_LO, + SID_OPTION_COUNT +}; + +enum Poly3rdOrderCoeff { + LEAKAGE_TEMPERATURE_SCALAR, + LEAKAGE_VOLTAGE_SCALAR, + DYNAMIC_VOLTAGE_SCALAR, + POLY_3RD_ORDER_COUNT +}; + +struct SMU7_Poly3rdOrder_Data { + int32_t a; + int32_t b; + int32_t c; + int32_t d; + uint8_t a_shift; + uint8_t b_shift; + uint8_t c_shift; + uint8_t x_shift; +}; + +typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; + +struct Power_Calculator_Data { + uint16_t NoLoadVoltage; + uint16_t LoadVoltage; + uint16_t Resistance; + uint16_t Temperature; + uint16_t BaseLeakage; + uint16_t LkgTempScalar; + uint16_t LkgVoltScalar; + uint16_t LkgAreaScalar; + uint16_t LkgPower; + uint16_t DynVoltScalar; + uint32_t Cac; + uint32_t DynPower; + uint32_t TotalCurrent; + uint32_t TotalPower; +}; + +typedef struct Power_Calculator_Data PowerCalculatorData_t; + +struct Gc_Cac_Weight_Data { + uint8_t index; + uint32_t value; +}; + +typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; + + +typedef struct { + uint32_t high; + uint32_t low; +} data_64_t; + +typedef struct { + data_64_t high; + data_64_t low; +} data_128_t; + +#define SMU7_CONTEXT_ID_SMC 1 +#define SMU7_CONTEXT_ID_VBIOS 2 + +#define SMU74_MAX_LEVELS_VDDC 16 +#define SMU74_MAX_LEVELS_VDDGFX 16 +#define SMU74_MAX_LEVELS_VDDCI 8 +#define SMU74_MAX_LEVELS_MVDD 4 + +#define SMU_MAX_SMIO_LEVELS 4 + +#define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */ +#define SMU74_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */ +#define SMU74_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */ +#define SMU74_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes */ +#define SMU74_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD */ +#define SMU74_MAX_LEVELS_VCE 8 /* ECLK levels for VCE */ +#define SMU74_MAX_LEVELS_ACP 8 /* ACLK levels for ACP */ +#define SMU74_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU */ +#define SMU74_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table */ + +#define DPM_NO_LIMIT 0 +#define DPM_NO_UP 1 +#define DPM_GO_DOWN 2 +#define DPM_GO_UP 3 + +#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 +#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 + +#define GPIO_CLAMP_MODE_VRHOT 1 +#define GPIO_CLAMP_MODE_THERM 2 +#define GPIO_CLAMP_MODE_DC 4 + +#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 +#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<backend); priv->avfs.AvfsBtcStatus = AVFS_LOAD_VIRUS; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c new file mode 100644 index 000000000000..de618ead9db8 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -0,0 +1,984 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "smumgr.h" +#include "smu74.h" +#include "smu_ucode_xfer_vi.h" +#include "polaris10_smumgr.h" +#include "smu74_discrete.h" +#include "smu/smu_7_1_3_d.h" +#include "smu/smu_7_1_3_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" +#include "oss/oss_3_0_d.h" +#include "gca/gfx_8_0_d.h" +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" +#include "polaris10_pwrvirus.h" +#include "ppatomctrl.h" +#include "pp_debug.h" +#include "cgs_common.h" + +#define POLARIS10_SMC_SIZE 0x20000 +#define VOLTAGE_SCALE 4 + +/* Microcode file is stored in this buffer */ +#define BUFFER_SIZE 80000 +#define MAX_STRING_SIZE 15 +#define BUFFER_SIZETWO 131072 /* 128 *1024 */ + +#define SMC_RAM_END 0x40000 + +static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { + /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */ + /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */ + { 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } }, + { 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } }, + { 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } } +}; + +static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = + {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00}; + +/** +* Set the address for reading/writing the SMC SRAM space. +* @param smumgr the address of the powerplay hardware manager. +* @param smcAddress the address in the SMC RAM to access. +*/ +static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) +{ + PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); + PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); + + cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr); + SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); + + return 0; +} + +/** +* Copy bytes from SMC RAM space into driver memory. +* +* @param smumgr the address of the powerplay SMU manager. +* @param smc_start_address the start address in the SMC RAM to copy bytes from +* @param src the byte array to copy the bytes to. +* @param byte_count the number of bytes to copy. +*/ +int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) +{ + uint32_t data; + uint32_t addr; + uint8_t *dest_byte; + uint8_t i, data_byte[4] = {0}; + uint32_t *pdata = (uint32_t *)&data_byte; + + PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;); + PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1); + + addr = smc_start_address; + + while (byte_count >= 4) { + polaris10_read_smc_sram_dword(smumgr, addr, &data, limit); + + *dest = PP_SMC_TO_HOST_UL(data); + + dest += 1; + byte_count -= 4; + addr += 4; + } + + if (byte_count) { + polaris10_read_smc_sram_dword(smumgr, addr, &data, limit); + *pdata = PP_SMC_TO_HOST_UL(data); + /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */ + dest_byte = (uint8_t *)dest; + for (i = 0; i < byte_count; i++) + dest_byte[i] = data_byte[i]; + } + + return 0; +} + +/** +* Copy bytes from an array into the SMC RAM space. +* +* @param pSmuMgr the address of the powerplay SMU manager. +* @param smc_start_address the start address in the SMC RAM to copy bytes to. +* @param src the byte array to copy the bytes from. +* @param byte_count the number of bytes to copy. +*/ +int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, + const uint8_t *src, uint32_t byte_count, uint32_t limit) +{ + int result; + uint32_t data = 0; + uint32_t original_data; + uint32_t addr = 0; + uint32_t extra_shift; + + PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1); + PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1); + + addr = smc_start_address; + + while (byte_count >= 4) { + /* Bytes are written into the SMC addres space with the MSB first. */ + data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; + + result = polaris10_set_smc_sram_address(smumgr, addr, limit); + + if (0 != result) + return result; + + cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); + + src += 4; + byte_count -= 4; + addr += 4; + } + + if (0 != byte_count) { + + data = 0; + + result = polaris10_set_smc_sram_address(smumgr, addr, limit); + + if (0 != result) + return result; + + + original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); + + extra_shift = 8 * (4 - byte_count); + + while (byte_count > 0) { + /* Bytes are written into the SMC addres space with the MSB first. */ + data = (0x100 * data) + *src++; + byte_count--; + } + + data <<= extra_shift; + + data |= (original_data & ~((~0UL) << extra_shift)); + + result = polaris10_set_smc_sram_address(smumgr, addr, limit); + + if (0 != result) + return result; + + cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); + } + + return 0; +} + + +static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr) +{ + static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; + + polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); + + return 0; +} + +/** +* Return if the SMC is currently running. +* +* @param smumgr the address of the powerplay hardware manager. +*/ +bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr) +{ + return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) + && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); +} + +/** +* Send a message to the SMC, and wait for its response. +* +* @param smumgr the address of the powerplay hardware manager. +* @param msg the message to send. +* @return The response that came from the SMC. +*/ +int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +{ + if (!polaris10_is_smc_ram_running(smumgr)) + return -1; + + SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + + if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) + printk("Failed to send Previous Message.\n"); + + + cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); + + SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + + if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) + printk("Failed to send Message.\n"); + + return 0; +} + + +/** +* Send a message to the SMC, and do not wait for its response. +* +* @param smumgr the address of the powerplay hardware manager. +* @param msg the message to send. +* @return Always return 0. +*/ +int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg) +{ + cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); + + return 0; +} + +/** +* Send a message to the SMC with parameter +* +* @param smumgr: the address of the powerplay hardware manager. +* @param msg: the message to send. +* @param parameter: the parameter to send +* @return The response that came from the SMC. +*/ +int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) +{ + if (!polaris10_is_smc_ram_running(smumgr)) { + return -1; + } + + SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + + cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); + + return polaris10_send_msg_to_smc(smumgr, msg); +} + + +/** +* Send a message to the SMC with parameter, do not wait for response +* +* @param smumgr: the address of the powerplay hardware manager. +* @param msg: the message to send. +* @param parameter: the parameter to send +* @return The response that came from the SMC. +*/ +int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) +{ + cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); + + return polaris10_send_msg_to_smc_without_waiting(smumgr, msg); +} + +int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr) +{ + cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); + + cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); + + SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + + if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) + printk("Failed to send Message.\n"); + + return 0; +} + +/** +* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction. +* +* @param smumgr the address of the powerplay hardware manager. +* @param msg the message to send. +* @return The response that came from the SMC. +*/ +int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr) +{ + /* If the SMC is not even on it qualifies as inactive. */ + if (!polaris10_is_smc_ram_running(smumgr)) + return -1; + + SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0); + return 0; +} + + +/** +* Upload the SMC firmware to the SMC microcontroller. +* +* @param smumgr the address of the powerplay hardware manager. +* @param pFirmware the data structure containing the various sections of the firmware. +*/ +static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit) +{ + uint32_t byte_count = length; + + PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1); + + cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000); + SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); + + for (; byte_count >= 4; byte_count -= 4) + cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++); + + SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); + + PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1); + + return 0; +} + +static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type) +{ + enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM; + + switch (fw_type) { + case UCODE_ID_SMU: + result = CGS_UCODE_ID_SMU; + break; + case UCODE_ID_SMU_SK: + result = CGS_UCODE_ID_SMU_SK; + break; + case UCODE_ID_SDMA0: + result = CGS_UCODE_ID_SDMA0; + break; + case UCODE_ID_SDMA1: + result = CGS_UCODE_ID_SDMA1; + break; + case UCODE_ID_CP_CE: + result = CGS_UCODE_ID_CP_CE; + break; + case UCODE_ID_CP_PFP: + result = CGS_UCODE_ID_CP_PFP; + break; + case UCODE_ID_CP_ME: + result = CGS_UCODE_ID_CP_ME; + break; + case UCODE_ID_CP_MEC: + result = CGS_UCODE_ID_CP_MEC; + break; + case UCODE_ID_CP_MEC_JT1: + result = CGS_UCODE_ID_CP_MEC_JT1; + break; + case UCODE_ID_CP_MEC_JT2: + result = CGS_UCODE_ID_CP_MEC_JT2; + break; + case UCODE_ID_RLC_G: + result = CGS_UCODE_ID_RLC_G; + break; + default: + break; + } + + return result; +} + +static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr) +{ + int result = 0; + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + struct cgs_firmware_info info = {0}; + + if (smu_data->security_hard_key == 1) + cgs_get_firmware_info(smumgr->device, + polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); + else + cgs_get_firmware_info(smumgr->device, + polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); + + /* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/ + result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE); + + return result; +} + +/** +* Read a 32bit value from the SMC SRAM space. +* ALL PARAMETERS ARE IN HOST BYTE ORDER. +* @param smumgr the address of the powerplay hardware manager. +* @param smcAddress the address in the SMC RAM to access. +* @param value and output parameter for the data read from the SMC SRAM. +*/ +int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) +{ + int result; + + result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit); + + if (result) + return result; + + *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); + return 0; +} + +/** +* Write a 32bit value to the SMC SRAM space. +* ALL PARAMETERS ARE IN HOST BYTE ORDER. +* @param smumgr the address of the powerplay hardware manager. +* @param smc_addr the address in the SMC RAM to access. +* @param value to write to the SMC SRAM. +*/ +int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit) +{ + int result; + + result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit); + + if (result) + return result; + + cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value); + + return 0; +} + + +int polaris10_smu_fini(struct pp_smumgr *smumgr) +{ + if (smumgr->backend) { + kfree(smumgr->backend); + smumgr->backend = NULL; + } + return 0; +} + +/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */ +static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type) +{ + uint32_t result = 0; + + switch (fw_type) { + case UCODE_ID_SDMA0: + result = UCODE_ID_SDMA0_MASK; + break; + case UCODE_ID_SDMA1: + result = UCODE_ID_SDMA1_MASK; + break; + case UCODE_ID_CP_CE: + result = UCODE_ID_CP_CE_MASK; + break; + case UCODE_ID_CP_PFP: + result = UCODE_ID_CP_PFP_MASK; + break; + case UCODE_ID_CP_ME: + result = UCODE_ID_CP_ME_MASK; + break; + case UCODE_ID_CP_MEC_JT1: + case UCODE_ID_CP_MEC_JT2: + result = UCODE_ID_CP_MEC_MASK; + break; + case UCODE_ID_RLC_G: + result = UCODE_ID_RLC_G_MASK; + break; + default: + printk("UCode type is out of range! \n"); + result = 0; + } + + return result; +} + +/* Populate one firmware image to the data structure */ + +static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr, + uint32_t fw_type, + struct SMU_Entry *entry) +{ + int result = 0; + struct cgs_firmware_info info = {0}; + + result = cgs_get_firmware_info(smumgr->device, + polaris10_convert_fw_type_to_cgs(fw_type), + &info); + + if (!result) { + entry->version = info.version; + entry->id = (uint16_t)fw_type; + entry->image_addr_high = smu_upper_32_bits(info.mc_addr); + entry->image_addr_low = smu_lower_32_bits(info.mc_addr); + entry->meta_data_addr_high = 0; + entry->meta_data_addr_low = 0; + entry->data_size_byte = info.image_size; + entry->num_register_entries = 0; + } + + if (fw_type == UCODE_ID_RLC_G) + entry->flags = 1; + else + entry->flags = 0; + + return 0; +} + +static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr) +{ + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + uint32_t fw_to_load; + + int result = 0; + struct SMU_DRAMData_TOC *toc; + + if (!smumgr->reload_fw) { + printk(KERN_INFO "[ powerplay ] skip reloading...\n"); + return 0; + } + + if (smu_data->soft_regs_start) + cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus), + 0x0); + + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); + + toc = (struct SMU_DRAMData_TOC *)smu_data->header; + toc->num_entries = 0; + toc->structure_version = 1; + + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); + + fw_to_load = UCODE_ID_RLC_G_MASK + + UCODE_ID_SDMA0_MASK + + UCODE_ID_SDMA1_MASK + + UCODE_ID_CP_CE_MASK + + UCODE_ID_CP_ME_MASK + + UCODE_ID_CP_PFP_MASK + + UCODE_ID_CP_MEC_MASK; + + if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) + printk(KERN_ERR "Fail to Request SMU Load uCode"); + + return result; +} + +/* Check if the FW has been loaded, SMU will not return if loading has not finished. */ +static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type) +{ + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type); + uint32_t ret; + /* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */ + ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11, + smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus), + fw_mask, fw_mask); + + return ret; +} + +static int polaris10_reload_firmware(struct pp_smumgr *smumgr) +{ + return smumgr->smumgr_funcs->start_smu(smumgr); +} + +static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) +{ + int i; + int result = -1; + uint32_t reg, data; + + const PWR_Command_Table *pvirus = pwr_virus_table; + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + + for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { + switch (pvirus->command) { + case PwrCmdWrite: + reg = pvirus->reg; + data = pvirus->data; + cgs_write_register(smumgr->device, reg, data); + break; + + case PwrCmdEnd: + result = 0; + break; + + default: + printk("Table Exit with Invalid Command!"); + smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; + result = -1; + break; + } + pvirus++; + } + + return result; +} + +static int polaris10_perform_btc(struct pp_smumgr *smumgr) +{ + int result = 0; + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + if (0 != smu_data->avfs.avfs_btc_param) { + if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { + printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed"); + result = -1; + } + } + if (smu_data->avfs.avfs_btc_param > 1) { + /* Soft-Reset to reset the engine before loading uCode */ + /* halt */ + cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); + /* reset everything */ + cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); + cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); + } + return result; +} + + +int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) +{ + uint32_t vr_config; + uint32_t dpm_table_start; + + uint16_t u16_boot_mvdd; + uint32_t graphics_level_address, vr_config_address, graphics_level_size; + + graphics_level_size = sizeof(avfs_graphics_level_polaris10); + u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE); + + PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), + &dpm_table_start, 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", + return -1); + + /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */ + vr_config = 0x01000500; /* Real value:0x50001 */ + + vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); + + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address, + (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", + return -1); + + graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); + + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, + (uint8_t *)(&avfs_graphics_level_polaris10), + graphics_level_size, 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", + return -1); + + graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); + + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, + (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", + return -1); + + /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */ + + graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); + + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, + (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!", + return -1); + + return 0; +} + +int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) +{ + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + switch (smu_data->avfs.avfs_btc_status) { + case AVFS_BTC_COMPLETED_PREVIOUSLY: + break; + + case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */ + + smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED; + PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", + return -1); + + if (smu_data->avfs.avfs_btc_param > 1) { + printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); + smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; + PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", + return -1); + } + + smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; + PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled", + return -1); + + break; + + case AVFS_BTC_DISABLED: + case AVFS_BTC_NOTSUPPORTED: + break; + + default: + printk("[AVFS] Something is broken. See log!"); + break; + } + + return 0; +} + +static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr) +{ + int result = 0; + + /* Wait for smc boot up */ + /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ + + /* Assert reset */ + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 1); + + result = polaris10_upload_smu_firmware_image(smumgr); + if (result != 0) + return result; + + /* Clear status */ + cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); + + /* De-assert reset */ + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 0); + + + SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); + + + /* Call Test SMU message with 0x20000 offset to trigger SMU start */ + polaris10_send_msg_to_smc_offset(smumgr); + + /* Wait done bit to be set */ + /* Check pass/failed indicator */ + + SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); + + if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMU_STATUS, SMU_PASS)) + PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); + + cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 1); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 0); + + /* Wait for firmware to initialize */ + SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); + + return result; +} + +static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) +{ + int result = 0; + + /* wait for smc boot up */ + SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); + + /* Clear firmware interrupt enable flag */ + /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ + cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + ixFIRMWARE_FLAGS, 0); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, + rst_reg, 1); + + result = polaris10_upload_smu_firmware_image(smumgr); + if (result != 0) + return result; + + /* Set smc instruct start point at 0x0 */ + polaris10_program_jump_on_start(smumgr); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 0); + + /* Wait for firmware to initialize */ + + SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, + FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); + + return result; +} + +static int polaris10_start_smu(struct pp_smumgr *smumgr) +{ + int result = 0; + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + bool SMU_VFT_INTACT; + + /* Only start SMC if SMC RAM is not running */ + if (!polaris10_is_smc_ram_running(smumgr)) { + SMU_VFT_INTACT = false; + smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); + smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); + + /* Check if SMU is running in protected mode */ + if (smu_data->protected_mode == 0) { + result = polaris10_start_smu_in_non_protection_mode(smumgr); + } else { + result = polaris10_start_smu_in_protection_mode(smumgr); + + /* If failed, try with different security Key. */ + if (result != 0) { + smu_data->security_hard_key ^= 1; + result = polaris10_start_smu_in_protection_mode(smumgr); + } + } + + if (result != 0) + PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); + + polaris10_avfs_event_mgr(smumgr, true); + } else + SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */ + + smu_data->post_initial_boot = true; + polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT); + /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ + polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), + &(smu_data->soft_regs_start), 0x40000); + + result = polaris10_request_smu_load_fw(smumgr); + + return result; +} + +static int polaris10_smu_init(struct pp_smumgr *smumgr) +{ + struct polaris10_smumgr *smu_data; + uint8_t *internal_buf; + uint64_t mc_addr = 0; + /* Allocate memory for backend private data */ + smu_data = (struct polaris10_smumgr *)(smumgr->backend); + smu_data->header_buffer.data_size = + ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; + smu_data->smu_buffer.data_size = 200*4096; + smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED; +/* Allocate FW image data structure and header buffer and + * send the header buffer address to SMU */ + smu_allocate_memory(smumgr->device, + smu_data->header_buffer.data_size, + CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, + PAGE_SIZE, + &mc_addr, + &smu_data->header_buffer.kaddr, + &smu_data->header_buffer.handle); + + smu_data->header = smu_data->header_buffer.kaddr; + smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); + smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); + + PP_ASSERT_WITH_CODE((NULL != smu_data->header), + "Out of memory.", + kfree(smumgr->backend); + cgs_free_gpu_mem(smumgr->device, + (cgs_handle_t)smu_data->header_buffer.handle); + return -1); + +/* Allocate buffer for SMU internal buffer and send the address to SMU. + * Iceland SMU does not need internal buffer.*/ + smu_allocate_memory(smumgr->device, + smu_data->smu_buffer.data_size, + CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, + PAGE_SIZE, + &mc_addr, + &smu_data->smu_buffer.kaddr, + &smu_data->smu_buffer.handle); + + internal_buf = smu_data->smu_buffer.kaddr; + smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); + smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); + + PP_ASSERT_WITH_CODE((NULL != internal_buf), + "Out of memory.", + kfree(smumgr->backend); + cgs_free_gpu_mem(smumgr->device, + (cgs_handle_t)smu_data->smu_buffer.handle); + return -1;); + + return 0; +} + +static const struct pp_smumgr_func ellsemere_smu_funcs = { + .smu_init = polaris10_smu_init, + .smu_fini = polaris10_smu_fini, + .start_smu = polaris10_start_smu, + .check_fw_load_finish = polaris10_check_fw_load_finish, + .request_smu_load_fw = polaris10_reload_firmware, + .request_smu_load_specific_fw = NULL, + .send_msg_to_smc = polaris10_send_msg_to_smc, + .send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter, + .download_pptable_settings = NULL, + .upload_pptable_settings = NULL, +}; + +int polaris10_smum_init(struct pp_smumgr *smumgr) +{ + struct polaris10_smumgr *polaris10_smu = NULL; + + polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL); + + if (polaris10_smu == NULL) + return -1; + + smumgr->backend = polaris10_smu; + smumgr->smumgr_funcs = &ellsemere_smu_funcs; + + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h new file mode 100644 index 000000000000..e5377aec057f --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h @@ -0,0 +1,68 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _POLARIS10_SMUMANAGER_H +#define _POLARIS10_SMUMANAGER_H + +#include +#include + +struct polaris10_avfs { + enum AVFS_BTC_STATUS avfs_btc_status; + uint32_t avfs_btc_param; +}; + +struct polaris10_buffer_entry { + uint32_t data_size; + uint32_t mc_addr_low; + uint32_t mc_addr_high; + void *kaddr; + unsigned long handle; +}; + +struct polaris10_smumgr { + uint8_t *header; + uint8_t *mec_image; + struct polaris10_buffer_entry smu_buffer; + struct polaris10_buffer_entry header_buffer; + uint32_t soft_regs_start; + uint8_t *read_rrm_straps; + uint32_t read_drm_straps_mc_address_high; + uint32_t read_drm_straps_mc_address_low; + uint32_t acpi_optimization; + bool post_initial_boot; + uint8_t protected_mode; + uint8_t security_hard_key; + struct polaris10_avfs avfs; +}; + + +int polaris10_smum_init(struct pp_smumgr *smumgr); + +int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit); +int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit); +int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, + const uint8_t *src, uint32_t byte_count, uint32_t limit); + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c index 063ae71c9830..c483baf6b4fb 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c @@ -30,6 +30,7 @@ #include "cz_smumgr.h" #include "tonga_smumgr.h" #include "fiji_smumgr.h" +#include "polaris10_smumgr.h" int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle) { @@ -62,6 +63,10 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle) case CHIP_FIJI: fiji_smum_init(smumgr); break; + case CHIP_POLARIS11: + case CHIP_POLARIS10: + polaris10_smum_init(smumgr); + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index ebdb43a8daef..32820b680d88 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -145,7 +145,7 @@ out: int tonga_program_jump_on_start(struct pp_smumgr *smumgr) { - static unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 }; + static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 }; tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1); diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index a5ff9458d359..c16248cee779 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -319,6 +319,48 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job) return added; } +static void amd_sched_free_job(struct fence *f, struct fence_cb *cb) { + struct amd_sched_job *job = container_of(cb, struct amd_sched_job, cb_free_job); + schedule_work(&job->work_free_job); +} + +/* job_finish is called after hw fence signaled, and + * the job had already been deleted from ring_mirror_list + */ +void amd_sched_job_finish(struct amd_sched_job *s_job) +{ + struct amd_sched_job *next; + struct amd_gpu_scheduler *sched = s_job->sched; + + if (sched->timeout != MAX_SCHEDULE_TIMEOUT) { + if (cancel_delayed_work(&s_job->work_tdr)) + amd_sched_job_put(s_job); + + /* queue TDR for next job */ + next = list_first_entry_or_null(&sched->ring_mirror_list, + struct amd_sched_job, node); + + if (next) { + INIT_DELAYED_WORK(&next->work_tdr, s_job->timeout_callback); + amd_sched_job_get(next); + schedule_delayed_work(&next->work_tdr, sched->timeout); + } + } +} + +void amd_sched_job_begin(struct amd_sched_job *s_job) +{ + struct amd_gpu_scheduler *sched = s_job->sched; + + if (sched->timeout != MAX_SCHEDULE_TIMEOUT && + list_first_entry_or_null(&sched->ring_mirror_list, struct amd_sched_job, node) == s_job) + { + INIT_DELAYED_WORK(&s_job->work_tdr, s_job->timeout_callback); + amd_sched_job_get(s_job); + schedule_delayed_work(&s_job->work_tdr, sched->timeout); + } +} + /** * Submit a job to the job queue * @@ -330,11 +372,39 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job) { struct amd_sched_entity *entity = sched_job->s_entity; + sched_job->use_sched = 1; + fence_add_callback(&sched_job->s_fence->base, + &sched_job->cb_free_job, amd_sched_free_job); trace_amd_sched_job(sched_job); wait_event(entity->sched->job_scheduled, amd_sched_entity_in(sched_job)); } +/* init a sched_job with basic field */ +int amd_sched_job_init(struct amd_sched_job *job, + struct amd_gpu_scheduler *sched, + struct amd_sched_entity *entity, + void (*timeout_cb)(struct work_struct *work), + void (*free_cb)(struct kref *refcount), + void *owner, struct fence **fence) +{ + INIT_LIST_HEAD(&job->node); + kref_init(&job->refcount); + job->sched = sched; + job->s_entity = entity; + job->s_fence = amd_sched_fence_create(entity, owner); + if (!job->s_fence) + return -ENOMEM; + + job->s_fence->s_job = job; + job->timeout_callback = timeout_cb; + job->free_callback = free_cb; + + if (fence) + *fence = &job->s_fence->base; + return 0; +} + /** * Return ture if we can push more jobs to the hw. */ @@ -383,47 +453,26 @@ static void amd_sched_process_job(struct fence *f, struct fence_cb *cb) unsigned long flags; atomic_dec(&sched->hw_rq_count); + + /* remove job from ring_mirror_list */ + spin_lock_irqsave(&sched->job_list_lock, flags); + list_del_init(&s_fence->s_job->node); + sched->ops->finish_job(s_fence->s_job); + spin_unlock_irqrestore(&sched->job_list_lock, flags); + amd_sched_fence_signal(s_fence); - if (sched->timeout != MAX_SCHEDULE_TIMEOUT) { - cancel_delayed_work(&s_fence->dwork); - spin_lock_irqsave(&sched->fence_list_lock, flags); - list_del_init(&s_fence->list); - spin_unlock_irqrestore(&sched->fence_list_lock, flags); - } + trace_amd_sched_process_job(s_fence); fence_put(&s_fence->base); wake_up_interruptible(&sched->wake_up_worker); } -static void amd_sched_fence_work_func(struct work_struct *work) -{ - struct amd_sched_fence *s_fence = - container_of(work, struct amd_sched_fence, dwork.work); - struct amd_gpu_scheduler *sched = s_fence->sched; - struct amd_sched_fence *entity, *tmp; - unsigned long flags; - - DRM_ERROR("[%s] scheduler is timeout!\n", sched->name); - - /* Clean all pending fences */ - spin_lock_irqsave(&sched->fence_list_lock, flags); - list_for_each_entry_safe(entity, tmp, &sched->fence_list, list) { - DRM_ERROR(" fence no %d\n", entity->base.seqno); - cancel_delayed_work(&entity->dwork); - list_del_init(&entity->list); - fence_put(&entity->base); - } - spin_unlock_irqrestore(&sched->fence_list_lock, flags); -} - static int amd_sched_main(void *param) { struct sched_param sparam = {.sched_priority = 1}; struct amd_gpu_scheduler *sched = (struct amd_gpu_scheduler *)param; int r, count; - spin_lock_init(&sched->fence_list_lock); - INIT_LIST_HEAD(&sched->fence_list); sched_setscheduler(current, SCHED_FIFO, &sparam); while (!kthread_should_stop()) { @@ -431,7 +480,6 @@ static int amd_sched_main(void *param) struct amd_sched_fence *s_fence; struct amd_sched_job *sched_job; struct fence *fence; - unsigned long flags; wait_event_interruptible(sched->wake_up_worker, (entity = amd_sched_select_entity(sched)) || @@ -446,15 +494,8 @@ static int amd_sched_main(void *param) s_fence = sched_job->s_fence; - if (sched->timeout != MAX_SCHEDULE_TIMEOUT) { - INIT_DELAYED_WORK(&s_fence->dwork, amd_sched_fence_work_func); - schedule_delayed_work(&s_fence->dwork, sched->timeout); - spin_lock_irqsave(&sched->fence_list_lock, flags); - list_add_tail(&s_fence->list, &sched->fence_list); - spin_unlock_irqrestore(&sched->fence_list_lock, flags); - } - atomic_inc(&sched->hw_rq_count); + amd_sched_job_pre_schedule(sched, sched_job); fence = sched->ops->run_job(sched_job); amd_sched_fence_scheduled(s_fence); if (fence) { @@ -489,7 +530,7 @@ static int amd_sched_main(void *param) * Return 0 on success, otherwise error code. */ int amd_sched_init(struct amd_gpu_scheduler *sched, - struct amd_sched_backend_ops *ops, + const struct amd_sched_backend_ops *ops, unsigned hw_submission, long timeout, const char *name) { int i; @@ -502,6 +543,8 @@ int amd_sched_init(struct amd_gpu_scheduler *sched, init_waitqueue_head(&sched->wake_up_worker); init_waitqueue_head(&sched->job_scheduled); + INIT_LIST_HEAD(&sched->ring_mirror_list); + spin_lock_init(&sched->job_list_lock); atomic_set(&sched->hw_rq_count, 0); if (atomic_inc_return(&sched_fence_slab_ref) == 1) { sched_fence_slab = kmem_cache_create( diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 9403145d7bee..070095a9433c 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -37,7 +37,7 @@ extern atomic_t sched_fence_slab_ref; /** * A scheduler entity is a wrapper around a job queue or a group - * of other entities. Entities take turns emitting jobs from their + * of other entities. Entities take turns emitting jobs from their * job queues to corresponding hardware ring based on scheduling * policy. */ @@ -74,14 +74,21 @@ struct amd_sched_fence { struct amd_gpu_scheduler *sched; spinlock_t lock; void *owner; - struct delayed_work dwork; - struct list_head list; + struct amd_sched_job *s_job; }; struct amd_sched_job { + struct kref refcount; struct amd_gpu_scheduler *sched; struct amd_sched_entity *s_entity; struct amd_sched_fence *s_fence; + bool use_sched; /* true if the job goes to scheduler */ + struct fence_cb cb_free_job; + struct work_struct work_free_job; + struct list_head node; + struct delayed_work work_tdr; + void (*timeout_callback) (struct work_struct *work); + void (*free_callback)(struct kref *refcount); }; extern const struct fence_ops amd_sched_fence_ops; @@ -102,6 +109,8 @@ static inline struct amd_sched_fence *to_amd_sched_fence(struct fence *f) struct amd_sched_backend_ops { struct fence *(*dependency)(struct amd_sched_job *sched_job); struct fence *(*run_job)(struct amd_sched_job *sched_job); + void (*begin_job)(struct amd_sched_job *sched_job); + void (*finish_job)(struct amd_sched_job *sched_job); }; enum amd_sched_priority { @@ -114,7 +123,7 @@ enum amd_sched_priority { * One scheduler is implemented for each hardware ring */ struct amd_gpu_scheduler { - struct amd_sched_backend_ops *ops; + const struct amd_sched_backend_ops *ops; uint32_t hw_submission_limit; long timeout; const char *name; @@ -122,13 +131,13 @@ struct amd_gpu_scheduler { wait_queue_head_t wake_up_worker; wait_queue_head_t job_scheduled; atomic_t hw_rq_count; - struct list_head fence_list; - spinlock_t fence_list_lock; struct task_struct *thread; + struct list_head ring_mirror_list; + spinlock_t job_list_lock; }; int amd_sched_init(struct amd_gpu_scheduler *sched, - struct amd_sched_backend_ops *ops, + const struct amd_sched_backend_ops *ops, uint32_t hw_submission, long timeout, const char *name); void amd_sched_fini(struct amd_gpu_scheduler *sched); @@ -144,5 +153,24 @@ struct amd_sched_fence *amd_sched_fence_create( struct amd_sched_entity *s_entity, void *owner); void amd_sched_fence_scheduled(struct amd_sched_fence *fence); void amd_sched_fence_signal(struct amd_sched_fence *fence); +int amd_sched_job_init(struct amd_sched_job *job, + struct amd_gpu_scheduler *sched, + struct amd_sched_entity *entity, + void (*timeout_cb)(struct work_struct *work), + void (*free_cb)(struct kref* refcount), + void *owner, struct fence **fence); +void amd_sched_job_pre_schedule(struct amd_gpu_scheduler *sched , + struct amd_sched_job *s_job); +void amd_sched_job_finish(struct amd_sched_job *s_job); +void amd_sched_job_begin(struct amd_sched_job *s_job); +static inline void amd_sched_job_get(struct amd_sched_job *job) { + if (job) + kref_get(&job->refcount); +} + +static inline void amd_sched_job_put(struct amd_sched_job *job) { + if (job) + kref_put(&job->refcount, job->free_callback); +} #endif diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c index dc115aea352b..2a732c490375 100644 --- a/drivers/gpu/drm/amd/scheduler/sched_fence.c +++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c @@ -57,6 +57,16 @@ void amd_sched_fence_signal(struct amd_sched_fence *fence) FENCE_TRACE(&fence->base, "was already signaled\n"); } +void amd_sched_job_pre_schedule(struct amd_gpu_scheduler *sched , + struct amd_sched_job *s_job) +{ + unsigned long flags; + spin_lock_irqsave(&sched->job_list_lock, flags); + list_add_tail(&s_job->node, &sched->ring_mirror_list); + sched->ops->begin_job(s_job); + spin_unlock_irqrestore(&sched->job_list_lock, flags); +} + void amd_sched_fence_scheduled(struct amd_sched_fence *s_fence) { struct fence_cb *cur, *tmp; diff --git a/drivers/gpu/drm/arc/Kconfig b/drivers/gpu/drm/arc/Kconfig new file mode 100644 index 000000000000..f9a13b658fea --- /dev/null +++ b/drivers/gpu/drm/arc/Kconfig @@ -0,0 +1,10 @@ +config DRM_ARCPGU + tristate "ARC PGU" + depends on DRM && OF + select DRM_KMS_CMA_HELPER + select DRM_KMS_FB_HELPER + select DRM_KMS_HELPER + help + Choose this option if you have an ARC PGU controller. + + If M is selected the module will be called arcpgu. diff --git a/drivers/gpu/drm/arc/Makefile b/drivers/gpu/drm/arc/Makefile new file mode 100644 index 000000000000..d48fda70f857 --- /dev/null +++ b/drivers/gpu/drm/arc/Makefile @@ -0,0 +1,2 @@ +arcpgu-y := arcpgu_crtc.o arcpgu_hdmi.o arcpgu_drv.o +obj-$(CONFIG_DRM_ARCPGU) += arcpgu.o diff --git a/drivers/gpu/drm/arc/arcpgu.h b/drivers/gpu/drm/arc/arcpgu.h new file mode 100644 index 000000000000..86574b698a78 --- /dev/null +++ b/drivers/gpu/drm/arc/arcpgu.h @@ -0,0 +1,50 @@ +/* + * ARC PGU DRM driver. + * + * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ARCPGU_H_ +#define _ARCPGU_H_ + +struct arcpgu_drm_private { + void __iomem *regs; + struct clk *clk; + struct drm_fbdev_cma *fbdev; + struct drm_framebuffer *fb; + struct list_head event_list; + struct drm_crtc crtc; + struct drm_plane *plane; +}; + +#define crtc_to_arcpgu_priv(x) container_of(x, struct arcpgu_drm_private, crtc) + +static inline void arc_pgu_write(struct arcpgu_drm_private *arcpgu, + unsigned int reg, u32 value) +{ + iowrite32(value, arcpgu->regs + reg); +} + +static inline u32 arc_pgu_read(struct arcpgu_drm_private *arcpgu, + unsigned int reg) +{ + return ioread32(arcpgu->regs + reg); +} + +int arc_pgu_setup_crtc(struct drm_device *dev); +int arcpgu_drm_hdmi_init(struct drm_device *drm, struct device_node *np); +struct drm_fbdev_cma *arcpgu_fbdev_cma_init(struct drm_device *dev, + unsigned int preferred_bpp, unsigned int num_crtc, + unsigned int max_conn_count); + +#endif diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c b/drivers/gpu/drm/arc/arcpgu_crtc.c new file mode 100644 index 000000000000..92f8beff8e60 --- /dev/null +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c @@ -0,0 +1,257 @@ +/* + * ARC PGU DRM driver. + * + * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "arcpgu.h" +#include "arcpgu_regs.h" + +#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1)) + +static struct simplefb_format supported_formats[] = { + { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 }, + { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 }, +}; + +static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc) +{ + struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); + uint32_t pixel_format = crtc->primary->state->fb->pixel_format; + struct simplefb_format *format = NULL; + int i; + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (supported_formats[i].fourcc == pixel_format) + format = &supported_formats[i]; + } + + if (WARN_ON(!format)) + return; + + if (format->fourcc == DRM_FORMAT_RGB888) + arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, + arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) | + ARCPGU_MODE_RGB888_MASK); + +} + +static const struct drm_crtc_funcs arc_pgu_crtc_funcs = { + .destroy = drm_crtc_cleanup, + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, + .reset = drm_atomic_helper_crtc_reset, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +}; + +static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc) +{ + struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); + struct drm_display_mode *m = &crtc->state->adjusted_mode; + u32 val; + + arc_pgu_write(arcpgu, ARCPGU_REG_FMT, + ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal)); + + arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC, + ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay, + m->crtc_hsync_end - m->crtc_hdisplay)); + + arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC, + ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay, + m->crtc_vsync_end - m->crtc_vdisplay)); + + arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE, + ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start, + m->crtc_vblank_end - m->crtc_vblank_start)); + + val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); + + if (m->flags & DRM_MODE_FLAG_PVSYNC) + val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST; + else + val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST); + + if (m->flags & DRM_MODE_FLAG_PHSYNC) + val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST; + else + val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST); + + arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val); + arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0); + arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1); + + arc_pgu_set_pxl_fmt(crtc); + + clk_set_rate(arcpgu->clk, m->crtc_clock * 1000); +} + +static void arc_pgu_crtc_enable(struct drm_crtc *crtc) +{ + struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); + + clk_prepare_enable(arcpgu->clk); + arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, + arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) | + ARCPGU_CTRL_ENABLE_MASK); +} + +static void arc_pgu_crtc_disable(struct drm_crtc *crtc) +{ + struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); + + if (!crtc->primary->fb) + return; + + clk_disable_unprepare(arcpgu->clk); + arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, + arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) & + ~ARCPGU_CTRL_ENABLE_MASK); +} + +static int arc_pgu_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); + struct drm_display_mode *mode = &state->adjusted_mode; + long rate, clk_rate = mode->clock * 1000; + + rate = clk_round_rate(arcpgu->clk, clk_rate); + if (rate != clk_rate) + return -EINVAL; + + return 0; +} + +static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); + unsigned long flags; + + if (crtc->state->event) { + struct drm_pending_vblank_event *event = crtc->state->event; + + crtc->state->event = NULL; + event->pipe = drm_crtc_index(crtc); + + WARN_ON(drm_crtc_vblank_get(crtc) != 0); + + spin_lock_irqsave(&crtc->dev->event_lock, flags); + list_add_tail(&event->base.link, &arcpgu->event_list); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + } +} + +static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = { + .mode_set = drm_helper_crtc_mode_set, + .mode_set_base = drm_helper_crtc_mode_set_base, + .mode_set_nofb = arc_pgu_crtc_mode_set_nofb, + .enable = arc_pgu_crtc_enable, + .disable = arc_pgu_crtc_disable, + .prepare = arc_pgu_crtc_disable, + .commit = arc_pgu_crtc_enable, + .atomic_check = arc_pgu_crtc_atomic_check, + .atomic_begin = arc_pgu_crtc_atomic_begin, +}; + +static void arc_pgu_plane_atomic_update(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct arcpgu_drm_private *arcpgu; + struct drm_gem_cma_object *gem; + + if (!plane->state->crtc || !plane->state->fb) + return; + + arcpgu = crtc_to_arcpgu_priv(plane->state->crtc); + gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0); + arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr); +} + +static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = { + .prepare_fb = NULL, + .cleanup_fb = NULL, + .atomic_update = arc_pgu_plane_atomic_update, +}; + +static void arc_pgu_plane_destroy(struct drm_plane *plane) +{ + drm_plane_helper_disable(plane); + drm_plane_cleanup(plane); +} + +static const struct drm_plane_funcs arc_pgu_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = arc_pgu_plane_destroy, + .reset = drm_atomic_helper_plane_reset, + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, +}; + +static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm) +{ + struct arcpgu_drm_private *arcpgu = drm->dev_private; + struct drm_plane *plane = NULL; + u32 formats[ARRAY_SIZE(supported_formats)], i; + int ret; + + plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); + if (!plane) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) + formats[i] = supported_formats[i].fourcc; + + ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs, + formats, ARRAY_SIZE(formats), + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) + return ERR_PTR(ret); + + drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs); + arcpgu->plane = plane; + + return plane; +} + +int arc_pgu_setup_crtc(struct drm_device *drm) +{ + struct arcpgu_drm_private *arcpgu = drm->dev_private; + struct drm_plane *primary; + int ret; + + primary = arc_pgu_plane_init(drm); + if (IS_ERR(primary)) + return PTR_ERR(primary); + + ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL, + &arc_pgu_crtc_funcs, NULL); + if (ret) { + arc_pgu_plane_destroy(primary); + return ret; + } + + drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs); + return 0; +} diff --git a/drivers/gpu/drm/arc/arcpgu_drv.c b/drivers/gpu/drm/arc/arcpgu_drv.c new file mode 100644 index 000000000000..76e187a5bde0 --- /dev/null +++ b/drivers/gpu/drm/arc/arcpgu_drv.c @@ -0,0 +1,288 @@ +/* + * ARC PGU DRM driver. + * + * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "arcpgu.h" +#include "arcpgu_regs.h" + +static void arcpgu_fb_output_poll_changed(struct drm_device *dev) +{ + struct arcpgu_drm_private *arcpgu = dev->dev_private; + + if (arcpgu->fbdev) + drm_fbdev_cma_hotplug_event(arcpgu->fbdev); +} + +static int arcpgu_atomic_commit(struct drm_device *dev, + struct drm_atomic_state *state, bool async) +{ + return drm_atomic_helper_commit(dev, state, false); +} + +static struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = { + .fb_create = drm_fb_cma_create, + .output_poll_changed = arcpgu_fb_output_poll_changed, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = arcpgu_atomic_commit, +}; + +static void arcpgu_setup_mode_config(struct drm_device *drm) +{ + drm_mode_config_init(drm); + drm->mode_config.min_width = 0; + drm->mode_config.min_height = 0; + drm->mode_config.max_width = 1920; + drm->mode_config.max_height = 1080; + drm->mode_config.funcs = &arcpgu_drm_modecfg_funcs; +} + +int arcpgu_gem_mmap(struct file *filp, struct vm_area_struct *vma) +{ + int ret; + + ret = drm_gem_mmap(filp, vma); + if (ret) + return ret; + + vma->vm_page_prot = pgprot_noncached(vm_get_page_prot(vma->vm_flags)); + return 0; +} + +static const struct file_operations arcpgu_drm_ops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .unlocked_ioctl = drm_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = drm_compat_ioctl, +#endif + .poll = drm_poll, + .read = drm_read, + .llseek = no_llseek, + .mmap = arcpgu_gem_mmap, +}; + +static void arcpgu_preclose(struct drm_device *drm, struct drm_file *file) +{ + struct arcpgu_drm_private *arcpgu = drm->dev_private; + struct drm_pending_vblank_event *e, *t; + unsigned long flags; + + spin_lock_irqsave(&drm->event_lock, flags); + list_for_each_entry_safe(e, t, &arcpgu->event_list, base.link) { + if (e->base.file_priv != file) + continue; + list_del(&e->base.link); + e->base.destroy(&e->base); + } + spin_unlock_irqrestore(&drm->event_lock, flags); +} + +static void arcpgu_lastclose(struct drm_device *drm) +{ + struct arcpgu_drm_private *arcpgu = drm->dev_private; + + drm_fbdev_cma_restore_mode(arcpgu->fbdev); +} + +static int arcpgu_load(struct drm_device *drm) +{ + struct platform_device *pdev = to_platform_device(drm->dev); + struct arcpgu_drm_private *arcpgu; + struct device_node *encoder_node; + struct resource *res; + int ret; + + arcpgu = devm_kzalloc(&pdev->dev, sizeof(*arcpgu), GFP_KERNEL); + if (arcpgu == NULL) + return -ENOMEM; + + drm->dev_private = arcpgu; + + arcpgu->clk = devm_clk_get(drm->dev, "pxlclk"); + if (IS_ERR(arcpgu->clk)) + return PTR_ERR(arcpgu->clk); + + INIT_LIST_HEAD(&arcpgu->event_list); + + arcpgu_setup_mode_config(drm); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + arcpgu->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(arcpgu->regs)) { + dev_err(drm->dev, "Could not remap IO mem\n"); + return PTR_ERR(arcpgu->regs); + } + + dev_info(drm->dev, "arc_pgu ID: 0x%x\n", + arc_pgu_read(arcpgu, ARCPGU_REG_ID)); + + /* Get the optional framebuffer memory resource */ + ret = of_reserved_mem_device_init(drm->dev); + if (ret && ret != -ENODEV) + return ret; + + if (dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32))) + return -ENODEV; + + if (arc_pgu_setup_crtc(drm) < 0) + return -ENODEV; + + /* find the encoder node and initialize it */ + encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0); + if (!encoder_node) { + dev_err(drm->dev, "failed to get an encoder slave node\n"); + return -ENODEV; + } + + ret = arcpgu_drm_hdmi_init(drm, encoder_node); + if (ret < 0) + return ret; + + drm_mode_config_reset(drm); + drm_kms_helper_poll_init(drm); + + arcpgu->fbdev = drm_fbdev_cma_init(drm, 16, + drm->mode_config.num_crtc, + drm->mode_config.num_connector); + if (IS_ERR(arcpgu->fbdev)) { + ret = PTR_ERR(arcpgu->fbdev); + arcpgu->fbdev = NULL; + return -ENODEV; + } + + platform_set_drvdata(pdev, arcpgu); + return 0; +} + +int arcpgu_unload(struct drm_device *drm) +{ + struct arcpgu_drm_private *arcpgu = drm->dev_private; + + if (arcpgu->fbdev) { + drm_fbdev_cma_fini(arcpgu->fbdev); + arcpgu->fbdev = NULL; + } + drm_kms_helper_poll_fini(drm); + drm_vblank_cleanup(drm); + drm_mode_config_cleanup(drm); + + return 0; +} + +static struct drm_driver arcpgu_drm_driver = { + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | + DRIVER_ATOMIC, + .preclose = arcpgu_preclose, + .lastclose = arcpgu_lastclose, + .name = "drm-arcpgu", + .desc = "ARC PGU Controller", + .date = "20160219", + .major = 1, + .minor = 0, + .patchlevel = 0, + .fops = &arcpgu_drm_ops, + .dumb_create = drm_gem_cma_dumb_create, + .dumb_map_offset = drm_gem_cma_dumb_map_offset, + .dumb_destroy = drm_gem_dumb_destroy, + .get_vblank_counter = drm_vblank_no_hw_counter, + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_free_object = drm_gem_cma_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + .gem_prime_export = drm_gem_prime_export, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, + .gem_prime_vmap = drm_gem_cma_prime_vmap, + .gem_prime_vunmap = drm_gem_cma_prime_vunmap, + .gem_prime_mmap = drm_gem_cma_prime_mmap, +}; + +static int arcpgu_probe(struct platform_device *pdev) +{ + struct drm_device *drm; + int ret; + + drm = drm_dev_alloc(&arcpgu_drm_driver, &pdev->dev); + if (!drm) + return -ENOMEM; + + ret = arcpgu_load(drm); + if (ret) + goto err_unref; + + ret = drm_dev_register(drm, 0); + if (ret) + goto err_unload; + + ret = drm_connector_register_all(drm); + if (ret) + goto err_unregister; + + return 0; + +err_unregister: + drm_dev_unregister(drm); + +err_unload: + arcpgu_unload(drm); + +err_unref: + drm_dev_unref(drm); + + return ret; +} + +static int arcpgu_remove(struct platform_device *pdev) +{ + struct drm_device *drm = platform_get_drvdata(pdev); + + drm_connector_unregister_all(drm); + drm_dev_unregister(drm); + arcpgu_unload(drm); + drm_dev_unref(drm); + + return 0; +} + +static const struct of_device_id arcpgu_of_table[] = { + {.compatible = "snps,arcpgu"}, + {} +}; + +MODULE_DEVICE_TABLE(of, arcpgu_of_table); + +static struct platform_driver arcpgu_platform_driver = { + .probe = arcpgu_probe, + .remove = arcpgu_remove, + .driver = { + .name = "arcpgu", + .of_match_table = arcpgu_of_table, + }, +}; + +module_platform_driver(arcpgu_platform_driver); + +MODULE_AUTHOR("Carlos Palminha "); +MODULE_DESCRIPTION("ARC PGU DRM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/arc/arcpgu_hdmi.c b/drivers/gpu/drm/arc/arcpgu_hdmi.c new file mode 100644 index 000000000000..08b6baeb320d --- /dev/null +++ b/drivers/gpu/drm/arc/arcpgu_hdmi.c @@ -0,0 +1,201 @@ +/* + * ARC PGU DRM driver. + * + * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +#include "arcpgu.h" + +struct arcpgu_drm_connector { + struct drm_connector connector; + struct drm_encoder_slave *encoder_slave; +}; + +static int arcpgu_drm_connector_get_modes(struct drm_connector *connector) +{ + const struct drm_encoder_slave_funcs *sfuncs; + struct drm_encoder_slave *slave; + struct arcpgu_drm_connector *con = + container_of(connector, struct arcpgu_drm_connector, connector); + + slave = con->encoder_slave; + if (slave == NULL) { + dev_err(connector->dev->dev, + "connector_get_modes: cannot find slave encoder for connector\n"); + return 0; + } + + sfuncs = slave->slave_funcs; + if (sfuncs->get_modes == NULL) + return 0; + + return sfuncs->get_modes(&slave->base, connector); +} + +struct drm_encoder * +arcpgu_drm_connector_best_encoder(struct drm_connector *connector) +{ + struct drm_encoder_slave *slave; + struct arcpgu_drm_connector *con = + container_of(connector, struct arcpgu_drm_connector, connector); + + slave = con->encoder_slave; + if (slave == NULL) { + dev_err(connector->dev->dev, + "connector_best_encoder: cannot find slave encoder for connector\n"); + return NULL; + } + + return &slave->base; +} + +static enum drm_connector_status +arcpgu_drm_connector_detect(struct drm_connector *connector, bool force) +{ + enum drm_connector_status status = connector_status_unknown; + const struct drm_encoder_slave_funcs *sfuncs; + struct drm_encoder_slave *slave; + + struct arcpgu_drm_connector *con = + container_of(connector, struct arcpgu_drm_connector, connector); + + slave = con->encoder_slave; + if (slave == NULL) { + dev_err(connector->dev->dev, + "connector_detect: cannot find slave encoder for connector\n"); + return status; + } + + sfuncs = slave->slave_funcs; + if (sfuncs && sfuncs->detect) + return sfuncs->detect(&slave->base, connector); + + dev_err(connector->dev->dev, "connector_detect: could not detect slave funcs\n"); + return status; +} + +static void arcpgu_drm_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} + +static const struct drm_connector_helper_funcs +arcpgu_drm_connector_helper_funcs = { + .get_modes = arcpgu_drm_connector_get_modes, + .best_encoder = arcpgu_drm_connector_best_encoder, +}; + +static const struct drm_connector_funcs arcpgu_drm_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .reset = drm_atomic_helper_connector_reset, + .detect = arcpgu_drm_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = arcpgu_drm_connector_destroy, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static struct drm_encoder_helper_funcs arcpgu_drm_encoder_helper_funcs = { + .dpms = drm_i2c_encoder_dpms, + .mode_fixup = drm_i2c_encoder_mode_fixup, + .mode_set = drm_i2c_encoder_mode_set, + .prepare = drm_i2c_encoder_prepare, + .commit = drm_i2c_encoder_commit, + .detect = drm_i2c_encoder_detect, +}; + +static struct drm_encoder_funcs arcpgu_drm_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +int arcpgu_drm_hdmi_init(struct drm_device *drm, struct device_node *np) +{ + struct arcpgu_drm_connector *arcpgu_connector; + struct drm_i2c_encoder_driver *driver; + struct drm_encoder_slave *encoder; + struct drm_connector *connector; + struct i2c_client *i2c_slave; + int ret; + + encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL); + if (encoder == NULL) + return -ENOMEM; + + i2c_slave = of_find_i2c_device_by_node(np); + if (!i2c_slave || !i2c_get_clientdata(i2c_slave)) { + dev_err(drm->dev, "failed to find i2c slave encoder\n"); + return -EPROBE_DEFER; + } + + if (i2c_slave->dev.driver == NULL) { + dev_err(drm->dev, "failed to find i2c slave driver\n"); + return -EPROBE_DEFER; + } + + driver = + to_drm_i2c_encoder_driver(to_i2c_driver(i2c_slave->dev.driver)); + ret = driver->encoder_init(i2c_slave, drm, encoder); + if (ret) { + dev_err(drm->dev, "failed to initialize i2c encoder slave\n"); + return ret; + } + + encoder->base.possible_crtcs = 1; + encoder->base.possible_clones = 0; + ret = drm_encoder_init(drm, &encoder->base, &arcpgu_drm_encoder_funcs, + DRM_MODE_ENCODER_TMDS, NULL); + if (ret) + return ret; + + drm_encoder_helper_add(&encoder->base, + &arcpgu_drm_encoder_helper_funcs); + + arcpgu_connector = devm_kzalloc(drm->dev, sizeof(*arcpgu_connector), + GFP_KERNEL); + if (!arcpgu_connector) { + ret = -ENOMEM; + goto error_encoder_cleanup; + } + + connector = &arcpgu_connector->connector; + drm_connector_helper_add(connector, &arcpgu_drm_connector_helper_funcs); + ret = drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret < 0) { + dev_err(drm->dev, "failed to initialize drm connector\n"); + goto error_encoder_cleanup; + } + + ret = drm_mode_connector_attach_encoder(connector, &encoder->base); + if (ret < 0) { + dev_err(drm->dev, "could not attach connector to encoder\n"); + drm_connector_unregister(connector); + goto error_connector_cleanup; + } + + arcpgu_connector->encoder_slave = encoder; + + return 0; + +error_connector_cleanup: + drm_connector_cleanup(connector); + +error_encoder_cleanup: + drm_encoder_cleanup(&encoder->base); + return ret; +} diff --git a/drivers/gpu/drm/arc/arcpgu_regs.h b/drivers/gpu/drm/arc/arcpgu_regs.h new file mode 100644 index 000000000000..95a13a84c373 --- /dev/null +++ b/drivers/gpu/drm/arc/arcpgu_regs.h @@ -0,0 +1,40 @@ +/* + * ARC PGU DRM driver. + * + * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ARC_PGU_REGS_H_ +#define _ARC_PGU_REGS_H_ + +#define ARCPGU_REG_CTRL 0x00 +#define ARCPGU_REG_STAT 0x04 +#define ARCPGU_REG_FMT 0x10 +#define ARCPGU_REG_HSYNC 0x14 +#define ARCPGU_REG_VSYNC 0x18 +#define ARCPGU_REG_ACTIVE 0x1c +#define ARCPGU_REG_BUF0_ADDR 0x40 +#define ARCPGU_REG_STRIDE 0x50 +#define ARCPGU_REG_START_SET 0x84 + +#define ARCPGU_REG_ID 0x3FC + +#define ARCPGU_CTRL_ENABLE_MASK 0x02 +#define ARCPGU_CTRL_VS_POL_MASK 0x1 +#define ARCPGU_CTRL_VS_POL_OFST 0x3 +#define ARCPGU_CTRL_HS_POL_MASK 0x1 +#define ARCPGU_CTRL_HS_POL_OFST 0x4 +#define ARCPGU_MODE_RGB888_MASK 0x04 +#define ARCPGU_STAT_BUSY_MASK 0x02 + +#endif diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c index 3ac1ae4d8caf..b987c63ba8d6 100644 --- a/drivers/gpu/drm/arm/hdlcd_drv.c +++ b/drivers/gpu/drm/arm/hdlcd_drv.c @@ -113,7 +113,7 @@ static void hdlcd_fb_output_poll_changed(struct drm_device *drm) } static int hdlcd_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, bool async) + struct drm_atomic_state *state, bool nonblock) { return drm_atomic_helper_commit(dev, state, false); } @@ -379,7 +379,6 @@ static int hdlcd_drm_bind(struct device *dev) DRM_ERROR("failed to initialise vblank\n"); goto err_vblank; } - drm->vblank_disable_allowed = true; drm_mode_config_reset(drm); drm_kms_helper_poll_init(drm); diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 0293eb74d777..3130aa8bcdd0 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -897,7 +897,6 @@ static void cursor_update(void *data) static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h) { - struct drm_device *dev = crtc->dev; struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); struct armada_gem_object *obj = NULL; int ret; @@ -911,7 +910,7 @@ static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc, if (w > 64 || h > 64 || (w > 32 && h > 32)) return -ENOMEM; - obj = armada_gem_object_lookup(dev, file, handle); + obj = armada_gem_object_lookup(file, handle); if (!obj) return -ENOENT; diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c index 82043c204b76..439824a61aa5 100644 --- a/drivers/gpu/drm/armada/armada_drv.c +++ b/drivers/gpu/drm/armada/armada_drv.c @@ -113,7 +113,6 @@ static int armada_drm_load(struct drm_device *dev, unsigned long flags) goto err_comp; dev->irq_enabled = true; - dev->vblank_disable_allowed = 1; ret = armada_fbdev_init(dev); if (ret) diff --git a/drivers/gpu/drm/armada/armada_fb.c b/drivers/gpu/drm/armada/armada_fb.c index 5fa4bf20b232..f03c212b754d 100644 --- a/drivers/gpu/drm/armada/armada_fb.c +++ b/drivers/gpu/drm/armada/armada_fb.c @@ -120,7 +120,7 @@ static struct drm_framebuffer *armada_fb_create(struct drm_device *dev, goto err; } - obj = armada_gem_object_lookup(dev, dfile, mode->handles[0]); + obj = armada_gem_object_lookup(dfile, mode->handles[0]); if (!obj) { ret = -ENOENT; goto err; diff --git a/drivers/gpu/drm/armada/armada_gem.c b/drivers/gpu/drm/armada/armada_gem.c index aca7f9cc6109..88e7fc797721 100644 --- a/drivers/gpu/drm/armada/armada_gem.c +++ b/drivers/gpu/drm/armada/armada_gem.c @@ -278,7 +278,7 @@ int armada_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, struct armada_gem_object *obj; int ret = 0; - obj = armada_gem_object_lookup(dev, file, handle); + obj = armada_gem_object_lookup(file, handle); if (!obj) { DRM_ERROR("failed to lookup gem object\n"); return -EINVAL; @@ -348,7 +348,7 @@ int armada_gem_mmap_ioctl(struct drm_device *dev, void *data, struct armada_gem_object *dobj; unsigned long addr; - dobj = armada_gem_object_lookup(dev, file, args->handle); + dobj = armada_gem_object_lookup(file, args->handle); if (dobj == NULL) return -ENOENT; @@ -391,7 +391,7 @@ int armada_gem_pwrite_ioctl(struct drm_device *dev, void *data, if (ret) return ret; - dobj = armada_gem_object_lookup(dev, file, args->handle); + dobj = armada_gem_object_lookup(file, args->handle); if (dobj == NULL) return -ENOENT; diff --git a/drivers/gpu/drm/armada/armada_gem.h b/drivers/gpu/drm/armada/armada_gem.h index b000ea3a829a..b88d2b9853c7 100644 --- a/drivers/gpu/drm/armada/armada_gem.h +++ b/drivers/gpu/drm/armada/armada_gem.h @@ -45,9 +45,9 @@ struct drm_gem_object *armada_gem_prime_import(struct drm_device *, int armada_gem_map_import(struct armada_gem_object *); static inline struct armada_gem_object *armada_gem_object_lookup( - struct drm_device *dev, struct drm_file *dfile, unsigned handle) + struct drm_file *dfile, unsigned handle) { - struct drm_gem_object *obj = drm_gem_object_lookup(dev, dfile, handle); + struct drm_gem_object *obj = drm_gem_object_lookup(dfile, handle); return obj ? drm_to_armada_gem(obj) : NULL; } diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c index 9a32d9dfdd26..fcd9c0714836 100644 --- a/drivers/gpu/drm/ast/ast_drv.c +++ b/drivers/gpu/drm/ast/ast_drv.c @@ -218,10 +218,8 @@ static struct drm_driver driver = { static int __init ast_init(void) { -#ifdef CONFIG_VGA_CONSOLE if (vgacon_text_force() && ast_modeset == -1) return -EINVAL; -#endif if (ast_modeset == 0) return -EINVAL; diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index eb5715994ac2..908011d2c8f5 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -367,7 +367,7 @@ static inline int ast_bo_reserve(struct ast_bo *bo, bool no_wait) { int ret; - ret = ttm_bo_reserve(&bo->bo, true, no_wait, false, NULL); + ret = ttm_bo_reserve(&bo->bo, true, no_wait, NULL); if (ret) { if (ret != -ERESTARTSYS && ret != -EBUSY) DRM_ERROR("reserve failed %p\n", bo); diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index b1480acbb3c3..7bc3aa6dda8c 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -333,7 +333,7 @@ ast_user_framebuffer_create(struct drm_device *dev, struct ast_framebuffer *ast_fb; int ret; - obj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]); + obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]); if (obj == NULL) return ERR_PTR(-ENOENT); @@ -574,7 +574,7 @@ ast_dumb_mmap_offset(struct drm_file *file, struct drm_gem_object *obj; struct ast_bo *bo; - obj = drm_gem_object_lookup(dev, file, handle); + obj = drm_gem_object_lookup(file, handle); if (obj == NULL) return -ENOENT; diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index a965e7e8ad6e..c337922606e3 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -1141,7 +1141,7 @@ static int ast_cursor_set(struct drm_crtc *crtc, if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT) return -EINVAL; - obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); + obj = drm_gem_object_lookup(file_priv, handle); if (!obj) { DRM_ERROR("Cannot find cursor object %x for crtc\n", handle); return -ENOENT; diff --git a/drivers/gpu/drm/ast/ast_ttm.c b/drivers/gpu/drm/ast/ast_ttm.c index 08f82eae6939..59f2f93b6f84 100644 --- a/drivers/gpu/drm/ast/ast_ttm.c +++ b/drivers/gpu/drm/ast/ast_ttm.c @@ -245,6 +245,8 @@ struct ttm_bo_driver ast_bo_driver = { .verify_access = ast_bo_verify_access, .io_mem_reserve = &ast_ttm_io_mem_reserve, .io_mem_free = &ast_ttm_io_mem_free, + .lru_tail = &ttm_bo_default_lru_tail, + .swap_lru_tail = &ttm_bo_default_swap_lru_tail, }; int ast_mm_init(struct ast_private *ast) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 58c4f785cf84..cf23a755f777 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -31,6 +31,23 @@ #include "atmel_hlcdc_dc.h" +/** + * Atmel HLCDC CRTC state structure + * + * @base: base CRTC state + * @output_mode: RGBXXX output mode + */ +struct atmel_hlcdc_crtc_state { + struct drm_crtc_state base; + unsigned int output_mode; +}; + +static inline struct atmel_hlcdc_crtc_state * +drm_crtc_state_to_atmel_hlcdc_crtc_state(struct drm_crtc_state *state) +{ + return container_of(state, struct atmel_hlcdc_crtc_state, base); +} + /** * Atmel HLCDC CRTC structure * @@ -59,6 +76,7 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); struct regmap *regmap = crtc->dc->hlcdc->regmap; struct drm_display_mode *adj = &c->state->adjusted_mode; + struct atmel_hlcdc_crtc_state *state; unsigned long mode_rate; struct videomode vm; unsigned long prate; @@ -112,15 +130,27 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) if (adj->flags & DRM_MODE_FLAG_NHSYNC) cfg |= ATMEL_HLCDC_HSPOL; + state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); + cfg |= state->output_mode << 8; + regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5), ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL | ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE | ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY | ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO | - ATMEL_HLCDC_GUARDTIME_MASK, + ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK, cfg); } +static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *c, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + + return atmel_hlcdc_dc_mode_valid(crtc->dc, adjusted_mode) == MODE_OK; +} + static void atmel_hlcdc_crtc_disable(struct drm_crtc *c) { struct drm_device *dev = c->dev; @@ -221,15 +251,79 @@ void atmel_hlcdc_crtc_resume(struct drm_crtc *c) } } +#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) +#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) +#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) +#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) +#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) + +static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) +{ + unsigned int output_fmts = ATMEL_HLCDC_OUTPUT_MODE_MASK; + struct atmel_hlcdc_crtc_state *hstate; + struct drm_connector_state *cstate; + struct drm_connector *connector; + struct atmel_hlcdc_crtc *crtc; + int i; + + crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc); + + for_each_connector_in_state(state->state, connector, cstate, i) { + struct drm_display_info *info = &connector->display_info; + unsigned int supported_fmts = 0; + int j; + + if (!cstate->crtc) + continue; + + for (j = 0; j < info->num_bus_formats; j++) { + switch (info->bus_formats[j]) { + case MEDIA_BUS_FMT_RGB444_1X12: + supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB565_1X16: + supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT; + break; + default: + break; + } + } + + if (crtc->dc->desc->conflicting_output_formats) + output_fmts &= supported_fmts; + else + output_fmts |= supported_fmts; + } + + if (!output_fmts) + return -EINVAL; + + hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state); + hstate->output_mode = fls(output_fmts) - 1; + + return 0; +} + static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c, struct drm_crtc_state *s) { - struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + int ret; - if (atmel_hlcdc_dc_mode_valid(crtc->dc, &s->adjusted_mode) != MODE_OK) - return -EINVAL; + ret = atmel_hlcdc_crtc_select_output_mode(s); + if (ret) + return ret; - return atmel_hlcdc_plane_prepare_disc_area(s); + ret = atmel_hlcdc_plane_prepare_disc_area(s); + if (ret) + return ret; + + return atmel_hlcdc_plane_prepare_ahb_routing(s); } static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c, @@ -254,6 +348,7 @@ static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = { + .mode_fixup = atmel_hlcdc_crtc_mode_fixup, .mode_set = drm_helper_crtc_mode_set, .mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb, .mode_set_base = drm_helper_crtc_mode_set_base, @@ -292,13 +387,60 @@ void atmel_hlcdc_crtc_irq(struct drm_crtc *c) atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c)); } +void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) +{ + struct atmel_hlcdc_crtc_state *state; + + if (crtc->state && crtc->state->mode_blob) + drm_property_unreference_blob(crtc->state->mode_blob); + + if (crtc->state) { + state = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state); + kfree(state); + } + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (state) { + crtc->state = &state->base; + crtc->state->crtc = crtc; + } +} + +static struct drm_crtc_state * +atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) +{ + struct atmel_hlcdc_crtc_state *state, *cur; + + if (WARN_ON(!crtc->state)) + return NULL; + + state = kmalloc(sizeof(*state), GFP_KERNEL); + if (state) + __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); + + cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state); + state->output_mode = cur->output_mode; + + return &state->base; +} + +static void atmel_hlcdc_crtc_destroy_state(struct drm_crtc *crtc, + struct drm_crtc_state *s) +{ + struct atmel_hlcdc_crtc_state *state; + + state = drm_crtc_state_to_atmel_hlcdc_crtc_state(s); + __drm_atomic_helper_crtc_destroy_state(s); + kfree(state); +} + static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = { .page_flip = drm_atomic_helper_page_flip, .set_config = drm_atomic_helper_set_config, .destroy = atmel_hlcdc_crtc_destroy, - .reset = drm_atomic_helper_crtc_reset, - .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, + .reset = atmel_hlcdc_crtc_reset, + .atomic_duplicate_state = atmel_hlcdc_crtc_duplicate_state, + .atomic_destroy_state = atmel_hlcdc_crtc_destroy_state, }; int atmel_hlcdc_crtc_create(struct drm_device *dev) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index 3d8d16402d07..8ded7645747e 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -50,6 +50,10 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = { .min_height = 0, .max_width = 1280, .max_height = 860, + .max_spw = 0x3f, + .max_vpw = 0x3f, + .max_hpw = 0xff, + .conflicting_output_formats = true, .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers), .layers = atmel_hlcdc_at91sam9n12_layers, }; @@ -134,6 +138,10 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = { .min_height = 0, .max_width = 800, .max_height = 600, + .max_spw = 0x3f, + .max_vpw = 0x3f, + .max_hpw = 0xff, + .conflicting_output_formats = true, .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers), .layers = atmel_hlcdc_at91sam9x5_layers, }; @@ -237,6 +245,10 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = { .min_height = 0, .max_width = 2048, .max_height = 2048, + .max_spw = 0x3f, + .max_vpw = 0x3f, + .max_hpw = 0x1ff, + .conflicting_output_formats = true, .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers), .layers = atmel_hlcdc_sama5d3_layers, }; @@ -320,6 +332,9 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = { .min_height = 0, .max_width = 2048, .max_height = 2048, + .max_spw = 0xff, + .max_vpw = 0xff, + .max_hpw = 0x3ff, .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers), .layers = atmel_hlcdc_sama5d4_layers, }; @@ -358,19 +373,19 @@ int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc, int hback_porch = mode->htotal - mode->hsync_end; int hsync_len = mode->hsync_end - mode->hsync_start; - if (hsync_len > 0x40 || hsync_len < 1) + if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1) return MODE_HSYNC; - if (vsync_len > 0x40 || vsync_len < 1) + if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1) return MODE_VSYNC; - if (hfront_porch > 0x200 || hfront_porch < 1 || - hback_porch > 0x200 || hback_porch < 1 || + if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 || + hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 || mode->hdisplay < 1) return MODE_H_ILLEGAL; - if (vfront_porch > 0x40 || vfront_porch < 1 || - vback_porch > 0x40 || vback_porch < 0 || + if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 || + vback_porch > dc->desc->max_vpw || vback_porch < 0 || mode->vdisplay < 1) return MODE_V_ILLEGAL; @@ -427,11 +442,102 @@ static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev) } } +struct atmel_hlcdc_dc_commit { + struct work_struct work; + struct drm_device *dev; + struct drm_atomic_state *state; +}; + +static void +atmel_hlcdc_dc_atomic_complete(struct atmel_hlcdc_dc_commit *commit) +{ + struct drm_device *dev = commit->dev; + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct drm_atomic_state *old_state = commit->state; + + /* Apply the atomic update. */ + drm_atomic_helper_commit_modeset_disables(dev, old_state); + drm_atomic_helper_commit_planes(dev, old_state, false); + drm_atomic_helper_commit_modeset_enables(dev, old_state); + + drm_atomic_helper_wait_for_vblanks(dev, old_state); + + drm_atomic_helper_cleanup_planes(dev, old_state); + + drm_atomic_state_free(old_state); + + /* Complete the commit, wake up any waiter. */ + spin_lock(&dc->commit.wait.lock); + dc->commit.pending = false; + wake_up_all_locked(&dc->commit.wait); + spin_unlock(&dc->commit.wait.lock); + + kfree(commit); +} + +static void atmel_hlcdc_dc_atomic_work(struct work_struct *work) +{ + struct atmel_hlcdc_dc_commit *commit = + container_of(work, struct atmel_hlcdc_dc_commit, work); + + atmel_hlcdc_dc_atomic_complete(commit); +} + +static int atmel_hlcdc_dc_atomic_commit(struct drm_device *dev, + struct drm_atomic_state *state, + bool async) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct atmel_hlcdc_dc_commit *commit; + int ret; + + ret = drm_atomic_helper_prepare_planes(dev, state); + if (ret) + return ret; + + /* Allocate the commit object. */ + commit = kzalloc(sizeof(*commit), GFP_KERNEL); + if (!commit) { + ret = -ENOMEM; + goto error; + } + + INIT_WORK(&commit->work, atmel_hlcdc_dc_atomic_work); + commit->dev = dev; + commit->state = state; + + spin_lock(&dc->commit.wait.lock); + ret = wait_event_interruptible_locked(dc->commit.wait, + !dc->commit.pending); + if (ret == 0) + dc->commit.pending = true; + spin_unlock(&dc->commit.wait.lock); + + if (ret) { + kfree(commit); + goto error; + } + + /* Swap the state, this is the point of no return. */ + drm_atomic_helper_swap_state(dev, state); + + if (async) + queue_work(dc->wq, &commit->work); + else + atmel_hlcdc_dc_atomic_complete(commit); + + return 0; + +error: + drm_atomic_helper_cleanup_planes(dev, state); + return ret; +} + static const struct drm_mode_config_funcs mode_config_funcs = { .fb_create = atmel_hlcdc_fb_create, .output_poll_changed = atmel_hlcdc_fb_output_poll_changed, .atomic_check = drm_atomic_helper_check, - .atomic_commit = drm_atomic_helper_commit, + .atomic_commit = atmel_hlcdc_dc_atomic_commit, }; static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev) @@ -445,7 +551,7 @@ static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev) ret = atmel_hlcdc_create_outputs(dev); if (ret) { - dev_err(dev->dev, "failed to create panel: %d\n", ret); + dev_err(dev->dev, "failed to create HLCDC outputs: %d\n", ret); return ret; } @@ -509,6 +615,7 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev) if (!dc->wq) return -ENOMEM; + init_waitqueue_head(&dc->commit.wait); dc->desc = match->data; dc->hlcdc = dev_get_drvdata(dev->dev->parent); dev->dev_private = dc; @@ -584,38 +691,10 @@ static void atmel_hlcdc_dc_unload(struct drm_device *dev) destroy_workqueue(dc->wq); } -static int atmel_hlcdc_dc_connector_plug_all(struct drm_device *dev) -{ - struct drm_connector *connector, *failed; - int ret; - - mutex_lock(&dev->mode_config.mutex); - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - ret = drm_connector_register(connector); - if (ret) { - failed = connector; - goto err; - } - } - mutex_unlock(&dev->mode_config.mutex); - return 0; - -err: - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - if (failed == connector) - break; - - drm_connector_unregister(connector); - } - mutex_unlock(&dev->mode_config.mutex); - - return ret; -} - static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev) { mutex_lock(&dev->mode_config.mutex); - drm_connector_unplug_all(dev); + drm_connector_unregister_all(dev); mutex_unlock(&dev->mode_config.mutex); } @@ -736,7 +815,7 @@ static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev) if (ret) goto err_unload; - ret = atmel_hlcdc_dc_connector_plug_all(ddev); + ret = drm_connector_register_all(ddev); if (ret) goto err_unregister; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index fed517f297da..7a47f8c094d0 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -50,6 +50,11 @@ * @min_height: minimum height supported by the Display Controller * @max_width: maximum width supported by the Display Controller * @max_height: maximum height supported by the Display Controller + * @max_spw: maximum vertical/horizontal pulse width + * @max_vpw: maximum vertical back/front porch width + * @max_hpw: maximum horizontal back/front porch width + * @conflicting_output_formats: true if RGBXXX output formats conflict with + * each other. * @layers: a layer description table describing available layers * @nlayers: layer description table size */ @@ -58,6 +63,10 @@ struct atmel_hlcdc_dc_desc { int min_height; int max_width; int max_height; + int max_spw; + int max_vpw; + int max_hpw; + bool conflicting_output_formats; const struct atmel_hlcdc_layer_desc *layers; int nlayers; }; @@ -128,6 +137,7 @@ struct atmel_hlcdc_planes { * @planes: instantiated planes * @layers: active HLCDC layer * @wq: display controller workqueue + * @commit: used for async commit handling */ struct atmel_hlcdc_dc { const struct atmel_hlcdc_dc_desc *desc; @@ -137,6 +147,10 @@ struct atmel_hlcdc_dc { struct atmel_hlcdc_planes *planes; struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; struct workqueue_struct *wq; + struct { + wait_queue_head_t wait; + bool pending; + } commit; }; extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; @@ -149,6 +163,7 @@ struct atmel_hlcdc_planes * atmel_hlcdc_create_planes(struct drm_device *dev); int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state); +int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state); void atmel_hlcdc_crtc_irq(struct drm_crtc *c); diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c index 0f7ec016e7a9..39802c0539b6 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c @@ -26,16 +26,6 @@ #include "atmel_hlcdc_dc.h" -/** - * Atmel HLCDC RGB output mode - */ -enum atmel_hlcdc_connector_rgb_mode { - ATMEL_HLCDC_CONNECTOR_RGB444, - ATMEL_HLCDC_CONNECTOR_RGB565, - ATMEL_HLCDC_CONNECTOR_RGB666, - ATMEL_HLCDC_CONNECTOR_RGB888, -}; - /** * Atmel HLCDC RGB connector structure * @@ -44,13 +34,13 @@ enum atmel_hlcdc_connector_rgb_mode { * @connector: DRM connector * @encoder: DRM encoder * @dc: pointer to the atmel_hlcdc_dc structure - * @dpms: current DPMS mode + * @panel: panel connected on the RGB output */ struct atmel_hlcdc_rgb_output { struct drm_connector connector; struct drm_encoder encoder; struct atmel_hlcdc_dc *dc; - int dpms; + struct drm_panel *panel; }; static inline struct atmel_hlcdc_rgb_output * @@ -66,91 +56,31 @@ drm_encoder_to_atmel_hlcdc_rgb_output(struct drm_encoder *encoder) return container_of(encoder, struct atmel_hlcdc_rgb_output, encoder); } -/** - * Atmel HLCDC Panel device structure - * - * This structure is specialization of the slave device structure to - * interface with drm panels. - * - * @base: base slave device fields - * @panel: drm panel attached to this slave device - */ -struct atmel_hlcdc_panel { - struct atmel_hlcdc_rgb_output base; - struct drm_panel *panel; -}; - -static inline struct atmel_hlcdc_panel * -atmel_hlcdc_rgb_output_to_panel(struct atmel_hlcdc_rgb_output *output) -{ - return container_of(output, struct atmel_hlcdc_panel, base); -} - -static void atmel_hlcdc_panel_encoder_enable(struct drm_encoder *encoder) +static void atmel_hlcdc_rgb_encoder_enable(struct drm_encoder *encoder) { struct atmel_hlcdc_rgb_output *rgb = drm_encoder_to_atmel_hlcdc_rgb_output(encoder); - struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb); - drm_panel_enable(panel->panel); -} - -static void atmel_hlcdc_panel_encoder_disable(struct drm_encoder *encoder) -{ - struct atmel_hlcdc_rgb_output *rgb = - drm_encoder_to_atmel_hlcdc_rgb_output(encoder); - struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb); - - drm_panel_disable(panel->panel); -} - -static bool -atmel_hlcdc_panel_encoder_mode_fixup(struct drm_encoder *encoder, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted) -{ - return true; -} - -static void -atmel_hlcdc_rgb_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted) -{ - struct atmel_hlcdc_rgb_output *rgb = - drm_encoder_to_atmel_hlcdc_rgb_output(encoder); - struct drm_display_info *info = &rgb->connector.display_info; - unsigned int cfg; - - cfg = 0; - - if (info->num_bus_formats) { - switch (info->bus_formats[0]) { - case MEDIA_BUS_FMT_RGB565_1X16: - cfg |= ATMEL_HLCDC_CONNECTOR_RGB565 << 8; - break; - case MEDIA_BUS_FMT_RGB666_1X18: - cfg |= ATMEL_HLCDC_CONNECTOR_RGB666 << 8; - break; - case MEDIA_BUS_FMT_RGB888_1X24: - cfg |= ATMEL_HLCDC_CONNECTOR_RGB888 << 8; - break; - case MEDIA_BUS_FMT_RGB444_1X12: - default: - break; - } + if (rgb->panel) { + drm_panel_prepare(rgb->panel); + drm_panel_enable(rgb->panel); } +} - regmap_update_bits(rgb->dc->hlcdc->regmap, ATMEL_HLCDC_CFG(5), - ATMEL_HLCDC_MODE_MASK, - cfg); +static void atmel_hlcdc_rgb_encoder_disable(struct drm_encoder *encoder) +{ + struct atmel_hlcdc_rgb_output *rgb = + drm_encoder_to_atmel_hlcdc_rgb_output(encoder); + + if (rgb->panel) { + drm_panel_disable(rgb->panel); + drm_panel_unprepare(rgb->panel); + } } static const struct drm_encoder_helper_funcs atmel_hlcdc_panel_encoder_helper_funcs = { - .mode_fixup = atmel_hlcdc_panel_encoder_mode_fixup, - .mode_set = atmel_hlcdc_rgb_encoder_mode_set, - .disable = atmel_hlcdc_panel_encoder_disable, - .enable = atmel_hlcdc_panel_encoder_enable, + .disable = atmel_hlcdc_rgb_encoder_disable, + .enable = atmel_hlcdc_rgb_encoder_enable, }; static void atmel_hlcdc_rgb_encoder_destroy(struct drm_encoder *encoder) @@ -167,9 +97,11 @@ static int atmel_hlcdc_panel_get_modes(struct drm_connector *connector) { struct atmel_hlcdc_rgb_output *rgb = drm_connector_to_atmel_hlcdc_rgb_output(connector); - struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb); - return panel->panel->funcs->get_modes(panel->panel); + if (rgb->panel) + return rgb->panel->funcs->get_modes(rgb->panel); + + return 0; } static int atmel_hlcdc_rgb_mode_valid(struct drm_connector *connector, @@ -201,7 +133,13 @@ static const struct drm_connector_helper_funcs atmel_hlcdc_panel_connector_helpe static enum drm_connector_status atmel_hlcdc_panel_connector_detect(struct drm_connector *connector, bool force) { - return connector_status_connected; + struct atmel_hlcdc_rgb_output *rgb = + drm_connector_to_atmel_hlcdc_rgb_output(connector); + + if (rgb->panel) + return connector_status_connected; + + return connector_status_disconnected; } static void @@ -209,9 +147,10 @@ atmel_hlcdc_panel_connector_destroy(struct drm_connector *connector) { struct atmel_hlcdc_rgb_output *rgb = drm_connector_to_atmel_hlcdc_rgb_output(connector); - struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb); - drm_panel_detach(panel->panel); + if (rgb->panel) + drm_panel_detach(rgb->panel); + drm_connector_cleanup(connector); } @@ -225,88 +164,122 @@ static const struct drm_connector_funcs atmel_hlcdc_panel_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, }; -static int atmel_hlcdc_create_panel_output(struct drm_device *dev, - struct of_endpoint *ep) +static int atmel_hlcdc_check_endpoint(struct drm_device *dev, + const struct of_endpoint *ep) { - struct atmel_hlcdc_dc *dc = dev->dev_private; struct device_node *np; - struct drm_panel *p = NULL; - struct atmel_hlcdc_panel *panel; - int ret; + void *obj; np = of_graph_get_remote_port_parent(ep->local_node); - if (!np) - return -EINVAL; - p = of_drm_find_panel(np); + obj = of_drm_find_panel(np); + if (!obj) + obj = of_drm_find_bridge(np); + of_node_put(np); - if (!p) - return -EPROBE_DEFER; + return obj ? 0 : -EPROBE_DEFER; +} - panel = devm_kzalloc(dev->dev, sizeof(*panel), GFP_KERNEL); - if (!panel) +static int atmel_hlcdc_attach_endpoint(struct drm_device *dev, + const struct of_endpoint *ep) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct atmel_hlcdc_rgb_output *output; + struct device_node *np; + struct drm_panel *panel; + struct drm_bridge *bridge; + int ret; + + output = devm_kzalloc(dev->dev, sizeof(*output), GFP_KERNEL); + if (!output) return -EINVAL; - panel->base.dpms = DRM_MODE_DPMS_OFF; + output->dc = dc; - panel->base.dc = dc; - - drm_encoder_helper_add(&panel->base.encoder, + drm_encoder_helper_add(&output->encoder, &atmel_hlcdc_panel_encoder_helper_funcs); - ret = drm_encoder_init(dev, &panel->base.encoder, + ret = drm_encoder_init(dev, &output->encoder, &atmel_hlcdc_panel_encoder_funcs, - DRM_MODE_ENCODER_LVDS, NULL); + DRM_MODE_ENCODER_NONE, NULL); if (ret) return ret; - panel->base.connector.dpms = DRM_MODE_DPMS_OFF; - panel->base.connector.polled = DRM_CONNECTOR_POLL_CONNECT; - drm_connector_helper_add(&panel->base.connector, - &atmel_hlcdc_panel_connector_helper_funcs); - ret = drm_connector_init(dev, &panel->base.connector, - &atmel_hlcdc_panel_connector_funcs, - DRM_MODE_CONNECTOR_LVDS); - if (ret) - goto err_encoder_cleanup; + output->encoder.possible_crtcs = 0x1; - drm_mode_connector_attach_encoder(&panel->base.connector, - &panel->base.encoder); - panel->base.encoder.possible_crtcs = 0x1; + np = of_graph_get_remote_port_parent(ep->local_node); - drm_panel_attach(p, &panel->base.connector); - panel->panel = p; + ret = -EPROBE_DEFER; - return 0; + panel = of_drm_find_panel(np); + if (panel) { + of_node_put(np); + output->connector.dpms = DRM_MODE_DPMS_OFF; + output->connector.polled = DRM_CONNECTOR_POLL_CONNECT; + drm_connector_helper_add(&output->connector, + &atmel_hlcdc_panel_connector_helper_funcs); + ret = drm_connector_init(dev, &output->connector, + &atmel_hlcdc_panel_connector_funcs, + DRM_MODE_CONNECTOR_Unknown); + if (ret) + goto err_encoder_cleanup; + + drm_mode_connector_attach_encoder(&output->connector, + &output->encoder); + + ret = drm_panel_attach(panel, &output->connector); + if (ret) { + drm_connector_cleanup(&output->connector); + goto err_encoder_cleanup; + } + + output->panel = panel; + + return 0; + } + + bridge = of_drm_find_bridge(np); + of_node_put(np); + + if (bridge) { + output->encoder.bridge = bridge; + bridge->encoder = &output->encoder; + ret = drm_bridge_attach(dev, bridge); + if (!ret) + return 0; + } err_encoder_cleanup: - drm_encoder_cleanup(&panel->base.encoder); + drm_encoder_cleanup(&output->encoder); return ret; } int atmel_hlcdc_create_outputs(struct drm_device *dev) { - struct device_node *port_np, *np; + struct device_node *ep_np = NULL; struct of_endpoint ep; int ret; - port_np = of_get_child_by_name(dev->dev->of_node, "port"); - if (!port_np) - return -EINVAL; + for_each_endpoint_of_node(dev->dev->of_node, ep_np) { + ret = of_graph_parse_endpoint(ep_np, &ep); + if (!ret) + ret = atmel_hlcdc_check_endpoint(dev, &ep); - np = of_get_child_by_name(port_np, "endpoint"); - of_node_put(port_np); + of_node_put(ep_np); + if (ret) + return ret; + } - if (!np) - return -EINVAL; + for_each_endpoint_of_node(dev->dev->of_node, ep_np) { + ret = of_graph_parse_endpoint(ep_np, &ep); + if (!ret) + ret = atmel_hlcdc_attach_endpoint(dev, &ep); - ret = of_graph_parse_endpoint(np, &ep); - of_node_put(port_np); + of_node_put(ep_np); + if (ret) + return ret; + } - if (ret) - return ret; - - /* We currently only support panel output */ - return atmel_hlcdc_create_panel_output(dev, &ep); + return 0; } diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index d65dcaee3832..aef3ca8a81fa 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -37,6 +37,7 @@ * @xstride: value to add to the pixel pointer between each line * @pstride: value to add to the pixel pointer between each pixel * @nplanes: number of planes (deduced from pixel_format) + * @prepared: plane update has been prepared */ struct atmel_hlcdc_plane_state { struct drm_plane_state base; @@ -58,12 +59,15 @@ struct atmel_hlcdc_plane_state { int disc_w; int disc_h; + int ahb_id; + /* These fields are private and should not be touched */ int bpp[ATMEL_HLCDC_MAX_PLANES]; unsigned int offsets[ATMEL_HLCDC_MAX_PLANES]; int xstride[ATMEL_HLCDC_MAX_PLANES]; int pstride[ATMEL_HLCDC_MAX_PLANES]; int nplanes; + bool prepared; }; static inline struct atmel_hlcdc_plane_state * @@ -359,8 +363,10 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, atmel_hlcdc_layer_update_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG_ID, - ATMEL_HLCDC_LAYER_DMA_BLEN_MASK, - ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16); + ATMEL_HLCDC_LAYER_DMA_BLEN_MASK | + ATMEL_HLCDC_LAYER_DMA_SIF, + ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | + state->ahb_id); atmel_hlcdc_layer_update_cfg(&plane->layer, layout->general_config, ATMEL_HLCDC_LAYER_ITER2BL | @@ -435,6 +441,41 @@ static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane, } } +int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state) +{ + unsigned int ahb_load[2] = { }; + struct drm_plane *plane; + + drm_atomic_crtc_state_for_each_plane(plane, c_state) { + struct atmel_hlcdc_plane_state *plane_state; + struct drm_plane_state *plane_s; + unsigned int pixels, load = 0; + int i; + + plane_s = drm_atomic_get_plane_state(c_state->state, plane); + if (IS_ERR(plane_s)) + return PTR_ERR(plane_s); + + plane_state = + drm_plane_state_to_atmel_hlcdc_plane_state(plane_s); + + pixels = (plane_state->src_w * plane_state->src_h) - + (plane_state->disc_w * plane_state->disc_h); + + for (i = 0; i < plane_state->nplanes; i++) + load += pixels * plane_state->bpp[i]; + + if (ahb_load[0] <= ahb_load[1]) + plane_state->ahb_id = 0; + else + plane_state->ahb_id = 1; + + ahb_load[plane_state->ahb_id] += load; + } + + return 0; +} + int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state) { @@ -714,12 +755,54 @@ static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, static int atmel_hlcdc_plane_prepare_fb(struct drm_plane *p, const struct drm_plane_state *new_state) { + /* + * FIXME: we should avoid this const -> non-const cast but it's + * currently the only solution we have to modify the ->prepared + * state and rollback the update request. + * Ideally, we should rework the code to attach all the resources + * to atmel_hlcdc_plane_state (including the DMA desc allocation), + * but this require a complete rework of the atmel_hlcdc_layer + * code. + */ + struct drm_plane_state *s = (struct drm_plane_state *)new_state; struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + struct atmel_hlcdc_plane_state *state = + drm_plane_state_to_atmel_hlcdc_plane_state(s); + int ret; - if (!new_state->fb) - return 0; + ret = atmel_hlcdc_layer_update_start(&plane->layer); + if (!ret) + state->prepared = true; - return atmel_hlcdc_layer_update_start(&plane->layer); + return ret; +} + +static void atmel_hlcdc_plane_cleanup_fb(struct drm_plane *p, + const struct drm_plane_state *old_state) +{ + /* + * FIXME: we should avoid this const -> non-const cast but it's + * currently the only solution we have to modify the ->prepared + * state and rollback the update request. + * Ideally, we should rework the code to attach all the resources + * to atmel_hlcdc_plane_state (including the DMA desc allocation), + * but this require a complete rework of the atmel_hlcdc_layer + * code. + */ + struct drm_plane_state *s = (struct drm_plane_state *)old_state; + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + struct atmel_hlcdc_plane_state *state = + drm_plane_state_to_atmel_hlcdc_plane_state(s); + + /* + * The Request has already been applied or cancelled, nothing to do + * here. + */ + if (!state->prepared) + return; + + atmel_hlcdc_layer_update_rollback(&plane->layer); + state->prepared = false; } static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, @@ -844,6 +927,7 @@ static void atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane, static struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = { .prepare_fb = atmel_hlcdc_plane_prepare_fb, + .cleanup_fb = atmel_hlcdc_plane_cleanup_fb, .atomic_check = atmel_hlcdc_plane_atomic_check, .atomic_update = atmel_hlcdc_plane_atomic_update, .atomic_disable = atmel_hlcdc_plane_atomic_disable, @@ -883,6 +967,7 @@ atmel_hlcdc_plane_atomic_duplicate_state(struct drm_plane *p) return NULL; copy->disc_updated = false; + copy->prepared = false; if (copy->base.fb) drm_framebuffer_reference(copy->base.fb); diff --git a/drivers/gpu/drm/bochs/bochs_fbdev.c b/drivers/gpu/drm/bochs/bochs_fbdev.c index 7520bf81fc25..e1ec498a6b6e 100644 --- a/drivers/gpu/drm/bochs/bochs_fbdev.c +++ b/drivers/gpu/drm/bochs/bochs_fbdev.c @@ -82,7 +82,7 @@ static int bochsfb_create(struct drm_fb_helper *helper, bo = gem_to_bochs_bo(gobj); - ret = ttm_bo_reserve(&bo->bo, true, false, false, NULL); + ret = ttm_bo_reserve(&bo->bo, true, false, NULL); if (ret) return ret; @@ -162,22 +162,7 @@ static int bochs_fbdev_destroy(struct bochs_device *bochs) return 0; } -void bochs_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, - u16 blue, int regno) -{ -} - -void bochs_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, int regno) -{ - *red = regno; - *green = regno; - *blue = regno; -} - static const struct drm_fb_helper_funcs bochs_fb_helper_funcs = { - .gamma_set = bochs_fb_gamma_set, - .gamma_get = bochs_fb_gamma_get, .fb_probe = bochsfb_create, }; diff --git a/drivers/gpu/drm/bochs/bochs_kms.c b/drivers/gpu/drm/bochs/bochs_kms.c index 96926f09e0c9..207a2cbcc113 100644 --- a/drivers/gpu/drm/bochs/bochs_kms.c +++ b/drivers/gpu/drm/bochs/bochs_kms.c @@ -43,7 +43,7 @@ static int bochs_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, if (old_fb) { bochs_fb = to_bochs_framebuffer(old_fb); bo = gem_to_bochs_bo(bochs_fb->obj); - ret = ttm_bo_reserve(&bo->bo, true, false, false, NULL); + ret = ttm_bo_reserve(&bo->bo, true, false, NULL); if (ret) { DRM_ERROR("failed to reserve old_fb bo\n"); } else { @@ -57,7 +57,7 @@ static int bochs_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, bochs_fb = to_bochs_framebuffer(crtc->primary->fb); bo = gem_to_bochs_bo(bochs_fb->obj); - ret = ttm_bo_reserve(&bo->bo, true, false, false, NULL); + ret = ttm_bo_reserve(&bo->bo, true, false, NULL); if (ret) return ret; @@ -93,11 +93,6 @@ static void bochs_crtc_commit(struct drm_crtc *crtc) { } -static void bochs_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ -} - static int bochs_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, @@ -120,7 +115,6 @@ static int bochs_crtc_page_flip(struct drm_crtc *crtc, /* These provide the minimum set of functions required to handle a CRTC */ static const struct drm_crtc_funcs bochs_crtc_funcs = { - .gamma_set = bochs_crtc_gamma_set, .set_config = drm_crtc_helper_set_config, .destroy = drm_crtc_cleanup, .page_flip = bochs_crtc_page_flip, @@ -140,7 +134,6 @@ static void bochs_crtc_init(struct drm_device *dev) struct drm_crtc *crtc = &bochs->crtc; drm_crtc_init(dev, crtc, &bochs_crtc_funcs); - drm_mode_crtc_set_gamma_size(crtc, 256); drm_crtc_helper_add(crtc, &bochs_helper_funcs); } diff --git a/drivers/gpu/drm/bochs/bochs_mm.c b/drivers/gpu/drm/bochs/bochs_mm.c index d812ad014da5..6cf912c45e48 100644 --- a/drivers/gpu/drm/bochs/bochs_mm.c +++ b/drivers/gpu/drm/bochs/bochs_mm.c @@ -212,6 +212,8 @@ struct ttm_bo_driver bochs_bo_driver = { .verify_access = bochs_bo_verify_access, .io_mem_reserve = &bochs_ttm_io_mem_reserve, .io_mem_free = &bochs_ttm_io_mem_free, + .lru_tail = &ttm_bo_default_lru_tail, + .swap_lru_tail = &ttm_bo_default_swap_lru_tail, }; int bochs_mm_init(struct bochs_device *bochs) @@ -456,7 +458,7 @@ int bochs_dumb_mmap_offset(struct drm_file *file, struct drm_device *dev, struct drm_gem_object *obj; struct bochs_bo *bo; - obj = drm_gem_object_lookup(dev, file, handle); + obj = drm_gem_object_lookup(file, handle); if (obj == NULL) return -ENOENT; @@ -518,7 +520,7 @@ bochs_user_framebuffer_create(struct drm_device *dev, if (mode_cmd->pixel_format != DRM_FORMAT_XRGB8888) return ERR_PTR(-ENOENT); - obj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]); + obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]); if (obj == NULL) return ERR_PTR(-ENOENT); diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 27e2022de89d..8f7423f18da5 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -7,6 +7,16 @@ config DRM_BRIDGE menu "Display Interface Bridges" depends on DRM && DRM_BRIDGE +config DRM_ANALOGIX_ANX78XX + tristate "Analogix ANX78XX bridge" + select DRM_KMS_HELPER + select REGMAP_I2C + ---help--- + ANX78XX is an ultra-low Full-HD SlimPort transmitter + designed for portable devices. The ANX78XX transforms + the HDMI output of an application processor to MyDP + or DisplayPort. + config DRM_DW_HDMI tristate select DRM_KMS_HELPER @@ -40,4 +50,6 @@ config DRM_PARADE_PS8622 ---help--- Parade eDP-LVDS bridge chip driver. +source "drivers/gpu/drm/bridge/analogix/Kconfig" + endmenu diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index f13c33d67c03..96b13b30e6ab 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -1,6 +1,8 @@ ccflags-y := -Iinclude/drm +obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix-anx78xx.c new file mode 100644 index 000000000000..d087b054c360 --- /dev/null +++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c @@ -0,0 +1,1514 @@ +/* + * Copyright(c) 2016, Analogix Semiconductor. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Based on anx7808 driver obtained from chromeos with copyright: + * Copyright(c) 2013, Google Inc. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "analogix-anx78xx.h" + +#define I2C_NUM_ADDRESSES 5 +#define I2C_IDX_TX_P0 0 +#define I2C_IDX_TX_P1 1 +#define I2C_IDX_TX_P2 2 +#define I2C_IDX_RX_P0 3 +#define I2C_IDX_RX_P1 4 + +#define XTAL_CLK 270 /* 27M */ +#define AUX_CH_BUFFER_SIZE 16 +#define AUX_WAIT_TIMEOUT_MS 15 + +static const u8 anx78xx_i2c_addresses[] = { + [I2C_IDX_TX_P0] = TX_P0, + [I2C_IDX_TX_P1] = TX_P1, + [I2C_IDX_TX_P2] = TX_P2, + [I2C_IDX_RX_P0] = RX_P0, + [I2C_IDX_RX_P1] = RX_P1, +}; + +struct anx78xx_platform_data { + struct regulator *dvdd10; + struct gpio_desc *gpiod_hpd; + struct gpio_desc *gpiod_pd; + struct gpio_desc *gpiod_reset; + + int hpd_irq; + int intp_irq; +}; + +struct anx78xx { + struct drm_dp_aux aux; + struct drm_bridge bridge; + struct i2c_client *client; + struct edid *edid; + struct drm_connector connector; + struct drm_dp_link link; + struct anx78xx_platform_data pdata; + struct mutex lock; + + /* + * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2, + * RX_P0 and RX_P1. + */ + struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES]; + struct regmap *map[I2C_NUM_ADDRESSES]; + + u16 chipid; + u8 dpcd[DP_RECEIVER_CAP_SIZE]; + + bool powered; +}; + +static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c) +{ + return container_of(c, struct anx78xx, connector); +} + +static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge) +{ + return container_of(bridge, struct anx78xx, bridge); +} + +static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask) +{ + return regmap_update_bits(map, reg, mask, mask); +} + +static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask) +{ + return regmap_update_bits(map, reg, mask, 0); +} + +static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx) +{ + unsigned int value; + int err; + + err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG, + &value); + if (err < 0) + return false; + + return (value & SP_AUX_EN) == 0; +} + +static int anx78xx_aux_wait(struct anx78xx *anx78xx) +{ + unsigned long timeout; + unsigned int status; + int err; + + timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1; + + while (!anx78xx_aux_op_finished(anx78xx)) { + if (time_after(jiffies, timeout)) { + if (!anx78xx_aux_op_finished(anx78xx)) { + DRM_ERROR("Timed out waiting AUX to finish\n"); + return -ETIMEDOUT; + } + + break; + } + + usleep_range(1000, 2000); + } + + /* Read the AUX channel access status */ + err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG, + &status); + if (err < 0) { + DRM_ERROR("Failed to read from AUX channel: %d\n", err); + return err; + } + + if (status & SP_AUX_STATUS) { + DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n", + status); + return -ETIMEDOUT; + } + + return 0; +} + +static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr) +{ + int err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG, + addr & 0xff); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG, + (addr & 0xff00) >> 8); + if (err) + return err; + + /* + * DP AUX CH Address Register #2, only update bits[3:0] + * [7:4] RESERVED + * [3:0] AUX_ADDR[19:16], Register control AUX CH address. + */ + err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_AUX_ADDR_19_16_REG, + SP_AUX_ADDR_19_16_MASK, + (addr & 0xf0000) >> 16); + + if (err) + return err; + + return 0; +} + +static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux); + u8 ctrl1 = msg->request; + u8 ctrl2 = SP_AUX_EN; + u8 *buffer = msg->buffer; + int err; + + /* The DP AUX transmit and receive buffer has 16 bytes. */ + if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE)) + return -E2BIG; + + /* Zero-sized messages specify address-only transactions. */ + if (msg->size < 1) + ctrl2 |= SP_ADDR_ONLY; + else /* For non-zero-sized set the length field. */ + ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT; + + if ((msg->request & DP_AUX_I2C_READ) == 0) { + /* When WRITE | MOT write values to data buffer */ + err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_BUF_DATA0_REG, buffer, + msg->size); + if (err) + return err; + } + + /* Write address and request */ + err = anx78xx_aux_address(anx78xx, msg->address); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG, + ctrl1); + if (err) + return err; + + /* Start transaction */ + err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY | + SP_AUX_EN, ctrl2); + if (err) + return err; + + err = anx78xx_aux_wait(anx78xx); + if (err) + return err; + + msg->reply = DP_AUX_I2C_REPLY_ACK; + + if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) { + /* Read values from data buffer */ + err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_BUF_DATA0_REG, buffer, + msg->size); + if (err) + return err; + } + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY); + if (err) + return err; + + return msg->size; +} + +static int anx78xx_set_hpd(struct anx78xx *anx78xx) +{ + int err; + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], + SP_TMDS_CTRL_BASE + 7, SP_PD_RT); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, + SP_HPD_OUT); + if (err) + return err; + + return 0; +} + +static int anx78xx_clear_hpd(struct anx78xx *anx78xx) +{ + int err; + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, + SP_HPD_OUT); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], + SP_TMDS_CTRL_BASE + 7, SP_PD_RT); + if (err) + return err; + + return 0; +} + +static const struct reg_sequence tmds_phy_initialization[] = { + { SP_TMDS_CTRL_BASE + 1, 0x90 }, + { SP_TMDS_CTRL_BASE + 2, 0xa9 }, + { SP_TMDS_CTRL_BASE + 6, 0x92 }, + { SP_TMDS_CTRL_BASE + 7, 0x80 }, + { SP_TMDS_CTRL_BASE + 20, 0xf2 }, + { SP_TMDS_CTRL_BASE + 22, 0xc4 }, + { SP_TMDS_CTRL_BASE + 23, 0x18 }, +}; + +static int anx78xx_rx_initialization(struct anx78xx *anx78xx) +{ + int err; + + err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, + SP_AUD_MUTE | SP_VID_MUTE); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG, + SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN | + SP_DIGITAL_CKDT_EN); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], + SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST | + SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST); + if (err) + return err; + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], + SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST | + SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST); + if (err) + return err; + + /* Sync detect change, GP set mute */ + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], + SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) | + BIT(6)); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], + SP_AUD_EXCEPTION_ENABLE_BASE + 3, + SP_AEC_EN21); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG, + SP_AVC_EN | SP_AAC_OE | SP_AAC_EN); + if (err) + return err; + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], + SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], + SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT); + if (err) + return err; + + /* Enable DDC stretch */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR); + if (err) + return err; + + /* TMDS phy initialization */ + err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0], + tmds_phy_initialization, + ARRAY_SIZE(tmds_phy_initialization)); + if (err) + return err; + + err = anx78xx_clear_hpd(anx78xx); + if (err) + return err; + + return 0; +} + +static const u8 dp_tx_output_precise_tune_bits[20] = { + 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f, + 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00, + 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e, +}; + +static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx) +{ + int err; + + /* + * REVISIT : It is writing to a RESERVED bits in Analog Control 0 + * register. + */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG, + 0x02); + if (err) + return err; + + /* + * Write DP TX output emphasis precise tune bits. + */ + err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1], + SP_DP_TX_LT_CTRL0_REG, + dp_tx_output_precise_tune_bits, + ARRAY_SIZE(dp_tx_output_precise_tune_bits)); + + if (err) + return err; + + return 0; +} + +static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx) +{ + unsigned int value; + int err; + + err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2], + SP_ANALOG_DEBUG2_REG, + SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS, + SP_XTAL_FRQ_27M); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG, + XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG, + ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10)); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], + SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], + SP_I2C_GEN_10US_TIMER1_REG, + (XTAL_CLK & 0xff00) >> 8); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG, + XTAL_CLK / 10 - 1); + if (err) + return err; + + err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], + SP_HDMI_US_TIMER_CTRL_REG, + &value); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], + SP_HDMI_US_TIMER_CTRL_REG, + (value & SP_MS_TIMER_MARGIN_10_8_MASK) | + ((((XTAL_CLK / 10) >> 1) - 2) << 3)); + if (err) + return err; + + return 0; +} + +static const struct reg_sequence otp_key_protect[] = { + { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 }, + { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 }, + { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 }, +}; + +static int anx78xx_tx_initialization(struct anx78xx *anx78xx) +{ + int err; + + /* Set terminal resistor to 50 ohm */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG, + 0x30); + if (err) + return err; + + /* Enable aux double diff output */ + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_AUX_CH_CTRL2_REG, 0x08); + if (err) + return err; + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_HDCP_CTRL_REG, SP_AUTO_EN | + SP_AUTO_START); + if (err) + return err; + + err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0], + otp_key_protect, + ARRAY_SIZE(otp_key_protect)); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG, + SP_VID_VRES_TH); + if (err) + return err; + + /* + * DP HDCP auto authentication wait timer (when downstream starts to + * auth, DP side will wait for this period then do auth automatically) + */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG, + 0x00); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], + SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS); + if (err) + return err; + + err = anx78xx_xtal_clk_sel(anx78xx); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG, + SP_DEFER_CTRL_EN | 0x0c); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_POLLING_CTRL_REG, + SP_AUTO_POLLING_DISABLE); + if (err) + return err; + + /* + * Short the link integrity check timer to speed up bstatus + * polling for HDCP CTS item 1A-07 + */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], + SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP); + if (err) + return err; + + /* Power down the main link by default */ + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD); + if (err) + return err; + + err = anx78xx_link_phy_initialization(anx78xx); + if (err) + return err; + + /* Gen m_clk with downspreading */ + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL); + if (err) + return err; + + return 0; +} + +static int anx78xx_enable_interrupts(struct anx78xx *anx78xx) +{ + int err; + + /* + * BIT0: INT pin assertion polarity: 1 = assert high + * BIT1: INT pin output type: 0 = push/pull + */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], + SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG, + SP_TRAINING_FINISH); + if (err) + return err; + + err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG, + SP_CKDT_CHG | SP_SCDT_CHG); + if (err) + return err; + + return 0; +} + +static void anx78xx_poweron(struct anx78xx *anx78xx) +{ + struct anx78xx_platform_data *pdata = &anx78xx->pdata; + int err; + + if (WARN_ON(anx78xx->powered)) + return; + + if (pdata->dvdd10) { + err = regulator_enable(pdata->dvdd10); + if (err) { + DRM_ERROR("Failed to enable DVDD10 regulator: %d\n", + err); + return; + } + + usleep_range(1000, 2000); + } + + gpiod_set_value_cansleep(pdata->gpiod_reset, 1); + usleep_range(1000, 2000); + + gpiod_set_value_cansleep(pdata->gpiod_pd, 0); + usleep_range(1000, 2000); + + gpiod_set_value_cansleep(pdata->gpiod_reset, 0); + + /* Power on registers module */ + anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, + SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD); + anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, + SP_REGISTER_PD | SP_TOTAL_PD); + + anx78xx->powered = true; +} + +static void anx78xx_poweroff(struct anx78xx *anx78xx) +{ + struct anx78xx_platform_data *pdata = &anx78xx->pdata; + int err; + + if (WARN_ON(!anx78xx->powered)) + return; + + gpiod_set_value_cansleep(pdata->gpiod_reset, 1); + usleep_range(1000, 2000); + + gpiod_set_value_cansleep(pdata->gpiod_pd, 1); + usleep_range(1000, 2000); + + if (pdata->dvdd10) { + err = regulator_disable(pdata->dvdd10); + if (err) { + DRM_ERROR("Failed to disable DVDD10 regulator: %d\n", + err); + return; + } + + usleep_range(1000, 2000); + } + + anx78xx->powered = false; +} + +static int anx78xx_start(struct anx78xx *anx78xx) +{ + int err; + + /* Power on all modules */ + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], + SP_POWERDOWN_CTRL_REG, + SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | + SP_LINK_PD); + + err = anx78xx_enable_interrupts(anx78xx); + if (err) { + DRM_ERROR("Failed to enable interrupts: %d\n", err); + goto err_poweroff; + } + + err = anx78xx_rx_initialization(anx78xx); + if (err) { + DRM_ERROR("Failed receiver initialization: %d\n", err); + goto err_poweroff; + } + + err = anx78xx_tx_initialization(anx78xx); + if (err) { + DRM_ERROR("Failed transmitter initialization: %d\n", err); + goto err_poweroff; + } + + /* + * This delay seems to help keep the hardware in a good state. Without + * it, there are times where it fails silently. + */ + usleep_range(10000, 15000); + + return 0; + +err_poweroff: + DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err); + anx78xx_poweroff(anx78xx); + + return err; +} + +static int anx78xx_init_pdata(struct anx78xx *anx78xx) +{ + struct anx78xx_platform_data *pdata = &anx78xx->pdata; + struct device *dev = &anx78xx->client->dev; + + /* 1.0V digital core power regulator */ + pdata->dvdd10 = devm_regulator_get(dev, "dvdd10"); + if (IS_ERR(pdata->dvdd10)) { + DRM_ERROR("DVDD10 regulator not found\n"); + return PTR_ERR(pdata->dvdd10); + } + + /* GPIO for HPD */ + pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN); + if (IS_ERR(pdata->gpiod_hpd)) + return PTR_ERR(pdata->gpiod_hpd); + + /* GPIO for chip power down */ + pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH); + if (IS_ERR(pdata->gpiod_pd)) + return PTR_ERR(pdata->gpiod_pd); + + /* GPIO for chip reset */ + pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + + return PTR_ERR_OR_ZERO(pdata->gpiod_reset); +} + +static int anx78xx_dp_link_training(struct anx78xx *anx78xx) +{ + u8 dp_bw, value; + int err; + + err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, + 0x0); + if (err) + return err; + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], + SP_POWERDOWN_CTRL_REG, + SP_TOTAL_PD); + if (err) + return err; + + err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw); + if (err < 0) + return err; + + switch (dp_bw) { + case DP_LINK_BW_1_62: + case DP_LINK_BW_2_7: + case DP_LINK_BW_5_4: + break; + + default: + DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw); + return -EINVAL; + } + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, + SP_VIDEO_MUTE); + if (err) + return err; + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], + SP_VID_CTRL1_REG, SP_VIDEO_EN); + if (err) + return err; + + /* Get DPCD info */ + err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV, + &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); + if (err < 0) { + DRM_ERROR("Failed to read DPCD: %d\n", err); + return err; + } + + /* Clear channel x SERDES power down */ + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD); + if (err) + return err; + + /* Check link capabilities */ + err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link); + if (err < 0) { + DRM_ERROR("Failed to probe link capabilities: %d\n", err); + return err; + } + + /* Power up the sink */ + err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link); + if (err < 0) { + DRM_ERROR("Failed to power up DisplayPort link: %d\n", err); + return err; + } + + /* Possibly enable downspread on the sink */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_DOWNSPREAD_CTRL1_REG, 0); + if (err) + return err; + + if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { + DRM_DEBUG("Enable downspread on the sink\n"); + /* 4000PPM */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_DOWNSPREAD_CTRL1_REG, 8); + if (err) + return err; + + err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, + DP_SPREAD_AMP_0_5); + if (err < 0) + return err; + } else { + err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0); + if (err < 0) + return err; + } + + /* Set the lane count and the link rate on the sink */ + if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_SYSTEM_CTRL_BASE + 4, + SP_ENHANCED_MODE); + else + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_SYSTEM_CTRL_BASE + 4, + SP_ENHANCED_MODE); + if (err) + return err; + + value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate); + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], + SP_DP_MAIN_LINK_BW_SET_REG, value); + if (err) + return err; + + err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link); + if (err < 0) { + DRM_ERROR("Failed to configure DisplayPort link: %d\n", err); + return err; + } + + /* Start training on the source */ + err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG, + SP_LT_EN); + if (err) + return err; + + return 0; +} + +static int anx78xx_config_dp_output(struct anx78xx *anx78xx) +{ + int err; + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, + SP_VIDEO_MUTE); + if (err) + return err; + + /* Enable DP output */ + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, + SP_VIDEO_EN); + if (err) + return err; + + return 0; +} + +static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx, + struct hdmi_avi_infoframe *frame) +{ + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; + int err; + + err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer)); + if (err < 0) { + DRM_ERROR("Failed to pack AVI infoframe: %d\n", err); + return err; + } + + err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN); + if (err) + return err; + + err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2], + SP_INFOFRAME_AVI_DB1_REG, buffer, + frame->length); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD); + if (err) + return err; + + err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], + SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN); + if (err) + return err; + + return 0; +} + +static int anx78xx_get_downstream_info(struct anx78xx *anx78xx) +{ + u8 value; + int err; + + err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value); + if (err < 0) { + DRM_ERROR("Get sink count failed %d\n", err); + return err; + } + + if (!DP_GET_SINK_COUNT(value)) { + DRM_ERROR("Downstream disconnected\n"); + return -EIO; + } + + return 0; +} + +static int anx78xx_get_modes(struct drm_connector *connector) +{ + struct anx78xx *anx78xx = connector_to_anx78xx(connector); + int err, num_modes = 0; + + if (WARN_ON(!anx78xx->powered)) + return 0; + + if (anx78xx->edid) + return drm_add_edid_modes(connector, anx78xx->edid); + + mutex_lock(&anx78xx->lock); + + err = anx78xx_get_downstream_info(anx78xx); + if (err) { + DRM_ERROR("Failed to get downstream info: %d\n", err); + goto unlock; + } + + anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc); + if (!anx78xx->edid) { + DRM_ERROR("Failed to read EDID\n"); + goto unlock; + } + + err = drm_mode_connector_update_edid_property(connector, + anx78xx->edid); + if (err) { + DRM_ERROR("Failed to update EDID property: %d\n", err); + goto unlock; + } + + num_modes = drm_add_edid_modes(connector, anx78xx->edid); + /* Store the ELD */ + drm_edid_to_eld(connector, anx78xx->edid); + +unlock: + mutex_unlock(&anx78xx->lock); + + return num_modes; +} + +static struct drm_encoder *anx78xx_best_encoder(struct drm_connector *connector) +{ + struct anx78xx *anx78xx = connector_to_anx78xx(connector); + + return anx78xx->bridge.encoder; +} + +static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = { + .get_modes = anx78xx_get_modes, + .best_encoder = anx78xx_best_encoder, +}; + +static enum drm_connector_status anx78xx_detect(struct drm_connector *connector, + bool force) +{ + struct anx78xx *anx78xx = connector_to_anx78xx(connector); + + if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd)) + return connector_status_disconnected; + + return connector_status_connected; +} + +static void anx78xx_connector_destroy(struct drm_connector *connector) +{ + drm_connector_cleanup(connector); +} + +static const struct drm_connector_funcs anx78xx_connector_funcs = { + .dpms = drm_atomic_helper_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = anx78xx_detect, + .destroy = anx78xx_connector_destroy, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int anx78xx_bridge_attach(struct drm_bridge *bridge) +{ + struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); + int err; + + if (!bridge->encoder) { + DRM_ERROR("Parent encoder object not found"); + return -ENODEV; + } + + /* Register aux channel */ + anx78xx->aux.name = "DP-AUX"; + anx78xx->aux.dev = &anx78xx->client->dev; + anx78xx->aux.transfer = anx78xx_aux_transfer; + + err = drm_dp_aux_register(&anx78xx->aux); + if (err < 0) { + DRM_ERROR("Failed to register aux channel: %d\n", err); + return err; + } + + err = drm_connector_init(bridge->dev, &anx78xx->connector, + &anx78xx_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort); + if (err) { + DRM_ERROR("Failed to initialize connector: %d\n", err); + return err; + } + + drm_connector_helper_add(&anx78xx->connector, + &anx78xx_connector_helper_funcs); + + err = drm_connector_register(&anx78xx->connector); + if (err) { + DRM_ERROR("Failed to register connector: %d\n", err); + return err; + } + + anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD; + + err = drm_mode_connector_attach_encoder(&anx78xx->connector, + bridge->encoder); + if (err) { + DRM_ERROR("Failed to link up connector to encoder: %d\n", err); + return err; + } + + return 0; +} + +static bool anx78xx_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + return false; + + /* Max 1200p at 5.4 Ghz, one lane */ + if (mode->clock > 154000) + return false; + + return true; +} + +static void anx78xx_bridge_disable(struct drm_bridge *bridge) +{ + struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); + + /* Power off all modules except configuration registers access */ + anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, + SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD); +} + +static void anx78xx_bridge_mode_set(struct drm_bridge *bridge, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); + struct hdmi_avi_infoframe frame; + int err; + + if (WARN_ON(!anx78xx->powered)) + return; + + mutex_lock(&anx78xx->lock); + + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, adjusted_mode); + if (err) { + DRM_ERROR("Failed to setup AVI infoframe: %d\n", err); + goto unlock; + } + + err = anx78xx_send_video_infoframe(anx78xx, &frame); + if (err) + DRM_ERROR("Failed to send AVI infoframe: %d\n", err); + +unlock: + mutex_unlock(&anx78xx->lock); +} + +static void anx78xx_bridge_enable(struct drm_bridge *bridge) +{ + struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); + int err; + + err = anx78xx_start(anx78xx); + if (err) { + DRM_ERROR("Failed to initialize: %d\n", err); + return; + } + + err = anx78xx_set_hpd(anx78xx); + if (err) + DRM_ERROR("Failed to set HPD: %d\n", err); +} + +static const struct drm_bridge_funcs anx78xx_bridge_funcs = { + .attach = anx78xx_bridge_attach, + .mode_fixup = anx78xx_bridge_mode_fixup, + .disable = anx78xx_bridge_disable, + .mode_set = anx78xx_bridge_mode_set, + .enable = anx78xx_bridge_enable, +}; + +static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data) +{ + struct anx78xx *anx78xx = data; + int err; + + if (anx78xx->powered) + return IRQ_HANDLED; + + mutex_lock(&anx78xx->lock); + + /* Cable is pulled, power on the chip */ + anx78xx_poweron(anx78xx); + + err = anx78xx_enable_interrupts(anx78xx); + if (err) + DRM_ERROR("Failed to enable interrupts: %d\n", err); + + mutex_unlock(&anx78xx->lock); + + return IRQ_HANDLED; +} + +static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq) +{ + int err; + + DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq); + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG, + irq); + if (err) + return err; + + if (irq & SP_TRAINING_FINISH) { + DRM_DEBUG_KMS("IRQ: hardware link training finished\n"); + err = anx78xx_config_dp_output(anx78xx); + } + + return err; +} + +static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq) +{ + bool event = false; + int err; + + DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq); + + err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], + SP_COMMON_INT_STATUS4_REG, irq); + if (err) { + DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err); + return event; + } + + if (irq & SP_HPD_LOST) { + DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n"); + event = true; + anx78xx_poweroff(anx78xx); + /* Free cached EDID */ + kfree(anx78xx->edid); + anx78xx->edid = NULL; + } else if (irq & SP_HPD_PLUG) { + DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n"); + event = true; + } + + return event; +} + +static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq) +{ + unsigned int value; + int err; + + DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq); + + err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG, + irq); + if (err) { + DRM_ERROR("Write HDMI int 1 failed: %d\n", err); + return; + } + + if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) { + DRM_DEBUG_KMS("IRQ: HDMI input detected\n"); + + err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], + SP_SYSTEM_STATUS_REG, &value); + if (err) { + DRM_ERROR("Read system status reg failed: %d\n", err); + return; + } + + if (!(value & SP_TMDS_CLOCK_DET)) { + DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n"); + return; + } + + if (!(value & SP_TMDS_DE_DET)) { + DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n"); + return; + } + + err = anx78xx_dp_link_training(anx78xx); + if (err) + DRM_ERROR("Failed to start link training: %d\n", err); + } +} + +static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data) +{ + struct anx78xx *anx78xx = data; + bool event = false; + unsigned int irq; + int err; + + mutex_lock(&anx78xx->lock); + + err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG, + &irq); + if (err) { + DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err); + goto unlock; + } + + if (irq) + anx78xx_handle_dp_int_1(anx78xx, irq); + + err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], + SP_COMMON_INT_STATUS4_REG, &irq); + if (err) { + DRM_ERROR("Failed to read common interrupt 4 status: %d\n", + err); + goto unlock; + } + + if (irq) + event = anx78xx_handle_common_int_4(anx78xx, irq); + + /* Make sure we are still powered after handle HPD events */ + if (!anx78xx->powered) + goto unlock; + + err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG, + &irq); + if (err) { + DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err); + goto unlock; + } + + if (irq) + anx78xx_handle_hdmi_int_1(anx78xx, irq); + +unlock: + mutex_unlock(&anx78xx->lock); + + if (event) + drm_helper_hpd_irq_event(anx78xx->connector.dev); + + return IRQ_HANDLED; +} + +static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++) + if (anx78xx->i2c_dummy[i]) + i2c_unregister_device(anx78xx->i2c_dummy[i]); +} + +static const struct regmap_config anx78xx_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static const u16 anx78xx_chipid_list[] = { + 0x7812, + 0x7814, + 0x7818, +}; + +static int anx78xx_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct anx78xx *anx78xx; + struct anx78xx_platform_data *pdata; + unsigned int i, idl, idh, version; + bool found = false; + int err; + + anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL); + if (!anx78xx) + return -ENOMEM; + + pdata = &anx78xx->pdata; + + mutex_init(&anx78xx->lock); + +#if IS_ENABLED(CONFIG_OF) + anx78xx->bridge.of_node = client->dev.of_node; +#endif + + anx78xx->client = client; + i2c_set_clientdata(client, anx78xx); + + err = anx78xx_init_pdata(anx78xx); + if (err) { + DRM_ERROR("Failed to initialize pdata: %d\n", err); + return err; + } + + pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd); + if (pdata->hpd_irq < 0) { + DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq); + return -ENODEV; + } + + pdata->intp_irq = client->irq; + if (!pdata->intp_irq) { + DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n"); + return -ENODEV; + } + + /* Map slave addresses of ANX7814 */ + for (i = 0; i < I2C_NUM_ADDRESSES; i++) { + anx78xx->i2c_dummy[i] = i2c_new_dummy(client->adapter, + anx78xx_i2c_addresses[i] >> 1); + if (!anx78xx->i2c_dummy[i]) { + err = -ENOMEM; + DRM_ERROR("Failed to reserve I2C bus %02x\n", + anx78xx_i2c_addresses[i]); + goto err_unregister_i2c; + } + + anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i], + &anx78xx_regmap_config); + if (IS_ERR(anx78xx->map[i])) { + err = PTR_ERR(anx78xx->map[i]); + DRM_ERROR("Failed regmap initialization %02x\n", + anx78xx_i2c_addresses[i]); + goto err_unregister_i2c; + } + } + + /* Look for supported chip ID */ + anx78xx_poweron(anx78xx); + + err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG, + &idl); + if (err) + goto err_poweroff; + + err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG, + &idh); + if (err) + goto err_poweroff; + + anx78xx->chipid = (u8)idl | ((u8)idh << 8); + + err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG, + &version); + if (err) + goto err_poweroff; + + for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) { + if (anx78xx->chipid == anx78xx_chipid_list[i]) { + DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n", + anx78xx->chipid, version); + found = true; + break; + } + } + + if (!found) { + DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n", + anx78xx->chipid, version); + err = -ENODEV; + goto err_poweroff; + } + + err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL, + anx78xx_hpd_threaded_handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "anx78xx-hpd", anx78xx); + if (err) { + DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n", + err); + goto err_poweroff; + } + + err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL, + anx78xx_intp_threaded_handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "anx78xx-intp", anx78xx); + if (err) { + DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err); + goto err_poweroff; + } + + anx78xx->bridge.funcs = &anx78xx_bridge_funcs; + + err = drm_bridge_add(&anx78xx->bridge); + if (err < 0) { + DRM_ERROR("Failed to add drm bridge: %d\n", err); + goto err_poweroff; + } + + /* If cable is pulled out, just poweroff and wait for HPD event */ + if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd)) + anx78xx_poweroff(anx78xx); + + return 0; + +err_poweroff: + anx78xx_poweroff(anx78xx); + +err_unregister_i2c: + unregister_i2c_dummy_clients(anx78xx); + return err; +} + +static int anx78xx_i2c_remove(struct i2c_client *client) +{ + struct anx78xx *anx78xx = i2c_get_clientdata(client); + + drm_bridge_remove(&anx78xx->bridge); + + unregister_i2c_dummy_clients(anx78xx); + + kfree(anx78xx->edid); + + return 0; +} + +static const struct i2c_device_id anx78xx_id[] = { + { "anx7814", 0 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(i2c, anx78xx_id); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id anx78xx_match_table[] = { + { .compatible = "analogix,anx7814", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, anx78xx_match_table); +#endif + +static struct i2c_driver anx78xx_driver = { + .driver = { + .name = "anx7814", + .of_match_table = of_match_ptr(anx78xx_match_table), + }, + .probe = anx78xx_i2c_probe, + .remove = anx78xx_i2c_remove, + .id_table = anx78xx_id, +}; +module_i2c_driver(anx78xx_driver); + +MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver"); +MODULE_AUTHOR("Enric Balletbo i Serra "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.h b/drivers/gpu/drm/bridge/analogix-anx78xx.h new file mode 100644 index 000000000000..38753c870137 --- /dev/null +++ b/drivers/gpu/drm/bridge/analogix-anx78xx.h @@ -0,0 +1,719 @@ +/* + * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ANX78xx_H +#define __ANX78xx_H + +#define TX_P0 0x70 +#define TX_P1 0x7a +#define TX_P2 0x72 + +#define RX_P0 0x7e +#define RX_P1 0x80 + +/***************************************************************/ +/* Register definition of device address 0x7e */ +/***************************************************************/ + +/* + * System Control and Status + */ + +/* Software Reset Register 1 */ +#define SP_SOFTWARE_RESET1_REG 0x11 +#define SP_VIDEO_RST BIT(4) +#define SP_HDCP_MAN_RST BIT(2) +#define SP_TMDS_RST BIT(1) +#define SP_SW_MAN_RST BIT(0) + +/* System Status Register */ +#define SP_SYSTEM_STATUS_REG 0x14 +#define SP_TMDS_CLOCK_DET BIT(1) +#define SP_TMDS_DE_DET BIT(0) + +/* HDMI Status Register */ +#define SP_HDMI_STATUS_REG 0x15 +#define SP_HDMI_AUD_LAYOUT BIT(3) +#define SP_HDMI_DET BIT(0) +# define SP_DVI_MODE 0 +# define SP_HDMI_MODE 1 + +/* HDMI Mute Control Register */ +#define SP_HDMI_MUTE_CTRL_REG 0x16 +#define SP_AUD_MUTE BIT(1) +#define SP_VID_MUTE BIT(0) + +/* System Power Down Register 1 */ +#define SP_SYSTEM_POWER_DOWN1_REG 0x18 +#define SP_PWDN_CTRL BIT(0) + +/* + * Audio and Video Auto Control + */ + +/* Auto Audio and Video Control register */ +#define SP_AUDVID_CTRL_REG 0x20 +#define SP_AVC_OE BIT(7) +#define SP_AAC_OE BIT(6) +#define SP_AVC_EN BIT(1) +#define SP_AAC_EN BIT(0) + +/* Audio Exception Enable Registers */ +#define SP_AUD_EXCEPTION_ENABLE_BASE (0x24 - 1) +/* Bits for Audio Exception Enable Register 3 */ +#define SP_AEC_EN21 BIT(5) + +/* + * Interrupt + */ + +/* Interrupt Status Register 1 */ +#define SP_INT_STATUS1_REG 0x31 +/* Bits for Interrupt Status Register 1 */ +#define SP_HDMI_DVI BIT(7) +#define SP_CKDT_CHG BIT(6) +#define SP_SCDT_CHG BIT(5) +#define SP_PCLK_CHG BIT(4) +#define SP_PLL_UNLOCK BIT(3) +#define SP_CABLE_PLUG_CHG BIT(2) +#define SP_SET_MUTE BIT(1) +#define SP_SW_INTR BIT(0) +/* Bits for Interrupt Status Register 2 */ +#define SP_HDCP_ERR BIT(5) +#define SP_AUDIO_SAMPLE_CHG BIT(0) /* undocumented */ +/* Bits for Interrupt Status Register 3 */ +#define SP_AUD_MODE_CHG BIT(0) +/* Bits for Interrupt Status Register 5 */ +#define SP_AUDIO_RCV BIT(0) +/* Bits for Interrupt Status Register 6 */ +#define SP_INT_STATUS6_REG 0x36 +#define SP_CTS_RCV BIT(7) +#define SP_NEW_AUD_PKT BIT(4) +#define SP_NEW_AVI_PKT BIT(1) +#define SP_NEW_CP_PKT BIT(0) +/* Bits for Interrupt Status Register 7 */ +#define SP_NO_VSI BIT(7) +#define SP_NEW_VS BIT(4) + +/* Interrupt Mask 1 Status Registers */ +#define SP_INT_MASK1_REG 0x41 + +/* HDMI US TIMER Control Register */ +#define SP_HDMI_US_TIMER_CTRL_REG 0x49 +#define SP_MS_TIMER_MARGIN_10_8_MASK 0x07 + +/* + * TMDS Control + */ + +/* TMDS Control Registers */ +#define SP_TMDS_CTRL_BASE (0x50 - 1) +/* Bits for TMDS Control Register 7 */ +#define SP_PD_RT BIT(0) + +/* + * Video Control + */ + +/* Video Status Register */ +#define SP_VIDEO_STATUS_REG 0x70 +#define SP_COLOR_DEPTH_MASK 0xf0 +#define SP_COLOR_DEPTH_SHIFT 4 +# define SP_COLOR_DEPTH_MODE_LEGACY 0x00 +# define SP_COLOR_DEPTH_MODE_24BIT 0x04 +# define SP_COLOR_DEPTH_MODE_30BIT 0x05 +# define SP_COLOR_DEPTH_MODE_36BIT 0x06 +# define SP_COLOR_DEPTH_MODE_48BIT 0x07 + +/* Video Data Range Control Register */ +#define SP_VID_DATA_RANGE_CTRL_REG 0x83 +#define SP_R2Y_INPUT_LIMIT BIT(1) + +/* Pixel Clock High Resolution Counter Registers */ +#define SP_PCLK_HIGHRES_CNT_BASE (0x8c - 1) + +/* + * Audio Control + */ + +/* Number of Audio Channels Status Registers */ +#define SP_AUD_CH_STATUS_REG_NUM 6 + +/* Audio IN S/PDIF Channel Status Registers */ +#define SP_AUD_SPDIF_CH_STATUS_BASE 0xc7 + +/* Audio IN S/PDIF Channel Status Register 4 */ +#define SP_FS_FREQ_MASK 0x0f +# define SP_FS_FREQ_44100HZ 0x00 +# define SP_FS_FREQ_48000HZ 0x02 +# define SP_FS_FREQ_32000HZ 0x03 +# define SP_FS_FREQ_88200HZ 0x08 +# define SP_FS_FREQ_96000HZ 0x0a +# define SP_FS_FREQ_176400HZ 0x0c +# define SP_FS_FREQ_192000HZ 0x0e + +/* + * Micellaneous Control Block + */ + +/* CHIP Control Register */ +#define SP_CHIP_CTRL_REG 0xe3 +#define SP_MAN_HDMI5V_DET BIT(3) +#define SP_PLLLOCK_CKDT_EN BIT(2) +#define SP_ANALOG_CKDT_EN BIT(1) +#define SP_DIGITAL_CKDT_EN BIT(0) + +/* Packet Receiving Status Register */ +#define SP_PACKET_RECEIVING_STATUS_REG 0xf3 +#define SP_AVI_RCVD BIT(5) +#define SP_VSI_RCVD BIT(1) + +/***************************************************************/ +/* Register definition of device address 0x80 */ +/***************************************************************/ + +/* HDCP BCAPS Shadow Register */ +#define SP_HDCP_BCAPS_SHADOW_REG 0x2a +#define SP_BCAPS_REPEATER BIT(5) + +/* HDCP Status Register */ +#define SP_RX_HDCP_STATUS_REG 0x3f +#define SP_AUTH_EN BIT(4) + +/* + * InfoFrame and Control Packet Registers + */ + +/* AVI InfoFrame packet checksum */ +#define SP_AVI_INFOFRAME_CHECKSUM 0xa3 + +/* AVI InfoFrame Registers */ +#define SP_AVI_INFOFRAME_DATA_BASE 0xa4 + +#define SP_AVI_COLOR_F_MASK 0x60 +#define SP_AVI_COLOR_F_SHIFT 5 + +/* Audio InfoFrame Registers */ +#define SP_AUD_INFOFRAME_DATA_BASE 0xc4 +#define SP_AUD_INFOFRAME_LAYOUT_MASK 0x0f + +/* MPEG/HDMI Vendor Specific InfoFrame Packet type code */ +#define SP_MPEG_VS_INFOFRAME_TYPE_REG 0xe0 + +/* MPEG/HDMI Vendor Specific InfoFrame Packet length */ +#define SP_MPEG_VS_INFOFRAME_LEN_REG 0xe2 + +/* MPEG/HDMI Vendor Specific InfoFrame Packet version number */ +#define SP_MPEG_VS_INFOFRAME_VER_REG 0xe1 + +/* MPEG/HDMI Vendor Specific InfoFrame Packet content */ +#define SP_MPEG_VS_INFOFRAME_DATA_BASE 0xe4 + +/* General Control Packet Register */ +#define SP_GENERAL_CTRL_PACKET_REG 0x9f +#define SP_CLEAR_AVMUTE BIT(4) +#define SP_SET_AVMUTE BIT(0) + +/***************************************************************/ +/* Register definition of device address 0x70 */ +/***************************************************************/ + +/* HDCP Status Register */ +#define SP_TX_HDCP_STATUS_REG 0x00 +#define SP_AUTH_FAIL BIT(5) +#define SP_AUTHEN_PASS BIT(1) + +/* HDCP Control Register 0 */ +#define SP_HDCP_CTRL0_REG 0x01 +#define SP_RX_REPEATER BIT(6) +#define SP_RE_AUTH BIT(5) +#define SP_SW_AUTH_OK BIT(4) +#define SP_HARD_AUTH_EN BIT(3) +#define SP_HDCP_ENC_EN BIT(2) +#define SP_BKSV_SRM_PASS BIT(1) +#define SP_KSVLIST_VLD BIT(0) +/* HDCP Function Enabled */ +#define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +/* HDCP Receiver BSTATUS Register 0 */ +#define SP_HDCP_RX_BSTATUS0_REG 0x1b +/* HDCP Receiver BSTATUS Register 1 */ +#define SP_HDCP_RX_BSTATUS1_REG 0x1c + +/* HDCP Embedded "Blue Screen" Content Registers */ +#define SP_HDCP_VID0_BLUE_SCREEN_REG 0x2c +#define SP_HDCP_VID1_BLUE_SCREEN_REG 0x2d +#define SP_HDCP_VID2_BLUE_SCREEN_REG 0x2e + +/* HDCP Wait R0 Timing Register */ +#define SP_HDCP_WAIT_R0_TIME_REG 0x40 + +/* HDCP Link Integrity Check Timer Register */ +#define SP_HDCP_LINK_CHECK_TIMER_REG 0x41 + +/* HDCP Repeater Ready Wait Timer Register */ +#define SP_HDCP_RPTR_RDY_WAIT_TIME_REG 0x42 + +/* HDCP Auto Timer Register */ +#define SP_HDCP_AUTO_TIMER_REG 0x51 + +/* HDCP Key Status Register */ +#define SP_HDCP_KEY_STATUS_REG 0x5e + +/* HDCP Key Command Register */ +#define SP_HDCP_KEY_COMMAND_REG 0x5f +#define SP_DISABLE_SYNC_HDCP BIT(2) + +/* OTP Memory Key Protection Registers */ +#define SP_OTP_KEY_PROTECT1_REG 0x60 +#define SP_OTP_KEY_PROTECT2_REG 0x61 +#define SP_OTP_KEY_PROTECT3_REG 0x62 +#define SP_OTP_PSW1 0xa2 +#define SP_OTP_PSW2 0x7e +#define SP_OTP_PSW3 0xc6 + +/* DP System Control Registers */ +#define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1) +/* Bits for DP System Control Register 2 */ +#define SP_CHA_STA BIT(2) +/* Bits for DP System Control Register 3 */ +#define SP_HPD_STATUS BIT(6) +#define SP_STRM_VALID BIT(2) +/* Bits for DP System Control Register 4 */ +#define SP_ENHANCED_MODE BIT(3) + +/* DP Video Control Register */ +#define SP_DP_VIDEO_CTRL_REG 0x84 +#define SP_COLOR_F_MASK 0x06 +#define SP_COLOR_F_SHIFT 1 +#define SP_BPC_MASK 0xe0 +#define SP_BPC_SHIFT 5 +# define SP_BPC_6BITS 0x00 +# define SP_BPC_8BITS 0x01 +# define SP_BPC_10BITS 0x02 +# define SP_BPC_12BITS 0x03 + +/* DP Audio Control Register */ +#define SP_DP_AUDIO_CTRL_REG 0x87 +#define SP_AUD_EN BIT(0) + +/* 10us Pulse Generate Timer Registers */ +#define SP_I2C_GEN_10US_TIMER0_REG 0x88 +#define SP_I2C_GEN_10US_TIMER1_REG 0x89 + +/* Packet Send Control Register */ +#define SP_PACKET_SEND_CTRL_REG 0x90 +#define SP_AUD_IF_UP BIT(7) +#define SP_AVI_IF_UD BIT(6) +#define SP_MPEG_IF_UD BIT(5) +#define SP_SPD_IF_UD BIT(4) +#define SP_AUD_IF_EN BIT(3) +#define SP_AVI_IF_EN BIT(2) +#define SP_MPEG_IF_EN BIT(1) +#define SP_SPD_IF_EN BIT(0) + +/* DP HDCP Control Register */ +#define SP_DP_HDCP_CTRL_REG 0x92 +#define SP_AUTO_EN BIT(7) +#define SP_AUTO_START BIT(5) +#define SP_LINK_POLLING BIT(1) + +/* DP Main Link Bandwidth Setting Register */ +#define SP_DP_MAIN_LINK_BW_SET_REG 0xa0 +#define SP_LINK_BW_SET_MASK 0x1f +#define SP_INITIAL_SLIM_M_AUD_SEL BIT(5) + +/* DP Training Pattern Set Register */ +#define SP_DP_TRAINING_PATTERN_SET_REG 0xa2 + +/* DP Lane 0 Link Training Control Register */ +#define SP_DP_LANE0_LT_CTRL_REG 0xa3 +#define SP_TX_SW_SET_MASK 0x1b +#define SP_MAX_PRE_REACH BIT(5) +#define SP_MAX_DRIVE_REACH BIT(4) +#define SP_PRE_EMP_LEVEL1 BIT(3) +#define SP_DRVIE_CURRENT_LEVEL1 BIT(0) + +/* DP Link Training Control Register */ +#define SP_DP_LT_CTRL_REG 0xa8 +#define SP_LT_ERROR_TYPE_MASK 0x70 +# define SP_LT_NO_ERROR 0x00 +# define SP_LT_AUX_WRITE_ERROR 0x01 +# define SP_LT_MAX_DRIVE_REACHED 0x02 +# define SP_LT_WRONG_LANE_COUNT_SET 0x03 +# define SP_LT_LOOP_SAME_5_TIME 0x04 +# define SP_LT_CR_FAIL_IN_EQ 0x05 +# define SP_LT_EQ_LOOP_5_TIME 0x06 +#define SP_LT_EN BIT(0) + +/* DP CEP Training Control Registers */ +#define SP_DP_CEP_TRAINING_CTRL0_REG 0xa9 +#define SP_DP_CEP_TRAINING_CTRL1_REG 0xaa + +/* DP Debug Register 1 */ +#define SP_DP_DEBUG1_REG 0xb0 +#define SP_DEBUG_PLL_LOCK BIT(4) +#define SP_POLLING_EN BIT(1) + +/* DP Polling Control Register */ +#define SP_DP_POLLING_CTRL_REG 0xb4 +#define SP_AUTO_POLLING_DISABLE BIT(0) + +/* DP Link Debug Control Register */ +#define SP_DP_LINK_DEBUG_CTRL_REG 0xb8 +#define SP_M_VID_DEBUG BIT(5) +#define SP_NEW_PRBS7 BIT(4) +#define SP_INSERT_ER BIT(1) +#define SP_PRBS31_EN BIT(0) + +/* AUX Misc control Register */ +#define SP_AUX_MISC_CTRL_REG 0xbf + +/* DP PLL control Register */ +#define SP_DP_PLL_CTRL_REG 0xc7 +#define SP_PLL_RST BIT(6) + +/* DP Analog Power Down Register */ +#define SP_DP_ANALOG_POWER_DOWN_REG 0xc8 +#define SP_CH0_PD BIT(0) + +/* DP Misc Control Register */ +#define SP_DP_MISC_CTRL_REG 0xcd +#define SP_EQ_TRAINING_LOOP BIT(6) + +/* DP Extra I2C Device Address Register */ +#define SP_DP_EXTRA_I2C_DEV_ADDR_REG 0xce +#define SP_I2C_STRETCH_DISABLE BIT(7) + +#define SP_I2C_EXTRA_ADDR 0x50 + +/* DP Downspread Control Register 1 */ +#define SP_DP_DOWNSPREAD_CTRL1_REG 0xd0 + +/* DP M Value Calculation Control Register */ +#define SP_DP_M_CALCULATION_CTRL_REG 0xd9 +#define SP_M_GEN_CLK_SEL BIT(0) + +/* AUX Channel Access Status Register */ +#define SP_AUX_CH_STATUS_REG 0xe0 +#define SP_AUX_STATUS 0x0f + +/* AUX Channel DEFER Control Register */ +#define SP_AUX_DEFER_CTRL_REG 0xe2 +#define SP_DEFER_CTRL_EN BIT(7) + +/* DP Buffer Data Count Register */ +#define SP_BUF_DATA_COUNT_REG 0xe4 +#define SP_BUF_DATA_COUNT_MASK 0x1f +#define SP_BUF_CLR BIT(7) + +/* DP AUX Channel Control Register 1 */ +#define SP_DP_AUX_CH_CTRL1_REG 0xe5 +#define SP_AUX_TX_COMM_MASK 0x0f +#define SP_AUX_LENGTH_MASK 0xf0 +#define SP_AUX_LENGTH_SHIFT 4 + +/* DP AUX CH Address Register 0 */ +#define SP_AUX_ADDR_7_0_REG 0xe6 + +/* DP AUX CH Address Register 1 */ +#define SP_AUX_ADDR_15_8_REG 0xe7 + +/* DP AUX CH Address Register 2 */ +#define SP_AUX_ADDR_19_16_REG 0xe8 +#define SP_AUX_ADDR_19_16_MASK 0x0f + +/* DP AUX Channel Control Register 2 */ +#define SP_DP_AUX_CH_CTRL2_REG 0xe9 +#define SP_AUX_SEL_RXCM BIT(6) +#define SP_AUX_CHSEL BIT(3) +#define SP_AUX_PN_INV BIT(2) +#define SP_ADDR_ONLY BIT(1) +#define SP_AUX_EN BIT(0) + +/* DP Video Stream Control InfoFrame Register */ +#define SP_DP_3D_VSC_CTRL_REG 0xea +#define SP_INFO_FRAME_VSC_EN BIT(0) + +/* DP Video Stream Data Byte 1 Register */ +#define SP_DP_VSC_DB1_REG 0xeb + +/* DP AUX Channel Control Register 3 */ +#define SP_DP_AUX_CH_CTRL3_REG 0xec +#define SP_WAIT_COUNTER_7_0_MASK 0xff + +/* DP AUX Channel Control Register 4 */ +#define SP_DP_AUX_CH_CTRL4_REG 0xed + +/* DP AUX Buffer Data Registers */ +#define SP_DP_BUF_DATA0_REG 0xf0 + +/***************************************************************/ +/* Register definition of device address 0x72 */ +/***************************************************************/ + +/* + * Core Register Definitions + */ + +/* Device ID Low Byte Register */ +#define SP_DEVICE_IDL_REG 0x02 + +/* Device ID High Byte Register */ +#define SP_DEVICE_IDH_REG 0x03 + +/* Device version register */ +#define SP_DEVICE_VERSION_REG 0x04 + +/* Power Down Control Register */ +#define SP_POWERDOWN_CTRL_REG 0x05 +#define SP_REGISTER_PD BIT(7) +#define SP_HDCP_PD BIT(5) +#define SP_AUDIO_PD BIT(4) +#define SP_VIDEO_PD BIT(3) +#define SP_LINK_PD BIT(2) +#define SP_TOTAL_PD BIT(1) + +/* Reset Control Register 1 */ +#define SP_RESET_CTRL1_REG 0x06 +#define SP_MISC_RST BIT(7) +#define SP_VIDCAP_RST BIT(6) +#define SP_VIDFIF_RST BIT(5) +#define SP_AUDFIF_RST BIT(4) +#define SP_AUDCAP_RST BIT(3) +#define SP_HDCP_RST BIT(2) +#define SP_SW_RST BIT(1) +#define SP_HW_RST BIT(0) + +/* Reset Control Register 2 */ +#define SP_RESET_CTRL2_REG 0x07 +#define SP_AUX_RST BIT(2) +#define SP_SERDES_FIFO_RST BIT(1) +#define SP_I2C_REG_RST BIT(0) + +/* Video Control Register 1 */ +#define SP_VID_CTRL1_REG 0x08 +#define SP_VIDEO_EN BIT(7) +#define SP_VIDEO_MUTE BIT(2) +#define SP_DE_GEN BIT(1) +#define SP_DEMUX BIT(0) + +/* Video Control Register 2 */ +#define SP_VID_CTRL2_REG 0x09 +#define SP_IN_COLOR_F_MASK 0x03 +#define SP_IN_YC_BIT_SEL BIT(2) +#define SP_IN_BPC_MASK 0x70 +#define SP_IN_BPC_SHIFT 4 +# define SP_IN_BPC_12BIT 0x03 +# define SP_IN_BPC_10BIT 0x02 +# define SP_IN_BPC_8BIT 0x01 +# define SP_IN_BPC_6BIT 0x00 +#define SP_IN_D_RANGE BIT(7) + +/* Video Control Register 3 */ +#define SP_VID_CTRL3_REG 0x0a +#define SP_HPD_OUT BIT(6) + +/* Video Control Register 5 */ +#define SP_VID_CTRL5_REG 0x0c +#define SP_CSC_STD_SEL BIT(7) +#define SP_XVYCC_RNG_LMT BIT(6) +#define SP_RANGE_Y2R BIT(5) +#define SP_CSPACE_Y2R BIT(4) +#define SP_RGB_RNG_LMT BIT(3) +#define SP_Y_RNG_LMT BIT(2) +#define SP_RANGE_R2Y BIT(1) +#define SP_CSPACE_R2Y BIT(0) + +/* Video Control Register 6 */ +#define SP_VID_CTRL6_REG 0x0d +#define SP_TEST_PATTERN_EN BIT(7) +#define SP_VIDEO_PROCESS_EN BIT(6) +#define SP_VID_US_MODE BIT(3) +#define SP_VID_DS_MODE BIT(2) +#define SP_UP_SAMPLE BIT(1) +#define SP_DOWN_SAMPLE BIT(0) + +/* Video Control Register 8 */ +#define SP_VID_CTRL8_REG 0x0f +#define SP_VID_VRES_TH BIT(0) + +/* Total Line Status Low Byte Register */ +#define SP_TOTAL_LINE_STAL_REG 0x24 + +/* Total Line Status High Byte Register */ +#define SP_TOTAL_LINE_STAH_REG 0x25 + +/* Active Line Status Low Byte Register */ +#define SP_ACT_LINE_STAL_REG 0x26 + +/* Active Line Status High Byte Register */ +#define SP_ACT_LINE_STAH_REG 0x27 + +/* Vertical Front Porch Status Register */ +#define SP_V_F_PORCH_STA_REG 0x28 + +/* Vertical SYNC Width Status Register */ +#define SP_V_SYNC_STA_REG 0x29 + +/* Vertical Back Porch Status Register */ +#define SP_V_B_PORCH_STA_REG 0x2a + +/* Total Pixel Status Low Byte Register */ +#define SP_TOTAL_PIXEL_STAL_REG 0x2b + +/* Total Pixel Status High Byte Register */ +#define SP_TOTAL_PIXEL_STAH_REG 0x2c + +/* Active Pixel Status Low Byte Register */ +#define SP_ACT_PIXEL_STAL_REG 0x2d + +/* Active Pixel Status High Byte Register */ +#define SP_ACT_PIXEL_STAH_REG 0x2e + +/* Horizontal Front Porch Status Low Byte Register */ +#define SP_H_F_PORCH_STAL_REG 0x2f + +/* Horizontal Front Porch Statys High Byte Register */ +#define SP_H_F_PORCH_STAH_REG 0x30 + +/* Horizontal SYNC Width Status Low Byte Register */ +#define SP_H_SYNC_STAL_REG 0x31 + +/* Horizontal SYNC Width Status High Byte Register */ +#define SP_H_SYNC_STAH_REG 0x32 + +/* Horizontal Back Porch Status Low Byte Register */ +#define SP_H_B_PORCH_STAL_REG 0x33 + +/* Horizontal Back Porch Status High Byte Register */ +#define SP_H_B_PORCH_STAH_REG 0x34 + +/* InfoFrame AVI Packet DB1 Register */ +#define SP_INFOFRAME_AVI_DB1_REG 0x70 + +/* Bit Control Specific Register */ +#define SP_BIT_CTRL_SPECIFIC_REG 0x80 +#define SP_BIT_CTRL_SELECT_SHIFT 1 +#define SP_ENABLE_BIT_CTRL BIT(0) + +/* InfoFrame Audio Packet DB1 Register */ +#define SP_INFOFRAME_AUD_DB1_REG 0x83 + +/* InfoFrame MPEG Packet DB1 Register */ +#define SP_INFOFRAME_MPEG_DB1_REG 0xb0 + +/* Audio Channel Status Registers */ +#define SP_AUD_CH_STATUS_BASE 0xd0 + +/* Audio Channel Num Register 5 */ +#define SP_I2S_CHANNEL_NUM_MASK 0xe0 +# define SP_I2S_CH_NUM_1 (0x00 << 5) +# define SP_I2S_CH_NUM_2 (0x01 << 5) +# define SP_I2S_CH_NUM_3 (0x02 << 5) +# define SP_I2S_CH_NUM_4 (0x03 << 5) +# define SP_I2S_CH_NUM_5 (0x04 << 5) +# define SP_I2S_CH_NUM_6 (0x05 << 5) +# define SP_I2S_CH_NUM_7 (0x06 << 5) +# define SP_I2S_CH_NUM_8 (0x07 << 5) +#define SP_EXT_VUCP BIT(2) +#define SP_VBIT BIT(1) +#define SP_AUDIO_LAYOUT BIT(0) + +/* Analog Debug Register 2 */ +#define SP_ANALOG_DEBUG2_REG 0xdd +#define SP_FORCE_SW_OFF_BYPASS 0x20 +#define SP_XTAL_FRQ 0x1c +# define SP_XTAL_FRQ_19M2 (0x00 << 2) +# define SP_XTAL_FRQ_24M (0x01 << 2) +# define SP_XTAL_FRQ_25M (0x02 << 2) +# define SP_XTAL_FRQ_26M (0x03 << 2) +# define SP_XTAL_FRQ_27M (0x04 << 2) +# define SP_XTAL_FRQ_38M4 (0x05 << 2) +# define SP_XTAL_FRQ_52M (0x06 << 2) +#define SP_POWERON_TIME_1P5MS 0x03 + +/* Analog Control 0 Register */ +#define SP_ANALOG_CTRL0_REG 0xe1 + +/* Common Interrupt Status Register 1 */ +#define SP_COMMON_INT_STATUS_BASE (0xf1 - 1) +#define SP_PLL_LOCK_CHG 0x40 + +/* Common Interrupt Status Register 2 */ +#define SP_COMMON_INT_STATUS2 0xf2 +#define SP_HDCP_AUTH_CHG BIT(1) +#define SP_HDCP_AUTH_DONE BIT(0) + +#define SP_HDCP_LINK_CHECK_FAIL BIT(0) + +/* Common Interrupt Status Register 4 */ +#define SP_COMMON_INT_STATUS4_REG 0xf4 +#define SP_HPD_IRQ BIT(6) +#define SP_HPD_ESYNC_ERR BIT(4) +#define SP_HPD_CHG BIT(2) +#define SP_HPD_LOST BIT(1) +#define SP_HPD_PLUG BIT(0) + +/* DP Interrupt Status Register */ +#define SP_DP_INT_STATUS1_REG 0xf7 +#define SP_TRAINING_FINISH BIT(5) +#define SP_POLLING_ERR BIT(4) + +/* Common Interrupt Mask Register */ +#define SP_COMMON_INT_MASK_BASE (0xf8 - 1) + +#define SP_COMMON_INT_MASK4_REG 0xfb + +/* DP Interrupts Mask Register */ +#define SP_DP_INT_MASK1_REG 0xfe + +/* Interrupt Control Register */ +#define SP_INT_CTRL_REG 0xff + +/***************************************************************/ +/* Register definition of device address 0x7a */ +/***************************************************************/ + +/* DP TX Link Training Control Register */ +#define SP_DP_TX_LT_CTRL0_REG 0x30 + +/* PD 1.2 Lint Training 80bit Pattern Register */ +#define SP_DP_LT_80BIT_PATTERN0_REG 0x80 +#define SP_DP_LT_80BIT_PATTERN_REG_NUM 10 + +/* Audio Interface Control Register 0 */ +#define SP_AUD_INTERFACE_CTRL0_REG 0x5f +#define SP_AUD_INTERFACE_DISABLE 0x80 + +/* Audio Interface Control Register 2 */ +#define SP_AUD_INTERFACE_CTRL2_REG 0x60 +#define SP_M_AUD_ADJUST_ST 0x04 + +/* Audio Interface Control Register 3 */ +#define SP_AUD_INTERFACE_CTRL3_REG 0x62 + +/* Audio Interface Control Register 4 */ +#define SP_AUD_INTERFACE_CTRL4_REG 0x67 + +/* Audio Interface Control Register 5 */ +#define SP_AUD_INTERFACE_CTRL5_REG 0x68 + +/* Audio Interface Control Register 6 */ +#define SP_AUD_INTERFACE_CTRL6_REG 0x69 + +/* Firmware Version Register */ +#define SP_FW_VER_REG 0xb7 + +#endif diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig new file mode 100644 index 000000000000..80f286fa3a69 --- /dev/null +++ b/drivers/gpu/drm/bridge/analogix/Kconfig @@ -0,0 +1,3 @@ +config DRM_ANALOGIX_DP + tristate + depends on DRM diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile new file mode 100644 index 000000000000..cd4010ba6890 --- /dev/null +++ b/drivers/gpu/drm/bridge/analogix/Makefile @@ -0,0 +1,2 @@ +analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c new file mode 100644 index 000000000000..7699597070a1 --- /dev/null +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -0,0 +1,1430 @@ +/* +* Analogix DP (Display Port) core interface driver. +* +* Copyright (C) 2012 Samsung Electronics Co., Ltd. +* Author: Jingoo Han +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "analogix_dp_core.h" + +#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm) + +struct bridge_init { + struct i2c_client *client; + struct device_node *node; +}; + +static void analogix_dp_init_dp(struct analogix_dp_device *dp) +{ + analogix_dp_reset(dp); + + analogix_dp_swreset(dp); + + analogix_dp_init_analog_param(dp); + analogix_dp_init_interrupt(dp); + + /* SW defined function Normal operation */ + analogix_dp_enable_sw_function(dp); + + analogix_dp_config_interrupt(dp); + analogix_dp_init_analog_func(dp); + + analogix_dp_init_hpd(dp); + analogix_dp_init_aux(dp); +} + +static int analogix_dp_detect_hpd(struct analogix_dp_device *dp) +{ + int timeout_loop = 0; + + while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) { + if (analogix_dp_get_plug_in_status(dp) == 0) + return 0; + + timeout_loop++; + usleep_range(10, 11); + } + + /* + * Some edp screen do not have hpd signal, so we can't just + * return failed when hpd plug in detect failed, DT property + * "force-hpd" would indicate whether driver need this. + */ + if (!dp->force_hpd) + return -ETIMEDOUT; + + /* + * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH + * will not work, so we need to give a force hpd action to + * set HPD_STATUS manually. + */ + dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); + + analogix_dp_force_hpd(dp); + + if (analogix_dp_get_plug_in_status(dp) != 0) { + dev_err(dp->dev, "failed to get hpd plug in status\n"); + return -EINVAL; + } + + dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); + + return 0; +} + +static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) +{ + int i; + unsigned char sum = 0; + + for (i = 0; i < EDID_BLOCK_LENGTH; i++) + sum = sum + edid_data[i]; + + return sum; +} + +static int analogix_dp_read_edid(struct analogix_dp_device *dp) +{ + unsigned char *edid = dp->edid; + unsigned int extend_block = 0; + unsigned char sum; + unsigned char test_vector; + int retval; + + /* + * EDID device address is 0x50. + * However, if necessary, you must have set upper address + * into E-EDID in I2C device, 0x30. + */ + + /* Read Extension Flag, Number of 128-byte EDID extension blocks */ + retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, + EDID_EXTENSION_FLAG, + &extend_block); + if (retval) + return retval; + + if (extend_block > 0) { + dev_dbg(dp->dev, "EDID data includes a single extension!\n"); + + /* Read EDID data */ + retval = analogix_dp_read_bytes_from_i2c(dp, + I2C_EDID_DEVICE_ADDR, + EDID_HEADER_PATTERN, + EDID_BLOCK_LENGTH, + &edid[EDID_HEADER_PATTERN]); + if (retval != 0) { + dev_err(dp->dev, "EDID Read failed!\n"); + return -EIO; + } + sum = analogix_dp_calc_edid_check_sum(edid); + if (sum != 0) { + dev_err(dp->dev, "EDID bad checksum!\n"); + return -EIO; + } + + /* Read additional EDID data */ + retval = analogix_dp_read_bytes_from_i2c(dp, + I2C_EDID_DEVICE_ADDR, + EDID_BLOCK_LENGTH, + EDID_BLOCK_LENGTH, + &edid[EDID_BLOCK_LENGTH]); + if (retval != 0) { + dev_err(dp->dev, "EDID Read failed!\n"); + return -EIO; + } + sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); + if (sum != 0) { + dev_err(dp->dev, "EDID bad checksum!\n"); + return -EIO; + } + + analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, + &test_vector); + if (test_vector & DP_TEST_LINK_EDID_READ) { + analogix_dp_write_byte_to_dpcd(dp, + DP_TEST_EDID_CHECKSUM, + edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); + analogix_dp_write_byte_to_dpcd(dp, + DP_TEST_RESPONSE, + DP_TEST_EDID_CHECKSUM_WRITE); + } + } else { + dev_info(dp->dev, "EDID data does not include any extensions.\n"); + + /* Read EDID data */ + retval = analogix_dp_read_bytes_from_i2c(dp, + I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, + EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); + if (retval != 0) { + dev_err(dp->dev, "EDID Read failed!\n"); + return -EIO; + } + sum = analogix_dp_calc_edid_check_sum(edid); + if (sum != 0) { + dev_err(dp->dev, "EDID bad checksum!\n"); + return -EIO; + } + + analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, + &test_vector); + if (test_vector & DP_TEST_LINK_EDID_READ) { + analogix_dp_write_byte_to_dpcd(dp, + DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); + analogix_dp_write_byte_to_dpcd(dp, + DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); + } + } + + dev_dbg(dp->dev, "EDID Read success!\n"); + return 0; +} + +static int analogix_dp_handle_edid(struct analogix_dp_device *dp) +{ + u8 buf[12]; + int i; + int retval; + + /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ + retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); + if (retval) + return retval; + + /* Read EDID */ + for (i = 0; i < 3; i++) { + retval = analogix_dp_read_edid(dp); + if (!retval) + break; + } + + return retval; +} + +static void +analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, + bool enable) +{ + u8 data; + + analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); + + if (enable) + analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, + DP_LANE_COUNT_ENHANCED_FRAME_EN | + DPCD_LANE_COUNT_SET(data)); + else + analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, + DPCD_LANE_COUNT_SET(data)); +} + +static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) +{ + u8 data; + int retval; + + analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); + retval = DPCD_ENHANCED_FRAME_CAP(data); + + return retval; +} + +static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) +{ + u8 data; + + data = analogix_dp_is_enhanced_mode_available(dp); + analogix_dp_enable_rx_to_enhanced_mode(dp, data); + analogix_dp_enable_enhanced_mode(dp, data); +} + +static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) +{ + analogix_dp_set_training_pattern(dp, DP_NONE); + + analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, + DP_TRAINING_PATTERN_DISABLE); +} + +static void +analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp, + int pre_emphasis, int lane) +{ + switch (lane) { + case 0: + analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis); + break; + case 1: + analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis); + break; + + case 2: + analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis); + break; + + case 3: + analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis); + break; + } +} + +static int analogix_dp_link_start(struct analogix_dp_device *dp) +{ + u8 buf[4]; + int lane, lane_count, pll_tries, retval; + + lane_count = dp->link_train.lane_count; + + dp->link_train.lt_state = CLOCK_RECOVERY; + dp->link_train.eq_loop = 0; + + for (lane = 0; lane < lane_count; lane++) + dp->link_train.cr_loop[lane] = 0; + + /* Set link rate and count as you want to establish*/ + analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); + analogix_dp_set_lane_count(dp, dp->link_train.lane_count); + + /* Setup RX configuration */ + buf[0] = dp->link_train.link_rate; + buf[1] = dp->link_train.lane_count; + retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); + if (retval) + return retval; + + /* Set TX pre-emphasis to minimum */ + for (lane = 0; lane < lane_count; lane++) + analogix_dp_set_lane_lane_pre_emphasis(dp, + PRE_EMPHASIS_LEVEL_0, lane); + + /* Wait for PLL lock */ + pll_tries = 0; + while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { + dev_err(dp->dev, "Wait for PLL lock timed out\n"); + return -ETIMEDOUT; + } + + pll_tries++; + usleep_range(90, 120); + } + + /* Set training pattern 1 */ + analogix_dp_set_training_pattern(dp, TRAINING_PTN1); + + /* Set RX training pattern */ + retval = analogix_dp_write_byte_to_dpcd(dp, + DP_TRAINING_PATTERN_SET, + DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); + if (retval) + return retval; + + for (lane = 0; lane < lane_count; lane++) + buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | + DP_TRAIN_VOLTAGE_SWING_LEVEL_0; + + retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, + lane_count, buf); + + return retval; +} + +static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) +{ + int shift = (lane & 1) * 4; + u8 link_value = link_status[lane >> 1]; + + return (link_value >> shift) & 0xf; +} + +static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) +{ + int lane; + u8 lane_status; + + for (lane = 0; lane < lane_count; lane++) { + lane_status = analogix_dp_get_lane_status(link_status, lane); + if ((lane_status & DP_LANE_CR_DONE) == 0) + return -EINVAL; + } + return 0; +} + +static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, + int lane_count) +{ + int lane; + u8 lane_status; + + if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) + return -EINVAL; + + for (lane = 0; lane < lane_count; lane++) { + lane_status = analogix_dp_get_lane_status(link_status, lane); + lane_status &= DP_CHANNEL_EQ_BITS; + if (lane_status != DP_CHANNEL_EQ_BITS) + return -EINVAL; + } + + return 0; +} + +static unsigned char +analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) +{ + int shift = (lane & 1) * 4; + u8 link_value = adjust_request[lane >> 1]; + + return (link_value >> shift) & 0x3; +} + +static unsigned char analogix_dp_get_adjust_request_pre_emphasis( + u8 adjust_request[2], + int lane) +{ + int shift = (lane & 1) * 4; + u8 link_value = adjust_request[lane >> 1]; + + return ((link_value >> shift) & 0xc) >> 2; +} + +static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp, + u8 training_lane_set, int lane) +{ + switch (lane) { + case 0: + analogix_dp_set_lane0_link_training(dp, training_lane_set); + break; + case 1: + analogix_dp_set_lane1_link_training(dp, training_lane_set); + break; + + case 2: + analogix_dp_set_lane2_link_training(dp, training_lane_set); + break; + + case 3: + analogix_dp_set_lane3_link_training(dp, training_lane_set); + break; + } +} + +static unsigned int +analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, + int lane) +{ + u32 reg; + + switch (lane) { + case 0: + reg = analogix_dp_get_lane0_link_training(dp); + break; + case 1: + reg = analogix_dp_get_lane1_link_training(dp); + break; + case 2: + reg = analogix_dp_get_lane2_link_training(dp); + break; + case 3: + reg = analogix_dp_get_lane3_link_training(dp); + break; + default: + WARN_ON(1); + return 0; + } + + return reg; +} + +static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) +{ + analogix_dp_training_pattern_dis(dp); + analogix_dp_set_enhanced_mode(dp); + + dp->link_train.lt_state = FAILED; +} + +static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, + u8 adjust_request[2]) +{ + int lane, lane_count; + u8 voltage_swing, pre_emphasis, training_lane; + + lane_count = dp->link_train.lane_count; + for (lane = 0; lane < lane_count; lane++) { + voltage_swing = analogix_dp_get_adjust_request_voltage( + adjust_request, lane); + pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( + adjust_request, lane); + training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | + DPCD_PRE_EMPHASIS_SET(pre_emphasis); + + if (voltage_swing == VOLTAGE_LEVEL_3) + training_lane |= DP_TRAIN_MAX_SWING_REACHED; + if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) + training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; + + dp->link_train.training_lane[lane] = training_lane; + } +} + +static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) +{ + int lane, lane_count, retval; + u8 voltage_swing, pre_emphasis, training_lane; + u8 link_status[2], adjust_request[2]; + + usleep_range(100, 101); + + lane_count = dp->link_train.lane_count; + + retval = analogix_dp_read_bytes_from_dpcd(dp, + DP_LANE0_1_STATUS, 2, link_status); + if (retval) + return retval; + + retval = analogix_dp_read_bytes_from_dpcd(dp, + DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); + if (retval) + return retval; + + if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { + /* set training pattern 2 for EQ */ + analogix_dp_set_training_pattern(dp, TRAINING_PTN2); + + retval = analogix_dp_write_byte_to_dpcd(dp, + DP_TRAINING_PATTERN_SET, + DP_LINK_SCRAMBLING_DISABLE | + DP_TRAINING_PATTERN_2); + if (retval) + return retval; + + dev_info(dp->dev, "Link Training Clock Recovery success\n"); + dp->link_train.lt_state = EQUALIZER_TRAINING; + } else { + for (lane = 0; lane < lane_count; lane++) { + training_lane = analogix_dp_get_lane_link_training( + dp, lane); + voltage_swing = analogix_dp_get_adjust_request_voltage( + adjust_request, lane); + pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( + adjust_request, lane); + + if (DPCD_VOLTAGE_SWING_GET(training_lane) == + voltage_swing && + DPCD_PRE_EMPHASIS_GET(training_lane) == + pre_emphasis) + dp->link_train.cr_loop[lane]++; + + if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || + voltage_swing == VOLTAGE_LEVEL_3 || + pre_emphasis == PRE_EMPHASIS_LEVEL_3) { + dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", + dp->link_train.cr_loop[lane], + voltage_swing, pre_emphasis); + analogix_dp_reduce_link_rate(dp); + return -EIO; + } + } + } + + analogix_dp_get_adjust_training_lane(dp, adjust_request); + + for (lane = 0; lane < lane_count; lane++) + analogix_dp_set_lane_link_training(dp, + dp->link_train.training_lane[lane], lane); + + retval = analogix_dp_write_bytes_to_dpcd(dp, + DP_TRAINING_LANE0_SET, lane_count, + dp->link_train.training_lane); + if (retval) + return retval; + + return retval; +} + +static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) +{ + int lane, lane_count, retval; + u32 reg; + u8 link_align, link_status[2], adjust_request[2]; + + usleep_range(400, 401); + + lane_count = dp->link_train.lane_count; + + retval = analogix_dp_read_bytes_from_dpcd(dp, + DP_LANE0_1_STATUS, 2, link_status); + if (retval) + return retval; + + if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { + analogix_dp_reduce_link_rate(dp); + return -EIO; + } + + retval = analogix_dp_read_bytes_from_dpcd(dp, + DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); + if (retval) + return retval; + + retval = analogix_dp_read_byte_from_dpcd(dp, + DP_LANE_ALIGN_STATUS_UPDATED, &link_align); + if (retval) + return retval; + + analogix_dp_get_adjust_training_lane(dp, adjust_request); + + if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { + /* traing pattern Set to Normal */ + analogix_dp_training_pattern_dis(dp); + + dev_info(dp->dev, "Link Training success!\n"); + + analogix_dp_get_link_bandwidth(dp, ®); + dp->link_train.link_rate = reg; + dev_dbg(dp->dev, "final bandwidth = %.2x\n", + dp->link_train.link_rate); + + analogix_dp_get_lane_count(dp, ®); + dp->link_train.lane_count = reg; + dev_dbg(dp->dev, "final lane count = %.2x\n", + dp->link_train.lane_count); + + /* set enhanced mode if available */ + analogix_dp_set_enhanced_mode(dp); + dp->link_train.lt_state = FINISHED; + + return 0; + } + + /* not all locked */ + dp->link_train.eq_loop++; + + if (dp->link_train.eq_loop > MAX_EQ_LOOP) { + dev_err(dp->dev, "EQ Max loop\n"); + analogix_dp_reduce_link_rate(dp); + return -EIO; + } + + for (lane = 0; lane < lane_count; lane++) + analogix_dp_set_lane_link_training(dp, + dp->link_train.training_lane[lane], lane); + + retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, + lane_count, dp->link_train.training_lane); + + return retval; +} + +static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, + u8 *bandwidth) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps + */ + analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); + *bandwidth = data; +} + +static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, + u8 *lane_count) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum number of Main Link lanes + * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes + */ + analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); + *lane_count = DPCD_MAX_LANE_COUNT(data); +} + +static void analogix_dp_init_training(struct analogix_dp_device *dp, + enum link_lane_count_type max_lane, + int max_rate) +{ + /* + * MACRO_RST must be applied after the PLL_LOCK to avoid + * the DP inter pair skew issue for at least 10 us + */ + analogix_dp_reset_macro(dp); + + /* Initialize by reading RX's DPCD */ + analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); + analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + + if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && + (dp->link_train.link_rate != DP_LINK_BW_2_7) && + (dp->link_train.link_rate != DP_LINK_BW_5_4)) { + dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", + dp->link_train.link_rate); + dp->link_train.link_rate = DP_LINK_BW_1_62; + } + + if (dp->link_train.lane_count == 0) { + dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", + dp->link_train.lane_count); + dp->link_train.lane_count = (u8)LANE_COUNT1; + } + + /* Setup TX lane count & rate */ + if (dp->link_train.lane_count > max_lane) + dp->link_train.lane_count = max_lane; + if (dp->link_train.link_rate > max_rate) + dp->link_train.link_rate = max_rate; + + /* All DP analog module power up */ + analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); +} + +static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) +{ + int retval = 0, training_finished = 0; + + dp->link_train.lt_state = START; + + /* Process here */ + while (!retval && !training_finished) { + switch (dp->link_train.lt_state) { + case START: + retval = analogix_dp_link_start(dp); + if (retval) + dev_err(dp->dev, "LT link start failed!\n"); + break; + case CLOCK_RECOVERY: + retval = analogix_dp_process_clock_recovery(dp); + if (retval) + dev_err(dp->dev, "LT CR failed!\n"); + break; + case EQUALIZER_TRAINING: + retval = analogix_dp_process_equalizer_training(dp); + if (retval) + dev_err(dp->dev, "LT EQ failed!\n"); + break; + case FINISHED: + training_finished = 1; + break; + case FAILED: + return -EREMOTEIO; + } + } + if (retval) + dev_err(dp->dev, "eDP link training failed (%d)\n", retval); + + return retval; +} + +static int analogix_dp_set_link_train(struct analogix_dp_device *dp, + u32 count, u32 bwtype) +{ + int i; + int retval; + + for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { + analogix_dp_init_training(dp, count, bwtype); + retval = analogix_dp_sw_link_training(dp); + if (retval == 0) + break; + + usleep_range(100, 110); + } + + return retval; +} + +static int analogix_dp_config_video(struct analogix_dp_device *dp) +{ + int retval = 0; + int timeout_loop = 0; + int done_count = 0; + + analogix_dp_config_video_slave_mode(dp); + + analogix_dp_set_video_color_format(dp); + + if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + dev_err(dp->dev, "PLL is not locked yet.\n"); + return -EINVAL; + } + + for (;;) { + timeout_loop++; + if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) + break; + if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { + dev_err(dp->dev, "Timeout of video streamclk ok\n"); + return -ETIMEDOUT; + } + + usleep_range(1, 2); + } + + /* Set to use the register calculated M/N video */ + analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); + + /* For video bist, Video timing must be generated by register */ + analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); + + /* Disable video mute */ + analogix_dp_enable_video_mute(dp, 0); + + /* Configure video slave mode */ + analogix_dp_enable_video_master(dp, 0); + + timeout_loop = 0; + + for (;;) { + timeout_loop++; + if (analogix_dp_is_video_stream_on(dp) == 0) { + done_count++; + if (done_count > 10) + break; + } else if (done_count) { + done_count = 0; + } + if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { + dev_err(dp->dev, "Timeout of video streamclk ok\n"); + return -ETIMEDOUT; + } + + usleep_range(1000, 1001); + } + + if (retval != 0) + dev_err(dp->dev, "Video stream is not detected!\n"); + + return retval; +} + +static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, + bool enable) +{ + u8 data; + + if (enable) { + analogix_dp_enable_scrambling(dp); + + analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, + &data); + analogix_dp_write_byte_to_dpcd(dp, + DP_TRAINING_PATTERN_SET, + (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); + } else { + analogix_dp_disable_scrambling(dp); + + analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, + &data); + analogix_dp_write_byte_to_dpcd(dp, + DP_TRAINING_PATTERN_SET, + (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); + } +} + +static irqreturn_t analogix_dp_hardirq(int irq, void *arg) +{ + struct analogix_dp_device *dp = arg; + irqreturn_t ret = IRQ_NONE; + enum dp_irq_type irq_type; + + irq_type = analogix_dp_get_irq_type(dp); + if (irq_type != DP_IRQ_TYPE_UNKNOWN) { + analogix_dp_mute_hpd_interrupt(dp); + ret = IRQ_WAKE_THREAD; + } + + return ret; +} + +static irqreturn_t analogix_dp_irq_thread(int irq, void *arg) +{ + struct analogix_dp_device *dp = arg; + enum dp_irq_type irq_type; + + irq_type = analogix_dp_get_irq_type(dp); + if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN || + irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) { + dev_dbg(dp->dev, "Detected cable status changed!\n"); + if (dp->drm_dev) + drm_helper_hpd_irq_event(dp->drm_dev); + } + + if (irq_type != DP_IRQ_TYPE_UNKNOWN) { + analogix_dp_clear_hotplug_interrupts(dp); + analogix_dp_unmute_hpd_interrupt(dp); + } + + return IRQ_HANDLED; +} + +static void analogix_dp_commit(struct analogix_dp_device *dp) +{ + int ret; + + /* Keep the panel disabled while we configure video */ + if (dp->plat_data->panel) { + if (drm_panel_disable(dp->plat_data->panel)) + DRM_ERROR("failed to disable the panel\n"); + } + + ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, + dp->video_info.max_link_rate); + if (ret) { + dev_err(dp->dev, "unable to do link train\n"); + return; + } + + analogix_dp_enable_scramble(dp, 1); + analogix_dp_enable_rx_to_enhanced_mode(dp, 1); + analogix_dp_enable_enhanced_mode(dp, 1); + + analogix_dp_init_video(dp); + ret = analogix_dp_config_video(dp); + if (ret) + dev_err(dp->dev, "unable to config video\n"); + + /* Safe to enable the panel now */ + if (dp->plat_data->panel) { + if (drm_panel_enable(dp->plat_data->panel)) + DRM_ERROR("failed to enable the panel\n"); + } + + /* Enable video */ + analogix_dp_start_video(dp); +} + +int analogix_dp_get_modes(struct drm_connector *connector) +{ + struct analogix_dp_device *dp = to_dp(connector); + struct edid *edid = (struct edid *)dp->edid; + int num_modes = 0; + + if (analogix_dp_handle_edid(dp) == 0) { + drm_mode_connector_update_edid_property(&dp->connector, edid); + num_modes += drm_add_edid_modes(&dp->connector, edid); + } + + if (dp->plat_data->panel) + num_modes += drm_panel_get_modes(dp->plat_data->panel); + + if (dp->plat_data->get_modes) + num_modes += dp->plat_data->get_modes(dp->plat_data); + + return num_modes; +} + +static struct drm_encoder * +analogix_dp_best_encoder(struct drm_connector *connector) +{ + struct analogix_dp_device *dp = to_dp(connector); + + return dp->encoder; +} + +static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = { + .get_modes = analogix_dp_get_modes, + .best_encoder = analogix_dp_best_encoder, +}; + +enum drm_connector_status +analogix_dp_detect(struct drm_connector *connector, bool force) +{ + struct analogix_dp_device *dp = to_dp(connector); + + if (analogix_dp_detect_hpd(dp)) + return connector_status_disconnected; + + return connector_status_connected; +} + +static void analogix_dp_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); + +} + +static const struct drm_connector_funcs analogix_dp_connector_funcs = { + .dpms = drm_atomic_helper_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = analogix_dp_detect, + .destroy = analogix_dp_connector_destroy, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int analogix_dp_bridge_attach(struct drm_bridge *bridge) +{ + struct analogix_dp_device *dp = bridge->driver_private; + struct drm_encoder *encoder = dp->encoder; + struct drm_connector *connector = &dp->connector; + int ret; + + if (!bridge->encoder) { + DRM_ERROR("Parent encoder object not found"); + return -ENODEV; + } + + connector->polled = DRM_CONNECTOR_POLL_HPD; + + ret = drm_connector_init(dp->drm_dev, connector, + &analogix_dp_connector_funcs, + DRM_MODE_CONNECTOR_eDP); + if (ret) { + DRM_ERROR("Failed to initialize connector with drm\n"); + return ret; + } + + drm_connector_helper_add(connector, + &analogix_dp_connector_helper_funcs); + drm_mode_connector_attach_encoder(connector, encoder); + + /* + * NOTE: the connector registration is implemented in analogix + * platform driver, that to say connector would be exist after + * plat_data->attch return, that's why we record the connector + * point after plat attached. + */ + if (dp->plat_data->attach) { + ret = dp->plat_data->attach(dp->plat_data, bridge, connector); + if (ret) { + DRM_ERROR("Failed at platform attch func\n"); + return ret; + } + } + + if (dp->plat_data->panel) { + ret = drm_panel_attach(dp->plat_data->panel, &dp->connector); + if (ret) { + DRM_ERROR("Failed to attach panel\n"); + return ret; + } + } + + return 0; +} + +static void analogix_dp_bridge_enable(struct drm_bridge *bridge) +{ + struct analogix_dp_device *dp = bridge->driver_private; + + if (dp->dpms_mode == DRM_MODE_DPMS_ON) + return; + + pm_runtime_get_sync(dp->dev); + + if (dp->plat_data->power_on) + dp->plat_data->power_on(dp->plat_data); + + phy_power_on(dp->phy); + analogix_dp_init_dp(dp); + enable_irq(dp->irq); + analogix_dp_commit(dp); + + dp->dpms_mode = DRM_MODE_DPMS_ON; +} + +static void analogix_dp_bridge_disable(struct drm_bridge *bridge) +{ + struct analogix_dp_device *dp = bridge->driver_private; + + if (dp->dpms_mode != DRM_MODE_DPMS_ON) + return; + + if (dp->plat_data->panel) { + if (drm_panel_disable(dp->plat_data->panel)) { + DRM_ERROR("failed to disable the panel\n"); + return; + } + } + + disable_irq(dp->irq); + phy_power_off(dp->phy); + + if (dp->plat_data->power_off) + dp->plat_data->power_off(dp->plat_data); + + pm_runtime_put_sync(dp->dev); + + dp->dpms_mode = DRM_MODE_DPMS_OFF; +} + +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) +{ + struct analogix_dp_device *dp = bridge->driver_private; + struct drm_display_info *display_info = &dp->connector.display_info; + struct video_info *video = &dp->video_info; + struct device_node *dp_node = dp->dev->of_node; + int vic; + + /* Input video interlaces & hsync pol & vsync pol */ + video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); + video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + /* Input video dynamic_range & colorimetry */ + vic = drm_match_cea_mode(mode); + if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || + (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) { + video->dynamic_range = CEA; + video->ycbcr_coeff = COLOR_YCBCR601; + } else if (vic) { + video->dynamic_range = CEA; + video->ycbcr_coeff = COLOR_YCBCR709; + } else { + video->dynamic_range = VESA; + video->ycbcr_coeff = COLOR_YCBCR709; + } + + /* Input vide bpc and color_formats */ + switch (display_info->bpc) { + case 12: + video->color_depth = COLOR_12; + break; + case 10: + video->color_depth = COLOR_10; + break; + case 8: + video->color_depth = COLOR_8; + break; + case 6: + video->color_depth = COLOR_6; + break; + default: + video->color_depth = COLOR_8; + break; + } + if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444) + video->color_space = COLOR_YCBCR444; + else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422) + video->color_space = COLOR_YCBCR422; + else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444) + video->color_space = COLOR_RGB; + else + video->color_space = COLOR_RGB; + + /* + * NOTE: those property parsing code is used for providing backward + * compatibility for samsung platform. + * Due to we used the "of_property_read_u32" interfaces, when this + * property isn't present, the "video_info" can keep the original + * values and wouldn't be modified. + */ + of_property_read_u32(dp_node, "samsung,color-space", + &video->color_space); + of_property_read_u32(dp_node, "samsung,dynamic-range", + &video->dynamic_range); + of_property_read_u32(dp_node, "samsung,ycbcr-coeff", + &video->ycbcr_coeff); + of_property_read_u32(dp_node, "samsung,color-depth", + &video->color_depth); + if (of_property_read_bool(dp_node, "hsync-active-high")) + video->h_sync_polarity = true; + if (of_property_read_bool(dp_node, "vsync-active-high")) + video->v_sync_polarity = true; + if (of_property_read_bool(dp_node, "interlaced")) + video->interlaced = true; +} + +static void analogix_dp_bridge_nop(struct drm_bridge *bridge) +{ + /* do nothing */ +} + +static const struct drm_bridge_funcs analogix_dp_bridge_funcs = { + .enable = analogix_dp_bridge_enable, + .disable = analogix_dp_bridge_disable, + .pre_enable = analogix_dp_bridge_nop, + .post_disable = analogix_dp_bridge_nop, + .mode_set = analogix_dp_bridge_mode_set, + .attach = analogix_dp_bridge_attach, +}; + +static int analogix_dp_create_bridge(struct drm_device *drm_dev, + struct analogix_dp_device *dp) +{ + struct drm_bridge *bridge; + int ret; + + bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL); + if (!bridge) { + DRM_ERROR("failed to allocate for drm bridge\n"); + return -ENOMEM; + } + + dp->bridge = bridge; + + dp->encoder->bridge = bridge; + bridge->driver_private = dp; + bridge->encoder = dp->encoder; + bridge->funcs = &analogix_dp_bridge_funcs; + + ret = drm_bridge_attach(drm_dev, bridge); + if (ret) { + DRM_ERROR("failed to attach drm bridge\n"); + return -EINVAL; + } + + return 0; +} + +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) +{ + struct device_node *dp_node = dp->dev->of_node; + struct video_info *video_info = &dp->video_info; + + switch (dp->plat_data->dev_type) { + case RK3288_DP: + /* + * Like Rk3288 DisplayPort TRM indicate that "Main link + * containing 4 physical lanes of 2.7/1.62 Gbps/lane". + */ + video_info->max_link_rate = 0x0A; + video_info->max_lane_count = 0x04; + break; + case EXYNOS_DP: + /* + * NOTE: those property parseing code is used for + * providing backward compatibility for samsung platform. + */ + of_property_read_u32(dp_node, "samsung,link-rate", + &video_info->max_link_rate); + of_property_read_u32(dp_node, "samsung,lane-count", + &video_info->max_lane_count); + break; + } + + return 0; +} + +int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, + struct analogix_dp_plat_data *plat_data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct analogix_dp_device *dp; + struct resource *res; + unsigned int irq_flags; + int ret; + + if (!plat_data) { + dev_err(dev, "Invalided input plat_data\n"); + return -EINVAL; + } + + dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL); + if (!dp) + return -ENOMEM; + + dev_set_drvdata(dev, dp); + + dp->dev = &pdev->dev; + dp->dpms_mode = DRM_MODE_DPMS_OFF; + + /* + * platform dp driver need containor_of the plat_data to get + * the driver private data, so we need to store the point of + * plat_data, not the context of plat_data. + */ + dp->plat_data = plat_data; + + ret = analogix_dp_dt_parse_pdata(dp); + if (ret) + return ret; + + dp->phy = devm_phy_get(dp->dev, "dp"); + if (IS_ERR(dp->phy)) { + dev_err(dp->dev, "no DP phy configured\n"); + ret = PTR_ERR(dp->phy); + if (ret) { + /* + * phy itself is not enabled, so we can move forward + * assigning NULL to phy pointer. + */ + if (ret == -ENOSYS || ret == -ENODEV) + dp->phy = NULL; + else + return ret; + } + } + + dp->clock = devm_clk_get(&pdev->dev, "dp"); + if (IS_ERR(dp->clock)) { + dev_err(&pdev->dev, "failed to get clock\n"); + return PTR_ERR(dp->clock); + } + + clk_prepare_enable(dp->clock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + dp->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dp->reg_base)) + return PTR_ERR(dp->reg_base); + + dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd"); + + dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0); + if (!gpio_is_valid(dp->hpd_gpio)) + dp->hpd_gpio = of_get_named_gpio(dev->of_node, + "samsung,hpd-gpio", 0); + + if (gpio_is_valid(dp->hpd_gpio)) { + /* + * Set up the hotplug GPIO from the device tree as an interrupt. + * Simply specifying a different interrupt in the device tree + * doesn't work since we handle hotplug rather differently when + * using a GPIO. We also need the actual GPIO specifier so + * that we can get the current state of the GPIO. + */ + ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN, + "hpd_gpio"); + if (ret) { + dev_err(&pdev->dev, "failed to get hpd gpio\n"); + return ret; + } + dp->irq = gpio_to_irq(dp->hpd_gpio); + irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; + } else { + dp->hpd_gpio = -ENODEV; + dp->irq = platform_get_irq(pdev, 0); + irq_flags = 0; + } + + if (dp->irq == -ENXIO) { + dev_err(&pdev->dev, "failed to get irq\n"); + return -ENODEV; + } + + pm_runtime_enable(dev); + + phy_power_on(dp->phy); + + if (dp->plat_data->panel) { + if (drm_panel_prepare(dp->plat_data->panel)) { + DRM_ERROR("failed to setup the panel\n"); + return -EBUSY; + } + } + + analogix_dp_init_dp(dp); + + ret = devm_request_threaded_irq(&pdev->dev, dp->irq, + analogix_dp_hardirq, + analogix_dp_irq_thread, + irq_flags, "analogix-dp", dp); + if (ret) { + dev_err(&pdev->dev, "failed to request irq\n"); + goto err_disable_pm_runtime; + } + disable_irq(dp->irq); + + dp->drm_dev = drm_dev; + dp->encoder = dp->plat_data->encoder; + + ret = analogix_dp_create_bridge(drm_dev, dp); + if (ret) { + DRM_ERROR("failed to create bridge (%d)\n", ret); + drm_encoder_cleanup(dp->encoder); + goto err_disable_pm_runtime; + } + + return 0; + +err_disable_pm_runtime: + pm_runtime_disable(dev); + + return ret; +} +EXPORT_SYMBOL_GPL(analogix_dp_bind); + +void analogix_dp_unbind(struct device *dev, struct device *master, + void *data) +{ + struct analogix_dp_device *dp = dev_get_drvdata(dev); + + analogix_dp_bridge_disable(dp->bridge); + + if (dp->plat_data->panel) { + if (drm_panel_unprepare(dp->plat_data->panel)) + DRM_ERROR("failed to turnoff the panel\n"); + } + + pm_runtime_disable(dev); +} +EXPORT_SYMBOL_GPL(analogix_dp_unbind); + +#ifdef CONFIG_PM +int analogix_dp_suspend(struct device *dev) +{ + struct analogix_dp_device *dp = dev_get_drvdata(dev); + + clk_disable_unprepare(dp->clock); + + if (dp->plat_data->panel) { + if (drm_panel_unprepare(dp->plat_data->panel)) + DRM_ERROR("failed to turnoff the panel\n"); + } + + return 0; +} +EXPORT_SYMBOL_GPL(analogix_dp_suspend); + +int analogix_dp_resume(struct device *dev) +{ + struct analogix_dp_device *dp = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(dp->clock); + if (ret < 0) { + DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret); + return ret; + } + + if (dp->plat_data->panel) { + if (drm_panel_prepare(dp->plat_data->panel)) { + DRM_ERROR("failed to setup the panel\n"); + return -EBUSY; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(analogix_dp_resume); +#endif + +MODULE_AUTHOR("Jingoo Han "); +MODULE_DESCRIPTION("Analogix DP Core Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h new file mode 100644 index 000000000000..f09275d40f70 --- /dev/null +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -0,0 +1,281 @@ +/* + * Header file for Analogix DP (Display Port) core interface driver. + * + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _ANALOGIX_DP_CORE_H +#define _ANALOGIX_DP_CORE_H + +#include +#include + +#define DP_TIMEOUT_LOOP_COUNT 100 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 5 + +/* I2C EDID Chip ID, Slave Address */ +#define I2C_EDID_DEVICE_ADDR 0x50 +#define I2C_E_EDID_DEVICE_ADDR 0x30 + +#define EDID_BLOCK_LENGTH 0x80 +#define EDID_HEADER_PATTERN 0x00 +#define EDID_EXTENSION_FLAG 0x7e +#define EDID_CHECKSUM 0x7f + +/* DP_MAX_LANE_COUNT */ +#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) +#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) + +/* DP_LANE_COUNT_SET */ +#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) + +/* DP_TRAINING_LANE0_SET */ +#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) +#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) +#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) +#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) + +enum link_lane_count_type { + LANE_COUNT1 = 1, + LANE_COUNT2 = 2, + LANE_COUNT4 = 4 +}; + +enum link_training_state { + START, + CLOCK_RECOVERY, + EQUALIZER_TRAINING, + FINISHED, + FAILED +}; + +enum voltage_swing_level { + VOLTAGE_LEVEL_0, + VOLTAGE_LEVEL_1, + VOLTAGE_LEVEL_2, + VOLTAGE_LEVEL_3, +}; + +enum pre_emphasis_level { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +enum pattern_set { + PRBS7, + D10_2, + TRAINING_PTN1, + TRAINING_PTN2, + DP_NONE +}; + +enum color_space { + COLOR_RGB, + COLOR_YCBCR422, + COLOR_YCBCR444 +}; + +enum color_depth { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +enum color_coefficient { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +enum dynamic_range { + VESA, + CEA +}; + +enum pll_status { + PLL_UNLOCKED, + PLL_LOCKED +}; + +enum clock_recovery_m_value_type { + CALCULATED_M, + REGISTER_M +}; + +enum video_timing_recognition_type { + VIDEO_TIMING_FROM_CAPTURE, + VIDEO_TIMING_FROM_REGISTER +}; + +enum analog_power_block { + AUX_BLOCK, + CH0_BLOCK, + CH1_BLOCK, + CH2_BLOCK, + CH3_BLOCK, + ANALOG_TOTAL, + POWER_ALL +}; + +enum dp_irq_type { + DP_IRQ_TYPE_HP_CABLE_IN, + DP_IRQ_TYPE_HP_CABLE_OUT, + DP_IRQ_TYPE_HP_CHANGE, + DP_IRQ_TYPE_UNKNOWN, +}; + +struct video_info { + char *name; + + bool h_sync_polarity; + bool v_sync_polarity; + bool interlaced; + + enum color_space color_space; + enum dynamic_range dynamic_range; + enum color_coefficient ycbcr_coeff; + enum color_depth color_depth; + + int max_link_rate; + enum link_lane_count_type max_lane_count; +}; + +struct link_train { + int eq_loop; + int cr_loop[4]; + + u8 link_rate; + u8 lane_count; + u8 training_lane[4]; + + enum link_training_state lt_state; +}; + +struct analogix_dp_device { + struct drm_encoder *encoder; + struct device *dev; + struct drm_device *drm_dev; + struct drm_connector connector; + struct drm_bridge *bridge; + struct clk *clock; + unsigned int irq; + void __iomem *reg_base; + + struct video_info video_info; + struct link_train link_train; + struct phy *phy; + int dpms_mode; + int hpd_gpio; + bool force_hpd; + unsigned char edid[EDID_BLOCK_LENGTH * 2]; + + struct analogix_dp_plat_data *plat_data; +}; + +/* analogix_dp_reg.c */ +void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); +void analogix_dp_stop_video(struct analogix_dp_device *dp); +void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); +void analogix_dp_init_analog_param(struct analogix_dp_device *dp); +void analogix_dp_init_interrupt(struct analogix_dp_device *dp); +void analogix_dp_reset(struct analogix_dp_device *dp); +void analogix_dp_swreset(struct analogix_dp_device *dp); +void analogix_dp_config_interrupt(struct analogix_dp_device *dp); +void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); +void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); +enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); +void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); +void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, + enum analog_power_block block, + bool enable); +void analogix_dp_init_analog_func(struct analogix_dp_device *dp); +void analogix_dp_init_hpd(struct analogix_dp_device *dp); +void analogix_dp_force_hpd(struct analogix_dp_device *dp); +enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); +void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); +void analogix_dp_reset_aux(struct analogix_dp_device *dp); +void analogix_dp_init_aux(struct analogix_dp_device *dp); +int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); +void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); +int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); +int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, + unsigned int reg_addr, + unsigned char data); +int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, + unsigned int reg_addr, + unsigned char *data); +int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, + unsigned int reg_addr, + unsigned int count, + unsigned char data[]); +int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, + unsigned int reg_addr, + unsigned int count, + unsigned char data[]); +int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, + unsigned int device_addr, + unsigned int reg_addr); +int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, + unsigned int device_addr, + unsigned int reg_addr, + unsigned int *data); +int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, + unsigned int device_addr, + unsigned int reg_addr, + unsigned int count, + unsigned char edid[]); +void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); +void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); +void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); +void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); +void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, + bool enable); +void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, + enum pattern_set pattern); +void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, + u32 level); +void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, + u32 level); +void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, + u32 level); +void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, + u32 level); +void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, + u32 training_lane); +void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, + u32 training_lane); +void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, + u32 training_lane); +void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, + u32 training_lane); +u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp); +u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp); +u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp); +u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp); +void analogix_dp_reset_macro(struct analogix_dp_device *dp); +void analogix_dp_init_video(struct analogix_dp_device *dp); + +void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); +int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); +void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, + enum clock_recovery_m_value_type type, + u32 m_value, + u32 n_value); +void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); +void analogix_dp_enable_video_master(struct analogix_dp_device *dp, + bool enable); +void analogix_dp_start_video(struct analogix_dp_device *dp); +int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); +void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); +void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); +void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); +#endif /* _ANALOGIX_DP_CORE_H */ diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c new file mode 100644 index 000000000000..49205ef02be3 --- /dev/null +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -0,0 +1,1320 @@ +/* + * Analogix DP (Display port) core register interface driver. + * + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include + +#include + +#include "analogix_dp_core.h" +#include "analogix_dp_reg.h" + +#define COMMON_INT_MASK_1 0 +#define COMMON_INT_MASK_2 0 +#define COMMON_INT_MASK_3 0 +#define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) +#define INT_STA_MASK INT_HPD + +void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) +{ + u32 reg; + + if (enable) { + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + reg |= HDCP_VIDEO_MUTE; + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + } else { + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + reg &= ~HDCP_VIDEO_MUTE; + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + } +} + +void analogix_dp_stop_video(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + reg &= ~VIDEO_EN; + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); +} + +void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) +{ + u32 reg; + + if (enable) + reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | + LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; + else + reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | + LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; + + writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); +} + +void analogix_dp_init_analog_param(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = TX_TERMINAL_CTRL_50_OHM; + writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); + + reg = SEL_24M | TX_DVDD_BIT_1_0625V; + writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); + + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) { + writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1); + writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); + writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); + writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); + writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); + } + + reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; + writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); + + reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | + TX_CUR1_2X | TX_CUR_16_MA; + writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); + + reg = CH3_AMP_400_MV | CH2_AMP_400_MV | + CH1_AMP_400_MV | CH0_AMP_400_MV; + writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); +} + +void analogix_dp_init_interrupt(struct analogix_dp_device *dp) +{ + /* Set interrupt pin assertion polarity as high */ + writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL); + + /* Clear pending regisers */ + writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); + writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2); + writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3); + writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); + writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA); + + /* 0:mask,1: unmask */ + writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); + writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); + writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); + writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); +} + +void analogix_dp_reset(struct analogix_dp_device *dp) +{ + u32 reg; + + analogix_dp_stop_video(dp); + analogix_dp_enable_video_mute(dp, 0); + + reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | + AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | + HDCP_FUNC_EN_N | SW_FUNC_EN_N; + writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + + reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | + SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N; + writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + + usleep_range(20, 30); + + analogix_dp_lane_swap(dp, 0); + + writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); + writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); + writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + + writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); + writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL); + + writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L); + writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H); + + writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL); + + writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST); + + writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD); + writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN); + + writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH); + writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH); + + writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); +} + +void analogix_dp_swreset(struct analogix_dp_device *dp) +{ + writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET); +} + +void analogix_dp_config_interrupt(struct analogix_dp_device *dp) +{ + u32 reg; + + /* 0: mask, 1: unmask */ + reg = COMMON_INT_MASK_1; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); + + reg = COMMON_INT_MASK_2; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); + + reg = COMMON_INT_MASK_3; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); + + reg = COMMON_INT_MASK_4; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + + reg = INT_STA_MASK; + writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); +} + +void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) +{ + u32 reg; + + /* 0: mask, 1: unmask */ + reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + reg &= ~COMMON_INT_MASK_4; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + + reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); + reg &= ~INT_STA_MASK; + writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); +} + +void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) +{ + u32 reg; + + /* 0: mask, 1: unmask */ + reg = COMMON_INT_MASK_4; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + + reg = INT_STA_MASK; + writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); +} + +enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); + if (reg & PLL_LOCK) + return PLL_LOCKED; + else + return PLL_UNLOCKED; +} + +void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) +{ + u32 reg; + + if (enable) { + reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); + reg |= DP_PLL_PD; + writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); + } else { + reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); + reg &= ~DP_PLL_PD; + writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); + } +} + +void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, + enum analog_power_block block, + bool enable) +{ + u32 reg; + u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; + + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) + phy_pd_addr = ANALOGIX_DP_PD; + + switch (block) { + case AUX_BLOCK: + if (enable) { + reg = readl(dp->reg_base + phy_pd_addr); + reg |= AUX_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } else { + reg = readl(dp->reg_base + phy_pd_addr); + reg &= ~AUX_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } + break; + case CH0_BLOCK: + if (enable) { + reg = readl(dp->reg_base + phy_pd_addr); + reg |= CH0_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } else { + reg = readl(dp->reg_base + phy_pd_addr); + reg &= ~CH0_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } + break; + case CH1_BLOCK: + if (enable) { + reg = readl(dp->reg_base + phy_pd_addr); + reg |= CH1_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } else { + reg = readl(dp->reg_base + phy_pd_addr); + reg &= ~CH1_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } + break; + case CH2_BLOCK: + if (enable) { + reg = readl(dp->reg_base + phy_pd_addr); + reg |= CH2_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } else { + reg = readl(dp->reg_base + phy_pd_addr); + reg &= ~CH2_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } + break; + case CH3_BLOCK: + if (enable) { + reg = readl(dp->reg_base + phy_pd_addr); + reg |= CH3_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } else { + reg = readl(dp->reg_base + phy_pd_addr); + reg &= ~CH3_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } + break; + case ANALOG_TOTAL: + if (enable) { + reg = readl(dp->reg_base + phy_pd_addr); + reg |= DP_PHY_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } else { + reg = readl(dp->reg_base + phy_pd_addr); + reg &= ~DP_PHY_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } + break; + case POWER_ALL: + if (enable) { + reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | + CH1_PD | CH0_PD; + writel(reg, dp->reg_base + phy_pd_addr); + } else { + writel(0x00, dp->reg_base + phy_pd_addr); + } + break; + default: + break; + } +} + +void analogix_dp_init_analog_func(struct analogix_dp_device *dp) +{ + u32 reg; + int timeout_loop = 0; + + analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); + + reg = PLL_LOCK_CHG; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); + + reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); + reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); + writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); + + /* Power up PLL */ + if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + analogix_dp_set_pll_power_down(dp, 0); + + while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + timeout_loop++; + if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { + dev_err(dp->dev, "failed to get pll lock status\n"); + return; + } + usleep_range(10, 20); + } + } + + /* Enable Serdes FIFO function and Link symbol clock domain module */ + reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N + | AUX_FUNC_EN_N); + writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); +} + +void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) +{ + u32 reg; + + if (gpio_is_valid(dp->hpd_gpio)) + return; + + reg = HOTPLUG_CHG | HPD_LOST | PLUG; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); + + reg = INT_HPD; + writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); +} + +void analogix_dp_init_hpd(struct analogix_dp_device *dp) +{ + u32 reg; + + if (gpio_is_valid(dp->hpd_gpio)) + return; + + analogix_dp_clear_hotplug_interrupts(dp); + + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + reg &= ~(F_HPD | HPD_CTRL); + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); +} + +void analogix_dp_force_hpd(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + reg = (F_HPD | HPD_CTRL); + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); +} + +enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) +{ + u32 reg; + + if (gpio_is_valid(dp->hpd_gpio)) { + reg = gpio_get_value(dp->hpd_gpio); + if (reg) + return DP_IRQ_TYPE_HP_CABLE_IN; + else + return DP_IRQ_TYPE_HP_CABLE_OUT; + } else { + /* Parse hotplug interrupt status register */ + reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); + + if (reg & PLUG) + return DP_IRQ_TYPE_HP_CABLE_IN; + + if (reg & HPD_LOST) + return DP_IRQ_TYPE_HP_CABLE_OUT; + + if (reg & HOTPLUG_CHG) + return DP_IRQ_TYPE_HP_CHANGE; + + return DP_IRQ_TYPE_UNKNOWN; + } +} + +void analogix_dp_reset_aux(struct analogix_dp_device *dp) +{ + u32 reg; + + /* Disable AUX channel module */ + reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + reg |= AUX_FUNC_EN_N; + writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); +} + +void analogix_dp_init_aux(struct analogix_dp_device *dp) +{ + u32 reg; + + /* Clear inerrupts related to AUX channel */ + reg = RPLY_RECEIV | AUX_ERR; + writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); + + analogix_dp_reset_aux(dp); + + /* Disable AUX transaction H/W retry */ + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) + reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | + AUX_HW_RETRY_COUNT_SEL(3) | + AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; + else + reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | + AUX_HW_RETRY_COUNT_SEL(0) | + AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); + + /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ + reg = DEFER_CTRL_EN | DEFER_COUNT(1); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); + + /* Enable AUX channel module */ + reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + reg &= ~AUX_FUNC_EN_N; + writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); +} + +int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) +{ + u32 reg; + + if (gpio_is_valid(dp->hpd_gpio)) { + if (gpio_get_value(dp->hpd_gpio)) + return 0; + } else { + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + if (reg & HPD_STATUS) + return 0; + } + + return -EINVAL; +} + +void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + reg &= ~SW_FUNC_EN_N; + writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); +} + +int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) +{ + int reg; + int retval = 0; + int timeout_loop = 0; + + /* Enable AUX CH operation */ + reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); + reg |= AUX_EN; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); + + /* Is AUX CH command reply received? */ + reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); + while (!(reg & RPLY_RECEIV)) { + timeout_loop++; + if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { + dev_err(dp->dev, "AUX CH command reply failed!\n"); + return -ETIMEDOUT; + } + reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); + usleep_range(10, 11); + } + + /* Clear interrupt source for AUX CH command reply */ + writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); + + /* Clear interrupt source for AUX CH access error */ + reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); + if (reg & AUX_ERR) { + writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); + return -EREMOTEIO; + } + + /* Check AUX CH error access status */ + reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); + if ((reg & AUX_STATUS_MASK) != 0) { + dev_err(dp->dev, "AUX CH error happens: %d\n\n", + reg & AUX_STATUS_MASK); + return -EREMOTEIO; + } + + return retval; +} + +int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, + unsigned int reg_addr, + unsigned char data) +{ + u32 reg; + int i; + int retval; + + for (i = 0; i < 3; i++) { + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + + /* Select DPCD device address */ + reg = AUX_ADDR_7_0(reg_addr); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + reg = AUX_ADDR_15_8(reg_addr); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + reg = AUX_ADDR_19_16(reg_addr); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + + /* Write data buffer */ + reg = (unsigned int)data; + writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); + + /* + * Set DisplayPort transaction and write 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + + /* Start AUX transaction */ + retval = analogix_dp_start_aux_transaction(dp); + if (retval == 0) + break; + + dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); + } + + return retval; +} + +int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, + unsigned int reg_addr, + unsigned char *data) +{ + u32 reg; + int i; + int retval; + + for (i = 0; i < 3; i++) { + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + + /* Select DPCD device address */ + reg = AUX_ADDR_7_0(reg_addr); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + reg = AUX_ADDR_15_8(reg_addr); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + reg = AUX_ADDR_19_16(reg_addr); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + + /* + * Set DisplayPort transaction and read 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + + /* Start AUX transaction */ + retval = analogix_dp_start_aux_transaction(dp); + if (retval == 0) + break; + + dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); + } + + /* Read data buffer */ + reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0); + *data = (unsigned char)(reg & 0xff); + + return retval; +} + +int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, + unsigned int reg_addr, + unsigned int count, + unsigned char data[]) +{ + u32 reg; + unsigned int start_offset; + unsigned int cur_data_count; + unsigned int cur_data_idx; + int i; + int retval = 0; + + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + + start_offset = 0; + while (start_offset < count) { + /* Buffer size of AUX CH is 16 * 4bytes */ + if ((count - start_offset) > 16) + cur_data_count = 16; + else + cur_data_count = count - start_offset; + + for (i = 0; i < 3; i++) { + /* Select DPCD device address */ + reg = AUX_ADDR_7_0(reg_addr + start_offset); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + reg = AUX_ADDR_15_8(reg_addr + start_offset); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + reg = AUX_ADDR_19_16(reg_addr + start_offset); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + + for (cur_data_idx = 0; cur_data_idx < cur_data_count; + cur_data_idx++) { + reg = data[start_offset + cur_data_idx]; + writel(reg, dp->reg_base + + ANALOGIX_DP_BUF_DATA_0 + + 4 * cur_data_idx); + } + + /* + * Set DisplayPort transaction and write + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_LENGTH(cur_data_count) | + AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + + /* Start AUX transaction */ + retval = analogix_dp_start_aux_transaction(dp); + if (retval == 0) + break; + + dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", + __func__); + } + + start_offset += cur_data_count; + } + + return retval; +} + +int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, + unsigned int reg_addr, + unsigned int count, + unsigned char data[]) +{ + u32 reg; + unsigned int start_offset; + unsigned int cur_data_count; + unsigned int cur_data_idx; + int i; + int retval = 0; + + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + + start_offset = 0; + while (start_offset < count) { + /* Buffer size of AUX CH is 16 * 4bytes */ + if ((count - start_offset) > 16) + cur_data_count = 16; + else + cur_data_count = count - start_offset; + + /* AUX CH Request Transaction process */ + for (i = 0; i < 3; i++) { + /* Select DPCD device address */ + reg = AUX_ADDR_7_0(reg_addr + start_offset); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + reg = AUX_ADDR_15_8(reg_addr + start_offset); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + reg = AUX_ADDR_19_16(reg_addr + start_offset); + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + + /* + * Set DisplayPort transaction and read + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_LENGTH(cur_data_count) | + AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + + /* Start AUX transaction */ + retval = analogix_dp_start_aux_transaction(dp); + if (retval == 0) + break; + + dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", + __func__); + } + + for (cur_data_idx = 0; cur_data_idx < cur_data_count; + cur_data_idx++) { + reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + + 4 * cur_data_idx); + data[start_offset + cur_data_idx] = + (unsigned char)reg; + } + + start_offset += cur_data_count; + } + + return retval; +} + +int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, + unsigned int device_addr, + unsigned int reg_addr) +{ + u32 reg; + int retval; + + /* Set EDID device address */ + reg = device_addr; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + + /* Set offset from base address of EDID device */ + writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); + + /* + * Set I2C transaction and write address + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | + AUX_TX_COMM_WRITE; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + + /* Start AUX transaction */ + retval = analogix_dp_start_aux_transaction(dp); + if (retval != 0) + dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); + + return retval; +} + +int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, + unsigned int device_addr, + unsigned int reg_addr, + unsigned int *data) +{ + u32 reg; + int i; + int retval; + + for (i = 0; i < 3; i++) { + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + + /* Select EDID device */ + retval = analogix_dp_select_i2c_device(dp, device_addr, + reg_addr); + if (retval != 0) + continue; + + /* + * Set I2C transaction and read data + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_I2C_TRANSACTION | + AUX_TX_COMM_READ; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + + /* Start AUX transaction */ + retval = analogix_dp_start_aux_transaction(dp); + if (retval == 0) + break; + + dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); + } + + /* Read data */ + if (retval == 0) + *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0); + + return retval; +} + +int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, + unsigned int device_addr, + unsigned int reg_addr, + unsigned int count, + unsigned char edid[]) +{ + u32 reg; + unsigned int i, j; + unsigned int cur_data_idx; + unsigned int defer = 0; + int retval = 0; + + for (i = 0; i < count; i += 16) { + for (j = 0; j < 3; j++) { + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + + /* Set normal AUX CH command */ + reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); + reg &= ~ADDR_ONLY; + writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); + + /* + * If Rx sends defer, Tx sends only reads + * request without sending address + */ + if (!defer) + retval = analogix_dp_select_i2c_device(dp, + device_addr, reg_addr + i); + else + defer = 0; + + if (retval == 0) { + /* + * Set I2C transaction and write data + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_LENGTH(16) | + AUX_TX_COMM_I2C_TRANSACTION | + AUX_TX_COMM_READ; + writel(reg, dp->reg_base + + ANALOGIX_DP_AUX_CH_CTL_1); + + /* Start AUX transaction */ + retval = analogix_dp_start_aux_transaction(dp); + if (retval == 0) + break; + + dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", + __func__); + } + /* Check if Rx sends defer */ + reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); + if (reg == AUX_RX_COMM_AUX_DEFER || + reg == AUX_RX_COMM_I2C_DEFER) { + dev_err(dp->dev, "Defer: %d\n\n", reg); + defer = 1; + } + } + + for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { + reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + + 4 * cur_data_idx); + edid[i + cur_data_idx] = (unsigned char)reg; + } + } + + return retval; +} + +void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) +{ + u32 reg; + + reg = bwtype; + if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) + writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); +} + +void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); + *bwtype = reg; +} + +void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) +{ + u32 reg; + + reg = count; + writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); +} + +void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); + *count = reg; +} + +void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, + bool enable) +{ + u32 reg; + + if (enable) { + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg |= ENHANCED; + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + } else { + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg &= ~ENHANCED; + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + } +} + +void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, + enum pattern_set pattern) +{ + u32 reg; + + switch (pattern) { + case PRBS7: + reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; + writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + break; + case D10_2: + reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; + writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + break; + case TRAINING_PTN1: + reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; + writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + break; + case TRAINING_PTN2: + reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; + writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + break; + case DP_NONE: + reg = SCRAMBLING_ENABLE | + LINK_QUAL_PATTERN_SET_DISABLE | + SW_TRAINING_PATTERN_SET_NORMAL; + writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + break; + default: + break; + } +} + +void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, + u32 level) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); + reg &= ~PRE_EMPHASIS_SET_MASK; + reg |= level << PRE_EMPHASIS_SET_SHIFT; + writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); +} + +void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, + u32 level) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); + reg &= ~PRE_EMPHASIS_SET_MASK; + reg |= level << PRE_EMPHASIS_SET_SHIFT; + writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); +} + +void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, + u32 level) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); + reg &= ~PRE_EMPHASIS_SET_MASK; + reg |= level << PRE_EMPHASIS_SET_SHIFT; + writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); +} + +void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, + u32 level) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); + reg &= ~PRE_EMPHASIS_SET_MASK; + reg |= level << PRE_EMPHASIS_SET_SHIFT; + writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); +} + +void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, + u32 training_lane) +{ + u32 reg; + + reg = training_lane; + writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); +} + +void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, + u32 training_lane) +{ + u32 reg; + + reg = training_lane; + writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); +} + +void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, + u32 training_lane) +{ + u32 reg; + + reg = training_lane; + writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); +} + +void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, + u32 training_lane) +{ + u32 reg; + + reg = training_lane; + writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); +} + +u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); + return reg; +} + +u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); + return reg; +} + +u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); + return reg; +} + +u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); + return reg; +} + +void analogix_dp_reset_macro(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); + reg |= MACRO_RST; + writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); + + /* 10 us is the minimum reset time. */ + usleep_range(10, 20); + + reg &= ~MACRO_RST; + writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); +} + +void analogix_dp_init_video(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; + writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); + + reg = 0x0; + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); + + reg = CHA_CRI(4) | CHA_CTRL; + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); + + reg = 0x0; + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + + reg = VID_HRES_TH(2) | VID_VRES_TH(0); + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); +} + +void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) +{ + u32 reg; + + /* Configure the input color depth, color space, dynamic range */ + reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | + (dp->video_info.color_depth << IN_BPC_SHIFT) | + (dp->video_info.color_space << IN_COLOR_F_SHIFT); + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); + + /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); + reg &= ~IN_YC_COEFFI_MASK; + if (dp->video_info.ycbcr_coeff) + reg |= IN_YC_COEFFI_ITU709; + else + reg |= IN_YC_COEFFI_ITU601; + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); +} + +int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); + + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); + + if (!(reg & DET_STA)) { + dev_dbg(dp->dev, "Input stream clock not detected.\n"); + return -EINVAL; + } + + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); + + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); + dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); + + if (reg & CHA_STA) { + dev_dbg(dp->dev, "Input stream clk is changing\n"); + return -EINVAL; + } + + return 0; +} + +void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, + enum clock_recovery_m_value_type type, + u32 m_value, u32 n_value) +{ + u32 reg; + + if (type == REGISTER_M) { + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg |= FIX_M_VID; + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg = m_value & 0xff; + writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); + reg = (m_value >> 8) & 0xff; + writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); + reg = (m_value >> 16) & 0xff; + writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); + + reg = n_value & 0xff; + writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); + reg = (n_value >> 8) & 0xff; + writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); + reg = (n_value >> 16) & 0xff; + writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); + } else { + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg &= ~FIX_M_VID; + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + + writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0); + writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1); + writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2); + } +} + +void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) +{ + u32 reg; + + if (type == VIDEO_TIMING_FROM_CAPTURE) { + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg &= ~FORMAT_SEL; + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + } else { + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg |= FORMAT_SEL; + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + } +} + +void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) +{ + u32 reg; + + if (enable) { + reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + reg &= ~VIDEO_MODE_MASK; + reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; + writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + } else { + reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + reg &= ~VIDEO_MODE_MASK; + reg |= VIDEO_MODE_SLAVE_MODE; + writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + } +} + +void analogix_dp_start_video(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + reg |= VIDEO_EN; + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); +} + +int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + + reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + if (!(reg & STRM_VALID)) { + dev_dbg(dp->dev, "Input video stream is not detected.\n"); + return -EINVAL; + } + + return 0; +} + +void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); + reg |= MASTER_VID_FUNC_EN_N; + writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg &= ~INTERACE_SCAN_CFG; + reg |= (dp->video_info.interlaced << 2); + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg &= ~VSYNC_POLARITY_CFG; + reg |= (dp->video_info.v_sync_polarity << 1); + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + + reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg &= ~HSYNC_POLARITY_CFG; + reg |= (dp->video_info.h_sync_polarity << 0); + writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + + reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; + writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); +} + +void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + reg &= ~SCRAMBLING_DISABLE; + writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); +} + +void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + reg |= SCRAMBLING_DISABLE; + writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); +} diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h similarity index 62% rename from drivers/gpu/drm/exynos/exynos_dp_reg.h rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 2e9bd0e0b9f2..337912b0aeab 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -1,5 +1,5 @@ /* - * Register definition file for Samsung DP driver + * Register definition file for Analogix DP core driver * * Copyright (C) 2012 Samsung Electronics Co., Ltd. * Author: Jingoo Han @@ -9,96 +9,104 @@ * published by the Free Software Foundation. */ -#ifndef _EXYNOS_DP_REG_H -#define _EXYNOS_DP_REG_H +#ifndef _ANALOGIX_DP_REG_H +#define _ANALOGIX_DP_REG_H -#define EXYNOS_DP_TX_SW_RESET 0x14 -#define EXYNOS_DP_FUNC_EN_1 0x18 -#define EXYNOS_DP_FUNC_EN_2 0x1C -#define EXYNOS_DP_VIDEO_CTL_1 0x20 -#define EXYNOS_DP_VIDEO_CTL_2 0x24 -#define EXYNOS_DP_VIDEO_CTL_3 0x28 +#define ANALOGIX_DP_TX_SW_RESET 0x14 +#define ANALOGIX_DP_FUNC_EN_1 0x18 +#define ANALOGIX_DP_FUNC_EN_2 0x1C +#define ANALOGIX_DP_VIDEO_CTL_1 0x20 +#define ANALOGIX_DP_VIDEO_CTL_2 0x24 +#define ANALOGIX_DP_VIDEO_CTL_3 0x28 -#define EXYNOS_DP_VIDEO_CTL_8 0x3C -#define EXYNOS_DP_VIDEO_CTL_10 0x44 +#define ANALOGIX_DP_VIDEO_CTL_8 0x3C +#define ANALOGIX_DP_VIDEO_CTL_10 0x44 -#define EXYNOS_DP_LANE_MAP 0x35C +#define ANALOGIX_DP_PLL_REG_1 0xfc +#define ANALOGIX_DP_PLL_REG_2 0x9e4 +#define ANALOGIX_DP_PLL_REG_3 0x9e8 +#define ANALOGIX_DP_PLL_REG_4 0x9ec +#define ANALOGIX_DP_PLL_REG_5 0xa00 -#define EXYNOS_DP_ANALOG_CTL_1 0x370 -#define EXYNOS_DP_ANALOG_CTL_2 0x374 -#define EXYNOS_DP_ANALOG_CTL_3 0x378 -#define EXYNOS_DP_PLL_FILTER_CTL_1 0x37C -#define EXYNOS_DP_TX_AMP_TUNING_CTL 0x380 +#define ANALOGIX_DP_PD 0x12c -#define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390 +#define ANALOGIX_DP_LANE_MAP 0x35C -#define EXYNOS_DP_COMMON_INT_STA_1 0x3C4 -#define EXYNOS_DP_COMMON_INT_STA_2 0x3C8 -#define EXYNOS_DP_COMMON_INT_STA_3 0x3CC -#define EXYNOS_DP_COMMON_INT_STA_4 0x3D0 -#define EXYNOS_DP_INT_STA 0x3DC -#define EXYNOS_DP_COMMON_INT_MASK_1 0x3E0 -#define EXYNOS_DP_COMMON_INT_MASK_2 0x3E4 -#define EXYNOS_DP_COMMON_INT_MASK_3 0x3E8 -#define EXYNOS_DP_COMMON_INT_MASK_4 0x3EC -#define EXYNOS_DP_INT_STA_MASK 0x3F8 -#define EXYNOS_DP_INT_CTL 0x3FC +#define ANALOGIX_DP_ANALOG_CTL_1 0x370 +#define ANALOGIX_DP_ANALOG_CTL_2 0x374 +#define ANALOGIX_DP_ANALOG_CTL_3 0x378 +#define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C +#define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 -#define EXYNOS_DP_SYS_CTL_1 0x600 -#define EXYNOS_DP_SYS_CTL_2 0x604 -#define EXYNOS_DP_SYS_CTL_3 0x608 -#define EXYNOS_DP_SYS_CTL_4 0x60C +#define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 -#define EXYNOS_DP_PKT_SEND_CTL 0x640 -#define EXYNOS_DP_HDCP_CTL 0x648 +#define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 +#define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 +#define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC +#define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 +#define ANALOGIX_DP_INT_STA 0x3DC +#define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 +#define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 +#define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 +#define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC +#define ANALOGIX_DP_INT_STA_MASK 0x3F8 +#define ANALOGIX_DP_INT_CTL 0x3FC -#define EXYNOS_DP_LINK_BW_SET 0x680 -#define EXYNOS_DP_LANE_COUNT_SET 0x684 -#define EXYNOS_DP_TRAINING_PTN_SET 0x688 -#define EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C -#define EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690 -#define EXYNOS_DP_LN2_LINK_TRAINING_CTL 0x694 -#define EXYNOS_DP_LN3_LINK_TRAINING_CTL 0x698 +#define ANALOGIX_DP_SYS_CTL_1 0x600 +#define ANALOGIX_DP_SYS_CTL_2 0x604 +#define ANALOGIX_DP_SYS_CTL_3 0x608 +#define ANALOGIX_DP_SYS_CTL_4 0x60C -#define EXYNOS_DP_DEBUG_CTL 0x6C0 -#define EXYNOS_DP_HPD_DEGLITCH_L 0x6C4 -#define EXYNOS_DP_HPD_DEGLITCH_H 0x6C8 -#define EXYNOS_DP_LINK_DEBUG_CTL 0x6E0 +#define ANALOGIX_DP_PKT_SEND_CTL 0x640 +#define ANALOGIX_DP_HDCP_CTL 0x648 -#define EXYNOS_DP_M_VID_0 0x700 -#define EXYNOS_DP_M_VID_1 0x704 -#define EXYNOS_DP_M_VID_2 0x708 -#define EXYNOS_DP_N_VID_0 0x70C -#define EXYNOS_DP_N_VID_1 0x710 -#define EXYNOS_DP_N_VID_2 0x714 +#define ANALOGIX_DP_LINK_BW_SET 0x680 +#define ANALOGIX_DP_LANE_COUNT_SET 0x684 +#define ANALOGIX_DP_TRAINING_PTN_SET 0x688 +#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C +#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 +#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 +#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 -#define EXYNOS_DP_PLL_CTL 0x71C -#define EXYNOS_DP_PHY_PD 0x720 -#define EXYNOS_DP_PHY_TEST 0x724 +#define ANALOGIX_DP_DEBUG_CTL 0x6C0 +#define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 +#define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 +#define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 -#define EXYNOS_DP_VIDEO_FIFO_THRD 0x730 -#define EXYNOS_DP_AUDIO_MARGIN 0x73C +#define ANALOGIX_DP_M_VID_0 0x700 +#define ANALOGIX_DP_M_VID_1 0x704 +#define ANALOGIX_DP_M_VID_2 0x708 +#define ANALOGIX_DP_N_VID_0 0x70C +#define ANALOGIX_DP_N_VID_1 0x710 +#define ANALOGIX_DP_N_VID_2 0x714 -#define EXYNOS_DP_M_VID_GEN_FILTER_TH 0x764 -#define EXYNOS_DP_M_AUD_GEN_FILTER_TH 0x778 -#define EXYNOS_DP_AUX_CH_STA 0x780 -#define EXYNOS_DP_AUX_CH_DEFER_CTL 0x788 -#define EXYNOS_DP_AUX_RX_COMM 0x78C -#define EXYNOS_DP_BUFFER_DATA_CTL 0x790 -#define EXYNOS_DP_AUX_CH_CTL_1 0x794 -#define EXYNOS_DP_AUX_ADDR_7_0 0x798 -#define EXYNOS_DP_AUX_ADDR_15_8 0x79C -#define EXYNOS_DP_AUX_ADDR_19_16 0x7A0 -#define EXYNOS_DP_AUX_CH_CTL_2 0x7A4 +#define ANALOGIX_DP_PLL_CTL 0x71C +#define ANALOGIX_DP_PHY_PD 0x720 +#define ANALOGIX_DP_PHY_TEST 0x724 -#define EXYNOS_DP_BUF_DATA_0 0x7C0 +#define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 +#define ANALOGIX_DP_AUDIO_MARGIN 0x73C -#define EXYNOS_DP_SOC_GENERAL_CTL 0x800 +#define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 +#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 +#define ANALOGIX_DP_AUX_CH_STA 0x780 +#define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 +#define ANALOGIX_DP_AUX_RX_COMM 0x78C +#define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 +#define ANALOGIX_DP_AUX_CH_CTL_1 0x794 +#define ANALOGIX_DP_AUX_ADDR_7_0 0x798 +#define ANALOGIX_DP_AUX_ADDR_15_8 0x79C +#define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 +#define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 -/* EXYNOS_DP_TX_SW_RESET */ +#define ANALOGIX_DP_BUF_DATA_0 0x7C0 + +#define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 + +/* ANALOGIX_DP_TX_SW_RESET */ #define RESET_DP_TX (0x1 << 0) -/* EXYNOS_DP_FUNC_EN_1 */ +/* ANALOGIX_DP_FUNC_EN_1 */ #define MASTER_VID_FUNC_EN_N (0x1 << 7) #define SLAVE_VID_FUNC_EN_N (0x1 << 5) #define AUD_FIFO_FUNC_EN_N (0x1 << 4) @@ -107,17 +115,17 @@ #define CRC_FUNC_EN_N (0x1 << 1) #define SW_FUNC_EN_N (0x1 << 0) -/* EXYNOS_DP_FUNC_EN_2 */ +/* ANALOGIX_DP_FUNC_EN_2 */ #define SSC_FUNC_EN_N (0x1 << 7) #define AUX_FUNC_EN_N (0x1 << 2) #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) -/* EXYNOS_DP_VIDEO_CTL_1 */ +/* ANALOGIX_DP_VIDEO_CTL_1 */ #define VIDEO_EN (0x1 << 7) #define HDCP_VIDEO_MUTE (0x1 << 6) -/* EXYNOS_DP_VIDEO_CTL_1 */ +/* ANALOGIX_DP_VIDEO_CTL_1 */ #define IN_D_RANGE_MASK (0x1 << 7) #define IN_D_RANGE_SHIFT (7) #define IN_D_RANGE_CEA (0x1 << 7) @@ -134,7 +142,7 @@ #define IN_COLOR_F_YCBCR422 (0x1 << 0) #define IN_COLOR_F_RGB (0x0 << 0) -/* EXYNOS_DP_VIDEO_CTL_3 */ +/* ANALOGIX_DP_VIDEO_CTL_3 */ #define IN_YC_COEFFI_MASK (0x1 << 7) #define IN_YC_COEFFI_SHIFT (7) #define IN_YC_COEFFI_ITU709 (0x1 << 7) @@ -144,17 +152,21 @@ #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) -/* EXYNOS_DP_VIDEO_CTL_8 */ +/* ANALOGIX_DP_VIDEO_CTL_8 */ #define VID_HRES_TH(x) (((x) & 0xf) << 4) #define VID_VRES_TH(x) (((x) & 0xf) << 0) -/* EXYNOS_DP_VIDEO_CTL_10 */ +/* ANALOGIX_DP_VIDEO_CTL_10 */ #define FORMAT_SEL (0x1 << 4) #define INTERACE_SCAN_CFG (0x1 << 2) #define VSYNC_POLARITY_CFG (0x1 << 1) #define HSYNC_POLARITY_CFG (0x1 << 0) -/* EXYNOS_DP_LANE_MAP */ +/* ANALOGIX_DP_PLL_REG_1 */ +#define REF_CLK_24M (0x1 << 1) +#define REF_CLK_27M (0x0 << 1) + +/* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) @@ -172,30 +184,30 @@ #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) -/* EXYNOS_DP_ANALOG_CTL_1 */ +/* ANALOGIX_DP_ANALOG_CTL_1 */ #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) -/* EXYNOS_DP_ANALOG_CTL_2 */ +/* ANALOGIX_DP_ANALOG_CTL_2 */ #define SEL_24M (0x1 << 3) #define TX_DVDD_BIT_1_0625V (0x4 << 0) -/* EXYNOS_DP_ANALOG_CTL_3 */ +/* ANALOGIX_DP_ANALOG_CTL_3 */ #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) #define VCO_BIT_600_MICRO (0x5 << 0) -/* EXYNOS_DP_PLL_FILTER_CTL_1 */ +/* ANALOGIX_DP_PLL_FILTER_CTL_1 */ #define PD_RING_OSC (0x1 << 6) #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) #define TX_CUR1_2X (0x1 << 2) #define TX_CUR_16_MA (0x3 << 0) -/* EXYNOS_DP_TX_AMP_TUNING_CTL */ +/* ANALOGIX_DP_TX_AMP_TUNING_CTL */ #define CH3_AMP_400_MV (0x0 << 24) #define CH2_AMP_400_MV (0x0 << 16) #define CH1_AMP_400_MV (0x0 << 8) #define CH0_AMP_400_MV (0x0 << 0) -/* EXYNOS_DP_AUX_HW_RETRY_CTL */ +/* ANALOGIX_DP_AUX_HW_RETRY_CTL */ #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) @@ -204,7 +216,7 @@ #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) -/* EXYNOS_DP_COMMON_INT_STA_1 */ +/* ANALOGIX_DP_COMMON_INT_STA_1 */ #define VSYNC_DET (0x1 << 7) #define PLL_LOCK_CHG (0x1 << 6) #define SPDIF_ERR (0x1 << 5) @@ -214,19 +226,19 @@ #define VID_CLK_CHG (0x1 << 1) #define SW_INT (0x1 << 0) -/* EXYNOS_DP_COMMON_INT_STA_2 */ +/* ANALOGIX_DP_COMMON_INT_STA_2 */ #define ENC_EN_CHG (0x1 << 6) #define HW_BKSV_RDY (0x1 << 3) #define HW_SHA_DONE (0x1 << 2) #define HW_AUTH_STATE_CHG (0x1 << 1) #define HW_AUTH_DONE (0x1 << 0) -/* EXYNOS_DP_COMMON_INT_STA_3 */ +/* ANALOGIX_DP_COMMON_INT_STA_3 */ #define AFIFO_UNDER (0x1 << 7) #define AFIFO_OVER (0x1 << 6) #define R0_CHK_FLAG (0x1 << 5) -/* EXYNOS_DP_COMMON_INT_STA_4 */ +/* ANALOGIX_DP_COMMON_INT_STA_4 */ #define PSR_ACTIVE (0x1 << 7) #define PSR_INACTIVE (0x1 << 6) #define SPDIF_BI_PHASE_ERR (0x1 << 5) @@ -234,29 +246,29 @@ #define HPD_LOST (0x1 << 1) #define PLUG (0x1 << 0) -/* EXYNOS_DP_INT_STA */ +/* ANALOGIX_DP_INT_STA */ #define INT_HPD (0x1 << 6) #define HW_TRAINING_FINISH (0x1 << 5) #define RPLY_RECEIV (0x1 << 1) #define AUX_ERR (0x1 << 0) -/* EXYNOS_DP_INT_CTL */ +/* ANALOGIX_DP_INT_CTL */ #define SOFT_INT_CTRL (0x1 << 2) #define INT_POL1 (0x1 << 1) #define INT_POL0 (0x1 << 0) -/* EXYNOS_DP_SYS_CTL_1 */ +/* ANALOGIX_DP_SYS_CTL_1 */ #define DET_STA (0x1 << 2) #define FORCE_DET (0x1 << 1) #define DET_CTRL (0x1 << 0) -/* EXYNOS_DP_SYS_CTL_2 */ +/* ANALOGIX_DP_SYS_CTL_2 */ #define CHA_CRI(x) (((x) & 0xf) << 4) #define CHA_STA (0x1 << 2) #define FORCE_CHA (0x1 << 1) #define CHA_CTRL (0x1 << 0) -/* EXYNOS_DP_SYS_CTL_3 */ +/* ANALOGIX_DP_SYS_CTL_3 */ #define HPD_STATUS (0x1 << 6) #define F_HPD (0x1 << 5) #define HPD_CTRL (0x1 << 4) @@ -265,13 +277,13 @@ #define F_VALID (0x1 << 1) #define VALID_CTRL (0x1 << 0) -/* EXYNOS_DP_SYS_CTL_4 */ +/* ANALOGIX_DP_SYS_CTL_4 */ #define FIX_M_AUD (0x1 << 4) #define ENHANCED (0x1 << 3) #define FIX_M_VID (0x1 << 2) #define M_VID_UPDATE_CTRL (0x3 << 0) -/* EXYNOS_DP_TRAINING_PTN_SET */ +/* ANALOGIX_DP_TRAINING_PTN_SET */ #define SCRAMBLER_TYPE (0x1 << 9) #define HW_LINK_TRAINING_PATTERN (0x1 << 8) #define SCRAMBLING_DISABLE (0x1 << 5) @@ -285,24 +297,24 @@ #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) -/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ +/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ #define PRE_EMPHASIS_SET_MASK (0x3 << 3) #define PRE_EMPHASIS_SET_SHIFT (3) -/* EXYNOS_DP_DEBUG_CTL */ +/* ANALOGIX_DP_DEBUG_CTL */ #define PLL_LOCK (0x1 << 4) #define F_PLL_LOCK (0x1 << 3) #define PLL_LOCK_CTRL (0x1 << 2) #define PN_INV (0x1 << 0) -/* EXYNOS_DP_PLL_CTL */ +/* ANALOGIX_DP_PLL_CTL */ #define DP_PLL_PD (0x1 << 7) #define DP_PLL_RESET (0x1 << 6) #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) -/* EXYNOS_DP_PHY_PD */ +/* ANALOGIX_DP_PHY_PD */ #define DP_PHY_PD (0x1 << 5) #define AUX_PD (0x1 << 4) #define CH3_PD (0x1 << 3) @@ -310,28 +322,28 @@ #define CH1_PD (0x1 << 1) #define CH0_PD (0x1 << 0) -/* EXYNOS_DP_PHY_TEST */ +/* ANALOGIX_DP_PHY_TEST */ #define MACRO_RST (0x1 << 5) #define CH1_TEST (0x1 << 1) #define CH0_TEST (0x1 << 0) -/* EXYNOS_DP_AUX_CH_STA */ +/* ANALOGIX_DP_AUX_CH_STA */ #define AUX_BUSY (0x1 << 4) #define AUX_STATUS_MASK (0xf << 0) -/* EXYNOS_DP_AUX_CH_DEFER_CTL */ +/* ANALOGIX_DP_AUX_CH_DEFER_CTL */ #define DEFER_CTRL_EN (0x1 << 7) #define DEFER_COUNT(x) (((x) & 0x7f) << 0) -/* EXYNOS_DP_AUX_RX_COMM */ +/* ANALOGIX_DP_AUX_RX_COMM */ #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) -/* EXYNOS_DP_BUFFER_DATA_CTL */ +/* ANALOGIX_DP_BUFFER_DATA_CTL */ #define BUF_CLR (0x1 << 7) #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) -/* EXYNOS_DP_AUX_CH_CTL_1 */ +/* ANALOGIX_DP_AUX_CH_CTL_1 */ #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) #define AUX_TX_COMM_MASK (0xf << 0) #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) @@ -340,20 +352,20 @@ #define AUX_TX_COMM_WRITE (0x0 << 0) #define AUX_TX_COMM_READ (0x1 << 0) -/* EXYNOS_DP_AUX_ADDR_7_0 */ +/* ANALOGIX_DP_AUX_ADDR_7_0 */ #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) -/* EXYNOS_DP_AUX_ADDR_15_8 */ +/* ANALOGIX_DP_AUX_ADDR_15_8 */ #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) -/* EXYNOS_DP_AUX_ADDR_19_16 */ +/* ANALOGIX_DP_AUX_ADDR_19_16 */ #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) -/* EXYNOS_DP_AUX_CH_CTL_2 */ +/* ANALOGIX_DP_AUX_CH_CTL_2 */ #define ADDR_ONLY (0x1 << 1) #define AUX_EN (0x1 << 0) -/* EXYNOS_DP_SOC_GENERAL_CTL */ +/* ANALOGIX_DP_SOC_GENERAL_CTL */ #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) #define AUDIO_MODE_MASTER_MODE (0x0 << 8) #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) @@ -363,4 +375,4 @@ #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) #define VIDEO_MODE_MASTER_MODE (0x0 << 0) -#endif /* _EXYNOS_DP_REG_H */ +#endif /* _ANALOGIX_DP_REG_H */ diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c index 9795b72472ba..c9d941283d30 100644 --- a/drivers/gpu/drm/bridge/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/dw-hdmi.c @@ -1413,11 +1413,6 @@ static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) mutex_unlock(&hdmi->mutex); } -static void dw_hdmi_bridge_nop(struct drm_bridge *bridge) -{ - /* do nothing */ -} - static enum drm_connector_status dw_hdmi_connector_detect(struct drm_connector *connector, bool force) { @@ -1536,8 +1531,6 @@ static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { .enable = dw_hdmi_bridge_enable, .disable = dw_hdmi_bridge_disable, - .pre_enable = dw_hdmi_bridge_nop, - .post_disable = dw_hdmi_bridge_nop, .mode_set = dw_hdmi_bridge_mode_set, }; diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.c b/drivers/gpu/drm/cirrus/cirrus_drv.c index 7bc394ec9fb3..dc83f69da6f1 100644 --- a/drivers/gpu/drm/cirrus/cirrus_drv.c +++ b/drivers/gpu/drm/cirrus/cirrus_drv.c @@ -163,10 +163,8 @@ static struct pci_driver cirrus_pci_driver = { static int __init cirrus_init(void) { -#ifdef CONFIG_VGA_CONSOLE if (vgacon_text_force() && cirrus_modeset == -1) return -EINVAL; -#endif if (cirrus_modeset == 0) return -EINVAL; diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.h b/drivers/gpu/drm/cirrus/cirrus_drv.h index b774d637a00f..2188d6b61b3e 100644 --- a/drivers/gpu/drm/cirrus/cirrus_drv.h +++ b/drivers/gpu/drm/cirrus/cirrus_drv.h @@ -245,7 +245,7 @@ static inline int cirrus_bo_reserve(struct cirrus_bo *bo, bool no_wait) { int ret; - ret = ttm_bo_reserve(&bo->bo, true, no_wait, false, NULL); + ret = ttm_bo_reserve(&bo->bo, true, no_wait, NULL); if (ret) { if (ret != -ERESTARTSYS && ret != -EBUSY) DRM_ERROR("reserve failed %p\n", bo); diff --git a/drivers/gpu/drm/cirrus/cirrus_main.c b/drivers/gpu/drm/cirrus/cirrus_main.c index 0907715e90fd..32d32c5b7b17 100644 --- a/drivers/gpu/drm/cirrus/cirrus_main.c +++ b/drivers/gpu/drm/cirrus/cirrus_main.c @@ -61,7 +61,7 @@ cirrus_user_framebuffer_create(struct drm_device *dev, bpp, mode_cmd->pitches[0])) return ERR_PTR(-EINVAL); - obj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]); + obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]); if (obj == NULL) return ERR_PTR(-ENOENT); @@ -295,7 +295,7 @@ cirrus_dumb_mmap_offset(struct drm_file *file, struct drm_gem_object *obj; struct cirrus_bo *bo; - obj = drm_gem_object_lookup(dev, file, handle); + obj = drm_gem_object_lookup(file, handle); if (obj == NULL) return -ENOENT; diff --git a/drivers/gpu/drm/cirrus/cirrus_ttm.c b/drivers/gpu/drm/cirrus/cirrus_ttm.c index dfffd528517a..6768b7b1af32 100644 --- a/drivers/gpu/drm/cirrus/cirrus_ttm.c +++ b/drivers/gpu/drm/cirrus/cirrus_ttm.c @@ -245,6 +245,8 @@ struct ttm_bo_driver cirrus_bo_driver = { .verify_access = cirrus_bo_verify_access, .io_mem_reserve = &cirrus_ttm_io_mem_reserve, .io_mem_free = &cirrus_ttm_io_mem_free, + .lru_tail = &ttm_bo_default_lru_tail, + .swap_lru_tail = &ttm_bo_default_swap_lru_tail, }; int cirrus_mm_init(struct cirrus_device *cirrus) diff --git a/drivers/gpu/drm/drm_agpsupport.c b/drivers/gpu/drm/drm_agpsupport.c index a10ea6aec629..605bd243fb36 100644 --- a/drivers/gpu/drm/drm_agpsupport.c +++ b/drivers/gpu/drm/drm_agpsupport.c @@ -423,7 +423,7 @@ struct drm_agp_head *drm_agp_init(struct drm_device *dev) } /** - * drm_agp_clear - Clear AGP resource list + * drm_legacy_agp_clear - Clear AGP resource list * @dev: DRM device * * Iterate over all AGP resources and remove them. But keep the AGP head @@ -434,7 +434,7 @@ struct drm_agp_head *drm_agp_init(struct drm_device *dev) * resources from getting destroyed. Drivers are responsible of cleaning them up * during device shutdown. */ -void drm_agp_clear(struct drm_device *dev) +void drm_legacy_agp_clear(struct drm_device *dev) { struct drm_agp_mem *entry, *tempe; diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 8ee1db866e80..3ff1ed7b33db 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -31,6 +31,8 @@ #include #include +#include "drm_crtc_internal.h" + /** * drm_atomic_state_default_release - * release memory initialized by drm_atomic_state_init @@ -142,18 +144,11 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state) if (!connector) continue; - /* - * FIXME: Async commits can race with connector unplugging and - * there's currently nothing that prevents cleanup up state for - * deleted connectors. As long as the callback doesn't look at - * the connector we'll be fine though, so make sure that's the - * case by setting all connector pointers to NULL. - */ - state->connector_states[i]->connector = NULL; - connector->funcs->atomic_destroy_state(NULL, + connector->funcs->atomic_destroy_state(connector, state->connector_states[i]); state->connectors[i] = NULL; state->connector_states[i] = NULL; + drm_connector_unreference(connector); } for (i = 0; i < config->num_crtc; i++) { @@ -261,6 +256,8 @@ drm_atomic_get_crtc_state(struct drm_atomic_state *state, int ret, index = drm_crtc_index(crtc); struct drm_crtc_state *crtc_state; + WARN_ON(!state->acquire_ctx); + crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); if (crtc_state) return crtc_state; @@ -620,6 +617,8 @@ drm_atomic_get_plane_state(struct drm_atomic_state *state, int ret, index = drm_plane_index(plane); struct drm_plane_state *plane_state; + WARN_ON(!state->acquire_ctx); + plane_state = drm_atomic_get_existing_plane_state(state, plane); if (plane_state) return plane_state; @@ -888,6 +887,8 @@ drm_atomic_get_connector_state(struct drm_atomic_state *state, struct drm_mode_config *config = &connector->dev->mode_config; struct drm_connector_state *connector_state; + WARN_ON(!state->acquire_ctx); + ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx); if (ret) return ERR_PTR(ret); @@ -924,6 +925,7 @@ drm_atomic_get_connector_state(struct drm_atomic_state *state, if (!connector_state) return ERR_PTR(-ENOMEM); + drm_connector_reference(connector); state->connector_states[index] = connector_state; state->connectors[index] = connector; connector_state->state = state; @@ -1158,12 +1160,18 @@ drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state, { struct drm_crtc_state *crtc_state; - if (conn_state->crtc && conn_state->crtc != crtc) { + if (conn_state->crtc == crtc) + return 0; + + if (conn_state->crtc) { crtc_state = drm_atomic_get_existing_crtc_state(conn_state->state, conn_state->crtc); crtc_state->connector_mask &= ~(1 << drm_connector_index(conn_state->connector)); + + drm_connector_unreference(conn_state->connector); + conn_state->crtc = NULL; } if (crtc) { @@ -1173,16 +1181,16 @@ drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state, crtc_state->connector_mask |= 1 << drm_connector_index(conn_state->connector); - } - conn_state->crtc = crtc; + drm_connector_reference(conn_state->connector); + conn_state->crtc = crtc; - if (crtc) DRM_DEBUG_ATOMIC("Link connector state %p to [CRTC:%d:%s]\n", conn_state, crtc->base.id, crtc->name); - else + } else { DRM_DEBUG_ATOMIC("Link connector state %p to [NOCRTC]\n", conn_state); + } return 0; } @@ -1388,7 +1396,7 @@ int drm_atomic_commit(struct drm_atomic_state *state) EXPORT_SYMBOL(drm_atomic_commit); /** - * drm_atomic_async_commit - atomic&async configuration commit + * drm_atomic_nonblocking_commit - atomic&nonblocking configuration commit * @state: atomic configuration to check * * Note that this function can return -EDEADLK if the driver needed to acquire @@ -1403,7 +1411,7 @@ EXPORT_SYMBOL(drm_atomic_commit); * Returns: * 0 on success, negative error code on failure. */ -int drm_atomic_async_commit(struct drm_atomic_state *state) +int drm_atomic_nonblocking_commit(struct drm_atomic_state *state) { struct drm_mode_config *config = &state->dev->mode_config; int ret; @@ -1412,11 +1420,11 @@ int drm_atomic_async_commit(struct drm_atomic_state *state) if (ret) return ret; - DRM_DEBUG_ATOMIC("commiting %p asynchronously\n", state); + DRM_DEBUG_ATOMIC("commiting %p nonblocking\n", state); return config->funcs->atomic_commit(state->dev, state, true); } -EXPORT_SYMBOL(drm_atomic_async_commit); +EXPORT_SYMBOL(drm_atomic_nonblocking_commit); /* * The big monstor ioctl @@ -1614,12 +1622,19 @@ retry: } obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_ANY); - if (!obj || !obj->properties) { + if (!obj) { + ret = -ENOENT; + goto out; + } + + if (!obj->properties) { + drm_mode_object_unreference(obj); ret = -ENOENT; goto out; } if (get_user(count_props, count_props_ptr + copied_objs)) { + drm_mode_object_unreference(obj); ret = -EFAULT; goto out; } @@ -1632,12 +1647,14 @@ retry: struct drm_property *prop; if (get_user(prop_id, props_ptr + copied_props)) { + drm_mode_object_unreference(obj); ret = -EFAULT; goto out; } prop = drm_property_find(dev, prop_id); if (!prop) { + drm_mode_object_unreference(obj); ret = -ENOENT; goto out; } @@ -1645,13 +1662,16 @@ retry: if (copy_from_user(&prop_value, prop_values_ptr + copied_props, sizeof(prop_value))) { + drm_mode_object_unreference(obj); ret = -EFAULT; goto out; } ret = atomic_set_prop(state, obj, prop, prop_value); - if (ret) + if (ret) { + drm_mode_object_unreference(obj); goto out; + } copied_props++; } @@ -1662,6 +1682,7 @@ retry: plane_mask |= (1 << drm_plane_index(plane)); plane->old_fb = plane->fb; } + drm_mode_object_unreference(obj); } if (arg->flags & DRM_MODE_PAGE_FLIP_EVENT) { @@ -1685,7 +1706,7 @@ retry: */ ret = drm_atomic_check_only(state); } else if (arg->flags & DRM_MODE_ATOMIC_NONBLOCK) { - ret = drm_atomic_async_commit(state); + ret = drm_atomic_nonblocking_commit(state); } else { ret = drm_atomic_commit(state); } diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 4befe25c81c7..ddfa0d120e39 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -384,8 +384,6 @@ mode_fixup(struct drm_atomic_state *state) */ encoder = conn_state->best_encoder; funcs = encoder->helper_private; - if (!funcs) - continue; ret = drm_bridge_mode_fixup(encoder->bridge, &crtc_state->mode, &crtc_state->adjusted_mode); @@ -394,7 +392,7 @@ mode_fixup(struct drm_atomic_state *state) return -EINVAL; } - if (funcs->atomic_check) { + if (funcs && funcs->atomic_check) { ret = funcs->atomic_check(encoder, crtc_state, conn_state); if (ret) { @@ -402,7 +400,7 @@ mode_fixup(struct drm_atomic_state *state) encoder->base.id, encoder->name); return ret; } - } else if (funcs->mode_fixup) { + } else if (funcs && funcs->mode_fixup) { ret = funcs->mode_fixup(encoder, &crtc_state->mode, &crtc_state->adjusted_mode); if (!ret) { @@ -707,12 +705,14 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) drm_bridge_disable(encoder->bridge); /* Right function depends upon target state. */ - if (connector->state->crtc && funcs->prepare) - funcs->prepare(encoder); - else if (funcs->disable) - funcs->disable(encoder); - else - funcs->dpms(encoder, DRM_MODE_DPMS_OFF); + if (funcs) { + if (connector->state->crtc && funcs->prepare) + funcs->prepare(encoder); + else if (funcs->disable) + funcs->disable(encoder); + else if (funcs->dpms) + funcs->dpms(encoder, DRM_MODE_DPMS_OFF); + } drm_bridge_post_disable(encoder->bridge); } @@ -873,7 +873,7 @@ crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state) * Each encoder has at most one connector (since we always steal * it away), so we won't call mode_set hooks twice. */ - if (funcs->mode_set) + if (funcs && funcs->mode_set) funcs->mode_set(encoder, mode, adjusted_mode); drm_bridge_mode_set(encoder->bridge, mode, adjusted_mode); @@ -974,17 +974,29 @@ void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, */ drm_bridge_pre_enable(encoder->bridge); - if (funcs->enable) - funcs->enable(encoder); - else - funcs->commit(encoder); + if (funcs) { + if (funcs->enable) + funcs->enable(encoder); + else if (funcs->commit) + funcs->commit(encoder); + } drm_bridge_enable(encoder->bridge); } } EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_enables); -static void wait_for_fences(struct drm_device *dev, +/** + * drm_atomic_helper_wait_for_fences - wait for fences stashed in plane state + * @dev: DRM device + * @state: atomic state object with old state structures + * + * For implicit sync, driver should fish the exclusive fence out from the + * incoming fb's and stash it in the drm_plane_state. This is called after + * drm_atomic_helper_swap_state() so it uses the current plane state (and + * just uses the atomic state to find the changed planes) + */ +void drm_atomic_helper_wait_for_fences(struct drm_device *dev, struct drm_atomic_state *state) { struct drm_plane *plane; @@ -1002,6 +1014,7 @@ static void wait_for_fences(struct drm_device *dev, plane->state->fence = NULL; } } +EXPORT_SYMBOL(drm_atomic_helper_wait_for_fences); /** * drm_atomic_helper_framebuffer_changed - check if framebuffer has changed @@ -1092,6 +1105,8 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, drm_crtc_vblank_count(crtc), msecs_to_jiffies(50)); + WARN(!ret, "[CRTC:%d] vblank wait timed out\n", crtc->base.id); + drm_crtc_vblank_put(crtc); } } @@ -1101,13 +1116,13 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks); * drm_atomic_helper_commit - commit validated state object * @dev: DRM device * @state: the driver state object - * @async: asynchronous commit + * @nonblocking: whether nonblocking behavior is requested. * * This function commits a with drm_atomic_helper_check() pre-validated state * object. This can still fail when e.g. the framebuffer reservation fails. For - * now this doesn't implement asynchronous commits. + * now this doesn't implement nonblocking commits. * - * Note that right now this function does not support async commits, and hence + * Note that right now this function does not support nonblocking commits, hence * driver writers must implement their own version for now. Also note that the * default ordering of how the various stages are called is to match the legacy * modeset helper library closest. One peculiarity of that is that it doesn't @@ -1128,11 +1143,11 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks); */ int drm_atomic_helper_commit(struct drm_device *dev, struct drm_atomic_state *state, - bool async) + bool nonblock) { int ret; - if (async) + if (nonblock) return -EBUSY; ret = drm_atomic_helper_prepare_planes(dev, state); @@ -1163,7 +1178,7 @@ int drm_atomic_helper_commit(struct drm_device *dev, * current layout. */ - wait_for_fences(dev, state); + drm_atomic_helper_wait_for_fences(dev, state); drm_atomic_helper_commit_modeset_disables(dev, state); @@ -1182,20 +1197,20 @@ int drm_atomic_helper_commit(struct drm_device *dev, EXPORT_SYMBOL(drm_atomic_helper_commit); /** - * DOC: implementing async commit + * DOC: implementing nonblocking commit * - * For now the atomic helpers don't support async commit directly. If there is - * real need it could be added though, using the dma-buf fence infrastructure - * for generic synchronization with outstanding rendering. + * For now the atomic helpers don't support nonblocking commit directly. If + * there is real need it could be added though, using the dma-buf fence + * infrastructure for generic synchronization with outstanding rendering. * - * For now drivers have to implement async commit themselves, with the following - * sequence being the recommended one: + * For now drivers have to implement nonblocking commit themselves, with the + * following sequence being the recommended one: * * 1. Run drm_atomic_helper_prepare_planes() first. This is the only function * which commit needs to call which can fail, so we want to run it first and * synchronously. * - * 2. Synchronize with any outstanding asynchronous commit worker threads which + * 2. Synchronize with any outstanding nonblocking commit worker threads which * might be affected the new state update. This can be done by either cancelling * or flushing the work items, depending upon whether the driver can deal with * cancelled updates. Note that it is important to ensure that the framebuffer @@ -1209,9 +1224,9 @@ EXPORT_SYMBOL(drm_atomic_helper_commit); * 3. The software state is updated synchronously with * drm_atomic_helper_swap_state(). Doing this under the protection of all modeset * locks means concurrent callers never see inconsistent state. And doing this - * while it's guaranteed that no relevant async worker runs means that async - * workers do not need grab any locks. Actually they must not grab locks, for - * otherwise the work flushing will deadlock. + * while it's guaranteed that no relevant nonblocking worker runs means that + * nonblocking workers do not need grab any locks. Actually they must not grab + * locks, for otherwise the work flushing will deadlock. * * 4. Schedule a work item to do all subsequent steps, using the split-out * commit helpers: a) pre-plane commit b) plane commit c) post-plane commit and @@ -2358,11 +2373,11 @@ retry: goto fail; } - ret = drm_atomic_async_commit(state); + ret = drm_atomic_nonblocking_commit(state); if (ret != 0) goto fail; - /* Driver takes ownership of state on successful async commit. */ + /* Driver takes ownership of state on successful commit. */ return 0; fail: if (ret == -EDEADLK) @@ -2467,6 +2482,23 @@ backoff: } EXPORT_SYMBOL(drm_atomic_helper_connector_dpms); +/** + * drm_atomic_helper_best_encoder - Helper for &drm_connector_helper_funcs + * ->best_encoder callback + * @connector: Connector control structure + * + * This is a &drm_connector_helper_funcs ->best_encoder callback helper for + * connectors that support exactly 1 encoder, statically determined at driver + * init time. + */ +struct drm_encoder * +drm_atomic_helper_best_encoder(struct drm_connector *connector) +{ + WARN_ON(connector->encoder_ids[1]); + return drm_encoder_find(connector->dev, connector->encoder_ids[0]); +} +EXPORT_SYMBOL(drm_atomic_helper_best_encoder); + /** * DOC: atomic state reset and initialization * @@ -2497,12 +2529,9 @@ EXPORT_SYMBOL(drm_atomic_helper_connector_dpms); */ void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc) { - if (crtc->state) { - drm_property_unreference_blob(crtc->state->mode_blob); - drm_property_unreference_blob(crtc->state->degamma_lut); - drm_property_unreference_blob(crtc->state->ctm); - drm_property_unreference_blob(crtc->state->gamma_lut); - } + if (crtc->state) + __drm_atomic_helper_crtc_destroy_state(crtc->state); + kfree(crtc->state); crtc->state = kzalloc(sizeof(*crtc->state), GFP_KERNEL); @@ -2566,15 +2595,13 @@ EXPORT_SYMBOL(drm_atomic_helper_crtc_duplicate_state); /** * __drm_atomic_helper_crtc_destroy_state - release CRTC state - * @crtc: CRTC object * @state: CRTC state object to release * * Releases all resources stored in the CRTC state without actually freeing * the memory of the CRTC state. This is useful for drivers that subclass the * CRTC state. */ -void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, - struct drm_crtc_state *state) +void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state) { drm_property_unreference_blob(state->mode_blob); drm_property_unreference_blob(state->degamma_lut); @@ -2594,7 +2621,7 @@ EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state); void drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) { - __drm_atomic_helper_crtc_destroy_state(crtc, state); + __drm_atomic_helper_crtc_destroy_state(state); kfree(state); } EXPORT_SYMBOL(drm_atomic_helper_crtc_destroy_state); @@ -2608,8 +2635,8 @@ EXPORT_SYMBOL(drm_atomic_helper_crtc_destroy_state); */ void drm_atomic_helper_plane_reset(struct drm_plane *plane) { - if (plane->state && plane->state->fb) - drm_framebuffer_unreference(plane->state->fb); + if (plane->state) + __drm_atomic_helper_plane_destroy_state(plane->state); kfree(plane->state); plane->state = kzalloc(sizeof(*plane->state), GFP_KERNEL); @@ -2664,15 +2691,13 @@ EXPORT_SYMBOL(drm_atomic_helper_plane_duplicate_state); /** * __drm_atomic_helper_plane_destroy_state - release plane state - * @plane: plane object * @state: plane state object to release * * Releases all resources stored in the plane state without actually freeing * the memory of the plane state. This is useful for drivers that subclass the * plane state. */ -void __drm_atomic_helper_plane_destroy_state(struct drm_plane *plane, - struct drm_plane_state *state) +void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) { if (state->fb) drm_framebuffer_unreference(state->fb); @@ -2690,7 +2715,7 @@ EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); void drm_atomic_helper_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) { - __drm_atomic_helper_plane_destroy_state(plane, state); + __drm_atomic_helper_plane_destroy_state(state); kfree(state); } EXPORT_SYMBOL(drm_atomic_helper_plane_destroy_state); @@ -2730,6 +2755,9 @@ void drm_atomic_helper_connector_reset(struct drm_connector *connector) struct drm_connector_state *conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); + if (connector->state) + __drm_atomic_helper_connector_destroy_state(connector->state); + kfree(connector->state); __drm_atomic_helper_connector_reset(connector, conn_state); } @@ -2748,6 +2776,8 @@ __drm_atomic_helper_connector_duplicate_state(struct drm_connector *connector, struct drm_connector_state *state) { memcpy(state, connector->state, sizeof(*state)); + if (state->crtc) + drm_connector_reference(connector); } EXPORT_SYMBOL(__drm_atomic_helper_connector_duplicate_state); @@ -2859,7 +2889,6 @@ EXPORT_SYMBOL(drm_atomic_helper_duplicate_state); /** * __drm_atomic_helper_connector_destroy_state - release connector state - * @connector: connector object * @state: connector state object to release * * Releases all resources stored in the connector state without actually @@ -2867,14 +2896,15 @@ EXPORT_SYMBOL(drm_atomic_helper_duplicate_state); * subclass the connector state. */ void -__drm_atomic_helper_connector_destroy_state(struct drm_connector *connector, - struct drm_connector_state *state) +__drm_atomic_helper_connector_destroy_state(struct drm_connector_state *state) { /* * This is currently a placeholder so that drivers that subclass the * state will automatically do the right thing if code is ever added * to this function. */ + if (state->crtc) + drm_connector_unreference(state->connector); } EXPORT_SYMBOL(__drm_atomic_helper_connector_destroy_state); @@ -2889,7 +2919,7 @@ EXPORT_SYMBOL(__drm_atomic_helper_connector_destroy_state); void drm_atomic_helper_connector_destroy_state(struct drm_connector *connector, struct drm_connector_state *state) { - __drm_atomic_helper_connector_destroy_state(connector, state); + __drm_atomic_helper_connector_destroy_state(state); kfree(state); } EXPORT_SYMBOL(drm_atomic_helper_connector_destroy_state); diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c index f1a204d253cc..9b34158c0f77 100644 --- a/drivers/gpu/drm/drm_bufs.c +++ b/drivers/gpu/drm/drm_bufs.c @@ -396,6 +396,10 @@ int drm_legacy_addmap_ioctl(struct drm_device *dev, void *data, if (!(capable(CAP_SYS_ADMIN) || map->type == _DRM_AGP || map->type == _DRM_SHM)) return -EPERM; + if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) && + drm_core_check_feature(dev, DRIVER_MODESET)) + return -EINVAL; + err = drm_addmap_core(dev, map->offset, map->size, map->type, map->flags, &maplist); @@ -416,6 +420,62 @@ int drm_legacy_addmap_ioctl(struct drm_device *dev, void *data, return 0; } +/* + * Get a mapping information. + * + * \param inode device inode. + * \param file_priv DRM file private. + * \param cmd command. + * \param arg user argument, pointing to a drm_map structure. + * + * \return zero on success or a negative number on failure. + * + * Searches for the mapping with the specified offset and copies its information + * into userspace + */ +int drm_legacy_getmap_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_map *map = data; + struct drm_map_list *r_list = NULL; + struct list_head *list; + int idx; + int i; + + if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) && + drm_core_check_feature(dev, DRIVER_MODESET)) + return -EINVAL; + + idx = map->offset; + if (idx < 0) + return -EINVAL; + + i = 0; + mutex_lock(&dev->struct_mutex); + list_for_each(list, &dev->maplist) { + if (i == idx) { + r_list = list_entry(list, struct drm_map_list, head); + break; + } + i++; + } + if (!r_list || !r_list->map) { + mutex_unlock(&dev->struct_mutex); + return -EINVAL; + } + + map->offset = r_list->map->offset; + map->size = r_list->map->size; + map->type = r_list->map->type; + map->flags = r_list->map->flags; + map->handle = (void *)(unsigned long) r_list->user_token; + map->mtrr = arch_phys_wc_index(r_list->map->mtrr); + + mutex_unlock(&dev->struct_mutex); + + return 0; +} + /** * Remove a map private from list and deallocate resources if the mapping * isn't in use. @@ -482,18 +542,35 @@ int drm_legacy_rmmap_locked(struct drm_device *dev, struct drm_local_map *map) } EXPORT_SYMBOL(drm_legacy_rmmap_locked); -int drm_legacy_rmmap(struct drm_device *dev, struct drm_local_map *map) +void drm_legacy_rmmap(struct drm_device *dev, struct drm_local_map *map) { - int ret; + if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) && + drm_core_check_feature(dev, DRIVER_MODESET)) + return; mutex_lock(&dev->struct_mutex); - ret = drm_legacy_rmmap_locked(dev, map); + drm_legacy_rmmap_locked(dev, map); mutex_unlock(&dev->struct_mutex); - - return ret; } EXPORT_SYMBOL(drm_legacy_rmmap); +void drm_legacy_master_rmmaps(struct drm_device *dev, struct drm_master *master) +{ + struct drm_map_list *r_list, *list_temp; + + if (drm_core_check_feature(dev, DRIVER_MODESET)) + return; + + mutex_lock(&dev->struct_mutex); + list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) { + if (r_list->master == master) { + drm_legacy_rmmap_locked(dev, r_list->map); + r_list = NULL; + } + } + mutex_unlock(&dev->struct_mutex); +} + /* The rmmap ioctl appears to be unnecessary. All mappings are torn down on * the last close of the device, and this is necessary for cleanup when things * exit uncleanly. Therefore, having userland manually remove mappings seems @@ -517,6 +594,10 @@ int drm_legacy_rmmap_ioctl(struct drm_device *dev, void *data, struct drm_map_list *r_list; int ret; + if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) && + drm_core_check_feature(dev, DRIVER_MODESET)) + return -EINVAL; + mutex_lock(&dev->struct_mutex); list_for_each_entry(r_list, &dev->maplist, head) { if (r_list->map && diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index e08f962288d9..d2a6d958ca76 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -168,6 +168,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] = { { DRM_MODE_CONNECTOR_eDP, "eDP" }, { DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" }, { DRM_MODE_CONNECTOR_DSI, "DSI" }, + { DRM_MODE_CONNECTOR_DPI, "DPI" }, }; static const struct drm_prop_enum_list drm_encoder_enum_list[] = { @@ -179,6 +180,7 @@ static const struct drm_prop_enum_list drm_encoder_enum_list[] = { { DRM_MODE_ENCODER_VIRTUAL, "Virtual" }, { DRM_MODE_ENCODER_DSI, "DSI" }, { DRM_MODE_ENCODER_DPMST, "DP MST" }, + { DRM_MODE_ENCODER_DPI, "DPI" }, }; static const struct drm_prop_enum_list drm_subpixel_enum_list[] = { @@ -275,7 +277,8 @@ EXPORT_SYMBOL(drm_get_format_name); static int drm_mode_object_get_reg(struct drm_device *dev, struct drm_mode_object *obj, uint32_t obj_type, - bool register_obj) + bool register_obj, + void (*obj_free_cb)(struct kref *kref)) { int ret; @@ -288,6 +291,10 @@ static int drm_mode_object_get_reg(struct drm_device *dev, */ obj->id = ret; obj->type = obj_type; + if (obj_free_cb) { + obj->free_cb = obj_free_cb; + kref_init(&obj->refcount); + } } mutex_unlock(&dev->mode_config.idr_mutex); @@ -311,7 +318,7 @@ static int drm_mode_object_get_reg(struct drm_device *dev, int drm_mode_object_get(struct drm_device *dev, struct drm_mode_object *obj, uint32_t obj_type) { - return drm_mode_object_get_reg(dev, obj, obj_type, true); + return drm_mode_object_get_reg(dev, obj, obj_type, true, NULL); } static void drm_mode_object_register(struct drm_device *dev, @@ -323,19 +330,24 @@ static void drm_mode_object_register(struct drm_device *dev, } /** - * drm_mode_object_put - free a modeset identifer + * drm_mode_object_unregister - free a modeset identifer * @dev: DRM device * @object: object to free * - * Free @id from @dev's unique identifier pool. Note that despite the _get - * postfix modeset identifiers are _not_ reference counted. Hence don't use this + * Free @id from @dev's unique identifier pool. + * This function can be called multiple times, and guards against + * multiple removals. + * These modeset identifiers are _not_ reference counted. Hence don't use this * for reference counted modeset objects like framebuffers. */ -void drm_mode_object_put(struct drm_device *dev, +void drm_mode_object_unregister(struct drm_device *dev, struct drm_mode_object *object) { mutex_lock(&dev->mode_config.idr_mutex); - idr_remove(&dev->mode_config.crtc_idr, object->id); + if (object->id) { + idr_remove(&dev->mode_config.crtc_idr, object->id); + object->id = 0; + } mutex_unlock(&dev->mode_config.idr_mutex); } @@ -350,11 +362,11 @@ static struct drm_mode_object *_object_find(struct drm_device *dev, obj = NULL; if (obj && obj->id != id) obj = NULL; - /* don't leak out unref'd fb's */ - if (obj && - (obj->type == DRM_MODE_OBJECT_FB || - obj->type == DRM_MODE_OBJECT_BLOB)) - obj = NULL; + + if (obj && obj->free_cb) { + if (!kref_get_unless_zero(&obj->refcount)) + obj = NULL; + } mutex_unlock(&dev->mode_config.idr_mutex); return obj; @@ -366,24 +378,69 @@ static struct drm_mode_object *_object_find(struct drm_device *dev, * @id: id of the mode object * @type: type of the mode object * - * Note that framebuffers cannot be looked up with this functions - since those - * are reference counted, they need special treatment. Even with - * DRM_MODE_OBJECT_ANY (although that will simply return NULL - * rather than WARN_ON()). + * This function is used to look up a modeset object. It will acquire a + * reference for reference counted objects. This reference must be dropped again + * by callind drm_mode_object_unreference(). */ struct drm_mode_object *drm_mode_object_find(struct drm_device *dev, uint32_t id, uint32_t type) { struct drm_mode_object *obj = NULL; - /* Framebuffers are reference counted and need their own lookup - * function.*/ - WARN_ON(type == DRM_MODE_OBJECT_FB || type == DRM_MODE_OBJECT_BLOB); obj = _object_find(dev, id, type); return obj; } EXPORT_SYMBOL(drm_mode_object_find); +/** + * drm_mode_object_unreference - decr the object refcnt + * @obj: mode_object + * + * This functions decrements the object's refcount if it is a refcounted modeset + * object. It is a no-op on any other object. This is used to drop references + * acquired with drm_mode_object_reference(). + */ +void drm_mode_object_unreference(struct drm_mode_object *obj) +{ + if (obj->free_cb) { + DRM_DEBUG("OBJ ID: %d (%d)\n", obj->id, atomic_read(&obj->refcount.refcount)); + kref_put(&obj->refcount, obj->free_cb); + } +} +EXPORT_SYMBOL(drm_mode_object_unreference); + +/** + * drm_mode_object_reference - incr the object refcnt + * @obj: mode_object + * + * This functions increments the object's refcount if it is a refcounted modeset + * object. It is a no-op on any other object. References should be dropped again + * by calling drm_mode_object_unreference(). + */ +void drm_mode_object_reference(struct drm_mode_object *obj) +{ + if (obj->free_cb) { + DRM_DEBUG("OBJ ID: %d (%d)\n", obj->id, atomic_read(&obj->refcount.refcount)); + kref_get(&obj->refcount); + } +} +EXPORT_SYMBOL(drm_mode_object_reference); + +static void drm_framebuffer_free(struct kref *kref) +{ + struct drm_framebuffer *fb = + container_of(kref, struct drm_framebuffer, base.refcount); + struct drm_device *dev = fb->dev; + + /* + * The lookup idr holds a weak reference, which has not necessarily been + * removed at this point. Check for that. + */ + drm_mode_object_unregister(dev, &fb->base); + + fb->funcs->destroy(fb); +} + /** * drm_framebuffer_init - initialize a framebuffer * @dev: DRM device @@ -407,71 +464,26 @@ int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb, { int ret; - mutex_lock(&dev->mode_config.fb_lock); - kref_init(&fb->refcount); INIT_LIST_HEAD(&fb->filp_head); fb->dev = dev; fb->funcs = funcs; - ret = drm_mode_object_get(dev, &fb->base, DRM_MODE_OBJECT_FB); + ret = drm_mode_object_get_reg(dev, &fb->base, DRM_MODE_OBJECT_FB, + false, drm_framebuffer_free); if (ret) goto out; + mutex_lock(&dev->mode_config.fb_lock); dev->mode_config.num_fb++; list_add(&fb->head, &dev->mode_config.fb_list); -out: mutex_unlock(&dev->mode_config.fb_lock); + drm_mode_object_register(dev, &fb->base); +out: return ret; } EXPORT_SYMBOL(drm_framebuffer_init); -/* dev->mode_config.fb_lock must be held! */ -static void __drm_framebuffer_unregister(struct drm_device *dev, - struct drm_framebuffer *fb) -{ - drm_mode_object_put(dev, &fb->base); - - fb->base.id = 0; -} - -static void drm_framebuffer_free(struct kref *kref) -{ - struct drm_framebuffer *fb = - container_of(kref, struct drm_framebuffer, refcount); - struct drm_device *dev = fb->dev; - - /* - * The lookup idr holds a weak reference, which has not necessarily been - * removed at this point. Check for that. - */ - mutex_lock(&dev->mode_config.fb_lock); - if (fb->base.id) { - /* Mark fb as reaped and drop idr ref. */ - __drm_framebuffer_unregister(dev, fb); - } - mutex_unlock(&dev->mode_config.fb_lock); - - fb->funcs->destroy(fb); -} - -static struct drm_framebuffer *__drm_framebuffer_lookup(struct drm_device *dev, - uint32_t id) -{ - struct drm_mode_object *obj = NULL; - struct drm_framebuffer *fb; - - mutex_lock(&dev->mode_config.idr_mutex); - obj = idr_find(&dev->mode_config.crtc_idr, id); - if (!obj || (obj->type != DRM_MODE_OBJECT_FB) || (obj->id != id)) - fb = NULL; - else - fb = obj_to_fb(obj); - mutex_unlock(&dev->mode_config.idr_mutex); - - return fb; -} - /** * drm_framebuffer_lookup - look up a drm framebuffer and grab a reference * @dev: drm device @@ -484,46 +496,16 @@ static struct drm_framebuffer *__drm_framebuffer_lookup(struct drm_device *dev, struct drm_framebuffer *drm_framebuffer_lookup(struct drm_device *dev, uint32_t id) { - struct drm_framebuffer *fb; - - mutex_lock(&dev->mode_config.fb_lock); - fb = __drm_framebuffer_lookup(dev, id); - if (fb) { - if (!kref_get_unless_zero(&fb->refcount)) - fb = NULL; - } - mutex_unlock(&dev->mode_config.fb_lock); + struct drm_mode_object *obj; + struct drm_framebuffer *fb = NULL; + obj = _object_find(dev, id, DRM_MODE_OBJECT_FB); + if (obj) + fb = obj_to_fb(obj); return fb; } EXPORT_SYMBOL(drm_framebuffer_lookup); -/** - * drm_framebuffer_unreference - unref a framebuffer - * @fb: framebuffer to unref - * - * This functions decrements the fb's refcount and frees it if it drops to zero. - */ -void drm_framebuffer_unreference(struct drm_framebuffer *fb) -{ - DRM_DEBUG("%p: FB ID: %d (%d)\n", fb, fb->base.id, atomic_read(&fb->refcount.refcount)); - kref_put(&fb->refcount, drm_framebuffer_free); -} -EXPORT_SYMBOL(drm_framebuffer_unreference); - -/** - * drm_framebuffer_reference - incr the fb refcnt - * @fb: framebuffer - * - * This functions increments the fb's refcount. - */ -void drm_framebuffer_reference(struct drm_framebuffer *fb) -{ - DRM_DEBUG("%p: FB ID: %d (%d)\n", fb, fb->base.id, atomic_read(&fb->refcount.refcount)); - kref_get(&fb->refcount); -} -EXPORT_SYMBOL(drm_framebuffer_reference); - /** * drm_framebuffer_unregister_private - unregister a private fb from the lookup idr * @fb: fb to unregister @@ -542,10 +524,8 @@ void drm_framebuffer_unregister_private(struct drm_framebuffer *fb) dev = fb->dev; - mutex_lock(&dev->mode_config.fb_lock); /* Mark fb as reaped and drop idr ref. */ - __drm_framebuffer_unregister(dev, fb); - mutex_unlock(&dev->mode_config.fb_lock); + drm_mode_object_unregister(dev, &fb->base); } EXPORT_SYMBOL(drm_framebuffer_unregister_private); @@ -619,7 +599,7 @@ void drm_framebuffer_remove(struct drm_framebuffer *fb) * in-use fb with fb-id == 0. Userspace is allowed to shoot its own foot * in this manner. */ - if (atomic_read(&fb->refcount.refcount) > 1) { + if (drm_framebuffer_read_refcount(fb) > 1) { drm_modeset_lock_all(dev); /* remove from any CRTC */ drm_for_each_crtc(crtc, dev) { @@ -705,7 +685,7 @@ int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, drm_num_crtcs(dev)); } if (!crtc->name) { - drm_mode_object_put(dev, &crtc->base); + drm_mode_object_unregister(dev, &crtc->base); return -ENOMEM; } @@ -747,7 +727,7 @@ void drm_crtc_cleanup(struct drm_crtc *crtc) drm_modeset_lock_fini(&crtc->mutex); - drm_mode_object_put(dev, &crtc->base); + drm_mode_object_unregister(dev, &crtc->base); list_del(&crtc->head); dev->mode_config.num_crtc--; @@ -884,6 +864,16 @@ static void drm_connector_get_cmdline_mode(struct drm_connector *connector) mode->interlace ? " interlaced" : ""); } +static void drm_connector_free(struct kref *kref) +{ + struct drm_connector *connector = + container_of(kref, struct drm_connector, base.refcount); + struct drm_device *dev = connector->dev; + + drm_mode_object_unregister(dev, &connector->base); + connector->funcs->destroy(connector); +} + /** * drm_connector_init - Init a preallocated connector * @dev: DRM device @@ -909,7 +899,9 @@ int drm_connector_init(struct drm_device *dev, drm_modeset_lock_all(dev); - ret = drm_mode_object_get_reg(dev, &connector->base, DRM_MODE_OBJECT_CONNECTOR, false); + ret = drm_mode_object_get_reg(dev, &connector->base, + DRM_MODE_OBJECT_CONNECTOR, + false, drm_connector_free); if (ret) goto out_unlock; @@ -972,7 +964,7 @@ out_put_id: ida_remove(&config->connector_ida, connector->connector_id); out_put: if (ret) - drm_mode_object_put(dev, &connector->base); + drm_mode_object_unregister(dev, &connector->base); out_unlock: drm_modeset_unlock_all(dev); @@ -1010,7 +1002,7 @@ void drm_connector_cleanup(struct drm_connector *connector) connector->connector_id); kfree(connector->display_info.bus_formats); - drm_mode_object_put(dev, &connector->base); + drm_mode_object_unregister(dev, &connector->base); kfree(connector->name); connector->name = NULL; list_del(&connector->head); @@ -1038,8 +1030,6 @@ int drm_connector_register(struct drm_connector *connector) { int ret; - drm_mode_object_register(connector->dev, &connector->base); - ret = drm_sysfs_connector_add(connector); if (ret) return ret; @@ -1050,6 +1040,8 @@ int drm_connector_register(struct drm_connector *connector) return ret; } + drm_mode_object_register(connector->dev, &connector->base); + return 0; } EXPORT_SYMBOL(drm_connector_register); @@ -1067,25 +1059,65 @@ void drm_connector_unregister(struct drm_connector *connector) } EXPORT_SYMBOL(drm_connector_unregister); - /** - * drm_connector_unplug_all - unregister connector userspace interfaces + * drm_connector_register_all - register all connectors * @dev: drm device * - * This function unregisters all connector userspace interfaces in sysfs. Should - * be call when the device is disconnected, e.g. from an usb driver's - * ->disconnect callback. + * This function registers all connectors in sysfs and other places so that + * userspace can start to access them. Drivers can call it after calling + * drm_dev_register() to complete the device registration, if they don't call + * drm_connector_register() on each connector individually. + * + * When a device is unplugged and should be removed from userspace access, + * call drm_connector_unregister_all(), which is the inverse of this + * function. + * + * Returns: + * Zero on success, error code on failure. */ -void drm_connector_unplug_all(struct drm_device *dev) +int drm_connector_register_all(struct drm_device *dev) +{ + struct drm_connector *connector; + int ret; + + mutex_lock(&dev->mode_config.mutex); + + drm_for_each_connector(connector, dev) { + ret = drm_connector_register(connector); + if (ret) + goto err; + } + + mutex_unlock(&dev->mode_config.mutex); + + return 0; + +err: + mutex_unlock(&dev->mode_config.mutex); + drm_connector_unregister_all(dev); + return ret; +} +EXPORT_SYMBOL(drm_connector_register_all); + +/** + * drm_connector_unregister_all - unregister connector userspace interfaces + * @dev: drm device + * + * This functions unregisters all connectors from sysfs and other places so + * that userspace can no longer access them. Drivers should call this as the + * first step tearing down the device instace, or when the underlying + * physical device disappeared (e.g. USB unplug), right before calling + * drm_dev_unregister(). + */ +void drm_connector_unregister_all(struct drm_device *dev) { struct drm_connector *connector; /* FIXME: taking the mode config mutex ends up in a clash with sysfs */ list_for_each_entry(connector, &dev->mode_config.connector_list, head) drm_connector_unregister(connector); - } -EXPORT_SYMBOL(drm_connector_unplug_all); +EXPORT_SYMBOL(drm_connector_unregister_all); /** * drm_encoder_init - Init a preallocated encoder @@ -1138,7 +1170,7 @@ int drm_encoder_init(struct drm_device *dev, out_put: if (ret) - drm_mode_object_put(dev, &encoder->base); + drm_mode_object_unregister(dev, &encoder->base); out_unlock: drm_modeset_unlock_all(dev); @@ -1181,7 +1213,7 @@ void drm_encoder_cleanup(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; drm_modeset_lock_all(dev); - drm_mode_object_put(dev, &encoder->base); + drm_mode_object_unregister(dev, &encoder->base); kfree(encoder->name); list_del(&encoder->head); dev->mode_config.num_encoder--; @@ -1242,7 +1274,7 @@ int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane, GFP_KERNEL); if (!plane->format_types) { DRM_DEBUG_KMS("out of memory when allocating plane\n"); - drm_mode_object_put(dev, &plane->base); + drm_mode_object_unregister(dev, &plane->base); return -ENOMEM; } @@ -1258,7 +1290,7 @@ int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane, } if (!plane->name) { kfree(plane->format_types); - drm_mode_object_put(dev, &plane->base); + drm_mode_object_unregister(dev, &plane->base); return -ENOMEM; } @@ -1338,7 +1370,7 @@ void drm_plane_cleanup(struct drm_plane *plane) drm_modeset_lock_all(dev); kfree(plane->format_types); - drm_mode_object_put(dev, &plane->base); + drm_mode_object_unregister(dev, &plane->base); BUG_ON(list_empty(&plane->head)); @@ -1918,8 +1950,6 @@ int drm_mode_getresources(struct drm_device *dev, void *data, copied = 0; crtc_id = (uint32_t __user *)(unsigned long)card_res->crtc_id_ptr; drm_for_each_crtc(crtc, dev) { - DRM_DEBUG_KMS("[CRTC:%d:%s]\n", - crtc->base.id, crtc->name); if (put_user(crtc->base.id, crtc_id + copied)) { ret = -EFAULT; goto out; @@ -1934,8 +1964,6 @@ int drm_mode_getresources(struct drm_device *dev, void *data, copied = 0; encoder_id = (uint32_t __user *)(unsigned long)card_res->encoder_id_ptr; drm_for_each_encoder(encoder, dev) { - DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", encoder->base.id, - encoder->name); if (put_user(encoder->base.id, encoder_id + copied)) { ret = -EFAULT; @@ -1951,9 +1979,6 @@ int drm_mode_getresources(struct drm_device *dev, void *data, copied = 0; connector_id = (uint32_t __user *)(unsigned long)card_res->connector_id_ptr; drm_for_each_connector(connector, dev) { - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", - connector->base.id, - connector->name); if (put_user(connector->base.id, connector_id + copied)) { ret = -EFAULT; @@ -1964,9 +1989,6 @@ int drm_mode_getresources(struct drm_device *dev, void *data, } card_res->count_connectors = connector_count; - DRM_DEBUG_KMS("CRTC[%d] CONNECTORS[%d] ENCODERS[%d]\n", card_res->count_crtcs, - card_res->count_connectors, card_res->count_encoders); - out: mutex_unlock(&dev->mode_config.mutex); return ret; @@ -2125,11 +2147,9 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo)); - DRM_DEBUG_KMS("[CONNECTOR:%d:?]\n", out_resp->connector_id); - mutex_lock(&dev->mode_config.mutex); - connector = drm_connector_find(dev, out_resp->connector_id); + connector = drm_connector_lookup(dev, out_resp->connector_id); if (!connector) { ret = -ENOENT; goto out_unlock; @@ -2213,6 +2233,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, out: drm_modeset_unlock(&dev->mode_config.connection_mutex); + drm_connector_unreference(connector); out_unlock: mutex_unlock(&dev->mode_config.mutex); @@ -2857,13 +2878,14 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, } for (i = 0; i < crtc_req->count_connectors; i++) { + connector_set[i] = NULL; set_connectors_ptr = (uint32_t __user *)(unsigned long)crtc_req->set_connectors_ptr; if (get_user(out_id, &set_connectors_ptr[i])) { ret = -EFAULT; goto out; } - connector = drm_connector_find(dev, out_id); + connector = drm_connector_lookup(dev, out_id); if (!connector) { DRM_DEBUG_KMS("Connector id %d unknown\n", out_id); @@ -2891,6 +2913,12 @@ out: if (fb) drm_framebuffer_unreference(fb); + if (connector_set) { + for (i = 0; i < crtc_req->count_connectors; i++) { + if (connector_set[i]) + drm_connector_unreference(connector_set[i]); + } + } kfree(connector_set); drm_mode_destroy(dev, mode); drm_modeset_unlock_all(dev); @@ -3423,17 +3451,35 @@ int drm_mode_addfb2(struct drm_device *dev, if (IS_ERR(fb)) return PTR_ERR(fb); - /* Transfer ownership to the filp for reaping on close */ - DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id); - mutex_lock(&file_priv->fbs_lock); r->fb_id = fb->base.id; + + /* Transfer ownership to the filp for reaping on close */ + mutex_lock(&file_priv->fbs_lock); list_add(&fb->filp_head, &file_priv->fbs); mutex_unlock(&file_priv->fbs_lock); return 0; } +struct drm_mode_rmfb_work { + struct work_struct work; + struct list_head fbs; +}; + +static void drm_mode_rmfb_work_fn(struct work_struct *w) +{ + struct drm_mode_rmfb_work *arg = container_of(w, typeof(*arg), work); + + while (!list_empty(&arg->fbs)) { + struct drm_framebuffer *fb = + list_first_entry(&arg->fbs, typeof(*fb), filp_head); + + list_del_init(&fb->filp_head); + drm_framebuffer_remove(fb); + } +} + /** * drm_mode_rmfb - remove an FB from the configuration * @dev: drm device for the ioctl @@ -3458,30 +3504,49 @@ int drm_mode_rmfb(struct drm_device *dev, if (!drm_core_check_feature(dev, DRIVER_MODESET)) return -EINVAL; - mutex_lock(&file_priv->fbs_lock); - mutex_lock(&dev->mode_config.fb_lock); - fb = __drm_framebuffer_lookup(dev, *id); + fb = drm_framebuffer_lookup(dev, *id); if (!fb) - goto fail_lookup; + return -ENOENT; + mutex_lock(&file_priv->fbs_lock); list_for_each_entry(fbl, &file_priv->fbs, filp_head) if (fb == fbl) found = 1; - if (!found) - goto fail_lookup; + if (!found) { + mutex_unlock(&file_priv->fbs_lock); + goto fail_unref; + } list_del_init(&fb->filp_head); - mutex_unlock(&dev->mode_config.fb_lock); mutex_unlock(&file_priv->fbs_lock); + /* drop the reference we picked up in framebuffer lookup */ drm_framebuffer_unreference(fb); + /* + * we now own the reference that was stored in the fbs list + * + * drm_framebuffer_remove may fail with -EINTR on pending signals, + * so run this in a separate stack as there's no way to correctly + * handle this after the fb is already removed from the lookup table. + */ + if (drm_framebuffer_read_refcount(fb) > 1) { + struct drm_mode_rmfb_work arg; + + INIT_WORK_ONSTACK(&arg.work, drm_mode_rmfb_work_fn); + INIT_LIST_HEAD(&arg.fbs); + list_add_tail(&fb->filp_head, &arg.fbs); + + schedule_work(&arg.work); + flush_work(&arg.work); + destroy_work_on_stack(&arg.work); + } else + drm_framebuffer_unreference(fb); + return 0; -fail_lookup: - mutex_unlock(&dev->mode_config.fb_lock); - mutex_unlock(&file_priv->fbs_lock); - +fail_unref: + drm_framebuffer_unreference(fb); return -ENOENT; } @@ -3627,7 +3692,6 @@ out_err1: return ret; } - /** * drm_fb_release - remove and free the FBs on this file * @priv: drm file for the ioctl @@ -3642,6 +3706,9 @@ out_err1: void drm_fb_release(struct drm_file *priv) { struct drm_framebuffer *fb, *tfb; + struct drm_mode_rmfb_work arg; + + INIT_LIST_HEAD(&arg.fbs); /* * When the file gets released that means no one else can access the fb @@ -3654,10 +3721,22 @@ void drm_fb_release(struct drm_file *priv) * at it any more. */ list_for_each_entry_safe(fb, tfb, &priv->fbs, filp_head) { - list_del_init(&fb->filp_head); + if (drm_framebuffer_read_refcount(fb) > 1) { + list_move_tail(&fb->filp_head, &arg.fbs); + } else { + list_del_init(&fb->filp_head); - /* This drops the fpriv->fbs reference. */ - drm_framebuffer_unreference(fb); + /* This drops the fpriv->fbs reference. */ + drm_framebuffer_unreference(fb); + } + } + + if (!list_empty(&arg.fbs)) { + INIT_WORK_ONSTACK(&arg.work, drm_mode_rmfb_work_fn); + + schedule_work(&arg.work); + flush_work(&arg.work); + destroy_work_on_stack(&arg.work); } } @@ -4029,7 +4108,7 @@ void drm_property_destroy(struct drm_device *dev, struct drm_property *property) if (property->num_values) kfree(property->values); - drm_mode_object_put(dev, &property->base); + drm_mode_object_unregister(dev, &property->base); list_del(&property->head); kfree(property); } @@ -4234,6 +4313,20 @@ done: return ret; } +static void drm_property_free_blob(struct kref *kref) +{ + struct drm_property_blob *blob = + container_of(kref, struct drm_property_blob, base.refcount); + + mutex_lock(&blob->dev->mode_config.blob_lock); + list_del(&blob->head_global); + mutex_unlock(&blob->dev->mode_config.blob_lock); + + drm_mode_object_unregister(blob->dev, &blob->base); + + kfree(blob); +} + /** * drm_property_create_blob - Create new blob property * @@ -4271,47 +4364,22 @@ drm_property_create_blob(struct drm_device *dev, size_t length, if (data) memcpy(blob->data, data, length); - mutex_lock(&dev->mode_config.blob_lock); - - ret = drm_mode_object_get(dev, &blob->base, DRM_MODE_OBJECT_BLOB); + ret = drm_mode_object_get_reg(dev, &blob->base, DRM_MODE_OBJECT_BLOB, + true, drm_property_free_blob); if (ret) { kfree(blob); - mutex_unlock(&dev->mode_config.blob_lock); return ERR_PTR(-EINVAL); } - kref_init(&blob->refcount); - + mutex_lock(&dev->mode_config.blob_lock); list_add_tail(&blob->head_global, &dev->mode_config.property_blob_list); - mutex_unlock(&dev->mode_config.blob_lock); return blob; } EXPORT_SYMBOL(drm_property_create_blob); -/** - * drm_property_free_blob - Blob property destructor - * - * Internal free function for blob properties; must not be used directly. - * - * @kref: Reference - */ -static void drm_property_free_blob(struct kref *kref) -{ - struct drm_property_blob *blob = - container_of(kref, struct drm_property_blob, refcount); - - WARN_ON(!mutex_is_locked(&blob->dev->mode_config.blob_lock)); - - list_del(&blob->head_global); - list_del(&blob->head_file); - drm_mode_object_put(blob->dev, &blob->base); - - kfree(blob); -} - /** * drm_property_unreference_blob - Unreference a blob property * @@ -4321,41 +4389,13 @@ static void drm_property_free_blob(struct kref *kref) */ void drm_property_unreference_blob(struct drm_property_blob *blob) { - struct drm_device *dev; - if (!blob) return; - dev = blob->dev; - - DRM_DEBUG("%p: blob ID: %d (%d)\n", blob, blob->base.id, atomic_read(&blob->refcount.refcount)); - - if (kref_put_mutex(&blob->refcount, drm_property_free_blob, - &dev->mode_config.blob_lock)) - mutex_unlock(&dev->mode_config.blob_lock); - else - might_lock(&dev->mode_config.blob_lock); + drm_mode_object_unreference(&blob->base); } EXPORT_SYMBOL(drm_property_unreference_blob); -/** - * drm_property_unreference_blob_locked - Unreference a blob property with blob_lock held - * - * Drop a reference on a blob property. May free the object. This must be - * called with blob_lock held. - * - * @blob: Pointer to blob property - */ -static void drm_property_unreference_blob_locked(struct drm_property_blob *blob) -{ - if (!blob) - return; - - DRM_DEBUG("%p: blob ID: %d (%d)\n", blob, blob->base.id, atomic_read(&blob->refcount.refcount)); - - kref_put(&blob->refcount, drm_property_free_blob); -} - /** * drm_property_destroy_user_blobs - destroy all blobs created by this client * @dev: DRM device @@ -4366,14 +4406,14 @@ void drm_property_destroy_user_blobs(struct drm_device *dev, { struct drm_property_blob *blob, *bt; - mutex_lock(&dev->mode_config.blob_lock); - + /* + * When the file gets released that means no one else can access the + * blob list any more, so no need to grab dev->blob_lock. + */ list_for_each_entry_safe(blob, bt, &file_priv->blobs, head_file) { list_del_init(&blob->head_file); - drm_property_unreference_blob_locked(blob); + drm_property_unreference_blob(blob); } - - mutex_unlock(&dev->mode_config.blob_lock); } /** @@ -4385,35 +4425,11 @@ void drm_property_destroy_user_blobs(struct drm_device *dev, */ struct drm_property_blob *drm_property_reference_blob(struct drm_property_blob *blob) { - DRM_DEBUG("%p: blob ID: %d (%d)\n", blob, blob->base.id, atomic_read(&blob->refcount.refcount)); - kref_get(&blob->refcount); + drm_mode_object_reference(&blob->base); return blob; } EXPORT_SYMBOL(drm_property_reference_blob); -/* - * Like drm_property_lookup_blob, but does not return an additional reference. - * Must be called with blob_lock held. - */ -static struct drm_property_blob *__drm_property_lookup_blob(struct drm_device *dev, - uint32_t id) -{ - struct drm_mode_object *obj = NULL; - struct drm_property_blob *blob; - - WARN_ON(!mutex_is_locked(&dev->mode_config.blob_lock)); - - mutex_lock(&dev->mode_config.idr_mutex); - obj = idr_find(&dev->mode_config.crtc_idr, id); - if (!obj || (obj->type != DRM_MODE_OBJECT_BLOB) || (obj->id != id)) - blob = NULL; - else - blob = obj_to_blob(obj); - mutex_unlock(&dev->mode_config.idr_mutex); - - return blob; -} - /** * drm_property_lookup_blob - look up a blob property and take a reference * @dev: drm device @@ -4426,16 +4442,12 @@ static struct drm_property_blob *__drm_property_lookup_blob(struct drm_device *d struct drm_property_blob *drm_property_lookup_blob(struct drm_device *dev, uint32_t id) { - struct drm_property_blob *blob; - - mutex_lock(&dev->mode_config.blob_lock); - blob = __drm_property_lookup_blob(dev, id); - if (blob) { - if (!kref_get_unless_zero(&blob->refcount)) - blob = NULL; - } - mutex_unlock(&dev->mode_config.blob_lock); + struct drm_mode_object *obj; + struct drm_property_blob *blob = NULL; + obj = _object_find(dev, id, DRM_MODE_OBJECT_BLOB); + if (obj) + blob = obj_to_blob(obj); return blob; } EXPORT_SYMBOL(drm_property_lookup_blob); @@ -4540,26 +4552,21 @@ int drm_mode_getblob_ioctl(struct drm_device *dev, if (!drm_core_check_feature(dev, DRIVER_MODESET)) return -EINVAL; - drm_modeset_lock_all(dev); - mutex_lock(&dev->mode_config.blob_lock); - blob = __drm_property_lookup_blob(dev, out_resp->blob_id); - if (!blob) { - ret = -ENOENT; - goto done; - } + blob = drm_property_lookup_blob(dev, out_resp->blob_id); + if (!blob) + return -ENOENT; if (out_resp->length == blob->length) { blob_ptr = (void __user *)(unsigned long)out_resp->data; if (copy_to_user(blob_ptr, blob->data, blob->length)) { ret = -EFAULT; - goto done; + goto unref; } } out_resp->length = blob->length; +unref: + drm_property_unreference_blob(blob); -done: - mutex_unlock(&dev->mode_config.blob_lock); - drm_modeset_unlock_all(dev); return ret; } @@ -4638,13 +4645,11 @@ int drm_mode_destroyblob_ioctl(struct drm_device *dev, if (!drm_core_check_feature(dev, DRIVER_MODESET)) return -EINVAL; - mutex_lock(&dev->mode_config.blob_lock); - blob = __drm_property_lookup_blob(dev, out_resp->blob_id); - if (!blob) { - ret = -ENOENT; - goto err; - } + blob = drm_property_lookup_blob(dev, out_resp->blob_id); + if (!blob) + return -ENOENT; + mutex_lock(&dev->mode_config.blob_lock); /* Ensure the property was actually created by this user. */ list_for_each_entry(bt, &file_priv->blobs, head_file) { if (bt == blob) { @@ -4661,13 +4666,18 @@ int drm_mode_destroyblob_ioctl(struct drm_device *dev, /* We must drop head_file here, because we may not be the last * reference on the blob. */ list_del_init(&blob->head_file); - drm_property_unreference_blob_locked(blob); mutex_unlock(&dev->mode_config.blob_lock); + /* One reference from lookup, and one from the filp. */ + drm_property_unreference_blob(blob); + drm_property_unreference_blob(blob); + return 0; err: mutex_unlock(&dev->mode_config.blob_lock); + drm_property_unreference_blob(blob); + return ret; } @@ -4831,19 +4841,7 @@ bool drm_property_change_valid_get(struct drm_property *property, if (value == 0) return true; - /* handle refcnt'd objects specially: */ - if (property->values[0] == DRM_MODE_OBJECT_FB) { - struct drm_framebuffer *fb; - fb = drm_framebuffer_lookup(property->dev, value); - if (fb) { - *ref = &fb->base; - return true; - } else { - return false; - } - } else { - return _object_find(property->dev, value, property->values[0]) != NULL; - } + return _object_find(property->dev, value, property->values[0]) != NULL; } for (i = 0; i < property->num_values; i++) @@ -4859,8 +4857,7 @@ void drm_property_change_valid_put(struct drm_property *property, return; if (drm_property_type_is(property, DRM_MODE_PROP_OBJECT)) { - if (property->values[0] == DRM_MODE_OBJECT_FB) - drm_framebuffer_unreference(obj_to_fb(ref)); + drm_mode_object_unreference(ref); } else if (drm_property_type_is(property, DRM_MODE_PROP_BLOB)) drm_property_unreference_blob(obj_to_blob(ref)); } @@ -4991,7 +4988,7 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data, } if (!obj->properties) { ret = -EINVAL; - goto out; + goto out_unref; } ret = get_properties(obj, file_priv->atomic, @@ -4999,6 +4996,8 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data, (uint64_t __user *)(unsigned long)(arg->prop_values_ptr), &arg->count_props); +out_unref: + drm_mode_object_unreference(obj); out: drm_modeset_unlock_all(dev); return ret; @@ -5041,25 +5040,25 @@ int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data, goto out; } if (!arg_obj->properties) - goto out; + goto out_unref; for (i = 0; i < arg_obj->properties->count; i++) if (arg_obj->properties->properties[i]->base.id == arg->prop_id) break; if (i == arg_obj->properties->count) - goto out; + goto out_unref; prop_obj = drm_mode_object_find(dev, arg->prop_id, DRM_MODE_OBJECT_PROPERTY); if (!prop_obj) { ret = -ENOENT; - goto out; + goto out_unref; } property = obj_to_property(prop_obj); if (!drm_property_change_valid_get(property, arg->value, &ref)) - goto out; + goto out_unref; switch (arg_obj->type) { case DRM_MODE_OBJECT_CONNECTOR: @@ -5077,6 +5076,8 @@ int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data, drm_property_change_valid_put(property, ref); +out_unref: + drm_mode_object_unreference(arg_obj); out: drm_modeset_unlock_all(dev); return ret; @@ -5914,6 +5915,15 @@ void drm_mode_config_cleanup(struct drm_device *dev) drm_property_destroy(dev, property); } + list_for_each_entry_safe(plane, plt, &dev->mode_config.plane_list, + head) { + plane->funcs->destroy(plane); + } + + list_for_each_entry_safe(crtc, ct, &dev->mode_config.crtc_list, head) { + crtc->funcs->destroy(crtc); + } + list_for_each_entry_safe(blob, bt, &dev->mode_config.property_blob_list, head_global) { drm_property_unreference_blob(blob); @@ -5929,16 +5939,7 @@ void drm_mode_config_cleanup(struct drm_device *dev) */ WARN_ON(!list_empty(&dev->mode_config.fb_list)); list_for_each_entry_safe(fb, fbt, &dev->mode_config.fb_list, head) { - drm_framebuffer_free(&fb->refcount); - } - - list_for_each_entry_safe(plane, plt, &dev->mode_config.plane_list, - head) { - plane->funcs->destroy(plane); - } - - list_for_each_entry_safe(crtc, ct, &dev->mode_config.crtc_list, head) { - crtc->funcs->destroy(crtc); + drm_framebuffer_free(&fb->base.refcount); } ida_destroy(&dev->mode_config.connector_ida); diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 79555d2b1b87..a6e42433ef0e 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -170,11 +170,14 @@ drm_encoder_disable(struct drm_encoder *encoder) { const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; + if (!encoder_funcs) + return; + drm_bridge_disable(encoder->bridge); if (encoder_funcs->disable) (*encoder_funcs->disable)(encoder); - else + else if (encoder_funcs->dpms) (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); drm_bridge_post_disable(encoder->bridge); @@ -248,6 +251,9 @@ drm_crtc_prepare_encoders(struct drm_device *dev) drm_for_each_encoder(encoder, dev) { encoder_funcs = encoder->helper_private; + if (!encoder_funcs) + continue; + /* Disable unused encoders */ if (encoder->crtc == NULL) drm_encoder_disable(encoder); @@ -326,6 +332,10 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, if (encoder->crtc != crtc) continue; + encoder_funcs = encoder->helper_private; + if (!encoder_funcs) + continue; + ret = drm_bridge_mode_fixup(encoder->bridge, mode, adjusted_mode); if (!ret) { @@ -360,11 +370,15 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, if (encoder->crtc != crtc) continue; + encoder_funcs = encoder->helper_private; + if (!encoder_funcs) + continue; + drm_bridge_disable(encoder->bridge); - encoder_funcs = encoder->helper_private; /* Disable the encoders as the first thing we do. */ - encoder_funcs->prepare(encoder); + if (encoder_funcs->prepare) + encoder_funcs->prepare(encoder); drm_bridge_post_disable(encoder->bridge); } @@ -385,11 +399,15 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, if (encoder->crtc != crtc) continue; + encoder_funcs = encoder->helper_private; + if (!encoder_funcs) + continue; + DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", encoder->base.id, encoder->name, mode->base.id, mode->name); - encoder_funcs = encoder->helper_private; - encoder_funcs->mode_set(encoder, mode, adjusted_mode); + if (encoder_funcs->mode_set) + encoder_funcs->mode_set(encoder, mode, adjusted_mode); drm_bridge_mode_set(encoder->bridge, mode, adjusted_mode); } @@ -402,10 +420,14 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, if (encoder->crtc != crtc) continue; + encoder_funcs = encoder->helper_private; + if (!encoder_funcs) + continue; + drm_bridge_pre_enable(encoder->bridge); - encoder_funcs = encoder->helper_private; - encoder_funcs->commit(encoder); + if (encoder_funcs->commit) + encoder_funcs->commit(encoder); drm_bridge_enable(encoder->bridge); } @@ -456,6 +478,9 @@ drm_crtc_helper_disable(struct drm_crtc *crtc) * between them is henceforth no longer available. */ connector->dpms = DRM_MODE_DPMS_OFF; + + /* we keep a reference while the encoder is bound */ + drm_connector_unreference(connector); } } @@ -606,6 +631,11 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) mode_changed = true; } + /* take a reference on all connectors in set */ + for (ro = 0; ro < set->num_connectors; ro++) { + drm_connector_reference(set->connectors[ro]); + } + /* a) traverse passed in connector list and get encoders for them */ count = 0; drm_for_each_connector(connector, dev) { @@ -724,6 +754,12 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) } } + /* after fail drop reference on all connectors in save set */ + count = 0; + drm_for_each_connector(connector, dev) { + drm_connector_unreference(&save_connectors[count++]); + } + kfree(save_connectors); kfree(save_encoders); return 0; @@ -740,6 +776,11 @@ fail: *connector = save_connectors[count++]; } + /* after fail drop reference on all connectors in set */ + for (ro = 0; ro < set->num_connectors; ro++) { + drm_connector_unreference(set->connectors[ro]); + } + /* Try to restore the config */ if (mode_changed && !drm_crtc_helper_set_mode(save_set.crtc, save_set.mode, save_set.x, @@ -771,12 +812,15 @@ static void drm_helper_encoder_dpms(struct drm_encoder *encoder, int mode) struct drm_bridge *bridge = encoder->bridge; const struct drm_encoder_helper_funcs *encoder_funcs; + encoder_funcs = encoder->helper_private; + if (!encoder_funcs) + return; + if (mode == DRM_MODE_DPMS_ON) drm_bridge_pre_enable(bridge); else drm_bridge_disable(bridge); - encoder_funcs = encoder->helper_private; if (encoder_funcs->dpms) encoder_funcs->dpms(encoder, mode); @@ -1053,10 +1097,12 @@ int drm_helper_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, if (plane->funcs->atomic_duplicate_state) plane_state = plane->funcs->atomic_duplicate_state(plane); - else if (plane->state) + else { + if (!plane->state) + drm_atomic_helper_plane_reset(plane); + plane_state = drm_atomic_helper_plane_duplicate_state(plane); - else - plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL); + } if (!plane_state) return -ENOMEM; plane_state->plane = plane; diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index 247dc8b62564..a78c138282ea 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -33,8 +33,8 @@ int drm_mode_object_get(struct drm_device *dev, struct drm_mode_object *obj, uint32_t obj_type); -void drm_mode_object_put(struct drm_device *dev, - struct drm_mode_object *object); +void drm_mode_object_unregister(struct drm_device *dev, + struct drm_mode_object *object); /* drm_atomic.c */ int drm_atomic_get_property(struct drm_mode_object *obj, diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c index f73b38b33a8e..3334baacf43d 100644 --- a/drivers/gpu/drm/drm_dp_aux_dev.c +++ b/drivers/gpu/drm/drm_dp_aux_dev.c @@ -159,6 +159,12 @@ static ssize_t auxdev_read(struct file *file, char __user *buf, size_t count, uint8_t localbuf[DP_AUX_MAX_PAYLOAD_BYTES]; ssize_t todo = min_t(size_t, bytes_pending, sizeof(localbuf)); + if (signal_pending(current)) { + res = num_bytes_processed ? + num_bytes_processed : -ERESTARTSYS; + goto out; + } + res = drm_dp_dpcd_read(aux_dev->aux, *offset, localbuf, todo); if (res <= 0) { res = num_bytes_processed ? num_bytes_processed : res; @@ -202,6 +208,12 @@ static ssize_t auxdev_write(struct file *file, const char __user *buf, uint8_t localbuf[DP_AUX_MAX_PAYLOAD_BYTES]; ssize_t todo = min_t(size_t, bytes_pending, sizeof(localbuf)); + if (signal_pending(current)) { + res = num_bytes_processed ? + num_bytes_processed : -ERESTARTSYS; + goto out; + } + if (__copy_from_user(localbuf, buf + num_bytes_processed, todo)) { res = num_bytes_processed ? diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index df64ed1c0139..eeaf5a7c3aa7 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -178,8 +178,8 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, unsigned int offset, void *buffer, size_t size) { struct drm_dp_aux_msg msg; - unsigned int retry; - int err = 0; + unsigned int retry, native_reply; + int err = 0, ret = 0; memset(&msg, 0, sizeof(msg)); msg.address = offset; @@ -196,38 +196,39 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, * sufficient, bump to 32 which makes Dell 4k monitors happier. */ for (retry = 0; retry < 32; retry++) { - - err = aux->transfer(aux, &msg); - if (err < 0) { - if (err == -EBUSY) - continue; - - goto unlock; + if (ret != 0 && ret != -ETIMEDOUT) { + usleep_range(AUX_RETRY_INTERVAL, + AUX_RETRY_INTERVAL + 100); } + ret = aux->transfer(aux, &msg); - switch (msg.reply & DP_AUX_NATIVE_REPLY_MASK) { - case DP_AUX_NATIVE_REPLY_ACK: - if (err < size) - err = -EPROTO; - goto unlock; + if (ret > 0) { + native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; + if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { + if (ret == size) + goto unlock; - case DP_AUX_NATIVE_REPLY_NACK: - err = -EIO; - goto unlock; - - case DP_AUX_NATIVE_REPLY_DEFER: - usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); - break; + ret = -EPROTO; + } else + ret = -EIO; } + + /* + * We want the error we return to be the error we received on + * the first transaction, since we may get a different error the + * next time we retry + */ + if (!err) + err = ret; } DRM_DEBUG_KMS("too many retries, giving up\n"); - err = -EIO; + ret = err; unlock: mutex_unlock(&aux->hw_mutex); - return err; + return ret; } /** @@ -247,6 +248,25 @@ unlock: ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, void *buffer, size_t size) { + int ret; + + /* + * HP ZR24w corrupts the first DPCD access after entering power save + * mode. Eg. on a read, the entire buffer will be filled with the same + * byte. Do a throw away read to avoid corrupting anything we care + * about. Afterwards things will work correctly until the monitor + * gets woken up and subsequently re-enters power save mode. + * + * The user pressing any button on the monitor is enough to wake it + * up, so there is no particularly good place to do the workaround. + * We just have to do it before any DPCD access and hope that the + * monitor doesn't power down exactly after the throw away read. + */ + ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer, + 1); + if (ret != 1) + return ret; + return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer, size); } diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 71ea0521ea96..a13edf5de2d6 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -2756,7 +2756,7 @@ static void drm_dp_mst_dump_mstb(struct seq_file *m, seq_printf(m, "%smst: %p, %d\n", prefix, mstb, mstb->num_ports); list_for_each_entry(port, &mstb->ports, next) { - seq_printf(m, "%sport: %d: ddps: %d ldps: %d, sdp: %d/%d, %p, conn: %p\n", prefix, port->port_num, port->ddps, port->ldps, port->num_sdp_streams, port->num_sdp_stream_sinks, port, port->connector); + seq_printf(m, "%sport: %d: input: %d: pdt: %d, ddps: %d ldps: %d, sdp: %d/%d, %p, conn: %p\n", prefix, port->port_num, port->input, port->pdt, port->ddps, port->ldps, port->num_sdp_streams, port->num_sdp_stream_sinks, port, port->connector); if (port->mstb) drm_dp_mst_dump_mstb(m, port->mstb); } @@ -2777,6 +2777,16 @@ static bool dump_dp_payload_table(struct drm_dp_mst_topology_mgr *mgr, return false; } +static void fetch_monitor_name(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, char *name, + int namelen) +{ + struct edid *mst_edid; + + mst_edid = drm_dp_mst_get_edid(port->connector, mgr, port); + drm_edid_get_monitor_name(mst_edid, name, namelen); +} + /** * drm_dp_mst_dump_topology(): dump topology to seq file. * @m: seq_file to dump output to @@ -2789,6 +2799,7 @@ void drm_dp_mst_dump_topology(struct seq_file *m, { int i; struct drm_dp_mst_port *port; + mutex_lock(&mgr->lock); if (mgr->mst_primary) drm_dp_mst_dump_mstb(m, mgr->mst_primary); @@ -2797,14 +2808,21 @@ void drm_dp_mst_dump_topology(struct seq_file *m, mutex_unlock(&mgr->lock); mutex_lock(&mgr->payload_lock); - seq_printf(m, "vcpi: %lx %lx\n", mgr->payload_mask, mgr->vcpi_mask); + seq_printf(m, "vcpi: %lx %lx %d\n", mgr->payload_mask, mgr->vcpi_mask, + mgr->max_payloads); for (i = 0; i < mgr->max_payloads; i++) { if (mgr->proposed_vcpis[i]) { + char name[14]; + port = container_of(mgr->proposed_vcpis[i], struct drm_dp_mst_port, vcpi); - seq_printf(m, "vcpi %d: %d %d %d\n", i, port->port_num, port->vcpi.vcpi, port->vcpi.num_slots); + fetch_monitor_name(mgr, port, name, sizeof(name)); + seq_printf(m, "vcpi %d: %d %d %d sink name: %s\n", i, + port->port_num, port->vcpi.vcpi, + port->vcpi.num_slots, + (*name != 0) ? name : "Unknown"); } else - seq_printf(m, "vcpi %d:unsed\n", i); + seq_printf(m, "vcpi %d:unused\n", i); } for (i = 0; i < mgr->max_payloads; i++) { seq_printf(m, "payload %d: %d, %d, %d\n", @@ -2844,8 +2862,9 @@ void drm_dp_mst_dump_topology(struct seq_file *m, for (i = 0; i < 0x3; i++) seq_printf(m, "%02x", buf[i]); seq_printf(m, " devid: "); - for (i = 0x3; i < 0x8; i++) + for (i = 0x3; i < 0x8 && buf[i]; i++) seq_printf(m, "%c", buf[i]); + seq_printf(m, " revision: hw: %x.%x sw: %x.%x", buf[0x9] >> 4, buf[0x9] & 0xf, buf[0xa], buf[0xb]); seq_printf(m, "\n"); bret = dump_dp_payload_table(mgr, buf); diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 167c8d3d4a31..bff89226a344 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -37,13 +37,23 @@ #include "drm_legacy.h" #include "drm_internal.h" -unsigned int drm_debug = 0; /* bitmask of DRM_UT_x */ +/* + * drm_debug: Enable debug output. + * Bitmask of DRM_UT_x. See include/drm/drmP.h for details. + */ +unsigned int drm_debug = 0; EXPORT_SYMBOL(drm_debug); MODULE_AUTHOR(CORE_AUTHOR); MODULE_DESCRIPTION(CORE_DESC); MODULE_LICENSE("GPL and additional rights"); -MODULE_PARM_DESC(debug, "Enable debug output"); +MODULE_PARM_DESC(debug, "Enable debug output, where each bit enables a debug category.\n" +"\t\tBit 0 (0x01) will enable CORE messages (drm core code)\n" +"\t\tBit 1 (0x02) will enable DRIVER messages (drm controller code)\n" +"\t\tBit 2 (0x04) will enable KMS messages (modesetting code)\n" +"\t\tBit 3 (0x08) will enable PRIME messages (prime code)\n" +"\t\tBit 4 (0x10) will enable ATOMIC messages (atomic code)\n" +"\t\tBit 5 (0x20) will enable VBL messages (vblank code)"); module_param_named(debug, drm_debug, int, 0600); static DEFINE_SPINLOCK(drm_minor_lock); @@ -111,19 +121,11 @@ static void drm_master_destroy(struct kref *kref) { struct drm_master *master = container_of(kref, struct drm_master, refcount); struct drm_device *dev = master->minor->dev; - struct drm_map_list *r_list, *list_temp; - mutex_lock(&dev->struct_mutex); if (dev->driver->master_destroy) dev->driver->master_destroy(dev, master); - list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) { - if (r_list->master == master) { - drm_legacy_rmmap_locked(dev, r_list->map); - r_list = NULL; - } - } - mutex_unlock(&dev->struct_mutex); + drm_legacy_master_rmmaps(dev, master); idr_destroy(&master->magic_map); kfree(master->unique); @@ -588,6 +590,7 @@ struct drm_device *drm_dev_alloc(struct drm_driver *driver, spin_lock_init(&dev->buf_lock); spin_lock_init(&dev->event_lock); mutex_init(&dev->struct_mutex); + mutex_init(&dev->filelist_mutex); mutex_init(&dev->ctxlist_mutex); mutex_init(&dev->master_mutex); @@ -715,7 +718,11 @@ EXPORT_SYMBOL(drm_dev_unref); * * Register the DRM device @dev with the system, advertise device to user-space * and start normal device operation. @dev must be allocated via drm_dev_alloc() - * previously. + * previously. Right after drm_dev_register() the driver should call + * drm_connector_register_all() to register all connectors in sysfs. This is + * a separate call for backward compatibility with drivers still using + * the deprecated ->load() callback, where connectors are registered from within + * the ->load() callback. * * Never call this twice on any device! * diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 558ef9fc39e6..7df26d4b7ad8 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3293,6 +3293,46 @@ monitor_name(struct detailed_timing *t, void *data) *(u8 **)data = t->data.other_data.data.str.str; } +static int get_monitor_name(struct edid *edid, char name[13]) +{ + char *edid_name = NULL; + int mnl; + + if (!edid || !name) + return 0; + + drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); + for (mnl = 0; edid_name && mnl < 13; mnl++) { + if (edid_name[mnl] == 0x0a) + break; + + name[mnl] = edid_name[mnl]; + } + + return mnl; +} + +/** + * drm_edid_get_monitor_name - fetch the monitor name from the edid + * @edid: monitor EDID information + * @name: pointer to a character array to hold the name of the monitor + * @bufsize: The size of the name buffer (should be at least 14 chars.) + * + */ +void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) +{ + int name_length; + char buf[13]; + + if (bufsize <= 0) + return; + + name_length = min(get_monitor_name(edid, buf), bufsize - 1); + memcpy(name, buf, name_length); + name[name_length] = '\0'; +} +EXPORT_SYMBOL(drm_edid_get_monitor_name); + /** * drm_edid_to_eld - build ELD from EDID * @connector: connector corresponding to the HDMI/DP sink @@ -3306,7 +3346,6 @@ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) { uint8_t *eld = connector->eld; u8 *cea; - u8 *name; u8 *db; int total_sad_count = 0; int mnl; @@ -3320,14 +3359,8 @@ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) return; } - name = NULL; - drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); - /* max: 13 bytes EDID, 16 bytes ELD */ - for (mnl = 0; name && mnl < 13; mnl++) { - if (name[mnl] == 0x0a) - break; - eld[20 + mnl] = name[mnl]; - } + mnl = get_monitor_name(edid, eld + 20); + eld[4] = (cea[1] << 5) | mnl; DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); @@ -3868,6 +3901,133 @@ static void drm_add_display_info(struct edid *edid, info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; } +static int validate_displayid(u8 *displayid, int length, int idx) +{ + int i; + u8 csum = 0; + struct displayid_hdr *base; + + base = (struct displayid_hdr *)&displayid[idx]; + + DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", + base->rev, base->bytes, base->prod_id, base->ext_count); + + if (base->bytes + 5 > length - idx) + return -EINVAL; + for (i = idx; i <= base->bytes + 5; i++) { + csum += displayid[i]; + } + if (csum) { + DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); + return -EINVAL; + } + return 0; +} + +static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, + struct displayid_detailed_timings_1 *timings) +{ + struct drm_display_mode *mode; + unsigned pixel_clock = (timings->pixel_clock[0] | + (timings->pixel_clock[1] << 8) | + (timings->pixel_clock[2] << 16)); + unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; + unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; + unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; + unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; + unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; + unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; + unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; + unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; + bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; + bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; + mode = drm_mode_create(dev); + if (!mode) + return NULL; + + mode->clock = pixel_clock * 10; + mode->hdisplay = hactive; + mode->hsync_start = mode->hdisplay + hsync; + mode->hsync_end = mode->hsync_start + hsync_width; + mode->htotal = mode->hdisplay + hblank; + + mode->vdisplay = vactive; + mode->vsync_start = mode->vdisplay + vsync; + mode->vsync_end = mode->vsync_start + vsync_width; + mode->vtotal = mode->vdisplay + vblank; + + mode->flags = 0; + mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; + mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; + mode->type = DRM_MODE_TYPE_DRIVER; + + if (timings->flags & 0x80) + mode->type |= DRM_MODE_TYPE_PREFERRED; + mode->vrefresh = drm_mode_vrefresh(mode); + drm_mode_set_name(mode); + + return mode; +} + +static int add_displayid_detailed_1_modes(struct drm_connector *connector, + struct displayid_block *block) +{ + struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; + int i; + int num_timings; + struct drm_display_mode *newmode; + int num_modes = 0; + /* blocks must be multiple of 20 bytes length */ + if (block->num_bytes % 20) + return 0; + + num_timings = block->num_bytes / 20; + for (i = 0; i < num_timings; i++) { + struct displayid_detailed_timings_1 *timings = &det->timings[i]; + + newmode = drm_mode_displayid_detailed(connector->dev, timings); + if (!newmode) + continue; + + drm_mode_probed_add(connector, newmode); + num_modes++; + } + return num_modes; +} + +static int add_displayid_detailed_modes(struct drm_connector *connector, + struct edid *edid) +{ + u8 *displayid; + int ret; + int idx = 1; + int length = EDID_LENGTH; + struct displayid_block *block; + int num_modes = 0; + + displayid = drm_find_displayid_extension(edid); + if (!displayid) + return 0; + + ret = validate_displayid(displayid, length, idx); + if (ret) + return 0; + + idx += sizeof(struct displayid_hdr); + while (block = (struct displayid_block *)&displayid[idx], + idx + sizeof(struct displayid_block) <= length && + idx + sizeof(struct displayid_block) + block->num_bytes <= length && + block->num_bytes > 0) { + idx += block->num_bytes + sizeof(struct displayid_block); + switch (block->tag) { + case DATA_BLOCK_TYPE_1_DETAILED_TIMING: + num_modes += add_displayid_detailed_1_modes(connector, block); + break; + } + } + return num_modes; +} + /** * drm_add_edid_modes - add modes from EDID data, if available * @connector: connector we're probing @@ -3913,6 +4073,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) num_modes += add_established_modes(connector, edid); num_modes += add_cea_modes(connector, edid); num_modes += add_alternate_cea_modes(connector, edid); + num_modes += add_displayid_detailed_modes(connector, edid); if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) num_modes += add_inferred_modes(connector, edid); @@ -4119,96 +4280,98 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, } EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); +static int drm_parse_tiled_block(struct drm_connector *connector, + struct displayid_block *block) +{ + struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; + u16 w, h; + u8 tile_v_loc, tile_h_loc; + u8 num_v_tile, num_h_tile; + struct drm_tile_group *tg; + + w = tile->tile_size[0] | tile->tile_size[1] << 8; + h = tile->tile_size[2] | tile->tile_size[3] << 8; + + num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); + num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); + tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); + tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); + + connector->has_tile = true; + if (tile->tile_cap & 0x80) + connector->tile_is_single_monitor = true; + + connector->num_h_tile = num_h_tile + 1; + connector->num_v_tile = num_v_tile + 1; + connector->tile_h_loc = tile_h_loc; + connector->tile_v_loc = tile_v_loc; + connector->tile_h_size = w + 1; + connector->tile_v_size = h + 1; + + DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); + DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); + DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", + num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); + DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); + + tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); + if (!tg) { + tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); + } + if (!tg) + return -ENOMEM; + + if (connector->tile_group != tg) { + /* if we haven't got a pointer, + take the reference, drop ref to old tile group */ + if (connector->tile_group) { + drm_mode_put_tile_group(connector->dev, connector->tile_group); + } + connector->tile_group = tg; + } else + /* if same tile group, then release the ref we just took. */ + drm_mode_put_tile_group(connector->dev, tg); + return 0; +} + static int drm_parse_display_id(struct drm_connector *connector, u8 *displayid, int length, bool is_edid_extension) { /* if this is an EDID extension the first byte will be 0x70 */ int idx = 0; - struct displayid_hdr *base; struct displayid_block *block; - u8 csum = 0; - int i; + int ret; if (is_edid_extension) idx = 1; - base = (struct displayid_hdr *)&displayid[idx]; + ret = validate_displayid(displayid, length, idx); + if (ret) + return ret; - DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", - base->rev, base->bytes, base->prod_id, base->ext_count); + idx += sizeof(struct displayid_hdr); + while (block = (struct displayid_block *)&displayid[idx], + idx + sizeof(struct displayid_block) <= length && + idx + sizeof(struct displayid_block) + block->num_bytes <= length && + block->num_bytes > 0) { + idx += block->num_bytes + sizeof(struct displayid_block); + DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", + block->tag, block->rev, block->num_bytes); - if (base->bytes + 5 > length - idx) - return -EINVAL; - - for (i = idx; i <= base->bytes + 5; i++) { - csum += displayid[i]; - } - if (csum) { - DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); - return -EINVAL; - } - - block = (struct displayid_block *)&displayid[idx + 4]; - DRM_DEBUG_KMS("block id %d, rev %d, len %d\n", - block->tag, block->rev, block->num_bytes); - - switch (block->tag) { - case DATA_BLOCK_TILED_DISPLAY: { - struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; - - u16 w, h; - u8 tile_v_loc, tile_h_loc; - u8 num_v_tile, num_h_tile; - struct drm_tile_group *tg; - - w = tile->tile_size[0] | tile->tile_size[1] << 8; - h = tile->tile_size[2] | tile->tile_size[3] << 8; - - num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); - num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); - tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); - tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); - - connector->has_tile = true; - if (tile->tile_cap & 0x80) - connector->tile_is_single_monitor = true; - - connector->num_h_tile = num_h_tile + 1; - connector->num_v_tile = num_v_tile + 1; - connector->tile_h_loc = tile_h_loc; - connector->tile_v_loc = tile_v_loc; - connector->tile_h_size = w + 1; - connector->tile_v_size = h + 1; - - DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); - DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); - DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", - num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); - DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); - - tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); - if (!tg) { - tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); + switch (block->tag) { + case DATA_BLOCK_TILED_DISPLAY: + ret = drm_parse_tiled_block(connector, block); + if (ret) + return ret; + break; + case DATA_BLOCK_TYPE_1_DETAILED_TIMING: + /* handled in mode gathering code. */ + break; + default: + DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); + break; } - if (!tg) - return -ENOMEM; - - if (connector->tile_group != tg) { - /* if we haven't got a pointer, - take the reference, drop ref to old tile group */ - if (connector->tile_group) { - drm_mode_put_tile_group(connector->dev, connector->tile_group); - } - connector->tile_group = tg; - } else - /* if same tile group, then release the ref we just took. */ - drm_mode_put_tile_group(connector->dev, tg); - } - break; - default: - printk("unknown displayid tag %d\n", block->tag); - break; } return 0; } diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c index bb88e3df9257..172cafe11c71 100644 --- a/drivers/gpu/drm/drm_fb_cma_helper.c +++ b/drivers/gpu/drm/drm_fb_cma_helper.c @@ -25,6 +25,8 @@ #include #include +#define DEFAULT_FBDEFIO_DELAY_MS 50 + struct drm_fb_cma { struct drm_framebuffer fb; struct drm_gem_cma_object *obj[4]; @@ -35,6 +37,59 @@ struct drm_fbdev_cma { struct drm_fb_cma *fb; }; +/** + * DOC: framebuffer cma helper functions + * + * Provides helper functions for creating a cma (contiguous memory allocator) + * backed framebuffer. + * + * drm_fb_cma_create() is used in the &drm_mode_config_funcs ->fb_create + * callback function to create a cma backed framebuffer. + * + * An fbdev framebuffer backed by cma is also available by calling + * drm_fbdev_cma_init(). drm_fbdev_cma_fini() tears it down. + * If the &drm_framebuffer_funcs ->dirty callback is set, fb_deferred_io + * will be set up automatically. dirty() is called by + * drm_fb_helper_deferred_io() in process context (struct delayed_work). + * + * Example fbdev deferred io code: + * + * static int driver_fbdev_fb_dirty(struct drm_framebuffer *fb, + * struct drm_file *file_priv, + * unsigned flags, unsigned color, + * struct drm_clip_rect *clips, + * unsigned num_clips) + * { + * struct drm_gem_cma_object *cma = drm_fb_cma_get_gem_obj(fb, 0); + * ... push changes ... + * return 0; + * } + * + * static struct drm_framebuffer_funcs driver_fbdev_fb_funcs = { + * .destroy = drm_fb_cma_destroy, + * .create_handle = drm_fb_cma_create_handle, + * .dirty = driver_fbdev_fb_dirty, + * }; + * + * static int driver_fbdev_create(struct drm_fb_helper *helper, + * struct drm_fb_helper_surface_size *sizes) + * { + * return drm_fbdev_cma_create_with_funcs(helper, sizes, + * &driver_fbdev_fb_funcs); + * } + * + * static const struct drm_fb_helper_funcs driver_fb_helper_funcs = { + * .fb_probe = driver_fbdev_create, + * }; + * + * Initialize: + * fbdev = drm_fbdev_cma_init_with_funcs(dev, 16, + * dev->mode_config.num_crtc, + * dev->mode_config.num_connector, + * &driver_fb_helper_funcs); + * + */ + static inline struct drm_fbdev_cma *to_fbdev_cma(struct drm_fb_helper *helper) { return container_of(helper, struct drm_fbdev_cma, fb_helper); @@ -45,7 +100,7 @@ static inline struct drm_fb_cma *to_fb_cma(struct drm_framebuffer *fb) return container_of(fb, struct drm_fb_cma, fb); } -static void drm_fb_cma_destroy(struct drm_framebuffer *fb) +void drm_fb_cma_destroy(struct drm_framebuffer *fb) { struct drm_fb_cma *fb_cma = to_fb_cma(fb); int i; @@ -58,8 +113,9 @@ static void drm_fb_cma_destroy(struct drm_framebuffer *fb) drm_framebuffer_cleanup(fb); kfree(fb_cma); } +EXPORT_SYMBOL(drm_fb_cma_destroy); -static int drm_fb_cma_create_handle(struct drm_framebuffer *fb, +int drm_fb_cma_create_handle(struct drm_framebuffer *fb, struct drm_file *file_priv, unsigned int *handle) { struct drm_fb_cma *fb_cma = to_fb_cma(fb); @@ -67,6 +123,7 @@ static int drm_fb_cma_create_handle(struct drm_framebuffer *fb, return drm_gem_handle_create(file_priv, &fb_cma->obj[0]->base, handle); } +EXPORT_SYMBOL(drm_fb_cma_create_handle); static struct drm_framebuffer_funcs drm_fb_cma_funcs = { .destroy = drm_fb_cma_destroy, @@ -76,7 +133,7 @@ static struct drm_framebuffer_funcs drm_fb_cma_funcs = { static struct drm_fb_cma *drm_fb_cma_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_cma_object **obj, - unsigned int num_planes) + unsigned int num_planes, const struct drm_framebuffer_funcs *funcs) { struct drm_fb_cma *fb_cma; int ret; @@ -91,7 +148,7 @@ static struct drm_fb_cma *drm_fb_cma_alloc(struct drm_device *dev, for (i = 0; i < num_planes; i++) fb_cma->obj[i] = obj[i]; - ret = drm_framebuffer_init(dev, &fb_cma->fb, &drm_fb_cma_funcs); + ret = drm_framebuffer_init(dev, &fb_cma->fb, funcs); if (ret) { dev_err(dev->dev, "Failed to initialize framebuffer: %d\n", ret); kfree(fb_cma); @@ -102,13 +159,17 @@ static struct drm_fb_cma *drm_fb_cma_alloc(struct drm_device *dev, } /** - * drm_fb_cma_create() - (struct drm_mode_config_funcs *)->fb_create callback function + * drm_fb_cma_create_with_funcs() - helper function for the + * &drm_mode_config_funcs ->fb_create + * callback function * - * If your hardware has special alignment or pitch requirements these should be - * checked before calling this function. + * This can be used to set &drm_framebuffer_funcs for drivers that need the + * dirty() callback. Use drm_fb_cma_create() if you don't need to change + * &drm_framebuffer_funcs. */ -struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev, - struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) +struct drm_framebuffer *drm_fb_cma_create_with_funcs(struct drm_device *dev, + struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd, + const struct drm_framebuffer_funcs *funcs) { struct drm_fb_cma *fb_cma; struct drm_gem_cma_object *objs[4]; @@ -126,7 +187,7 @@ struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev, unsigned int height = mode_cmd->height / (i ? vsub : 1); unsigned int min_size; - obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[i]); + obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[i]); if (!obj) { dev_err(dev->dev, "Failed to lookup GEM object\n"); ret = -ENXIO; @@ -145,7 +206,7 @@ struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev, objs[i] = to_drm_gem_cma_obj(obj); } - fb_cma = drm_fb_cma_alloc(dev, mode_cmd, objs, i); + fb_cma = drm_fb_cma_alloc(dev, mode_cmd, objs, i, funcs); if (IS_ERR(fb_cma)) { ret = PTR_ERR(fb_cma); goto err_gem_object_unreference; @@ -158,6 +219,21 @@ err_gem_object_unreference: drm_gem_object_unreference_unlocked(&objs[i]->base); return ERR_PTR(ret); } +EXPORT_SYMBOL_GPL(drm_fb_cma_create_with_funcs); + +/** + * drm_fb_cma_create() - &drm_mode_config_funcs ->fb_create callback function + * + * If your hardware has special alignment or pitch requirements these should be + * checked before calling this function. Use drm_fb_cma_create_with_funcs() if + * you need to set &drm_framebuffer_funcs ->dirty. + */ +struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev, + struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) +{ + return drm_fb_cma_create_with_funcs(dev, file_priv, mode_cmd, + &drm_fb_cma_funcs); +} EXPORT_SYMBOL_GPL(drm_fb_cma_create); /** @@ -233,8 +309,67 @@ static struct fb_ops drm_fbdev_cma_ops = { .fb_setcmap = drm_fb_helper_setcmap, }; -static int drm_fbdev_cma_create(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes) +static int drm_fbdev_cma_deferred_io_mmap(struct fb_info *info, + struct vm_area_struct *vma) +{ + fb_deferred_io_mmap(info, vma); + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + return 0; +} + +static int drm_fbdev_cma_defio_init(struct fb_info *fbi, + struct drm_gem_cma_object *cma_obj) +{ + struct fb_deferred_io *fbdefio; + struct fb_ops *fbops; + + /* + * Per device structures are needed because: + * fbops: fb_deferred_io_cleanup() clears fbops.fb_mmap + * fbdefio: individual delays + */ + fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL); + fbops = kzalloc(sizeof(*fbops), GFP_KERNEL); + if (!fbdefio || !fbops) { + kfree(fbdefio); + return -ENOMEM; + } + + /* can't be offset from vaddr since dirty() uses cma_obj */ + fbi->screen_buffer = cma_obj->vaddr; + /* fb_deferred_io_fault() needs a physical address */ + fbi->fix.smem_start = page_to_phys(virt_to_page(fbi->screen_buffer)); + + *fbops = *fbi->fbops; + fbi->fbops = fbops; + + fbdefio->delay = msecs_to_jiffies(DEFAULT_FBDEFIO_DELAY_MS); + fbdefio->deferred_io = drm_fb_helper_deferred_io; + fbi->fbdefio = fbdefio; + fb_deferred_io_init(fbi); + fbi->fbops->fb_mmap = drm_fbdev_cma_deferred_io_mmap; + + return 0; +} + +static void drm_fbdev_cma_defio_fini(struct fb_info *fbi) +{ + if (!fbi->fbdefio) + return; + + fb_deferred_io_cleanup(fbi); + kfree(fbi->fbdefio); + kfree(fbi->fbops); +} + +/* + * For use in a (struct drm_fb_helper_funcs *)->fb_probe callback function that + * needs custom struct drm_framebuffer_funcs, like dirty() for deferred_io use. + */ +int drm_fbdev_cma_create_with_funcs(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes, + const struct drm_framebuffer_funcs *funcs) { struct drm_fbdev_cma *fbdev_cma = to_fbdev_cma(helper); struct drm_mode_fb_cmd2 mode_cmd = { 0 }; @@ -270,7 +405,7 @@ static int drm_fbdev_cma_create(struct drm_fb_helper *helper, goto err_gem_free_object; } - fbdev_cma->fb = drm_fb_cma_alloc(dev, &mode_cmd, &obj, 1); + fbdev_cma->fb = drm_fb_cma_alloc(dev, &mode_cmd, &obj, 1, funcs); if (IS_ERR(fbdev_cma->fb)) { dev_err(dev->dev, "Failed to allocate DRM framebuffer.\n"); ret = PTR_ERR(fbdev_cma->fb); @@ -296,31 +431,48 @@ static int drm_fbdev_cma_create(struct drm_fb_helper *helper, fbi->screen_size = size; fbi->fix.smem_len = size; + if (funcs->dirty) { + ret = drm_fbdev_cma_defio_init(fbi, obj); + if (ret) + goto err_cma_destroy; + } + return 0; +err_cma_destroy: + drm_framebuffer_unregister_private(&fbdev_cma->fb->fb); + drm_fb_cma_destroy(&fbdev_cma->fb->fb); err_fb_info_destroy: drm_fb_helper_release_fbi(helper); err_gem_free_object: dev->driver->gem_free_object(&obj->base); return ret; } +EXPORT_SYMBOL(drm_fbdev_cma_create_with_funcs); + +static int drm_fbdev_cma_create(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) +{ + return drm_fbdev_cma_create_with_funcs(helper, sizes, &drm_fb_cma_funcs); +} static const struct drm_fb_helper_funcs drm_fb_cma_helper_funcs = { .fb_probe = drm_fbdev_cma_create, }; /** - * drm_fbdev_cma_init() - Allocate and initializes a drm_fbdev_cma struct + * drm_fbdev_cma_init_with_funcs() - Allocate and initializes a drm_fbdev_cma struct * @dev: DRM device * @preferred_bpp: Preferred bits per pixel for the device * @num_crtc: Number of CRTCs * @max_conn_count: Maximum number of connectors + * @funcs: fb helper functions, in particular fb_probe() * * Returns a newly allocated drm_fbdev_cma struct or a ERR_PTR. */ -struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device *dev, +struct drm_fbdev_cma *drm_fbdev_cma_init_with_funcs(struct drm_device *dev, unsigned int preferred_bpp, unsigned int num_crtc, - unsigned int max_conn_count) + unsigned int max_conn_count, const struct drm_fb_helper_funcs *funcs) { struct drm_fbdev_cma *fbdev_cma; struct drm_fb_helper *helper; @@ -334,7 +486,7 @@ struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device *dev, helper = &fbdev_cma->fb_helper; - drm_fb_helper_prepare(dev, helper, &drm_fb_cma_helper_funcs); + drm_fb_helper_prepare(dev, helper, funcs); ret = drm_fb_helper_init(dev, helper, num_crtc, max_conn_count); if (ret < 0) { @@ -364,6 +516,24 @@ err_free: return ERR_PTR(ret); } +EXPORT_SYMBOL_GPL(drm_fbdev_cma_init_with_funcs); + +/** + * drm_fbdev_cma_init() - Allocate and initializes a drm_fbdev_cma struct + * @dev: DRM device + * @preferred_bpp: Preferred bits per pixel for the device + * @num_crtc: Number of CRTCs + * @max_conn_count: Maximum number of connectors + * + * Returns a newly allocated drm_fbdev_cma struct or a ERR_PTR. + */ +struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device *dev, + unsigned int preferred_bpp, unsigned int num_crtc, + unsigned int max_conn_count) +{ + return drm_fbdev_cma_init_with_funcs(dev, preferred_bpp, num_crtc, + max_conn_count, &drm_fb_cma_helper_funcs); +} EXPORT_SYMBOL_GPL(drm_fbdev_cma_init); /** @@ -373,6 +543,7 @@ EXPORT_SYMBOL_GPL(drm_fbdev_cma_init); void drm_fbdev_cma_fini(struct drm_fbdev_cma *fbdev_cma) { drm_fb_helper_unregister_fbi(&fbdev_cma->fb_helper); + drm_fbdev_cma_defio_fini(fbdev_cma->fb_helper.fbdev); drm_fb_helper_release_fbi(&fbdev_cma->fb_helper); if (fbdev_cma->fb) { diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 855108e6e1bd..7c2eb75db60f 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -84,6 +84,15 @@ static LIST_HEAD(kernel_fb_helper_list); * and set up an initial configuration using the detected hardware, drivers * should call drm_fb_helper_single_add_all_connectors() followed by * drm_fb_helper_initial_config(). + * + * If &drm_framebuffer_funcs ->dirty is set, the + * drm_fb_helper_{cfb,sys}_{write,fillrect,copyarea,imageblit} functions will + * accumulate changes and schedule &drm_fb_helper ->dirty_work to run right + * away. This worker then calls the dirty() function ensuring that it will + * always run in process context since the fb_*() function could be running in + * atomic context. If drm_fb_helper_deferred_io() is used as the deferred_io + * callback it will also schedule dirty_work with the damage collected from the + * mmap page writes. */ /** @@ -153,40 +162,13 @@ int drm_fb_helper_add_one_connector(struct drm_fb_helper *fb_helper, struct drm_ if (!fb_helper_connector) return -ENOMEM; + drm_connector_reference(connector); fb_helper_connector->connector = connector; fb_helper->connector_info[fb_helper->connector_count++] = fb_helper_connector; return 0; } EXPORT_SYMBOL(drm_fb_helper_add_one_connector); -static void remove_from_modeset(struct drm_mode_set *set, - struct drm_connector *connector) -{ - int i, j; - - for (i = 0; i < set->num_connectors; i++) { - if (set->connectors[i] == connector) - break; - } - - if (i == set->num_connectors) - return; - - for (j = i + 1; j < set->num_connectors; j++) { - set->connectors[j - 1] = set->connectors[j]; - } - set->num_connectors--; - - /* - * TODO maybe need to makes sure we set it back to !=NULL somewhere? - */ - if (set->num_connectors == 0) { - set->fb = NULL; - drm_mode_destroy(connector->dev, set->mode); - set->mode = NULL; - } -} - int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper, struct drm_connector *connector) { @@ -206,6 +188,7 @@ int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper, if (i == fb_helper->connector_count) return -EINVAL; fb_helper_connector = fb_helper->connector_info[i]; + drm_connector_unreference(fb_helper_connector->connector); for (j = i + 1; j < fb_helper->connector_count; j++) { fb_helper->connector_info[j - 1] = fb_helper->connector_info[j]; @@ -213,10 +196,6 @@ int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper, fb_helper->connector_count--; kfree(fb_helper_connector); - /* also cleanup dangling references to the connector: */ - for (i = 0; i < fb_helper->crtc_count; i++) - remove_from_modeset(&fb_helper->crtc_info[i].mode_set, connector); - return 0; } EXPORT_SYMBOL(drm_fb_helper_remove_one_connector); @@ -626,8 +605,10 @@ static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper) { int i; - for (i = 0; i < helper->connector_count; i++) + for (i = 0; i < helper->connector_count; i++) { + drm_connector_unreference(helper->connector_info[i]->connector); kfree(helper->connector_info[i]); + } kfree(helper->connector_info); for (i = 0; i < helper->crtc_count; i++) { kfree(helper->crtc_info[i].mode_set.connectors); @@ -637,6 +618,23 @@ static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper) kfree(helper->crtc_info); } +static void drm_fb_helper_dirty_work(struct work_struct *work) +{ + struct drm_fb_helper *helper = container_of(work, struct drm_fb_helper, + dirty_work); + struct drm_clip_rect *clip = &helper->dirty_clip; + struct drm_clip_rect clip_copy; + unsigned long flags; + + spin_lock_irqsave(&helper->dirty_lock, flags); + clip_copy = *clip; + clip->x1 = clip->y1 = ~0; + clip->x2 = clip->y2 = 0; + spin_unlock_irqrestore(&helper->dirty_lock, flags); + + helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, &clip_copy, 1); +} + /** * drm_fb_helper_prepare - setup a drm_fb_helper structure * @dev: DRM device @@ -650,6 +648,9 @@ void drm_fb_helper_prepare(struct drm_device *dev, struct drm_fb_helper *helper, const struct drm_fb_helper_funcs *funcs) { INIT_LIST_HEAD(&helper->kernel_fb_list); + spin_lock_init(&helper->dirty_lock); + INIT_WORK(&helper->dirty_work, drm_fb_helper_dirty_work); + helper->dirty_clip.x1 = helper->dirty_clip.y1 = ~0; helper->funcs = funcs; helper->dev = dev; } @@ -834,6 +835,59 @@ void drm_fb_helper_unlink_fbi(struct drm_fb_helper *fb_helper) } EXPORT_SYMBOL(drm_fb_helper_unlink_fbi); +static void drm_fb_helper_dirty(struct fb_info *info, u32 x, u32 y, + u32 width, u32 height) +{ + struct drm_fb_helper *helper = info->par; + struct drm_clip_rect *clip = &helper->dirty_clip; + unsigned long flags; + + if (!helper->fb->funcs->dirty) + return; + + spin_lock_irqsave(&helper->dirty_lock, flags); + clip->x1 = min_t(u32, clip->x1, x); + clip->y1 = min_t(u32, clip->y1, y); + clip->x2 = max_t(u32, clip->x2, x + width); + clip->y2 = max_t(u32, clip->y2, y + height); + spin_unlock_irqrestore(&helper->dirty_lock, flags); + + schedule_work(&helper->dirty_work); +} + +/** + * drm_fb_helper_deferred_io() - fbdev deferred_io callback function + * @info: fb_info struct pointer + * @pagelist: list of dirty mmap framebuffer pages + * + * This function is used as the &fb_deferred_io ->deferred_io + * callback function for flushing the fbdev mmap writes. + */ +void drm_fb_helper_deferred_io(struct fb_info *info, + struct list_head *pagelist) +{ + unsigned long start, end, min, max; + struct page *page; + u32 y1, y2; + + min = ULONG_MAX; + max = 0; + list_for_each_entry(page, pagelist, lru) { + start = page->index << PAGE_SHIFT; + end = start + PAGE_SIZE - 1; + min = min(min, start); + max = max(max, end); + } + + if (min < max) { + y1 = min / info->fix.line_length; + y2 = min_t(u32, DIV_ROUND_UP(max, info->fix.line_length), + info->var.yres); + drm_fb_helper_dirty(info, 0, y1, info->var.xres, y2 - y1); + } +} +EXPORT_SYMBOL(drm_fb_helper_deferred_io); + /** * drm_fb_helper_sys_read - wrapper around fb_sys_read * @info: fb_info struct pointer @@ -862,7 +916,14 @@ EXPORT_SYMBOL(drm_fb_helper_sys_read); ssize_t drm_fb_helper_sys_write(struct fb_info *info, const char __user *buf, size_t count, loff_t *ppos) { - return fb_sys_write(info, buf, count, ppos); + ssize_t ret; + + ret = fb_sys_write(info, buf, count, ppos); + if (ret > 0) + drm_fb_helper_dirty(info, 0, 0, info->var.xres, + info->var.yres); + + return ret; } EXPORT_SYMBOL(drm_fb_helper_sys_write); @@ -877,6 +938,8 @@ void drm_fb_helper_sys_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { sys_fillrect(info, rect); + drm_fb_helper_dirty(info, rect->dx, rect->dy, + rect->width, rect->height); } EXPORT_SYMBOL(drm_fb_helper_sys_fillrect); @@ -891,6 +954,8 @@ void drm_fb_helper_sys_copyarea(struct fb_info *info, const struct fb_copyarea *area) { sys_copyarea(info, area); + drm_fb_helper_dirty(info, area->dx, area->dy, + area->width, area->height); } EXPORT_SYMBOL(drm_fb_helper_sys_copyarea); @@ -905,6 +970,8 @@ void drm_fb_helper_sys_imageblit(struct fb_info *info, const struct fb_image *image) { sys_imageblit(info, image); + drm_fb_helper_dirty(info, image->dx, image->dy, + image->width, image->height); } EXPORT_SYMBOL(drm_fb_helper_sys_imageblit); @@ -919,6 +986,8 @@ void drm_fb_helper_cfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { cfb_fillrect(info, rect); + drm_fb_helper_dirty(info, rect->dx, rect->dy, + rect->width, rect->height); } EXPORT_SYMBOL(drm_fb_helper_cfb_fillrect); @@ -933,6 +1002,8 @@ void drm_fb_helper_cfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) { cfb_copyarea(info, area); + drm_fb_helper_dirty(info, area->dx, area->dy, + area->width, area->height); } EXPORT_SYMBOL(drm_fb_helper_cfb_copyarea); @@ -947,6 +1018,8 @@ void drm_fb_helper_cfb_imageblit(struct fb_info *info, const struct fb_image *image) { cfb_imageblit(info, image); + drm_fb_helper_dirty(info, image->dx, image->dy, + image->width, image->height); } EXPORT_SYMBOL(drm_fb_helper_cfb_imageblit); @@ -1895,7 +1968,6 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper, int n, int width, int height) { int c, o; - struct drm_device *dev = fb_helper->dev; struct drm_connector *connector; const struct drm_connector_helper_funcs *connector_funcs; struct drm_encoder *encoder; @@ -1914,7 +1986,7 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper, if (modes[n] == NULL) return best_score; - crtcs = kzalloc(dev->mode_config.num_connector * + crtcs = kzalloc(fb_helper->connector_count * sizeof(struct drm_fb_helper_crtc *), GFP_KERNEL); if (!crtcs) return best_score; @@ -1960,7 +2032,7 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper, if (score > best_score) { best_score = score; memcpy(best_crtcs, crtcs, - dev->mode_config.num_connector * + fb_helper->connector_count * sizeof(struct drm_fb_helper_crtc *)); } } @@ -2104,8 +2176,8 @@ out: * cmdline option. * * The other option is to just disable fbdev emulation since very likely the - * first modest from userspace will crash in the same way, and is even easier to - * debug. This can be done by setting the drm_kms_helper.fbdev_emulation=0 + * first modeset from userspace will crash in the same way, and is even easier + * to debug. This can be done by setting the drm_kms_helper.fbdev_emulation=0 * kernel cmdline option. * * RETURNS: @@ -2150,7 +2222,7 @@ EXPORT_SYMBOL(drm_fb_helper_initial_config); * hotplug interrupt). * * Note that drivers may call this even before calling - * drm_fb_helper_initial_config but only aftert drm_fb_helper_init. This allows + * drm_fb_helper_initial_config but only after drm_fb_helper_init. This allows * for a race-free fbcon setup and will make sure that the fbdev emulation will * not miss any hotplug events. * diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c index aeef58ed359b..7af7f8bcb355 100644 --- a/drivers/gpu/drm/drm_fops.c +++ b/drivers/gpu/drm/drm_fops.c @@ -297,9 +297,9 @@ static int drm_open_helper(struct file *filp, struct drm_minor *minor) } mutex_unlock(&dev->master_mutex); - mutex_lock(&dev->struct_mutex); + mutex_lock(&dev->filelist_mutex); list_add(&priv->lhead, &dev->filelist); - mutex_unlock(&dev->struct_mutex); + mutex_unlock(&dev->filelist_mutex); #ifdef __alpha__ /* @@ -381,14 +381,26 @@ static void drm_events_release(struct drm_file *file_priv) */ static void drm_legacy_dev_reinit(struct drm_device *dev) { - if (drm_core_check_feature(dev, DRIVER_MODESET)) - return; + if (dev->irq_enabled) + drm_irq_uninstall(dev); + + mutex_lock(&dev->struct_mutex); + + drm_legacy_agp_clear(dev); + + drm_legacy_sg_cleanup(dev); + drm_legacy_vma_flush(dev); + drm_legacy_dma_takedown(dev); + + mutex_unlock(&dev->struct_mutex); dev->sigdata.lock = NULL; dev->context_flag = 0; dev->last_context = 0; dev->if_version = 0; + + DRM_DEBUG("lastclose completed\n"); } /* @@ -400,7 +412,7 @@ static void drm_legacy_dev_reinit(struct drm_device *dev) * * \sa drm_device */ -int drm_lastclose(struct drm_device * dev) +void drm_lastclose(struct drm_device * dev) { DRM_DEBUG("\n"); @@ -408,23 +420,8 @@ int drm_lastclose(struct drm_device * dev) dev->driver->lastclose(dev); DRM_DEBUG("driver lastclose completed\n"); - if (dev->irq_enabled && !drm_core_check_feature(dev, DRIVER_MODESET)) - drm_irq_uninstall(dev); - - mutex_lock(&dev->struct_mutex); - - drm_agp_clear(dev); - - drm_legacy_sg_cleanup(dev); - drm_legacy_vma_flush(dev); - drm_legacy_dma_takedown(dev); - - mutex_unlock(&dev->struct_mutex); - - drm_legacy_dev_reinit(dev); - - DRM_DEBUG("lastclose completed\n"); - return 0; + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + drm_legacy_dev_reinit(dev); } /** @@ -445,14 +442,16 @@ int drm_release(struct inode *inode, struct file *filp) struct drm_file *file_priv = filp->private_data; struct drm_minor *minor = file_priv->minor; struct drm_device *dev = minor->dev; - int retcode = 0; mutex_lock(&drm_global_mutex); DRM_DEBUG("open_count = %d\n", dev->open_count); - mutex_lock(&dev->struct_mutex); + mutex_lock(&dev->filelist_mutex); list_del(&file_priv->lhead); + mutex_unlock(&dev->filelist_mutex); + + mutex_lock(&dev->struct_mutex); if (file_priv->magic) idr_remove(&file_priv->master->magic_map, file_priv->magic); mutex_unlock(&dev->struct_mutex); @@ -538,7 +537,7 @@ int drm_release(struct inode *inode, struct file *filp) */ if (!--dev->open_count) { - retcode = drm_lastclose(dev); + drm_lastclose(dev); if (drm_device_is_unplugged(dev)) drm_put_dev(dev); } @@ -546,7 +545,7 @@ int drm_release(struct inode *inode, struct file *filp) drm_minor_release(minor); - return retcode; + return 0; } EXPORT_SYMBOL(drm_release); diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index da0c5320789f..32156060b9c9 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -279,7 +279,6 @@ drm_gem_object_release_handle(int id, void *ptr, void *data) int drm_gem_handle_delete(struct drm_file *filp, u32 handle) { - struct drm_device *dev; struct drm_gem_object *obj; /* This is gross. The idr system doesn't let us try a delete and @@ -294,18 +293,19 @@ drm_gem_handle_delete(struct drm_file *filp, u32 handle) spin_lock(&filp->table_lock); /* Check if we currently have a reference on the object */ - obj = idr_find(&filp->object_idr, handle); - if (obj == NULL) { - spin_unlock(&filp->table_lock); + obj = idr_replace(&filp->object_idr, NULL, handle); + spin_unlock(&filp->table_lock); + if (IS_ERR_OR_NULL(obj)) return -EINVAL; - } - dev = obj->dev; - /* Release reference and decrement refcount. */ + /* Release driver's reference and decrement refcount. */ + drm_gem_object_release_handle(handle, obj, filp); + + /* And finally make the handle available for future allocations. */ + spin_lock(&filp->table_lock); idr_remove(&filp->object_idr, handle); spin_unlock(&filp->table_lock); - drm_gem_object_release_handle(handle, obj, filp); return 0; } EXPORT_SYMBOL(drm_gem_handle_delete); @@ -422,6 +422,10 @@ EXPORT_SYMBOL(drm_gem_handle_create); * @obj: obj in question * * This routine frees fake offsets allocated by drm_gem_create_mmap_offset(). + * + * Note that drm_gem_object_release() already calls this function, so drivers + * don't have to take care of releasing the mmap offset themselves when freeing + * the GEM object. */ void drm_gem_free_mmap_offset(struct drm_gem_object *obj) @@ -445,6 +449,9 @@ EXPORT_SYMBOL(drm_gem_free_mmap_offset); * This routine allocates and attaches a fake offset for @obj, in cases where * the virtual size differs from the physical size (ie. obj->size). Otherwise * just use drm_gem_create_mmap_offset(). + * + * This function is idempotent and handles an already allocated mmap offset + * transparently. Drivers do not need to check for this case. */ int drm_gem_create_mmap_offset_size(struct drm_gem_object *obj, size_t size) @@ -466,6 +473,9 @@ EXPORT_SYMBOL(drm_gem_create_mmap_offset_size); * structures. * * This routine allocates and attaches a fake offset for @obj. + * + * Drivers can call drm_gem_free_mmap_offset() before freeing @obj to release + * the fake offset again. */ int drm_gem_create_mmap_offset(struct drm_gem_object *obj) { @@ -578,7 +588,6 @@ EXPORT_SYMBOL(drm_gem_put_pages); /** * drm_gem_object_lookup - look up a GEM object from it's handle - * @dev: DRM device * @filp: DRM file private date * @handle: userspace handle * @@ -588,8 +597,7 @@ EXPORT_SYMBOL(drm_gem_put_pages); * otherwise. */ struct drm_gem_object * -drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, - u32 handle) +drm_gem_object_lookup(struct drm_file *filp, u32 handle) { struct drm_gem_object *obj; @@ -597,12 +605,8 @@ drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, /* Check if we currently have a reference on the object */ obj = idr_find(&filp->object_idr, handle); - if (obj == NULL) { - spin_unlock(&filp->table_lock); - return NULL; - } - - drm_gem_object_reference(obj); + if (obj) + drm_gem_object_reference(obj); spin_unlock(&filp->table_lock); @@ -655,7 +659,7 @@ drm_gem_flink_ioctl(struct drm_device *dev, void *data, if (!drm_core_check_feature(dev, DRIVER_GEM)) return -ENODEV; - obj = drm_gem_object_lookup(dev, file_priv, args->handle); + obj = drm_gem_object_lookup(file_priv, args->handle); if (obj == NULL) return -ENOENT; @@ -759,6 +763,13 @@ drm_gem_release(struct drm_device *dev, struct drm_file *file_private) idr_destroy(&file_private->object_idr); } +/** + * drm_gem_object_release - release GEM buffer object resources + * @obj: GEM buffer object + * + * This releases any structures and resources used by @obj and is the invers of + * drm_gem_object_init(). + */ void drm_gem_object_release(struct drm_gem_object *obj) { @@ -787,13 +798,66 @@ drm_gem_object_free(struct kref *kref) container_of(kref, struct drm_gem_object, refcount); struct drm_device *dev = obj->dev; - WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + if (dev->driver->gem_free_object_unlocked) { + dev->driver->gem_free_object_unlocked(obj); + } else if (dev->driver->gem_free_object) { + WARN_ON(!mutex_is_locked(&dev->struct_mutex)); - if (dev->driver->gem_free_object != NULL) dev->driver->gem_free_object(obj); + } } EXPORT_SYMBOL(drm_gem_object_free); +/** + * drm_gem_object_unreference_unlocked - release a GEM BO reference + * @obj: GEM buffer object + * + * This releases a reference to @obj. Callers must not hold the + * dev->struct_mutex lock when calling this function. + * + * See also __drm_gem_object_unreference(). + */ +void +drm_gem_object_unreference_unlocked(struct drm_gem_object *obj) +{ + struct drm_device *dev; + + if (!obj) + return; + + dev = obj->dev; + might_lock(&dev->struct_mutex); + + if (dev->driver->gem_free_object_unlocked) + kref_put(&obj->refcount, drm_gem_object_free); + else if (kref_put_mutex(&obj->refcount, drm_gem_object_free, + &dev->struct_mutex)) + mutex_unlock(&dev->struct_mutex); +} +EXPORT_SYMBOL(drm_gem_object_unreference_unlocked); + +/** + * drm_gem_object_unreference - release a GEM BO reference + * @obj: GEM buffer object + * + * This releases a reference to @obj. Callers must hold the dev->struct_mutex + * lock when calling this function, even when the driver doesn't use + * dev->struct_mutex for anything. + * + * For drivers not encumbered with legacy locking use + * drm_gem_object_unreference_unlocked() instead. + */ +void +drm_gem_object_unreference(struct drm_gem_object *obj) +{ + if (obj) { + WARN_ON(!mutex_is_locked(&obj->dev->struct_mutex)); + + kref_put(&obj->refcount, drm_gem_object_free); + } +} +EXPORT_SYMBOL(drm_gem_object_unreference); + /** * drm_gem_vm_open - vma->ops->open implementation for GEM * @vma: VM area structure diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c index 1f500a1b9969..e1ab008b3f08 100644 --- a/drivers/gpu/drm/drm_gem_cma_helper.c +++ b/drivers/gpu/drm/drm_gem_cma_helper.c @@ -291,7 +291,7 @@ int drm_gem_cma_dumb_map_offset(struct drm_file *file_priv, { struct drm_gem_object *gem_obj; - gem_obj = drm_gem_object_lookup(drm, file_priv, handle); + gem_obj = drm_gem_object_lookup(file_priv, handle); if (!gem_obj) { dev_err(drm->dev, "failed to lookup GEM object\n"); return -EINVAL; diff --git a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c index cbb4fc0fc969..5d469b2f26f4 100644 --- a/drivers/gpu/drm/drm_info.c +++ b/drivers/gpu/drm/drm_info.c @@ -174,7 +174,7 @@ int drm_clients_info(struct seq_file *m, void *data) /* dev->filelist is sorted youngest first, but we want to present * oldest first (i.e. kernel, servers, clients), so walk backwardss. */ - mutex_lock(&dev->struct_mutex); + mutex_lock(&dev->filelist_mutex); list_for_each_entry_reverse(priv, &dev->filelist, lhead) { struct task_struct *task; @@ -190,7 +190,7 @@ int drm_clients_info(struct seq_file *m, void *data) priv->magic); rcu_read_unlock(); } - mutex_unlock(&dev->struct_mutex); + mutex_unlock(&dev->filelist_mutex); return 0; } diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h index 43cbda3306ac..902cf6a15212 100644 --- a/drivers/gpu/drm/drm_internal.h +++ b/drivers/gpu/drm/drm_internal.h @@ -26,7 +26,7 @@ extern unsigned int drm_timestamp_monotonic; /* drm_fops.c */ extern struct mutex drm_global_mutex; -int drm_lastclose(struct drm_device *dev); +void drm_lastclose(struct drm_device *dev); /* drm_pci.c */ int drm_pci_set_unique(struct drm_device *dev, @@ -37,8 +37,6 @@ int drm_irq_by_busid(struct drm_device *dev, void *data, /* drm_vm.c */ int drm_vma_info(struct seq_file *m, void *data); -void drm_vm_open_locked(struct drm_device *dev, struct vm_area_struct *vma); -void drm_vm_close_locked(struct drm_device *dev, struct vm_area_struct *vma); /* drm_prime.c */ int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 8ce2a0c59116..b7a39771c152 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -149,58 +149,6 @@ static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv) return 0; } -/* - * Get a mapping information. - * - * \param inode device inode. - * \param file_priv DRM file private. - * \param cmd command. - * \param arg user argument, pointing to a drm_map structure. - * - * \return zero on success or a negative number on failure. - * - * Searches for the mapping with the specified offset and copies its information - * into userspace - */ -static int drm_getmap(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_map *map = data; - struct drm_map_list *r_list = NULL; - struct list_head *list; - int idx; - int i; - - idx = map->offset; - if (idx < 0) - return -EINVAL; - - i = 0; - mutex_lock(&dev->struct_mutex); - list_for_each(list, &dev->maplist) { - if (i == idx) { - r_list = list_entry(list, struct drm_map_list, head); - break; - } - i++; - } - if (!r_list || !r_list->map) { - mutex_unlock(&dev->struct_mutex); - return -EINVAL; - } - - map->offset = r_list->map->offset; - map->size = r_list->map->size; - map->type = r_list->map->type; - map->flags = r_list->map->flags; - map->handle = (void *)(unsigned long) r_list->user_token; - map->mtrr = arch_phys_wc_index(r_list->map->mtrr); - - mutex_unlock(&dev->struct_mutex); - - return 0; -} - /* * Get client information. * @@ -558,7 +506,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, 0), DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, 0), DRM_IOCTL_DEF(DRM_IOCTL_IRQ_BUSID, drm_irq_by_busid, DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_legacy_getmap_ioctl, DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_GET_CAP, drm_getcap, DRM_UNLOCKED|DRM_RENDER_ALLOW), diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index 881c5a6c180c..0fac801c18fe 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -348,9 +348,6 @@ static void vblank_disable_fn(unsigned long arg) unsigned int pipe = vblank->pipe; unsigned long irqflags; - if (!dev->vblank_disable_allowed) - return; - spin_lock_irqsave(&dev->vbl_lock, irqflags); if (atomic_read(&vblank->refcount) == 0 && vblank->enabled) { DRM_DEBUG("disabling vblank on crtc %u\n", pipe); @@ -437,8 +434,6 @@ int drm_vblank_init(struct drm_device *dev, unsigned int num_crtcs) "get_vblank_timestamp == NULL\n"); } - dev->vblank_disable_allowed = false; - return 0; err: @@ -863,10 +858,7 @@ int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, /* Subtract time delta from raw timestamp to get final * vblank_time timestamp for end of vblank. */ - if (delta_ns < 0) - etime = ktime_add_ns(etime, -delta_ns); - else - etime = ktime_sub_ns(etime, delta_ns); + etime = ktime_sub_ns(etime, delta_ns); *vblank_time = ktime_to_timeval(etime); DRM_DEBUG_VBL("crtc %u : v 0x%x p(%d,%d)@ %ld.%ld -> %ld.%ld [e %d us, %d rep]\n", @@ -1588,7 +1580,6 @@ void drm_vblank_post_modeset(struct drm_device *dev, unsigned int pipe) if (vblank->inmodeset) { spin_lock_irqsave(&dev->vbl_lock, irqflags); - dev->vblank_disable_allowed = true; drm_reset_vblank_timestamp(dev, pipe); spin_unlock_irqrestore(&dev->vbl_lock, irqflags); diff --git a/drivers/gpu/drm/drm_legacy.h b/drivers/gpu/drm/drm_legacy.h index 9b731786e4db..d3b6ee357a2b 100644 --- a/drivers/gpu/drm/drm_legacy.h +++ b/drivers/gpu/drm/drm_legacy.h @@ -63,6 +63,8 @@ int drm_legacy_getsareactx(struct drm_device *d, void *v, struct drm_file *f); #define DRM_MAP_HASH_OFFSET 0x10000000 +int drm_legacy_getmap_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); int drm_legacy_addmap_ioctl(struct drm_device *d, void *v, struct drm_file *f); int drm_legacy_rmmap_ioctl(struct drm_device *d, void *v, struct drm_file *f); int drm_legacy_addbufs(struct drm_device *d, void *v, struct drm_file *f); diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index f7448a5e95a9..7def3d58da18 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -98,7 +98,7 @@ void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode) if (!mode) return; - drm_mode_object_put(dev, &mode->base); + drm_mode_object_unregister(dev, &mode->base); kfree(mode); } diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c index 2ef988e037b7..3dfe3c886502 100644 --- a/drivers/gpu/drm/drm_panel.c +++ b/drivers/gpu/drm/drm_panel.c @@ -30,12 +30,36 @@ static DEFINE_MUTEX(panel_lock); static LIST_HEAD(panel_list); +/** + * DOC: drm panel + * + * The DRM panel helpers allow drivers to register panel objects with a + * central registry and provide functions to retrieve those panels in display + * drivers. + */ + +/** + * drm_panel_init - initialize a panel + * @panel: DRM panel + * + * Sets up internal fields of the panel so that it can subsequently be added + * to the registry. + */ void drm_panel_init(struct drm_panel *panel) { INIT_LIST_HEAD(&panel->list); } EXPORT_SYMBOL(drm_panel_init); +/** + * drm_panel_add - add a panel to the global registry + * @panel: panel to add + * + * Add a panel to the global registry so that it can be looked up by display + * drivers. + * + * Return: 0 on success or a negative error code on failure. + */ int drm_panel_add(struct drm_panel *panel) { mutex_lock(&panel_lock); @@ -46,6 +70,12 @@ int drm_panel_add(struct drm_panel *panel) } EXPORT_SYMBOL(drm_panel_add); +/** + * drm_panel_remove - remove a panel from the global registry + * @panel: DRM panel + * + * Removes a panel from the global registry. + */ void drm_panel_remove(struct drm_panel *panel) { mutex_lock(&panel_lock); @@ -54,6 +84,18 @@ void drm_panel_remove(struct drm_panel *panel) } EXPORT_SYMBOL(drm_panel_remove); +/** + * drm_panel_attach - attach a panel to a connector + * @panel: DRM panel + * @connector: DRM connector + * + * After obtaining a pointer to a DRM panel a display driver calls this + * function to attach a panel to a connector. + * + * An error is returned if the panel is already attached to another connector. + * + * Return: 0 on success or a negative error code on failure. + */ int drm_panel_attach(struct drm_panel *panel, struct drm_connector *connector) { if (panel->connector) @@ -66,6 +108,15 @@ int drm_panel_attach(struct drm_panel *panel, struct drm_connector *connector) } EXPORT_SYMBOL(drm_panel_attach); +/** + * drm_panel_detach - detach a panel from a connector + * @panel: DRM panel + * + * Detaches a panel from the connector it is attached to. If a panel is not + * attached to any connector this is effectively a no-op. + * + * Return: 0 on success or a negative error code on failure. + */ int drm_panel_detach(struct drm_panel *panel) { panel->connector = NULL; @@ -76,6 +127,16 @@ int drm_panel_detach(struct drm_panel *panel) EXPORT_SYMBOL(drm_panel_detach); #ifdef CONFIG_OF +/** + * of_drm_find_panel - look up a panel using a device tree node + * @np: device tree node of the panel + * + * Searches the set of registered panels for one that matches the given device + * tree node. If a matching panel is found, return a pointer to it. + * + * Return: A pointer to the panel registered for the specified device tree + * node or NULL if no panel matching the device tree node can be found. + */ struct drm_panel *of_drm_find_panel(struct device_node *np) { struct drm_panel *panel; diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c index a1fff1179a97..29d5a548d07a 100644 --- a/drivers/gpu/drm/drm_pci.c +++ b/drivers/gpu/drm/drm_pci.c @@ -250,7 +250,7 @@ void drm_pci_agp_destroy(struct drm_device *dev) { if (dev->agp) { arch_phys_wc_del(dev->agp->agp_mtrr); - drm_agp_clear(dev); + drm_legacy_agp_clear(dev); kfree(dev->agp); dev->agp = NULL; } diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index df6cdc76a16e..aab0f3f1f42d 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -407,7 +407,7 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev, struct dma_buf *dmabuf; mutex_lock(&file_priv->prime.lock); - obj = drm_gem_object_lookup(dev, file_priv, handle); + obj = drm_gem_object_lookup(file_priv, handle); if (!obj) { ret = -ENOENT; goto out_unlock; diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index e714b5a7955f..0329080d7f7c 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -264,10 +264,8 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, count = drm_add_edid_modes(connector, edid); drm_edid_to_eld(connector, edid); } else { -#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE count = drm_load_edid_firmware(connector); if (count == 0) -#endif count = (*connector_funcs->get_modes)(connector); } diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index d503f8e8c2d1..fa7fadce8063 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -208,9 +208,12 @@ static ssize_t status_show(struct device *device, char *buf) { struct drm_connector *connector = to_drm_connector(device); + enum drm_connector_status status; + + status = READ_ONCE(connector->status); return snprintf(buf, PAGE_SIZE, "%s\n", - drm_get_connector_status_name(connector->status)); + drm_get_connector_status_name(status)); } static ssize_t dpms_show(struct device *device, @@ -231,9 +234,11 @@ static ssize_t enabled_show(struct device *device, char *buf) { struct drm_connector *connector = to_drm_connector(device); + bool enabled; - return snprintf(buf, PAGE_SIZE, "%s\n", connector->encoder ? "enabled" : - "disabled"); + enabled = READ_ONCE(connector->encoder); + + return snprintf(buf, PAGE_SIZE, enabled ? "enabled\n" : "disabled\n"); } static ssize_t edid_show(struct file *filp, struct kobject *kobj, @@ -287,102 +292,6 @@ static ssize_t modes_show(struct device *device, return written; } -static ssize_t tv_subconnector_show(struct device *device, - struct device_attribute *attr, - char *buf) -{ - struct drm_connector *connector = to_drm_connector(device); - struct drm_device *dev = connector->dev; - struct drm_property *prop; - uint64_t subconnector; - int ret; - - prop = dev->mode_config.tv_subconnector_property; - if (!prop) { - DRM_ERROR("Unable to find subconnector property\n"); - return 0; - } - - ret = drm_object_property_get_value(&connector->base, prop, &subconnector); - if (ret) - return 0; - - return snprintf(buf, PAGE_SIZE, "%s", - drm_get_tv_subconnector_name((int)subconnector)); -} - -static ssize_t tv_select_subconnector_show(struct device *device, - struct device_attribute *attr, - char *buf) -{ - struct drm_connector *connector = to_drm_connector(device); - struct drm_device *dev = connector->dev; - struct drm_property *prop; - uint64_t subconnector; - int ret; - - prop = dev->mode_config.tv_select_subconnector_property; - if (!prop) { - DRM_ERROR("Unable to find select subconnector property\n"); - return 0; - } - - ret = drm_object_property_get_value(&connector->base, prop, &subconnector); - if (ret) - return 0; - - return snprintf(buf, PAGE_SIZE, "%s", - drm_get_tv_select_name((int)subconnector)); -} - -static ssize_t dvii_subconnector_show(struct device *device, - struct device_attribute *attr, - char *buf) -{ - struct drm_connector *connector = to_drm_connector(device); - struct drm_device *dev = connector->dev; - struct drm_property *prop; - uint64_t subconnector; - int ret; - - prop = dev->mode_config.dvi_i_subconnector_property; - if (!prop) { - DRM_ERROR("Unable to find subconnector property\n"); - return 0; - } - - ret = drm_object_property_get_value(&connector->base, prop, &subconnector); - if (ret) - return 0; - - return snprintf(buf, PAGE_SIZE, "%s", - drm_get_dvi_i_subconnector_name((int)subconnector)); -} - -static ssize_t dvii_select_subconnector_show(struct device *device, - struct device_attribute *attr, - char *buf) -{ - struct drm_connector *connector = to_drm_connector(device); - struct drm_device *dev = connector->dev; - struct drm_property *prop; - uint64_t subconnector; - int ret; - - prop = dev->mode_config.dvi_i_select_subconnector_property; - if (!prop) { - DRM_ERROR("Unable to find select subconnector property\n"); - return 0; - } - - ret = drm_object_property_get_value(&connector->base, prop, &subconnector); - if (ret) - return 0; - - return snprintf(buf, PAGE_SIZE, "%s", - drm_get_dvi_i_select_name((int)subconnector)); -} - static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(enabled); static DEVICE_ATTR_RO(dpms); @@ -396,54 +305,6 @@ static struct attribute *connector_dev_attrs[] = { NULL }; -static DEVICE_ATTR_RO(tv_subconnector); -static DEVICE_ATTR_RO(tv_select_subconnector); - -static struct attribute *connector_tv_dev_attrs[] = { - &dev_attr_tv_subconnector.attr, - &dev_attr_tv_select_subconnector.attr, - NULL -}; - -static DEVICE_ATTR_RO(dvii_subconnector); -static DEVICE_ATTR_RO(dvii_select_subconnector); - -static struct attribute *connector_dvii_dev_attrs[] = { - &dev_attr_dvii_subconnector.attr, - &dev_attr_dvii_select_subconnector.attr, - NULL -}; - -/* Connector type related helpers */ -static int kobj_connector_type(struct kobject *kobj) -{ - struct device *dev = kobj_to_dev(kobj); - struct drm_connector *connector = to_drm_connector(dev); - - return connector->connector_type; -} - -static umode_t connector_is_dvii(struct kobject *kobj, - struct attribute *attr, int idx) -{ - return kobj_connector_type(kobj) == DRM_MODE_CONNECTOR_DVII ? - attr->mode : 0; -} - -static umode_t connector_is_tv(struct kobject *kobj, - struct attribute *attr, int idx) -{ - switch (kobj_connector_type(kobj)) { - case DRM_MODE_CONNECTOR_Composite: - case DRM_MODE_CONNECTOR_SVIDEO: - case DRM_MODE_CONNECTOR_Component: - case DRM_MODE_CONNECTOR_TV: - return attr->mode; - } - - return 0; -} - static struct bin_attribute edid_attr = { .attr.name = "edid", .attr.mode = 0444, @@ -461,20 +322,8 @@ static const struct attribute_group connector_dev_group = { .bin_attrs = connector_bin_attrs, }; -static const struct attribute_group connector_tv_dev_group = { - .attrs = connector_tv_dev_attrs, - .is_visible = connector_is_tv, -}; - -static const struct attribute_group connector_dvii_dev_group = { - .attrs = connector_dvii_dev_attrs, - .is_visible = connector_is_dvii, -}; - static const struct attribute_group *connector_dev_groups[] = { &connector_dev_group, - &connector_tv_dev_group, - &connector_dvii_dev_group, NULL }; diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index f90bd5fe35ba..ac9f4b3ec615 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -395,16 +395,8 @@ static const struct vm_operations_struct drm_vm_sg_ops = { .close = drm_vm_close, }; -/** - * \c open method for shared virtual memory. - * - * \param vma virtual memory area. - * - * Create a new drm_vma_entry structure as the \p vma private data entry and - * add it to drm_device::vmalist. - */ -void drm_vm_open_locked(struct drm_device *dev, - struct vm_area_struct *vma) +static void drm_vm_open_locked(struct drm_device *dev, + struct vm_area_struct *vma) { struct drm_vma_entry *vma_entry; @@ -429,8 +421,8 @@ static void drm_vm_open(struct vm_area_struct *vma) mutex_unlock(&dev->struct_mutex); } -void drm_vm_close_locked(struct drm_device *dev, - struct vm_area_struct *vma) +static void drm_vm_close_locked(struct drm_device *dev, + struct vm_area_struct *vma) { struct drm_vma_entry *pt, *temp; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index e8858985f01e..3d4f56df8359 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -314,7 +314,7 @@ static int etnaviv_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, if (args->op & ~(ETNA_PREP_READ | ETNA_PREP_WRITE | ETNA_PREP_NOSYNC)) return -EINVAL; - obj = drm_gem_object_lookup(dev, file, args->handle); + obj = drm_gem_object_lookup(file, args->handle); if (!obj) return -ENOENT; @@ -335,7 +335,7 @@ static int etnaviv_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, if (args->flags) return -EINVAL; - obj = drm_gem_object_lookup(dev, file, args->handle); + obj = drm_gem_object_lookup(file, args->handle); if (!obj) return -ENOENT; @@ -356,7 +356,7 @@ static int etnaviv_ioctl_gem_info(struct drm_device *dev, void *data, if (args->pad) return -EINVAL; - obj = drm_gem_object_lookup(dev, file, args->handle); + obj = drm_gem_object_lookup(file, args->handle); if (!obj) return -ENOENT; @@ -441,7 +441,7 @@ static int etnaviv_ioctl_gem_wait(struct drm_device *dev, void *data, if (!gpu) return -ENXIO; - obj = drm_gem_object_lookup(dev, file, args->handle); + obj = drm_gem_object_lookup(file, args->handle); if (!obj) return -ENOENT; @@ -497,7 +497,7 @@ static struct drm_driver etnaviv_drm_driver = { .open = etnaviv_open, .preclose = etnaviv_preclose, .set_busid = drm_platform_set_busid, - .gem_free_object = etnaviv_gem_free_object, + .gem_free_object_unlocked = etnaviv_gem_free_object, .gem_vm_ops = &vm_ops, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c index 281c6eca20a8..df9bcbab922f 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c @@ -129,10 +129,9 @@ void etnaviv_gem_put_pages(struct etnaviv_gem_object *etnaviv_obj) /* when we start tracking the pin count, then do something here */ } -static int etnaviv_gem_mmap_obj(struct drm_gem_object *obj, +static int etnaviv_gem_mmap_obj(struct etnaviv_gem_object *etnaviv_obj, struct vm_area_struct *vma) { - struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj); pgprot_t vm_page_prot; vma->vm_flags &= ~VM_PFNMAP; @@ -151,9 +150,9 @@ static int etnaviv_gem_mmap_obj(struct drm_gem_object *obj, * in particular in the case of mmap'd dmabufs) */ fput(vma->vm_file); - get_file(obj->filp); + get_file(etnaviv_obj->base.filp); vma->vm_pgoff = 0; - vma->vm_file = obj->filp; + vma->vm_file = etnaviv_obj->base.filp; vma->vm_page_prot = vm_page_prot; } @@ -173,7 +172,7 @@ int etnaviv_gem_mmap(struct file *filp, struct vm_area_struct *vma) } obj = to_etnaviv_bo(vma->vm_private_data); - return etnaviv_gem_mmap_obj(vma->vm_private_data, vma); + return obj->ops->mmap(obj, vma); } int etnaviv_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) @@ -545,6 +544,7 @@ static const struct etnaviv_gem_ops etnaviv_gem_shmem_ops = { .get_pages = etnaviv_gem_shmem_get_pages, .release = etnaviv_gem_shmem_release, .vmap = etnaviv_gem_vmap_impl, + .mmap = etnaviv_gem_mmap_obj, }; void etnaviv_gem_free_object(struct drm_gem_object *obj) @@ -886,10 +886,17 @@ static void etnaviv_gem_userptr_release(struct etnaviv_gem_object *etnaviv_obj) put_task_struct(etnaviv_obj->userptr.task); } +static int etnaviv_gem_userptr_mmap_obj(struct etnaviv_gem_object *etnaviv_obj, + struct vm_area_struct *vma) +{ + return -EINVAL; +} + static const struct etnaviv_gem_ops etnaviv_gem_userptr_ops = { .get_pages = etnaviv_gem_userptr_get_pages, .release = etnaviv_gem_userptr_release, .vmap = etnaviv_gem_vmap_impl, + .mmap = etnaviv_gem_userptr_mmap_obj, }; int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file, diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.h b/drivers/gpu/drm/etnaviv/etnaviv_gem.h index 02665d8c10ee..e63ff116a3b3 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.h @@ -79,6 +79,7 @@ struct etnaviv_gem_ops { int (*get_pages)(struct etnaviv_gem_object *); void (*release)(struct etnaviv_gem_object *); void *(*vmap)(struct etnaviv_gem_object *); + int (*mmap)(struct etnaviv_gem_object *, struct vm_area_struct *); }; static inline bool is_active(struct etnaviv_gem_object *etnaviv_obj) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c index 4e67395f5fa1..b93618c1aa69 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -84,10 +84,17 @@ static void *etnaviv_gem_prime_vmap_impl(struct etnaviv_gem_object *etnaviv_obj) return dma_buf_vmap(etnaviv_obj->base.import_attach->dmabuf); } +static int etnaviv_gem_prime_mmap_obj(struct etnaviv_gem_object *etnaviv_obj, + struct vm_area_struct *vma) +{ + return dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0); +} + static const struct etnaviv_gem_ops etnaviv_gem_prime_ops = { /* .get_pages should never be called */ .release = etnaviv_gem_prime_release, .vmap = etnaviv_gem_prime_vmap_impl, + .mmap = etnaviv_gem_prime_mmap_obj, }; struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev, diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index d8a9a9c68e98..ff6aa5dfb2d7 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1528,8 +1528,8 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master, INIT_WORK(&gpu->recover_work, recover_worker); init_waitqueue_head(&gpu->fence_event); - setup_timer(&gpu->hangcheck_timer, hangcheck_handler, - (unsigned long)gpu); + setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler, + (unsigned long)gpu); priv->gpu[priv->num_gpus++] = gpu; diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index baddf33fb475..d814b3048ee5 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -71,8 +71,9 @@ config DRM_EXYNOS_DSI This enables support for Exynos MIPI-DSI device. config DRM_EXYNOS_DP - bool "Display Port" + bool "EXYNOS specific extensions for Analogix DP driver" depends on DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON + select DRM_ANALOGIX_DP default DRM_EXYNOS select DRM_PANEL help diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile index 23d2f958739b..f663490e949d 100644 --- a/drivers/gpu/drm/exynos/Makefile +++ b/drivers/gpu/drm/exynos/Makefile @@ -12,7 +12,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON) += exynos5433_drm_decon.o exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o -exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o +exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp.o exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER) += exynos_mixer.o exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI) += exynos_drm_vidi.o diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 5245bc5e82e9..ac21b4000835 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -28,6 +28,10 @@ #define WINDOWS_NR 3 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 +#define IFTYPE_I80 (1 << 0) +#define I80_HW_TRG (1 << 1) +#define IFTYPE_HDMI (1 << 2) + static const char * const decon_clks_name[] = { "pclk", "aclk_decon", @@ -38,12 +42,6 @@ static const char * const decon_clks_name[] = { "sclk_decon_eclk", }; -enum decon_iftype { - IFTYPE_RGB, - IFTYPE_I80, - IFTYPE_HDMI -}; - enum decon_flag_bits { BIT_CLKS_ENABLED, BIT_IRQS_ENABLED, @@ -61,7 +59,7 @@ struct decon_context { struct clk *clks[ARRAY_SIZE(decon_clks_name)]; int pipe; unsigned long flags; - enum decon_iftype out_type; + unsigned long out_type; int first_win; }; @@ -95,7 +93,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc *crtc) if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) { val = VIDINTCON0_INTEN; - if (ctx->out_type == IFTYPE_I80) + if (ctx->out_type & IFTYPE_I80) val |= VIDINTCON0_FRAMEDONE; else val |= VIDINTCON0_INTFRMEN; @@ -119,11 +117,11 @@ static void decon_disable_vblank(struct exynos_drm_crtc *crtc) static void decon_setup_trigger(struct decon_context *ctx) { - u32 val = (ctx->out_type != IFTYPE_HDMI) + u32 val = !(ctx->out_type & I80_HW_TRG) ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | - TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB; + TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN; writel(val, ctx->addr + DECON_TRIGCON); } @@ -136,7 +134,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc) if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; - if (ctx->out_type == IFTYPE_HDMI) { + if (ctx->out_type & IFTYPE_HDMI) { m->crtc_hsync_start = m->crtc_hdisplay + 10; m->crtc_hsync_end = m->crtc_htotal - 92; m->crtc_vsync_start = m->crtc_vdisplay + 1; @@ -149,19 +147,24 @@ static void decon_commit(struct exynos_drm_crtc *crtc) val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F; writel(val, ctx->addr + DECON_CMU); + if (ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)) + decon_setup_trigger(ctx); + /* lcd on and use command if */ val = VIDOUT_LCD_ON; - if (ctx->out_type == IFTYPE_I80) + if (ctx->out_type & IFTYPE_I80) { val |= VIDOUT_COMMAND_IF; - else + } else { val |= VIDOUT_RGB_IF; + } + writel(val, ctx->addr + DECON_VIDOUTCON0); val = VIDTCON2_LINEVAL(m->vdisplay - 1) | VIDTCON2_HOZVAL(m->hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON2); - if (ctx->out_type != IFTYPE_I80) { + if (!(ctx->out_type & IFTYPE_I80)) { val = VIDTCON00_VBPD_F( m->crtc_vtotal - m->crtc_vsync_end - 1) | VIDTCON00_VFPD_F( @@ -183,10 +186,10 @@ static void decon_commit(struct exynos_drm_crtc *crtc) writel(val, ctx->addr + DECON_VIDTCON11); } - decon_setup_trigger(ctx); - /* enable output and display signal */ decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); + + decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, @@ -300,7 +303,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, val = dma_addr + pitch * state->src.h; writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); - if (ctx->out_type != IFTYPE_HDMI) + if (!(ctx->out_type & IFTYPE_HDMI)) val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14) | BIT_VAL(state->crtc.w * bpp, 13, 0); else @@ -312,9 +315,6 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, /* window enable */ decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); - - /* standalone update */ - decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } static void decon_disable_plane(struct exynos_drm_crtc *crtc, @@ -326,15 +326,7 @@ static void decon_disable_plane(struct exynos_drm_crtc *crtc, if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; - decon_shadow_protect_win(ctx, win, true); - - /* window disable */ decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); - - decon_shadow_protect_win(ctx, win, false); - - /* standalone update */ - decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } static void decon_atomic_flush(struct exynos_drm_crtc *crtc) @@ -348,7 +340,10 @@ static void decon_atomic_flush(struct exynos_drm_crtc *crtc) for (i = ctx->first_win; i < WINDOWS_NR; i++) decon_shadow_protect_win(ctx, i, false); - if (ctx->out_type == IFTYPE_I80) + /* standalone update */ + decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); + + if (ctx->out_type & IFTYPE_I80) set_bit(BIT_WIN_UPDATED, &ctx->flags); } @@ -374,7 +369,7 @@ static void decon_swreset(struct decon_context *ctx) WARN(tries == 0, "failed to software reset DECON\n"); - if (ctx->out_type != IFTYPE_HDMI) + if (!(ctx->out_type & IFTYPE_HDMI)) return; writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); @@ -383,7 +378,6 @@ static void decon_swreset(struct decon_context *ctx) writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, ctx->addr + DECON_CRCCTRL); - decon_setup_trigger(ctx); } static void decon_enable(struct exynos_drm_crtc *crtc) @@ -395,8 +389,12 @@ static void decon_enable(struct exynos_drm_crtc *crtc) pm_runtime_get_sync(ctx->dev); + exynos_drm_pipe_clk_enable(crtc, true); + set_bit(BIT_CLKS_ENABLED, &ctx->flags); + decon_swreset(ctx); + /* if vblank was enabled status, enable it again. */ if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) decon_enable_vblank(ctx->crtc); @@ -424,6 +422,8 @@ static void decon_disable(struct exynos_drm_crtc *crtc) clear_bit(BIT_CLKS_ENABLED, &ctx->flags); + exynos_drm_pipe_clk_enable(crtc, false); + pm_runtime_put_sync(ctx->dev); set_bit(BIT_SUSPENDED, &ctx->flags); @@ -433,13 +433,12 @@ static void decon_te_irq_handler(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; - if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) + if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) || + (ctx->out_type & I80_HW_TRG)) return; if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags)) decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); - - drm_crtc_handle_vblank(&ctx->crtc->base); } static void decon_clear_channels(struct exynos_drm_crtc *crtc) @@ -459,8 +458,10 @@ static void decon_clear_channels(struct exynos_drm_crtc *crtc) decon_shadow_protect_win(ctx, win, true); decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); decon_shadow_protect_win(ctx, win, false); - decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } + + decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); + /* TODO: wait for possible vsync */ msleep(50); @@ -509,7 +510,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) } exynos_plane = &ctx->planes[ctx->first_win]; - out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI + out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI : EXYNOS_DISPLAY_TYPE_LCD; ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, ctx->pipe, out_type, @@ -570,6 +571,7 @@ static irqreturn_t decon_irq_handler(int irq, void *dev_id) /* clear */ writel(val, ctx->addr + DECON_VIDINTCON1); + drm_crtc_handle_vblank(&ctx->crtc->base); } out: @@ -617,11 +619,11 @@ static const struct dev_pm_ops exynos5433_decon_pm_ops = { static const struct of_device_id exynos5433_decon_driver_dt_match[] = { { .compatible = "samsung,exynos5433-decon", - .data = (void *)IFTYPE_RGB + .data = (void *)I80_HW_TRG }, { .compatible = "samsung,exynos5433-decon-tv", - .data = (void *)IFTYPE_HDMI + .data = (void *)(I80_HW_TRG | IFTYPE_HDMI) }, {}, }; @@ -629,7 +631,6 @@ MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); static int exynos5433_decon_probe(struct platform_device *pdev) { - const struct of_device_id *of_id; struct device *dev = &pdev->dev; struct decon_context *ctx; struct resource *res; @@ -642,14 +643,13 @@ static int exynos5433_decon_probe(struct platform_device *pdev) __set_bit(BIT_SUSPENDED, &ctx->flags); ctx->dev = dev; + ctx->out_type = (unsigned long)of_device_get_match_data(dev); - of_id = of_match_device(exynos5433_decon_driver_dt_match, &pdev->dev); - ctx->out_type = (enum decon_iftype)of_id->data; - - if (ctx->out_type == IFTYPE_HDMI) + if (ctx->out_type & IFTYPE_HDMI) { ctx->first_win = 1; - else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) - ctx->out_type = IFTYPE_I80; + } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) { + ctx->out_type |= IFTYPE_I80; + } for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { struct clk *clk; @@ -674,7 +674,7 @@ static int exynos5433_decon_probe(struct platform_device *pdev) } res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, - (ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync"); + (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync"); if (!res) { dev_err(dev, "cannot find IRQ resource\n"); return -ENXIO; diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 93361073af9a..f6223f907c15 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -593,7 +593,6 @@ static const struct exynos_drm_crtc_ops decon_crtc_ops = { .commit = decon_commit, .enable_vblank = decon_enable_vblank, .disable_vblank = decon_disable_vblank, - .wait_for_vblank = decon_wait_for_vblank, .atomic_begin = decon_atomic_begin, .update_plane = decon_update_plane, .disable_plane = decon_disable_plane, diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c new file mode 100644 index 000000000000..468498e3fec1 --- /dev/null +++ b/drivers/gpu/drm/exynos/exynos_dp.c @@ -0,0 +1,311 @@ +/* + * Samsung SoC DP (Display Port) interface driver. + * + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include