From b13d2a7b43654c7f52aba9dc04f93cf7055ebc8b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 15 Apr 2014 01:16:44 +0200 Subject: [PATCH 01/15] ARM: dts: rockchip: add cru nodes and update device clocks to use it This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and also updates the device nodes retrieve their clocks from there, instead of the previous gate clock nodes. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz --- arch/arm/boot/dts/rk3066a.dtsi | 28 +++++++++++++++++++--------- arch/arm/boot/dts/rk3188.dtsi | 18 ++++++++++++++---- arch/arm/boot/dts/rk3xxx.dtsi | 16 ++++++++-------- 3 files changed, 41 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4387cfd420ba..15c81d2c2d52 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "rk3xxx.dtsi" #include "rk3066a-clocks.dtsi" @@ -45,7 +46,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x20038000 0x100>; interrupts = ; - clocks = <&clk_gates1 0>, <&clk_gates7 7>; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; clock-names = "timer", "pclk"; }; @@ -53,7 +54,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x2003a000 0x100>; interrupts = ; - clocks = <&clk_gates1 1>, <&clk_gates7 8>; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; clock-names = "timer", "pclk"; }; @@ -61,7 +62,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x2000e000 0x100>; interrupts = ; - clocks = <&clk_gates1 2>, <&clk_gates7 9>; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; clock-names = "timer", "pclk"; }; @@ -78,6 +79,15 @@ }; }; + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; @@ -89,7 +99,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20034000 0x100>; interrupts = ; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -102,7 +112,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -115,7 +125,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -128,7 +138,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; @@ -141,7 +151,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = ; - clocks = <&clk_gates8 13>; + clocks = <&cru PCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; @@ -154,7 +164,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2000a000 0x100>; interrupts = ; - clocks = <&clk_gates8 15>; + clocks = <&cru PCLK_GPIO6>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 238c996d4a7f..bf0741a89b7c 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "rk3xxx.dtsi" #include "rk3188-clocks.dtsi" @@ -74,6 +75,15 @@ }; }; + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; @@ -87,7 +97,7 @@ compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = ; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -100,7 +110,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -113,7 +123,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -126,7 +136,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 2adf1cc9e85d..b47d5fe81187 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -60,14 +60,14 @@ compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; interrupts = ; - clocks = <&dummy150m>; + clocks = <&cru CORE_PERI>; }; local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>; interrupts = ; - clocks = <&dummy150m>; + clocks = <&cru CORE_PERI>; }; uart0: serial@10124000 { @@ -76,7 +76,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 8>; + clocks = <&cru SCLK_UART0>; status = "disabled"; }; @@ -86,7 +86,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 10>; + clocks = <&cru SCLK_UART1>; status = "disabled"; }; @@ -96,7 +96,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 12>; + clocks = <&cru SCLK_UART2>; status = "disabled"; }; @@ -106,7 +106,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 14>; + clocks = <&cru SCLK_UART3>; status = "disabled"; }; @@ -117,7 +117,7 @@ #address-cells = <1>; #size-cells = <0>; - clocks = <&clk_gates5 10>, <&clk_gates2 11>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; status = "disabled"; @@ -130,7 +130,7 @@ #address-cells = <1>; #size-cells = <0>; - clocks = <&clk_gates5 11>, <&clk_gates2 13>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu"; status = "disabled"; From 560106c1ca063e7cbbb527c0df2c6929cb36c6ae Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 15 Apr 2014 19:44:59 +0200 Subject: [PATCH 02/15] ARM: dts: rockchip: move oscillator input clock into main dtsi The clock definitions get a lot shorter due to the soc clocks being handled by rk3188-cru and only the input clock remains. These can now simply live in the main rk3xxx.dtsi without affecting readability. At the same time, rename the node to oscillator, adding a clock-output-names property to match how the rk3288 handles this. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz --- arch/arm/boot/dts/rk3066a-clocks.dtsi | 6 ------ arch/arm/boot/dts/rk3188-clocks.dtsi | 6 ------ arch/arm/boot/dts/rk3xxx.dtsi | 7 +++++++ 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi index 6e307fc4c451..0d4d667b82dc 100644 --- a/arch/arm/boot/dts/rk3066a-clocks.dtsi +++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi @@ -31,12 +31,6 @@ #clock-cells = <0>; }; - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - dummy48m: dummy48m { compatible = "fixed-clock"; clock-frequency = <48000000>; diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi index b1b92dc245ce..6bc0373a2fb8 100644 --- a/arch/arm/boot/dts/rk3188-clocks.dtsi +++ b/arch/arm/boot/dts/rk3188-clocks.dtsi @@ -31,12 +31,6 @@ #clock-cells = <0>; }; - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - dummy48m: dummy48m { compatible = "fixed-clock"; clock-frequency = <48000000>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index b47d5fe81187..6d163644c7cd 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -20,6 +20,13 @@ / { interrupt-parent = <&gic>; + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + clock-output-names = "xin24m"; + }; + soc { #address-cells = <1>; #size-cells = <1>; From d356d96f8558d69d4b0d4c72d95002e9b6533531 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 21 Jun 2014 17:03:40 +0200 Subject: [PATCH 03/15] arm: dts: rockchip: remove obsolete clock gate definitions The clock and reset unit is now provided by the rk3188-cru clock driver and thus the old style definitions of the gate clocks can go away. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz --- arch/arm/boot/dts/rk3066a-clocks.dtsi | 293 -------------------------- arch/arm/boot/dts/rk3066a.dtsi | 1 - arch/arm/boot/dts/rk3188-clocks.dtsi | 283 ------------------------- arch/arm/boot/dts/rk3188.dtsi | 1 - 4 files changed, 578 deletions(-) delete mode 100644 arch/arm/boot/dts/rk3066a-clocks.dtsi delete mode 100644 arch/arm/boot/dts/rk3188-clocks.dtsi diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi deleted file mode 100644 index 0d4d667b82dc..000000000000 --- a/arch/arm/boot/dts/rk3066a-clocks.dtsi +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - dummy48m: dummy48m { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - dummy150m: dummy150m { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_i2s0", - "gate_i2s0_frac", "gate_i2s1", - "gate_i2s1_frac", "gate_i2s2", - "gate_i2s2_frac", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer2", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@200000d8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d8 0x4>; - clocks = <&clk_gates2 1>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&clk_gates2 3>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_periph_src", "gate_aclk_periph", - "gate_hclk_periph", "gate_pclk_periph", - "gate_smc", "gate_mac", - "gate_hsadc", "gate_hsadc_frac", - "gate_saradc", "gate_spi0", - "gate_spi1", "gate_mmc0", - "gate_mac_lbtest", "gate_mmc1", - "gate_emmc", "gate_tsadc"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@200000dc { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000dc 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", - "gate_dclk_lcdc1", "gate_pclkin_cif0", - "gate_pclkin_cif1", "reserved", - "reserved", "gate_cif0_out", - "gate_cif1_out", "gate_aclk_vepu", - "gate_hclk_vepu", "gate_aclk_vdpu", - "gate_hclk_vdpu", "gate_gpu_src", - "reserved", "gate_xin27m"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@200000e0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e0 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates2 3>, - <&clk_gates2 1>, <&clk_gates2 1>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 3>, <&clk_gates0 3>, - <&clk_gates0 3>, <&clk_gates2 3>, - <&clk_gates0 4>; - - clock-output-names = - "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", - "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", - "gate_aclk_pei_niu", "gate_hclk_usb_peri", - "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", - "gate_hclk_cpubus", "gate_hclk_ahb2apb", - "gate_aclk_strc_sys", "gate_aclk_l2mem_con", - "gate_aclk_intmem", "gate_pclk_tsadc", - "gate_hclk_hdmi"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@200000e4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e4 0x4>; - clocks = <&clk_gates0 3>, <&clk_gates2 1>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 4>, <&clk_gates0 5>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates4 5>, - <&clk_gates4 5>, <&dummy>; - - clock-output-names = - "gate_aclk_dmac1", "gate_aclk_dmac2", - "gate_pclk_efuse", "gate_pclk_tzpc", - "gate_pclk_grf", "gate_pclk_pmu", - "gate_hclk_rom", "gate_pclk_ddrupctl", - "gate_aclk_smc", "gate_hclk_nandc", - "gate_hclk_mmc0", "gate_hclk_mmc1", - "gate_hclk_emmc", "gate_hclk_otg0", - "gate_hclk_otg1", "gate_aclk_gpu"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@200000e8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e8 0x4>; - clocks = <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0", "gate_hclk_lcdc0", - "gate_hclk_lcdc1", "gate_aclk_lcdc1", - "gate_hclk_cif0", "gate_aclk_cif0", - "gate_hclk_cif1", "gate_aclk_cif1", - "gate_aclk_ipp", "gate_hclk_ipp", - "gate_hclk_rga", "gate_aclk_rga", - "gate_hclk_vio_bus", "gate_aclk_vio0", - "gate_aclk_vcodec", "gate_shclk_vio_h2h"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@200000ec { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000ec 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>; - - clock-output-names = - "gate_hclk_emac", "gate_hclk_spdif", - "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch", - "gate_hclk_i2s_8ch", "gate_hclk_hsadc", - "gate_hclk_pidf", "gate_pclk_timer0", - "gate_pclk_timer1", "gate_pclk_timer2", - "gate_pclk_pwm01", "gate_pclk_pwm23", - "gate_pclk_spi0", "gate_pclk_spi1", - "gate_pclk_saradc", "gate_pclk_wdt"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@200000f0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f0 0x4>; - clocks = <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&dummy>, <&clk_gates0 5>; - - clock-output-names = - "gate_pclk_uart0", "gate_pclk_uart1", - "gate_pclk_uart2", "gate_pclk_uart3", - "gate_pclk_i2c0", "gate_pclk_i2c1", - "gate_pclk_i2c2", "gate_pclk_i2c3", - "gate_pclk_i2c4", "gate_pclk_gpio0", - "gate_pclk_gpio1", "gate_pclk_gpio2", - "gate_pclk_gpio3", "gate_pclk_gpio4", - "reserved", "gate_pclk_gpio6"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@200000f4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f4 0x4>; - clocks = <&dummy>, <&clk_gates0 5>, - <&dummy>, <&dummy>, - <&dummy>, <&clk_gates1 4>, - <&clk_gates0 5>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>; - - clock-output-names = - "gate_clk_core_dbg", "gate_pclk_dbg", - "gate_clk_trace", "gate_atclk", - "gate_clk_l2c", "gate_aclk_vio1", - "gate_pclk_publ", "gate_aclk_intmem0", - "gate_aclk_intmem1", "gate_aclk_intmem2", - "gate_aclk_intmem3"; - - #clock-cells = <1>; - }; - }; - -}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 15c81d2c2d52..6476ce7a2987 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -17,7 +17,6 @@ #include #include #include "rk3xxx.dtsi" -#include "rk3066a-clocks.dtsi" / { compatible = "rockchip,rk3066a"; diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi deleted file mode 100644 index 6bc0373a2fb8..000000000000 --- a/arch/arm/boot/dts/rk3188-clocks.dtsi +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - dummy48m: dummy48m { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - dummy150m: dummy150m { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy150m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_aclk_core", - "reserved", "gate_i2s0", - "gate_i2s0_frac", "reserved", - "reserved", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer3", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@200000d8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d8 0x4>; - clocks = <&clk_gates2 1>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&clk_gates2 3>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_periph_src", "gate_aclk_periph", - "gate_hclk_periph", "gate_pclk_periph", - "gate_smc", "gate_mac", - "gate_hsadc", "gate_hsadc_frac", - "gate_saradc", "gate_spi0", - "gate_spi1", "gate_mmc0", - "gate_mac_lbtest", "gate_mmc1", - "gate_emmc", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@200000dc { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000dc 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&xin24m>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", - "gate_dclk_lcdc1", "gate_pclkin_cif0", - "gate_timer2", "gate_timer4", - "gate_hsicphy", "gate_cif0_out", - "gate_timer5", "gate_aclk_vepu", - "gate_hclk_vepu", "gate_aclk_vdpu", - "gate_hclk_vdpu", "reserved", - "gate_timer6", "gate_aclk_gpu_src"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@200000e0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e0 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates2 3>, - <&clk_gates2 1>, <&clk_gates2 1>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 3>, <&dummy>, - <&clk_gates0 3>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", - "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", - "gate_aclk_pei_niu", "gate_hclk_usb_peri", - "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", - "gate_hclk_cpubus", "gate_hclk_ahb2apb", - "gate_aclk_strc_sys", "reserved", - "gate_aclk_intmem", "reserved", - "gate_hclk_imem1", "gate_hclk_imem0"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@200000e4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e4 0x4>; - clocks = <&clk_gates0 3>, <&clk_gates2 1>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 4>, <&clk_gates0 5>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates4 5>; - - clock-output-names = - "gate_aclk_dmac1", "gate_aclk_dmac2", - "gate_pclk_efuse", "gate_pclk_tzpc", - "gate_pclk_grf", "gate_pclk_pmu", - "gate_hclk_rom", "gate_pclk_ddrupctl", - "gate_aclk_smc", "gate_hclk_nandc", - "gate_hclk_mmc0", "gate_hclk_mmc1", - "gate_hclk_emmc", "gate_hclk_otg0"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@200000e8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e8 0x4>; - clocks = <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&dummy>, <&dummy>, - <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>; - - clock-output-names = - "gate_aclk_lcdc0", "gate_hclk_lcdc0", - "gate_hclk_lcdc1", "gate_aclk_lcdc1", - "gate_hclk_cif0", "gate_aclk_cif0", - "reserved", "reserved", - "gate_aclk_ipp", "gate_hclk_ipp", - "gate_hclk_rga", "gate_aclk_rga", - "gate_hclk_vio_bus", "gate_aclk_vio0"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@200000ec { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000ec 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates0 4>, - <&clk_gates0 4>, <&dummy>, - <&dummy>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates0 5>, - <&dummy>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>; - - clock-output-names = - "gate_hclk_emac", "gate_hclk_spdif", - "gate_hclk_i2s0_2ch", "gate_hclk_otg1", - "gate_hclk_hsic", "gate_hclk_hsadc", - "gate_hclk_pidf", "gate_pclk_timer0", - "reserved", "gate_pclk_timer2", - "gate_pclk_pwm01", "gate_pclk_pwm23", - "gate_pclk_spi0", "gate_pclk_spi1", - "gate_pclk_saradc", "gate_pclk_wdt"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@200000f0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f0 0x4>; - clocks = <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&dummy>; - - clock-output-names = - "gate_pclk_uart0", "gate_pclk_uart1", - "gate_pclk_uart2", "gate_pclk_uart3", - "gate_pclk_i2c0", "gate_pclk_i2c1", - "gate_pclk_i2c2", "gate_pclk_i2c3", - "gate_pclk_i2c4", "gate_pclk_gpio0", - "gate_pclk_gpio1", "gate_pclk_gpio2", - "gate_pclk_gpio3", "gate_aclk_gps"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@200000f4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f4 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_clk_core_dbg", "gate_pclk_dbg", - "gate_clk_trace", "gate_atclk", - "gate_clk_l2c", "gate_aclk_vio1", - "gate_pclk_publ", "gate_aclk_gpu"; - - #clock-cells = <1>; - }; - }; - -}; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index bf0741a89b7c..0db541c4e7b3 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -17,7 +17,6 @@ #include #include #include "rk3xxx.dtsi" -#include "rk3188-clocks.dtsi" / { compatible = "rockchip,rk3188"; From c3030d30d9c99c057b5ddfa289cffa637a2775f5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Jul 2014 18:44:35 +0200 Subject: [PATCH 04/15] ARM: dts: rockchip: remove soc subnodes Comments received from the rk3288 submission indicated that a generic subnode to group soc components should not be used. So to keep all rockchip devicetree files similar, remove it from rk3066 and rk3188. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 146 +++++---- arch/arm/boot/dts/rk3066a.dtsi | 418 ++++++++++++------------- arch/arm/boot/dts/rk3188-radxarock.dts | 95 +++--- arch/arm/boot/dts/rk3188.dtsi | 354 +++++++++++---------- arch/arm/boot/dts/rk3xxx.dtsi | 211 ++++++------- 5 files changed, 604 insertions(+), 620 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index afb327322a4a..6131675695eb 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -24,87 +24,85 @@ reg = <0x60000000 0x40000000>; }; - soc { - uart0: serial@10124000 { - status = "okay"; - }; + uart0: serial@10124000 { + status = "okay"; + }; - uart1: serial@10126000 { - status = "okay"; - }; + uart1: serial@10126000 { + status = "okay"; + }; - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; + uart2: serial@20064000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "okay"; + }; - uart3: serial@20068000 { - status = "okay"; - }; + uart3: serial@20068000 { + status = "okay"; + }; - vcc_sd0: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - }; + vcc_sd0: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + }; - dwmmc@10214000 { /* sdmmc */ - num-slots = <1>; - status = "okay"; + dwmmc@10214000 { /* sdmmc */ + num-slots = <1>; + status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; - vmmc-supply = <&vcc_sd0>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; + vmmc-supply = <&vcc_sd0>; - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - - dwmmc@10218000 { /* wifi */ - num-slots = <1>; - status = "okay"; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - button@0 { - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ - linux,code = <116>; - label = "GPIO Key Power"; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - button@1 { - gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ - linux,code = <104>; - label = "GPIO Key Vol-"; - linux,input-type = <1>; - gpio-key,wakeup = <0>; - debounce-interval = <100>; - }; - /* VOL+ comes somehow thru the ADC */ + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; }; }; + + dwmmc@10218000 { /* wifi */ + num-slots = <1>; + status = "okay"; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + button@0 { + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ + linux,code = <116>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + button@1 { + gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ + linux,code = <104>; + label = "GPIO Key Vol-"; + linux,input-type = <1>; + gpio-key,wakeup = <0>; + debounce-interval = <100>; + }; + /* VOL+ comes somehow thru the ADC */ + }; }; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 6476ce7a2987..4ad8f59503dd 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -40,255 +40,253 @@ }; }; - soc { - timer@20038000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x20038000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; + clock-names = "timer", "pclk"; + }; + + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; + clock-names = "timer", "pclk"; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x10000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pinctrl@20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - timer@2003a000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2003a000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - timer@2000e000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2000e000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x10000>; + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio6@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO6>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg_pull_default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + }; + + uart0_cts: uart0-cts { + rockchip,pins = ; + }; + + uart0_rts: uart0-rts { + rockchip,pins = ; }; }; - cru: clock-controller@20000000 { - compatible = "rockchip,rk3066a-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + }; - #clock-cells = <1>; - #reset-cells = <1>; + uart1_cts: uart1-cts { + rockchip,pins = ; + }; + + uart1_rts: uart1-rts { + rockchip,pins = ; + }; }; - pinctrl@20008000 { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + }; + /* no rts / cts for uart2 */ + }; - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = , + ; }; - gpio1: gpio1@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + uart3_cts: uart3-cts { + rockchip,pins = ; }; - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; + uart3_rts: uart3-rts { + rockchip,pins = ; + }; + }; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = ; }; - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + sd0_cmd: sd0-cmd { + rockchip,pins = ; }; - gpio4: gpio4@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + sd0_cd: sd0-cd { + rockchip,pins = ; }; - gpio6: gpio6@2000a000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + sd0_wp: sd0-wp { + rockchip,pins = ; }; - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default; + sd0_bus1: sd0-bus-width1 { + rockchip,pins = ; }; - pcfg_pull_none: pcfg_pull_none { - bias-disable; + sd0_bus4: sd0-bus-width4 { + rockchip,pins = , + , + , + ; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = ; }; - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = , - ; - }; - - uart0_cts: uart0-cts { - rockchip,pins = ; - }; - - uart0_rts: uart0-rts { - rockchip,pins = ; - }; + sd1_cmd: sd1-cmd { + rockchip,pins = ; }; - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = , - ; - }; - - uart1_cts: uart1-cts { - rockchip,pins = ; - }; - - uart1_rts: uart1-rts { - rockchip,pins = ; - }; + sd1_cd: sd1-cd { + rockchip,pins = ; }; - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - /* no rts / cts for uart2 */ + sd1_wp: sd1-wp { + rockchip,pins = ; }; - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = , - ; - }; - - uart3_cts: uart3-cts { - rockchip,pins = ; - }; - - uart3_rts: uart3-rts { - rockchip,pins = ; - }; + sd1_bus1: sd1-bus-width1 { + rockchip,pins = ; }; - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = ; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = ; - }; - - sd0_cd: sd0-cd { - rockchip,pins = ; - }; - - sd0_wp: sd0-wp { - rockchip,pins = ; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = ; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = ; - }; - - sd1_cd: sd1-cd { - rockchip,pins = ; - }; - - sd1_wp: sd1-wp { - rockchip,pins = ; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; - }; + sd1_bus4: sd1-bus-width4 { + rockchip,pins = , + , + , + ; }; }; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index a5eee55079cb..7a002f523ec4 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -23,59 +23,56 @@ reg = <0x60000000 0x80000000>; }; - soc { - uart0: serial@10124000 { - status = "okay"; + uart0: serial@10124000 { + status = "okay"; + }; + + uart1: serial@10126000 { + status = "okay"; + }; + + uart2: serial@20064000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "okay"; + }; + + uart3: serial@20068000 { + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + button@0 { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green { + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + default-state = "off"; }; - uart1: serial@10126000 { - status = "okay"; + yellow { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "off"; }; - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; + sleep { + gpios = <&gpio0 15 0>; + default-state = "off"; }; - - uart3: serial@20068000 { - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - button@0 { - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "GPIO Key Power"; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green { - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - yellow { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - sleep { - gpios = <&gpio0 15 0>; - default-state = "off"; - }; - }; - }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 0db541c4e7b3..038d9d45264c 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -52,223 +52,221 @@ }; }; - soc { - global-timer@1013c200 { - interrupts = ; + global-timer@1013c200 { + interrupts = ; + }; + + local-timer@1013c600 { + interrupts = ; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x8000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pinctrl@20008000 { + compatible = "rockchip,rk3188-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@0x2000a000 { + compatible = "rockchip,rk3188-gpio-bank0"; + reg = <0x2000a000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - local-timer@1013c600 { - interrupts = ; + gpio1: gpio1@0x2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg_pull_down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + }; + + uart0_cts: uart0-cts { + rockchip,pins = ; + }; + + uart0_rts: uart0-rts { + rockchip,pins = ; }; }; - cru: clock-controller@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + }; - #clock-cells = <1>; - #reset-cells = <1>; + uart1_cts: uart1-cts { + rockchip,pins = ; + }; + + uart1_rts: uart1-rts { + rockchip,pins = ; + }; }; - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + }; + /* no rts / cts for uart2 */ + }; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = , + ; }; - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + uart3_cts: uart3-cts { + rockchip,pins = ; }; - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; + uart3_rts: uart3-rts { + rockchip,pins = ; + }; + }; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = ; }; - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; + sd0_cmd: sd0-cmd { + rockchip,pins = ; }; - pcfg_pull_up: pcfg_pull_up { - bias-pull-up; + sd0_cd: sd0-cd { + rockchip,pins = ; }; - pcfg_pull_down: pcfg_pull_down { - bias-pull-down; + sd0_wp: sd0-wp { + rockchip,pins = ; }; - pcfg_pull_none: pcfg_pull_none { - bias-disable; + sd0_pwr: sd0-pwr { + rockchip,pins = ; }; - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = , - ; - }; - - uart0_cts: uart0-cts { - rockchip,pins = ; - }; - - uart0_rts: uart0-rts { - rockchip,pins = ; - }; + sd0_bus1: sd0-bus-width1 { + rockchip,pins = ; }; - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = , - ; - }; + sd0_bus4: sd0-bus-width4 { + rockchip,pins = , + , + , + ; + }; + }; - uart1_cts: uart1-cts { - rockchip,pins = ; - }; - - uart1_rts: uart1-rts { - rockchip,pins = ; - }; + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = ; }; - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - /* no rts / cts for uart2 */ + sd1_cmd: sd1-cmd { + rockchip,pins = ; }; - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = , - ; - }; - - uart3_cts: uart3-cts { - rockchip,pins = ; - }; - - uart3_rts: uart3-rts { - rockchip,pins = ; - }; + sd1_cd: sd1-cd { + rockchip,pins = ; }; - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = ; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = ; - }; - - sd0_cd: sd0-cd { - rockchip,pins = ; - }; - - sd0_wp: sd0-wp { - rockchip,pins = ; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = ; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; - }; + sd1_wp: sd1-wp { + rockchip,pins = ; }; - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = ; - }; + sd1_bus1: sd1-bus-width1 { + rockchip,pins = ; + }; - sd1_cmd: sd1-cmd { - rockchip,pins = ; - }; - - sd1_cd: sd1-cd { - rockchip,pins = ; - }; - - sd1_wp: sd1-wp { - rockchip,pins = ; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; - }; + sd1_bus4: sd1-bus-width4 { + rockchip,pins = , + , + , + ; }; }; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 6d163644c7cd..f70addd793a7 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -27,120 +27,113 @@ clock-output-names = "xin24m"; }; - soc { + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon"; + reg = <0x20004000 0x100>; + }; + + grf: grf@20008000 { + compatible = "syscon"; + reg = <0x20008000 0x200>; + }; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + global-timer@1013c200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1013c200 0x20>; + interrupts = ; + clocks = <&cru CORE_PERI>; + }; + + local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = ; + clocks = <&cru CORE_PERI>; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART0>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART1>; + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART2>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART3>; + status = "disabled"; + }; + + dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = ; #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; + #size-cells = <0>; - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; - reg = <0x20004000 0x100>; - }; + status = "disabled"; + }; - grf: grf@20008000 { - compatible = "syscon"; - reg = <0x20008000 0x200>; - }; + dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; + clock-names = "biu", "ciu"; - L2: l2-cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART1>; - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART3>; - status = "disabled"; - }; - - dwmmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; - - dwmmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; + status = "disabled"; }; }; From e40b43d6ea0c5c30ba3655b304d2d526539fc7ed Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Jul 2014 18:53:07 +0200 Subject: [PATCH 05/15] ARM: dts: rockchip: add handles for shared nodes that don't have one yet Some nodes that are changed in the dtsi hierarchy do not have handles yet. As it was suggested in the rk3288 submission to do subsequent nodes changes through such handle-references, add the missing ones. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 2 +- arch/arm/boot/dts/rk3188.dtsi | 2 +- arch/arm/boot/dts/rk3xxx.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4ad8f59503dd..ecf722ea5982 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -86,7 +86,7 @@ #reset-cells = <1>; }; - pinctrl@20008000 { + pinctrl: pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 038d9d45264c..7b631ec3102c 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -82,7 +82,7 @@ #reset-cells = <1>; }; - pinctrl@20008000 { + pinctrl: pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmu>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index f70addd793a7..10e7586c1dc2 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -57,14 +57,14 @@ cache-level = <2>; }; - global-timer@1013c200 { + global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; interrupts = ; clocks = <&cru CORE_PERI>; }; - local-timer@1013c600 { + local_timer: local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>; interrupts = ; @@ -111,7 +111,7 @@ status = "disabled"; }; - dwmmc@10214000 { + mmc0: dwmmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = ; @@ -124,7 +124,7 @@ status = "disabled"; }; - dwmmc@10218000 { + mmc1: dwmmc@10218000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = ; From fcbbf965254ff1693c26a5646e4e62adc3a6118d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Jul 2014 23:08:06 +0200 Subject: [PATCH 06/15] ARM: dts: uses handles to reference nodes for changes Use the handles for subsequent changes to nodes, similar to like the rk3288 submission does it. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 91 ++++++++++++-------------- arch/arm/boot/dts/rk3066a.dtsi | 30 +++++++++ arch/arm/boot/dts/rk3188-radxarock.dts | 36 +++++----- arch/arm/boot/dts/rk3188.dtsi | 36 +++++++--- 4 files changed, 119 insertions(+), 74 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 6131675695eb..38910f6992bf 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -24,24 +24,6 @@ reg = <0x60000000 0x40000000>; }; - uart0: serial@10124000 { - status = "okay"; - }; - - uart1: serial@10126000 { - status = "okay"; - }; - - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; - - uart3: serial@20068000 { - status = "okay"; - }; - vcc_sd0: fixed-regulator { compatible = "regulator-fixed"; regulator-name = "sdmmc-supply"; @@ -51,36 +33,6 @@ startup-delay-us = <100000>; }; - dwmmc@10214000 { /* sdmmc */ - num-slots = <1>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - - dwmmc@10218000 { /* wifi */ - num-slots = <1>; - status = "okay"; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -106,3 +58,46 @@ /* VOL+ comes somehow thru the ADC */ }; }; + +&mmc0 { /* sdmmc */ + num-slots = <1>; + status = "okay"; + vmmc-supply = <&vcc_sd0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; +}; + +&mmc1 { /* wifi */ + num-slots = <1>; + status = "okay"; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index ecf722ea5982..460932b2baa8 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -291,3 +291,33 @@ }; }; }; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 7a002f523ec4..241e2a4d4b99 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -23,24 +23,6 @@ reg = <0x60000000 0x80000000>; }; - uart0: serial@10124000 { - status = "okay"; - }; - - uart1: serial@10126000 { - status = "okay"; - }; - - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; - - uart3: serial@20068000 { - status = "okay"; - }; - gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -76,3 +58,21 @@ }; }; }; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 7b631ec3102c..4a9f7020c562 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -52,14 +52,6 @@ }; }; - global-timer@1013c200 { - interrupts = ; - }; - - local-timer@1013c600 { - interrupts = ; - }; - sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x8000>; @@ -271,3 +263,31 @@ }; }; }; + +&global_timer { + interrupts = ; +}; + +&local_timer { + interrupts = ; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; From 6e4b3b4b66dd6e7f4980a6626d54a532deb47517 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 22 Jul 2014 22:56:16 +0200 Subject: [PATCH 07/15] ARM: dts: rockchip: remove address from pinctrl nodes The pincontroller uses the GRF and PMU syscons nowadays, so should not contain an address in its device node. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 2 +- arch/arm/boot/dts/rk3188.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 460932b2baa8..3198394429c2 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -86,7 +86,7 @@ #reset-cells = <1>; }; - pinctrl: pinctrl@20008000 { + pinctrl: pinctrl { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 4a9f7020c562..dd7f61fe98d4 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -74,7 +74,7 @@ #reset-cells = <1>; }; - pinctrl: pinctrl@20008000 { + pinctrl: pinctrl { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmu>; From ff84b90ecd1cfd00af3d1832fd8bf3c18e555d4e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Jul 2014 23:28:03 +0200 Subject: [PATCH 08/15] ARM: dts: rockchip: oder nodes by register address To create some sort of ordering of nodes, they are suggested to be ordered by their register address. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 48 +++++++++---------- arch/arm/boot/dts/rk3xxx.dtsi | 86 +++++++++++++++++----------------- 2 files changed, 67 insertions(+), 67 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 3198394429c2..21b87dece38c 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -40,30 +40,6 @@ }; }; - timer@20038000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x20038000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; - - timer@2003a000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2003a000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; - }; - - timer@2000e000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2000e000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; - }; - sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; @@ -86,6 +62,30 @@ #reset-cells = <1>; }; + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; + clock-names = "timer", "pclk"; + }; + + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; + clock-names = "timer", "pclk"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 10e7586c1dc2..ad204da6c60f 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -27,29 +27,6 @@ clock-output-names = "xin24m"; }; - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; - reg = <0x20004000 0x100>; - }; - - grf: grf@20008000 { - compatible = "syscon"; - reg = <0x20008000 0x200>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - L2: l2-cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; @@ -57,6 +34,11 @@ cache-level = <2>; }; + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; @@ -71,6 +53,14 @@ clocks = <&cru CORE_PERI>; }; + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + uart0: serial@10124000 { compatible = "snps,dw-apb-uart"; reg = <0x10124000 0x400>; @@ -91,26 +81,6 @@ status = "disabled"; }; - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART3>; - status = "disabled"; - }; - mmc0: dwmmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; @@ -136,4 +106,34 @@ status = "disabled"; }; + + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon"; + reg = <0x20004000 0x100>; + }; + + grf: grf@20008000 { + compatible = "syscon"; + reg = <0x20008000 0x200>; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART2>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART3>; + status = "disabled"; + }; }; From 9cdffd8cb9b5f30495a9c284ab05d5b803f3b457 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 24 Jun 2014 20:12:06 +0200 Subject: [PATCH 09/15] ARM: dts: add rk3066 and rk3188 i2c device nodes and pinctrl settings The core controller settings themself are identical, only the compatible and pinctrl settings differ. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 60 ++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 65 ++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 84 ++++++++++++++++++++++++++++++++++ 3 files changed, 209 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 21b87dece38c..18e802c08a91 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -179,6 +179,41 @@ bias-disable; }; + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = , + ; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = , + ; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = , + ; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = , + ; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = , + ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -292,6 +327,31 @@ }; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index dd7f61fe98d4..ba1193ca00a7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -147,6 +147,41 @@ bias-disable; }; + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = , + ; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = , + ; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = , + ; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = , + ; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = , + ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -272,6 +307,36 @@ interrupts = ; }; +&i2c0 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index ad204da6c60f..d3fa4d1a2f8a 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -20,6 +20,14 @@ / { interrupt-parent = <&gic>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -117,6 +125,82 @@ reg = <0x20008000 0x200>; }; + i2c0: i2c@2002d000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002d000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + rockchip,bus-index = <0>; + + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + + status = "disabled"; + }; + + i2c1: i2c@2002f000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002f000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C1>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c2: i2c@20056000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x20056000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C2>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c3: i2c@2005a000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C3>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c4: i2c@2005e000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C4>; + clock-names = "i2c"; + + status = "disabled"; + }; + uart2: serial@20064000 { compatible = "snps,dw-apb-uart"; reg = <0x20064000 0x400>; From a953a6c77da2b8c2beb6db500b870e0b8c48fe64 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 26 Jun 2014 01:33:58 +0200 Subject: [PATCH 10/15] ARM: dts: rockchip: add tps65910 regulator for bqcurie2 The Curie2 uses a tps659102 as its main pmic, so add the i2c1 and tps65910 node as well as define the used voltages and regulator-names according to the schematics. Also fix the supply of the sd0 regulator, as it is supplied by the vio reg. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 87 ++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 38910f6992bf..8b479f767561 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -31,6 +31,7 @@ regulator-max-microvolt = <3000000>; gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; startup-delay-us = <100000>; + vin-supply = <&vcc_io>; }; gpio-keys { @@ -59,6 +60,92 @@ }; }; +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + + interrupt-parent = <&gpio6>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vcc_rtc: regulator@0 { + regulator-name = "vcc_rtc"; + regulator-always-on; + }; + + vcc_io: regulator@1 { + regulator-name = "vcc_io"; + regulator-always-on; + }; + + vdd_arm: regulator@2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_ddr: regulator@3 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc18_cif: regulator@5 { + regulator-name = "vcc18_cif"; + regulator-always-on; + }; + + vdd_11: regulator@6 { + regulator-name = "vdd_11"; + regulator-always-on; + }; + + vcc_25: regulator@7 { + regulator-name = "vcc_25"; + regulator-always-on; + }; + + vcc_18: regulator@8 { + regulator-name = "vcc_18"; + regulator-always-on; + }; + + vcc25_hdmi: regulator@9 { + regulator-name = "vcc25_hdmi"; + regulator-always-on; + }; + + vcca_33: regulator@10 { + regulator-name = "vcca_33"; + regulator-always-on; + }; + + vcc_tp: regulator@11 { + regulator-name = "vcc_tp"; + regulator-always-on; + }; + + vcc28_cif: regulator@12 { + regulator-name = "vcc28_cif"; + regulator-always-on; + }; + }; + }; +}; + +/* must be included after &tps gets defined */ +#include "tps65910.dtsi" + &mmc0 { /* sdmmc */ num-slots = <1>; status = "okay"; From fe2c89afa7797a7b5b949be298775d908d51f612 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sun, 22 Jun 2014 16:41:09 +0200 Subject: [PATCH 11/15] ARM: dts: add i2c and regulator nodes to rk3188-radxarock This enables the 2nd i2c bus and adds the act8846 pmic as device. Signed-off-by: Beniamino Galvani Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-radxarock.dts | 112 +++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 241e2a4d4b99..a2812932cc5e 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -59,6 +59,118 @@ }; }; +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&act8846_dvs0_ctl>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_log: REG2 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_arm: REG3 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + vcc_io: REG4 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG5 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_hdmi: REG6 { + regulator-name = "VDD_HDMI"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vcc18: REG7 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_rmii: REG9 { + regulator-name = "VCC_RMII"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_wl: REG10 { + regulator-name = "VCCIO_WL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC18_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc28: REG12 { + regulator-name = "VCC_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; +}; + +&pinctrl { + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + act8846_dvs0_ctl: act8846-dvs0-ctl { + rockchip,pins = ; + }; + }; +}; + &uart0 { status = "okay"; }; From b09e35a388ad23eb90497a352b8e5e5cb4b97bf2 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 26 Jun 2014 16:18:44 +0200 Subject: [PATCH 12/15] ARM: dts: rk3188-radxarock: enable sd-card slot The Radxa Rock contains one sd-card slot. Add the supplying regulator and enable its dw_mmc node. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-radxarock.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index a2812932cc5e..7628b4868d2a 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -57,6 +57,16 @@ default-state = "off"; }; }; + + vcc_sd0: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 1 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; }; &i2c1 { @@ -159,6 +169,18 @@ }; }; +&mmc0 { + num-slots = <1>; + status = "okay"; + vmmc-supply = <&vcc_sd0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; +}; + &pinctrl { pcfg_output_low: pcfg-output-low { output-low; From 69667ca2c4ad5bd346fb694a68e676fa46b2fba0 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 26 Jun 2014 16:06:12 +0200 Subject: [PATCH 13/15] ARM: dts: rockchip: add both clocks to uart nodes Use the newly ammended dw_8250 clock binding to define both the baudclk as well as the pclk supplying the ip. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3xxx.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index d3fa4d1a2f8a..989c33785ec4 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -75,7 +75,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; status = "disabled"; }; @@ -85,7 +86,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&cru SCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; status = "disabled"; }; @@ -207,7 +209,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&cru SCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; status = "disabled"; }; @@ -217,7 +220,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&cru SCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; status = "disabled"; }; }; From 550c7f4e6377cf5093b1b8d6b99cde2506bfea23 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Thu, 26 Jun 2014 20:03:41 +0200 Subject: [PATCH 14/15] ARM: dts: rockchip: add pwm nodes This adds the necessary nodex and pinctrl settings for the Rockchip PWM-driver. Signed-off-by: Beniamino Galvani Modified to use the new clock defines and added rk3066 pins. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 44 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 44 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 32 +++++++++++++++++++++++++ 3 files changed, 120 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 18e802c08a91..9c34da4d8aad 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -214,6 +214,30 @@ }; }; + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = ; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = ; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = ; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -362,6 +386,26 @@ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ba1193ca00a7..27215e0b5c3b 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -182,6 +182,30 @@ }; }; + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = ; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = ; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = ; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -337,6 +361,26 @@ pinctrl-0 = <&i2c4_xfer>; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 989c33785ec4..c6f05610ed2d 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -158,6 +158,38 @@ status = "disabled"; }; + pwm0: pwm@20030000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030000 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + pwm1: pwm@20030010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030010 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + i2c2: i2c@20056000 { compatible = "rockchip,rk3066-i2c"; reg = <0x20056000 0x1000>; From 08567053f5cc4255ab53b75277b6102a3202bd75 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sun, 13 Jul 2014 14:10:01 +0200 Subject: [PATCH 15/15] ARM: dts: rk3188-radxarock: add GPIO IR receiver node This adds a device tree node for the infrared receiver connected to a GPIO pin on the Radxa Rock. Signed-off-by: Beniamino Galvani Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-radxarock.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 7628b4868d2a..b7f34232e3d2 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -58,6 +58,13 @@ }; }; + ir_recv: gpio-ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 10 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_recv_pin>; + }; + vcc_sd0: sdmmc-regulator { compatible = "regulator-fixed"; regulator-name = "sdmmc-supply"; @@ -191,6 +198,12 @@ rockchip,pins = ; }; }; + + ir-receiver { + ir_recv_pin: ir-recv-pin { + rockchip,pins = ; + }; + }; }; &uart0 {