forked from Minki/linux
x86: cpu/common*.c have same cpu_init(), with copying and #ifdef
hard to merge by lines... (as here we have material differences between 32-bit and 64-bit mode) - will try to do it later. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
parent
d5494d4f51
commit
1ba76586f7
@ -901,7 +901,129 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
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* initialized (naturally) in the bootstrap process, such as the GDT
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* and IDT. We reload them nevertheless, this function acts as a
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* 'CPU state barrier', nothing should get across.
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* A lot of state is already set up in PDA init for 64 bit
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*/
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#ifdef CONFIG_X86_64
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void __cpuinit cpu_init(void)
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{
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int cpu = stack_smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
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unsigned long v;
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char *estacks = NULL;
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struct task_struct *me;
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int i;
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/* CPU 0 is initialised in head64.c */
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if (cpu != 0)
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pda_init(cpu);
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else
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estacks = boot_exception_stacks;
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me = current;
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if (cpu_test_and_set(cpu, cpu_initialized))
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panic("CPU#%d already initialized!\n", cpu);
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printk(KERN_INFO "Initializing CPU#%d\n", cpu);
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clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
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/*
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* Initialize the per-CPU GDT with the boot GDT,
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* and set up the GDT descriptor:
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*/
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switch_to_new_gdt();
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load_idt((const struct desc_ptr *)&idt_descr);
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memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
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syscall_init();
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wrmsrl(MSR_FS_BASE, 0);
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wrmsrl(MSR_KERNEL_GS_BASE, 0);
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barrier();
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check_efer();
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if (cpu != 0 && x2apic)
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enable_x2apic();
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/*
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* set up and load the per-CPU TSS
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*/
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if (!orig_ist->ist[0]) {
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static const unsigned int order[N_EXCEPTION_STACKS] = {
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[0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
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[DEBUG_STACK - 1] = DEBUG_STACK_ORDER
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};
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for (v = 0; v < N_EXCEPTION_STACKS; v++) {
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if (cpu) {
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estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
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if (!estacks)
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panic("Cannot allocate exception "
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"stack %ld %d\n", v, cpu);
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}
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estacks += PAGE_SIZE << order[v];
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orig_ist->ist[v] = t->x86_tss.ist[v] =
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(unsigned long)estacks;
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}
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}
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t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
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/*
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* <= is required because the CPU will access up to
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* 8 bits beyond the end of the IO permission bitmap.
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*/
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for (i = 0; i <= IO_BITMAP_LONGS; i++)
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t->io_bitmap[i] = ~0UL;
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atomic_inc(&init_mm.mm_count);
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me->active_mm = &init_mm;
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if (me->mm)
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BUG();
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enter_lazy_tlb(&init_mm, me);
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load_sp0(t, ¤t->thread);
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set_tss_desc(cpu, t);
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load_TR_desc();
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load_LDT(&init_mm.context);
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#ifdef CONFIG_KGDB
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/*
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* If the kgdb is connected no debug regs should be altered. This
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* is only applicable when KGDB and a KGDB I/O module are built
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* into the kernel and you are using early debugging with
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* kgdbwait. KGDB will control the kernel HW breakpoint registers.
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*/
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if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
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arch_kgdb_ops.correct_hw_break();
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else {
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#endif
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/*
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* Clear all 6 debug registers:
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*/
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set_debugreg(0UL, 0);
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set_debugreg(0UL, 1);
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set_debugreg(0UL, 2);
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set_debugreg(0UL, 3);
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set_debugreg(0UL, 6);
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set_debugreg(0UL, 7);
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#ifdef CONFIG_KGDB
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/* If the kgdb is connected no debug regs should be altered. */
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}
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#endif
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fpu_init();
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raw_local_save_flags(kernel_eflags);
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if (is_uv_system())
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uv_cpu_init();
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}
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#else
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void __cpuinit cpu_init(void)
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{
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int cpu = smp_processor_id();
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@ -982,3 +1104,5 @@ void __cpuinit cpu_uninit(void)
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per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
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}
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#endif
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#endif
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@ -855,8 +855,9 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
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* initialized (naturally) in the bootstrap process, such as the GDT
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* and IDT. We reload them nevertheless, this function acts as a
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* 'CPU state barrier', nothing should get across.
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* A lot of state is already set up in PDA init.
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* A lot of state is already set up in PDA init for 64 bit
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*/
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#ifdef CONFIG_X86_64
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void __cpuinit cpu_init(void)
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{
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int cpu = stack_smp_processor_id();
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@ -974,3 +975,88 @@ void __cpuinit cpu_init(void)
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if (is_uv_system())
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uv_cpu_init();
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}
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#else
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void __cpuinit cpu_init(void)
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{
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int cpu = smp_processor_id();
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struct task_struct *curr = current;
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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struct thread_struct *thread = &curr->thread;
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if (cpu_test_and_set(cpu, cpu_initialized)) {
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printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
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for (;;) local_irq_enable();
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}
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printk(KERN_INFO "Initializing CPU#%d\n", cpu);
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if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
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clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
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load_idt(&idt_descr);
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switch_to_new_gdt();
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/*
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* Set up and load the per-CPU TSS and LDT
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*/
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atomic_inc(&init_mm.mm_count);
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curr->active_mm = &init_mm;
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if (curr->mm)
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BUG();
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enter_lazy_tlb(&init_mm, curr);
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load_sp0(t, thread);
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set_tss_desc(cpu, t);
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load_TR_desc();
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load_LDT(&init_mm.context);
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#ifdef CONFIG_DOUBLEFAULT
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/* Set up doublefault TSS pointer in the GDT */
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__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
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#endif
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/* Clear %gs. */
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asm volatile ("mov %0, %%gs" : : "r" (0));
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/* Clear all 6 debug registers: */
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set_debugreg(0, 0);
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set_debugreg(0, 1);
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set_debugreg(0, 2);
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set_debugreg(0, 3);
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set_debugreg(0, 6);
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set_debugreg(0, 7);
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/*
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* Force FPU initialization:
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*/
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if (cpu_has_xsave)
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current_thread_info()->status = TS_XSAVE;
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else
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current_thread_info()->status = 0;
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clear_used_math();
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mxcsr_feature_mask_init();
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/*
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* Boot processor to setup the FP and extended state context info.
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*/
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if (!smp_processor_id())
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init_thread_xstate();
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xsave_init();
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void __cpuinit cpu_uninit(void)
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{
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int cpu = raw_smp_processor_id();
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cpu_clear(cpu, cpu_initialized);
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/* lazy TLB state */
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per_cpu(cpu_tlbstate, cpu).state = 0;
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per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
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}
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#endif
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#endif
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