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drm/i915/psr: Mask PSR irq bits when re-enabling interrupts.

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gen8_de_irq_postinstall() wasn't masking the IRQ bit before passing the
debug flag to psr_irq_control(). This check was missed when new debug bits
were defined in  'commit c44301fce6 ("drm/i915: Allow control of PSR at
runtime through debugfs, v6")'. Instead of ANDing the irq bit in all the
callers, move it to the callee.

v2: Rebased.

Fixes: c44301fce6 ("drm/i915: Allow control of PSR at runtime through
debugfs, v6")
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180821221156.2442-3-dhinakaran.pandiyan@intel.com
This commit is contained in:
Dhinakaran Pandiyan 2018-08-21 15:11:56 -07:00
parent 9844d4bf3e
commit 1aeb1b5fa0
3 changed files with 5 additions and 5 deletions
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2
drivers/gpu/drm/i915/i915_irq.c
View File

@ -4048,7 +4048,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
if (IS_HASWELL(dev_priv)) {
gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug & I915_PSR_DEBUG_IRQ);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
}

2
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1944,7 +1944,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
void intel_psr_init(struct drm_i915_private *dev_priv);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,

6
drivers/gpu/drm/i915/intel_psr.c
View File

@ -79,7 +79,7 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
}
}
void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)
void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
{
u32 debug_mask, mask;
@ -100,7 +100,7 @@ void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)
EDP_PSR_PRE_ENTRY(TRANSCODER_C);
}
if (debug)
if (debug & I915_PSR_DEBUG_IRQ)
mask |= debug_mask;
I915_WRITE(EDP_PSR_IMR, ~mask);
@ -904,7 +904,7 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
if (crtc)
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug & I915_PSR_DEBUG_IRQ);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
if (dev_priv->psr.prepared && enable)
intel_psr_enable_locked(dev_priv, crtc_state);