forked from Minki/linux
ARM: imx6q: add cko1 clock
- add DEF_CLK_1B to define clocks using one bit gate - add cko1 clock and set ahb as the default parent imx6q-sabrelite board use it as audio codec clock. Signed-off-by: Richard Zhao <richard.zhao@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Richard Zhao
Shawn Guo
parent
89857353f9
commit
1aa0cf6779
@ -329,6 +329,12 @@
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#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
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#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
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#define BP_CCOSR_CKO1_EN 7
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#define BP_CCOSR_CKO1_PODF 4
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#define BM_CCOSR_CKO1_PODF (0x7 << 4)
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#define BP_CCOSR_CKO1_SEL 0
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#define BM_CCOSR_CKO1_SEL (0xf << 0)
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#define FREQ_480M 480000000
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#define FREQ_528M 528000000
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#define FREQ_594M 594000000
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@ -393,6 +399,7 @@ static struct clk ipu1_di1_clk;
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static struct clk ipu2_di0_clk;
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static struct clk ipu2_di1_clk;
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static struct clk enfc_clk;
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static struct clk cko1_clk;
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static struct clk dummy_clk = {};
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static unsigned long external_high_reference;
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@ -938,6 +945,24 @@ static void _clk_disable(struct clk *clk)
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writel_relaxed(reg, clk->enable_reg);
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}
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static int _clk_enable_1b(struct clk *clk)
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{
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u32 reg;
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reg = readl_relaxed(clk->enable_reg);
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reg |= 0x1 << clk->enable_shift;
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writel_relaxed(reg, clk->enable_reg);
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return 0;
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}
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static void _clk_disable_1b(struct clk *clk)
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{
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u32 reg;
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reg = readl_relaxed(clk->enable_reg);
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reg &= ~(0x1 << clk->enable_shift);
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writel_relaxed(reg, clk->enable_reg);
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}
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struct divider {
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struct clk *clk;
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void __iomem *reg;
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@ -983,6 +1008,7 @@ DEF_CLK_DIV1(ipu2_di0_pre_div, &ipu2_di0_pre_clk, CSCDR2, IPU2_DI0_PRE);
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DEF_CLK_DIV1(ipu2_di1_pre_div, &ipu2_di1_pre_clk, CSCDR2, IPU2_DI1_PRE);
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DEF_CLK_DIV1(ipu1_div, &ipu1_clk, CSCDR3, IPU1_HSP);
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DEF_CLK_DIV1(ipu2_div, &ipu2_clk, CSCDR3, IPU2_HSP);
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DEF_CLK_DIV1(cko1_div, &cko1_clk, CCOSR, CKO1);
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#define DEF_CLK_DIV2(d, c, r, b) \
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static struct divider d = { \
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@ -1038,6 +1064,7 @@ static struct divider *dividers[] = {
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&enfc_div,
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&spdif_div,
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&asrc_serial_div,
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&cko1_div,
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};
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static unsigned long ldb_di_clk_get_rate(struct clk *clk)
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@ -1625,6 +1652,32 @@ DEF_IPU_DI_MUX(CSCDR2, 2, 1);
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DEF_IPU_MUX(1);
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DEF_IPU_MUX(2);
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static struct multiplexer cko1_mux = {
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.clk = &cko1_clk,
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.reg = CCOSR,
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.bp = BP_CCOSR_CKO1_SEL,
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.bm = BM_CCOSR_CKO1_SEL,
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.parents = {
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&pll3_usb_otg,
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&pll2_bus,
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&pll1_sys,
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&pll5_video,
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&dummy_clk,
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&axi_clk,
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&enfc_clk,
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&ipu1_di0_clk,
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&ipu1_di1_clk,
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&ipu2_di0_clk,
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&ipu2_di1_clk,
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&ahb_clk,
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&ipg_clk,
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&ipg_perclk,
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&ckil_clk,
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&pll4_audio,
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NULL
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},
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};
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static struct multiplexer *multiplexers[] = {
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&axi_mux,
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&periph_mux,
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@ -1667,6 +1720,7 @@ static struct multiplexer *multiplexers[] = {
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&ipu2_di1_mux,
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&ipu1_mux,
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&ipu2_mux,
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&cko1_mux,
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};
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static int _clk_set_parent(struct clk *clk, struct clk *parent)
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@ -1690,7 +1744,7 @@ static int _clk_set_parent(struct clk *clk, struct clk *parent)
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break;
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i++;
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}
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if (!m->parents[i])
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if (!m->parents[i] || m->parents[i] == &dummy_clk)
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return -EINVAL;
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val = readl_relaxed(m->reg);
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@ -1745,6 +1799,20 @@ DEF_NG_CLK(asrc_serial_clk, &pll3_usb_otg);
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.secondary = s, \
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}
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#define DEF_CLK_1B(name, er, es, p, s) \
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static struct clk name = { \
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.enable_reg = er, \
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.enable_shift = es, \
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.enable = _clk_enable_1b, \
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.disable = _clk_disable_1b, \
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.get_rate = _clk_get_rate, \
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.set_rate = _clk_set_rate, \
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.round_rate = _clk_round_rate, \
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.set_parent = _clk_set_parent, \
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.parent = p, \
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.secondary = s, \
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}
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DEF_CLK(aips_tz1_clk, CCGR0, CG0, &ahb_clk, NULL);
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DEF_CLK(aips_tz2_clk, CCGR0, CG1, &ahb_clk, NULL);
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DEF_CLK(apbh_dma_clk, CCGR0, CG2, &ahb_clk, NULL);
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@ -1811,6 +1879,7 @@ DEF_CLK(usdhc4_clk, CCGR6, CG4, &pll2_pfd_400m, NULL);
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DEF_CLK(emi_slow_clk, CCGR6, CG5, &axi_clk, NULL);
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DEF_CLK(vdo_axi_clk, CCGR6, CG6, &axi_clk, NULL);
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DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, NULL);
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DEF_CLK_1B(cko1_clk, CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL);
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static int pcie_clk_enable(struct clk *clk)
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{
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@ -1922,6 +1991,7 @@ static struct clk_lookup lookups[] = {
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_REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
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_REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
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_REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
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_REGISTER_CLOCK(NULL, "cko1_clk", cko1_clk),
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};
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int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
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@ -2029,6 +2099,8 @@ int __init mx6q_clocks_init(void)
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clk_set_rate(&usdhc3_clk, 49500000);
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clk_set_rate(&usdhc4_clk, 49500000);
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clk_set_parent(&cko1_clk, &ahb_clk);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
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base = of_iomap(np, 0);
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WARN_ON(!base);
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