forked from Minki/linux
iwlwifi: dump prph registers in a common place for all transports
Currently the prph registers dump is in the transport layer, and each bus needs an additional dump implementation. Move the prph dump outside transport, and allow a common implementation for all of the buses. This is possible because prph base addresses are similar for all buses. Signed-off-by: Golan Ben-Ami <golan.ben.ami@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
This commit is contained in:
Golan Ben-Ami
Emmanuel Grumbach
parent
14ef1b433e
commit
1a616dd2f1
@ -1121,6 +1121,145 @@ void iwl_mvm_free_fw_dump_desc(struct iwl_mvm *mvm)
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#define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
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#define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
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static const struct {
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u32 start, end;
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} iwl_prph_dump_addr[] = {
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{ .start = 0x00a00000, .end = 0x00a00000 },
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{ .start = 0x00a0000c, .end = 0x00a00024 },
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{ .start = 0x00a0002c, .end = 0x00a0003c },
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{ .start = 0x00a00410, .end = 0x00a00418 },
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{ .start = 0x00a00420, .end = 0x00a00420 },
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{ .start = 0x00a00428, .end = 0x00a00428 },
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{ .start = 0x00a00430, .end = 0x00a0043c },
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{ .start = 0x00a00444, .end = 0x00a00444 },
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{ .start = 0x00a004c0, .end = 0x00a004cc },
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{ .start = 0x00a004d8, .end = 0x00a004d8 },
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{ .start = 0x00a004e0, .end = 0x00a004f0 },
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{ .start = 0x00a00840, .end = 0x00a00840 },
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{ .start = 0x00a00850, .end = 0x00a00858 },
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{ .start = 0x00a01004, .end = 0x00a01008 },
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{ .start = 0x00a01010, .end = 0x00a01010 },
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{ .start = 0x00a01018, .end = 0x00a01018 },
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{ .start = 0x00a01024, .end = 0x00a01024 },
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{ .start = 0x00a0102c, .end = 0x00a01034 },
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{ .start = 0x00a0103c, .end = 0x00a01040 },
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{ .start = 0x00a01048, .end = 0x00a01094 },
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{ .start = 0x00a01c00, .end = 0x00a01c20 },
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{ .start = 0x00a01c58, .end = 0x00a01c58 },
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{ .start = 0x00a01c7c, .end = 0x00a01c7c },
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{ .start = 0x00a01c28, .end = 0x00a01c54 },
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{ .start = 0x00a01c5c, .end = 0x00a01c5c },
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{ .start = 0x00a01c60, .end = 0x00a01cdc },
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{ .start = 0x00a01ce0, .end = 0x00a01d0c },
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{ .start = 0x00a01d18, .end = 0x00a01d20 },
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{ .start = 0x00a01d2c, .end = 0x00a01d30 },
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{ .start = 0x00a01d40, .end = 0x00a01d5c },
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{ .start = 0x00a01d80, .end = 0x00a01d80 },
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{ .start = 0x00a01d98, .end = 0x00a01d9c },
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{ .start = 0x00a01da8, .end = 0x00a01da8 },
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{ .start = 0x00a01db8, .end = 0x00a01df4 },
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{ .start = 0x00a01dc0, .end = 0x00a01dfc },
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{ .start = 0x00a01e00, .end = 0x00a01e2c },
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{ .start = 0x00a01e40, .end = 0x00a01e60 },
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{ .start = 0x00a01e68, .end = 0x00a01e6c },
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{ .start = 0x00a01e74, .end = 0x00a01e74 },
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{ .start = 0x00a01e84, .end = 0x00a01e90 },
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{ .start = 0x00a01e9c, .end = 0x00a01ec4 },
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{ .start = 0x00a01ed0, .end = 0x00a01ee0 },
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{ .start = 0x00a01f00, .end = 0x00a01f1c },
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{ .start = 0x00a01f44, .end = 0x00a01ffc },
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{ .start = 0x00a02000, .end = 0x00a02048 },
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{ .start = 0x00a02068, .end = 0x00a020f0 },
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{ .start = 0x00a02100, .end = 0x00a02118 },
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{ .start = 0x00a02140, .end = 0x00a0214c },
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{ .start = 0x00a02168, .end = 0x00a0218c },
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{ .start = 0x00a021c0, .end = 0x00a021c0 },
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{ .start = 0x00a02400, .end = 0x00a02410 },
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{ .start = 0x00a02418, .end = 0x00a02420 },
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{ .start = 0x00a02428, .end = 0x00a0242c },
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{ .start = 0x00a02434, .end = 0x00a02434 },
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{ .start = 0x00a02440, .end = 0x00a02460 },
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{ .start = 0x00a02468, .end = 0x00a024b0 },
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{ .start = 0x00a024c8, .end = 0x00a024cc },
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{ .start = 0x00a02500, .end = 0x00a02504 },
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{ .start = 0x00a0250c, .end = 0x00a02510 },
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{ .start = 0x00a02540, .end = 0x00a02554 },
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{ .start = 0x00a02580, .end = 0x00a025f4 },
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{ .start = 0x00a02600, .end = 0x00a0260c },
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{ .start = 0x00a02648, .end = 0x00a02650 },
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{ .start = 0x00a02680, .end = 0x00a02680 },
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{ .start = 0x00a026c0, .end = 0x00a026d0 },
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{ .start = 0x00a02700, .end = 0x00a0270c },
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{ .start = 0x00a02804, .end = 0x00a02804 },
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{ .start = 0x00a02818, .end = 0x00a0281c },
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{ .start = 0x00a02c00, .end = 0x00a02db4 },
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{ .start = 0x00a02df4, .end = 0x00a02fb0 },
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{ .start = 0x00a03000, .end = 0x00a03014 },
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{ .start = 0x00a0301c, .end = 0x00a0302c },
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{ .start = 0x00a03034, .end = 0x00a03038 },
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{ .start = 0x00a03040, .end = 0x00a03048 },
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{ .start = 0x00a03060, .end = 0x00a03068 },
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{ .start = 0x00a03070, .end = 0x00a03074 },
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{ .start = 0x00a0307c, .end = 0x00a0307c },
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{ .start = 0x00a03080, .end = 0x00a03084 },
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{ .start = 0x00a0308c, .end = 0x00a03090 },
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{ .start = 0x00a03098, .end = 0x00a03098 },
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{ .start = 0x00a030a0, .end = 0x00a030a0 },
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{ .start = 0x00a030a8, .end = 0x00a030b4 },
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{ .start = 0x00a030bc, .end = 0x00a030bc },
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{ .start = 0x00a030c0, .end = 0x00a0312c },
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{ .start = 0x00a03c00, .end = 0x00a03c5c },
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{ .start = 0x00a04400, .end = 0x00a04454 },
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{ .start = 0x00a04460, .end = 0x00a04474 },
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{ .start = 0x00a044c0, .end = 0x00a044ec },
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{ .start = 0x00a04500, .end = 0x00a04504 },
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{ .start = 0x00a04510, .end = 0x00a04538 },
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{ .start = 0x00a04540, .end = 0x00a04548 },
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{ .start = 0x00a04560, .end = 0x00a0457c },
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{ .start = 0x00a04590, .end = 0x00a04598 },
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{ .start = 0x00a045c0, .end = 0x00a045f4 },
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};
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static u32 iwl_dump_prph(struct iwl_trans *trans,
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struct iwl_fw_error_dump_data **data)
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{
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struct iwl_fw_error_dump_prph *prph;
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unsigned long flags;
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u32 prph_len = 0, i;
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if (!iwl_trans_grab_nic_access(trans, false, &flags))
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return 0;
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for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
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/* The range includes both boundaries */
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int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
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iwl_prph_dump_addr[i].start + 4;
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int reg;
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__le32 *val;
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prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
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(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
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(*data)->len = cpu_to_le32(sizeof(*prph) +
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num_bytes_in_chunk);
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prph = (void *)(*data)->data;
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prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
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val = (void *)prph->data;
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for (reg = iwl_prph_dump_addr[i].start;
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reg <= iwl_prph_dump_addr[i].end;
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reg += 4)
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*val++ = cpu_to_le32(iwl_read_prph_no_grab(trans,
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reg));
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*data = iwl_fw_error_next_data(*data);
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}
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iwl_trans_release_nic_access(trans, &flags);
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return prph_len;
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}
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void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
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{
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struct iwl_fw_error_dump_file *dump_file;
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@ -1134,6 +1273,7 @@ void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
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u32 smem_len = mvm->cfg->smem_len;
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u32 sram2_len = mvm->cfg->dccm2_len;
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bool monitor_dump_only = false;
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int i;
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lockdep_assert_held(&mvm->mutex);
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@ -1166,7 +1306,6 @@ void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
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/* reading RXF/TXF sizes */
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if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) {
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struct iwl_mvm_shared_mem_cfg *mem_cfg = &mvm->shared_mem_cfg;
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int i;
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fifo_data_len = 0;
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@ -1219,6 +1358,17 @@ void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
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sizeof(*dump_info);
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}
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/* Make room for PRPH registers */
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for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
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/* The range includes both boundaries */
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int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
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iwl_prph_dump_addr[i].start + 4;
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file_len += sizeof(*dump_data) +
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sizeof(struct iwl_fw_error_dump_prph) +
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num_bytes_in_chunk;
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}
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/*
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* In 8000 HW family B-step include the ICCM (which resides separately)
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*/
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@ -1343,6 +1493,9 @@ void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
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}
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}
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dump_data = iwl_fw_error_next_data(dump_data);
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iwl_dump_prph(mvm->trans, &dump_data);
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dump_trans_data:
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fw_error_dump->trans_ptr = iwl_trans_dump_data(mvm->trans,
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mvm->fw_dump_trig);
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@ -2144,144 +2144,6 @@ static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
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return cmdlen;
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}
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static const struct {
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u32 start, end;
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} iwl_prph_dump_addr[] = {
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{ .start = 0x00a00000, .end = 0x00a00000 },
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{ .start = 0x00a0000c, .end = 0x00a00024 },
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{ .start = 0x00a0002c, .end = 0x00a0003c },
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{ .start = 0x00a00410, .end = 0x00a00418 },
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{ .start = 0x00a00420, .end = 0x00a00420 },
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{ .start = 0x00a00428, .end = 0x00a00428 },
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{ .start = 0x00a00430, .end = 0x00a0043c },
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{ .start = 0x00a00444, .end = 0x00a00444 },
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{ .start = 0x00a004c0, .end = 0x00a004cc },
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{ .start = 0x00a004d8, .end = 0x00a004d8 },
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{ .start = 0x00a004e0, .end = 0x00a004f0 },
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{ .start = 0x00a00840, .end = 0x00a00840 },
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{ .start = 0x00a00850, .end = 0x00a00858 },
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{ .start = 0x00a01004, .end = 0x00a01008 },
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{ .start = 0x00a01010, .end = 0x00a01010 },
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{ .start = 0x00a01018, .end = 0x00a01018 },
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{ .start = 0x00a01024, .end = 0x00a01024 },
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{ .start = 0x00a0102c, .end = 0x00a01034 },
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{ .start = 0x00a0103c, .end = 0x00a01040 },
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{ .start = 0x00a01048, .end = 0x00a01094 },
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{ .start = 0x00a01c00, .end = 0x00a01c20 },
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{ .start = 0x00a01c58, .end = 0x00a01c58 },
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{ .start = 0x00a01c7c, .end = 0x00a01c7c },
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{ .start = 0x00a01c28, .end = 0x00a01c54 },
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{ .start = 0x00a01c5c, .end = 0x00a01c5c },
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{ .start = 0x00a01c60, .end = 0x00a01cdc },
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{ .start = 0x00a01ce0, .end = 0x00a01d0c },
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{ .start = 0x00a01d18, .end = 0x00a01d20 },
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{ .start = 0x00a01d2c, .end = 0x00a01d30 },
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{ .start = 0x00a01d40, .end = 0x00a01d5c },
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{ .start = 0x00a01d80, .end = 0x00a01d80 },
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{ .start = 0x00a01d98, .end = 0x00a01d9c },
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{ .start = 0x00a01da8, .end = 0x00a01da8 },
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{ .start = 0x00a01db8, .end = 0x00a01df4 },
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{ .start = 0x00a01dc0, .end = 0x00a01dfc },
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{ .start = 0x00a01e00, .end = 0x00a01e2c },
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{ .start = 0x00a01e40, .end = 0x00a01e60 },
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{ .start = 0x00a01e68, .end = 0x00a01e6c },
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{ .start = 0x00a01e74, .end = 0x00a01e74 },
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{ .start = 0x00a01e84, .end = 0x00a01e90 },
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{ .start = 0x00a01e9c, .end = 0x00a01ec4 },
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{ .start = 0x00a01ed0, .end = 0x00a01ee0 },
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{ .start = 0x00a01f00, .end = 0x00a01f1c },
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{ .start = 0x00a01f44, .end = 0x00a01ffc },
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{ .start = 0x00a02000, .end = 0x00a02048 },
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{ .start = 0x00a02068, .end = 0x00a020f0 },
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{ .start = 0x00a02100, .end = 0x00a02118 },
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{ .start = 0x00a02140, .end = 0x00a0214c },
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{ .start = 0x00a02168, .end = 0x00a0218c },
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{ .start = 0x00a021c0, .end = 0x00a021c0 },
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{ .start = 0x00a02400, .end = 0x00a02410 },
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{ .start = 0x00a02418, .end = 0x00a02420 },
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{ .start = 0x00a02428, .end = 0x00a0242c },
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{ .start = 0x00a02434, .end = 0x00a02434 },
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{ .start = 0x00a02440, .end = 0x00a02460 },
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{ .start = 0x00a02468, .end = 0x00a024b0 },
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{ .start = 0x00a024c8, .end = 0x00a024cc },
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{ .start = 0x00a02500, .end = 0x00a02504 },
|
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{ .start = 0x00a0250c, .end = 0x00a02510 },
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{ .start = 0x00a02540, .end = 0x00a02554 },
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||||
{ .start = 0x00a02580, .end = 0x00a025f4 },
|
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{ .start = 0x00a02600, .end = 0x00a0260c },
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||||
{ .start = 0x00a02648, .end = 0x00a02650 },
|
||||
{ .start = 0x00a02680, .end = 0x00a02680 },
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||||
{ .start = 0x00a026c0, .end = 0x00a026d0 },
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||||
{ .start = 0x00a02700, .end = 0x00a0270c },
|
||||
{ .start = 0x00a02804, .end = 0x00a02804 },
|
||||
{ .start = 0x00a02818, .end = 0x00a0281c },
|
||||
{ .start = 0x00a02c00, .end = 0x00a02db4 },
|
||||
{ .start = 0x00a02df4, .end = 0x00a02fb0 },
|
||||
{ .start = 0x00a03000, .end = 0x00a03014 },
|
||||
{ .start = 0x00a0301c, .end = 0x00a0302c },
|
||||
{ .start = 0x00a03034, .end = 0x00a03038 },
|
||||
{ .start = 0x00a03040, .end = 0x00a03048 },
|
||||
{ .start = 0x00a03060, .end = 0x00a03068 },
|
||||
{ .start = 0x00a03070, .end = 0x00a03074 },
|
||||
{ .start = 0x00a0307c, .end = 0x00a0307c },
|
||||
{ .start = 0x00a03080, .end = 0x00a03084 },
|
||||
{ .start = 0x00a0308c, .end = 0x00a03090 },
|
||||
{ .start = 0x00a03098, .end = 0x00a03098 },
|
||||
{ .start = 0x00a030a0, .end = 0x00a030a0 },
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{ .start = 0x00a030a8, .end = 0x00a030b4 },
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||||
{ .start = 0x00a030bc, .end = 0x00a030bc },
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{ .start = 0x00a030c0, .end = 0x00a0312c },
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||||
{ .start = 0x00a03c00, .end = 0x00a03c5c },
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||||
{ .start = 0x00a04400, .end = 0x00a04454 },
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||||
{ .start = 0x00a04460, .end = 0x00a04474 },
|
||||
{ .start = 0x00a044c0, .end = 0x00a044ec },
|
||||
{ .start = 0x00a04500, .end = 0x00a04504 },
|
||||
{ .start = 0x00a04510, .end = 0x00a04538 },
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||||
{ .start = 0x00a04540, .end = 0x00a04548 },
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||||
{ .start = 0x00a04560, .end = 0x00a0457c },
|
||||
{ .start = 0x00a04590, .end = 0x00a04598 },
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{ .start = 0x00a045c0, .end = 0x00a045f4 },
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};
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static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
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struct iwl_fw_error_dump_data **data)
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{
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struct iwl_fw_error_dump_prph *prph;
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unsigned long flags;
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u32 prph_len = 0, i;
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||||
if (!iwl_trans_grab_nic_access(trans, false, &flags))
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
|
||||
/* The range includes both boundaries */
|
||||
int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
|
||||
iwl_prph_dump_addr[i].start + 4;
|
||||
int reg;
|
||||
__le32 *val;
|
||||
|
||||
prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
|
||||
|
||||
(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
|
||||
(*data)->len = cpu_to_le32(sizeof(*prph) +
|
||||
num_bytes_in_chunk);
|
||||
prph = (void *)(*data)->data;
|
||||
prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
|
||||
val = (void *)prph->data;
|
||||
|
||||
for (reg = iwl_prph_dump_addr[i].start;
|
||||
reg <= iwl_prph_dump_addr[i].end;
|
||||
reg += 4)
|
||||
*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
|
||||
reg));
|
||||
*data = iwl_fw_error_next_data(*data);
|
||||
}
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
|
||||
return prph_len;
|
||||
}
|
||||
|
||||
static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
|
||||
struct iwl_fw_error_dump_data **data,
|
||||
int allocated_rb_nums)
|
||||
@ -2534,16 +2396,6 @@ static struct iwl_trans_dump_data
|
||||
/* CSR registers */
|
||||
len += sizeof(*data) + IWL_CSR_TO_DUMP;
|
||||
|
||||
/* PRPH registers */
|
||||
for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
|
||||
/* The range includes both boundaries */
|
||||
int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
|
||||
iwl_prph_dump_addr[i].start + 4;
|
||||
|
||||
len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
|
||||
num_bytes_in_chunk;
|
||||
}
|
||||
|
||||
/* FH registers */
|
||||
len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
|
||||
|
||||
@ -2591,7 +2443,6 @@ static struct iwl_trans_dump_data
|
||||
len += sizeof(*data);
|
||||
data = iwl_fw_error_next_data(data);
|
||||
|
||||
len += iwl_trans_pcie_dump_prph(trans, &data);
|
||||
len += iwl_trans_pcie_dump_csr(trans, &data);
|
||||
len += iwl_trans_pcie_fh_regs_dump(trans, &data);
|
||||
if (dump_rbs)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user