Merge tag 'tags/bcm2835-dt-next-2020-09-08' into devicetree/next
Maxime Ripard enables vc4 on BCM2711 (RPi4), which among other things adds HDMI functionality (no 4K yet). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
@@ -68,6 +68,14 @@
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};
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};
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&ddc0 {
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status = "okay";
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};
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&ddc1 {
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status = "okay";
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};
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&firmware {
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firmware_clocks: clocks {
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compatible = "raspberrypi,firmware-clocks";
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@@ -163,6 +171,38 @@
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"RGMII_TXD3";
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};
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&hdmi0 {
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clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
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clock-names = "hdmi", "bvb", "audio", "cec";
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status = "okay";
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};
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&hdmi1 {
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clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
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clock-names = "hdmi", "bvb", "audio", "cec";
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status = "okay";
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};
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&hvs {
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clocks = <&firmware_clocks 4>;
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};
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&pixelvalve0 {
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status = "okay";
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};
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&pixelvalve1 {
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status = "okay";
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};
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&pixelvalve2 {
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status = "okay";
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};
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&pixelvalve4 {
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status = "okay";
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
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@@ -231,3 +271,11 @@
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&vchiq {
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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&vc4 {
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status = "okay";
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};
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&vec {
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status = "disabled";
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};
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@@ -12,6 +12,18 @@
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interrupt-parent = <&gicv2>;
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vc4: gpu {
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compatible = "brcm,bcm2711-vc5";
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status = "disabled";
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};
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clk_27MHz: clk-27M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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clock-output-names = "27MHz-clock";
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};
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clk_108MHz: clk-108M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@@ -238,6 +250,27 @@
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status = "disabled";
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};
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pixelvalve0: pixelvalve@7e206000 {
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compatible = "brcm,bcm2711-pixelvalve0";
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reg = <0x7e206000 0x100>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pixelvalve1: pixelvalve@7e207000 {
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compatible = "brcm,bcm2711-pixelvalve1";
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reg = <0x7e207000 0x100>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pixelvalve2: pixelvalve@7e20a000 {
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compatible = "brcm,bcm2711-pixelvalve2";
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reg = <0x7e20a000 0x100>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pwm1: pwm@7e20c800 {
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compatible = "brcm,bcm2835-pwm";
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reg = <0x7e20c800 0x28>;
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@@ -248,10 +281,25 @@
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status = "disabled";
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};
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hvs@7e400000 {
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pixelvalve4: pixelvalve@7e216000 {
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compatible = "brcm,bcm2711-pixelvalve4";
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reg = <0x7e216000 0x100>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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hvs: hvs@7e400000 {
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compatible = "brcm,bcm2711-hvs";
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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};
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pixelvalve3: pixelvalve@7ec12000 {
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compatible = "brcm,bcm2711-pixelvalve3";
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reg = <0x7ec12000 0x100>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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dvp: clock@7ef00000 {
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compatible = "brcm,brcm2711-dvp";
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reg = <0x7ef00000 0x10>;
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@@ -259,6 +307,78 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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hdmi0: hdmi@7ef00700 {
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compatible = "brcm,bcm2711-hdmi0";
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reg = <0x7ef00700 0x300>,
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<0x7ef00300 0x200>,
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<0x7ef00f00 0x80>,
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<0x7ef00f80 0x80>,
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<0x7ef01b00 0x200>,
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<0x7ef01f00 0x400>,
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<0x7ef00200 0x80>,
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<0x7ef04300 0x100>,
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<0x7ef20000 0x100>;
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reg-names = "hdmi",
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"dvp",
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"phy",
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"rm",
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"packet",
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"metadata",
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"csc",
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"cec",
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"hd";
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clock-names = "hdmi", "bvb", "audio", "cec";
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resets = <&dvp 0>;
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ddc = <&ddc0>;
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dmas = <&dma 10>;
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dma-names = "audio-rx";
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status = "disabled";
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};
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ddc0: i2c@7ef04500 {
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compatible = "brcm,bcm2711-hdmi-i2c";
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reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
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reg-names = "bsc", "auto-i2c";
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clock-frequency = <97500>;
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status = "disabled";
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};
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hdmi1: hdmi@7ef05700 {
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compatible = "brcm,bcm2711-hdmi1";
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reg = <0x7ef05700 0x300>,
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<0x7ef05300 0x200>,
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<0x7ef05f00 0x80>,
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<0x7ef05f80 0x80>,
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<0x7ef06b00 0x200>,
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<0x7ef06f00 0x400>,
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<0x7ef00280 0x80>,
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<0x7ef09300 0x100>,
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<0x7ef20000 0x100>;
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reg-names = "hdmi",
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"dvp",
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"phy",
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"rm",
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"packet",
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"metadata",
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"csc",
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"cec",
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"hd";
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ddc = <&ddc1>;
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clock-names = "hdmi", "bvb", "audio", "cec";
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resets = <&dvp 1>;
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dmas = <&dma 17>;
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dma-names = "audio-rx";
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status = "disabled";
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};
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ddc1: i2c@7ef09500 {
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compatible = "brcm,bcm2711-hdmi-i2c";
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reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
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reg-names = "bsc", "auto-i2c";
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clock-frequency = <97500>;
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status = "disabled";
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};
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};
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/*
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