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Merge branch 'mt7621-dt'

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Arınç ÜNAL says:

====================
dt-bindings and mt7621 devicetree changes

This patch series removes old MediaTek bindings, improves mediatek,mt7530
and mt7621 memory controller bindings and improves mt7621 DTs.

v4:
- Keep memory-controller node name.
- Change syscon to memory-controller on mt7621.dtsi.

v3:
- Explain the mt7621 memory controller binding change in more details.
- Remove explaining the remaining DTC warnings from the patch log as there
are new schemas submitted for them.

v2:
- Change memory controller node name to syscon on the schema example.
- Keep cpu compatible string and syscon on the memory controller node.
- Add Rob and Sergio's tags.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2022-09-23 10:24:59 +01:00
commit 1a4019f492
8 changed files with 80 additions and 166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml
View File

@ -11,7 +11,9 @@ maintainers:
properties:
compatible:
const: mediatek,mt7621-memc
items:
- const: mediatek,mt7621-memc
- const: syscon
reg:
maxItems: 1
@ -25,6 +27,6 @@ additionalProperties: false
examples:
- |
memory-controller@5000 {
compatible = "mediatek,mt7621-memc";
compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};

34
Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
View File

@ -104,7 +104,14 @@ properties:
gpio-controller:
type: boolean
description:
If defined, MT7530's LED controller will run on GPIO mode.
If defined, LED controller of the MT7530 switch will run on GPIO mode.
There are 15 controllable pins.
port 0 LED 0..2 as GPIO 0..2
port 1 LED 0..2 as GPIO 3..5
port 2 LED 0..2 as GPIO 6..8
port 3 LED 0..2 as GPIO 9..11
port 4 LED 0..2 as GPIO 12..14
"#interrupt-cells":
const: 1
@ -263,6 +270,7 @@ allOf:
then:
$ref: "#/$defs/mt7531-dsa-port"
properties:
gpio-controller: false
mediatek,mcm: false
- if:
@ -285,9 +293,9 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch@1f {
compatible = "mediatek,mt7530";
reg = <0>;
reg = <0x1f>;
reset-gpios = <&pio 33 0>;
@ -346,9 +354,9 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch@1f {
compatible = "mediatek,mt7530";
reg = <0>;
reg = <0x1f>;
mediatek,mcm;
resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
@ -474,9 +482,9 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch@1f {
compatible = "mediatek,mt7621";
reg = <0>;
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
@ -560,9 +568,9 @@ examples:
reg = <4>;
};
switch@0 {
switch@1f {
compatible = "mediatek,mt7621";
reg = <0>;
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
@ -650,9 +658,9 @@ examples:
phy-mode = "rgmii";
};
switch@0 {
switch@1f {
compatible = "mediatek,mt7621";
reg = <0>;
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
@ -730,9 +738,9 @@ examples:
phy-mode = "rgmii";
};
switch@0 {
switch@1f {
compatible = "mediatek,mt7621";
reg = <0>;
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;

24
Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt
View File

@ -1,24 +0,0 @@
Mediatek Gigabit Switch
=======================
The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621).
Required properties:
- compatible: Should be "mediatek,mt7620-gsw" or "mediatek,mt7621-gsw"
- reg: Address and length of the register set for the device
- interrupts: Should contain the gigabit switches interrupt
- resets: Should contain the gigabit switches resets
- reset-names: Should contain the reset names "gsw"
Example:
gsw@10110000 {
compatible = "ralink,mt7620-gsw";
reg = <0x10110000 8000>;
resets = <&rstctrl 23>;
reset-names = "gsw";
interrupt-parent = <&intc>;
interrupts = <17>;
};

59
Documentation/devicetree/bindings/net/ralink,rt2880-net.txt
View File

@ -1,59 +0,0 @@
Ralink Frame Engine Ethernet controller
=======================================
The Ralink frame engine ethernet controller can be found on Ralink and
Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).
Depending on the SoC, there is a number of ports connected to the CPU port
directly and/or via a (gigabit-)switch.
* Ethernet controller node
Required properties:
- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
"ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
"mediatek,mt7620-eth", "mediatek,mt7621-eth"
- reg: Address and length of the register set for the device
- interrupts: Should contain the frame engines interrupt
- resets: Should contain the frame engines resets
- reset-names: Should contain the reset names "fe". If a switch is present
"esw" is also required.
* Ethernet port node
Required properties:
- compatible: Should be "ralink,eth-port"
- reg: The number of the physical port
- phy-handle: reference to the node describing the phy
Example:
mdio-bus {
...
phy0: ethernet-phy@0 {
phy-mode = "mii";
reg = <0>;
};
};
ethernet@400000 {
compatible = "ralink,rt2880-eth";
reg = <0x00400000 10000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rstctrl 18>;
reset-names = "fe";
interrupt-parent = <&cpuintc>;
interrupts = <5>;
port@0 {
compatible = "ralink,eth-port";
reg = <0>;
phy-handle = <&phy0>;
};
};

30
Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt
View File

@ -1,30 +0,0 @@
Ralink Fast Ethernet Embedded Switch
====================================
The ralink fast ethernet embedded switch can be found on Ralink and Mediatek
SoCs (RT3x5x, RT5350, MT76x8).
Required properties:
- compatible: Should be "ralink,rt3050-esw"
- reg: Address and length of the register set for the device
- interrupts: Should contain the embedded switches interrupt
- resets: Should contain the embedded switches resets
- reset-names: Should contain the reset names "esw"
Optional properties:
- ralink,portmap: can be used to choose if the default switch setup is
llllw or wllll
- ralink,led_polarity: override the active high/low settings of the leds
Example:
esw@10110000 {
compatible = "ralink,rt3050-esw";
reg = <0x10110000 8000>;
resets = <&rstctrl 23>;
reset-names = "esw";
interrupt-parent = <&intc>;
interrupts = <17>;
};

8
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
View File

@ -20,12 +20,6 @@
bootargs = "console=ttyS0,57600";
};
palmbus: palmbus@1e000000 {
i2c@900 {
status = "okay";
};
};
gpio-keys {
compatible = "gpio-keys";
@ -53,7 +47,7 @@
};
};
&sdhci {
&mmc {
status = "okay";
};

50
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
View File

@ -20,12 +20,6 @@
bootargs = "console=ttyS0,57600";
};
palmbus: palmbus@1e000000 {
i2c@900 {
status = "okay";
};
};
gpio-keys {
compatible = "gpio-keys";
@ -35,9 +29,45 @@
linux,code = <KEY_RESTART>;
};
};
gpio-leds {
compatible = "gpio-leds";
ethblack-green {
label = "green:ethblack";
gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
};
ethblue-green {
label = "green:ethblue";
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
};
ethyellow-green {
label = "green:ethyellow";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
ethyellow-orange {
label = "orange:ethyellow";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
};
power {
label = "green:power";
gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
system {
label = "green:system";
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
linux,default-trigger = "disk-activity";
};
};
};
&sdhci {
&mmc {
status = "okay";
};
@ -83,12 +113,12 @@
&gmac1 {
status = "okay";
phy-handle = <&ethphy7>;
phy-handle = <&ethphy5>;
};
&mdio {
ethphy7: ethernet-phy@7 {
reg = <7>;
ethphy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "rgmii-rxid";
};
};

35
arch/mips/boot/dts/ralink/mt7621.dtsi
View File

@ -33,11 +33,6 @@
compatible = "mti,cpu-interrupt-controller";
};
aliases {
serial0 = &uartlite;
};
mmc_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "mmc_power";
@ -110,17 +105,16 @@
pinctrl-0 = <&i2c_pins>;
};
memc: syscon@5000 {
memc: memory-controller@5000 {
compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
uartlite: uartlite@c00 {
serial0: serial@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
clocks = <&sysc MT7621_CLK_UART1>;
clock-names = "uart1";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
@ -236,7 +230,7 @@
};
};
sdhci: sdhci@1e130000 {
mmc: mmc@1e130000 {
status = "disabled";
compatible = "mediatek,mt7620-mmc";
@ -262,8 +256,8 @@
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
};
xhci: xhci@1e1c0000 {
compatible = "mediatek,mt8173-xhci";
usb: usb@1e1c0000 {
compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
reg = <0x1e1c0000 0x1000
0x1e1d0700 0x0100>;
reg-names = "mac", "ippc";
@ -338,23 +332,22 @@
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
status = "off";
phy-mode = "rgmii-rxid";
status = "disabled";
phy-mode = "rgmii";
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch0: switch0@0 {
switch0: switch@1f {
compatible = "mediatek,mt7621";
reg = <0>;
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ports {
@ -362,31 +355,31 @@
#size-cells = <0>;
port@0 {
status = "off";
status = "disabled";
reg = <0>;
label = "lan0";
};
port@1 {
status = "off";
status = "disabled";
reg = <1>;
label = "lan1";
};
port@2 {
status = "off";
status = "disabled";
reg = <2>;
label = "lan2";
};
port@3 {
status = "off";
status = "disabled";
reg = <3>;
label = "lan3";
};
port@4 {
status = "off";
status = "disabled";
reg = <4>;
label = "lan4";
};