forked from Minki/linux
Lots of updates for mt2701:
Rearrange the dt nodes and fix unit address for pincontroler Add nodes for: - clock controller subsystems - scpsys controller - iommu and smi - spi - nand - auxadc - thermal controller and zones Email address updated for mt7623 devicetree files. -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAliIioEXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00Nn5BAAho8TohilGoDXa6aozC74sQf3 w3ew/0DwdtUrPe6jS0MM9KAlscCiA+wcDKcg8bOoH9IlDBMkU1xFSDGjIKwEotL5 +qKmYse+8SV/TAlCKkHGROT7DTIS3/mC0v57mAGglJ47Z4D1aFVFeWTxEUfj9VxE pwGH4rZJ+qUw1fMnYZBmbdg5iA4J6q54gXi62l1BnhF6qSvv6fJTsx7l5kT8+viU alUmQLvHPoOVxDfXHAUgvhIgzoK1tcvMeO4nqSZ+upoMX+Tq9wyrSbyXQsIoThOd GnjVUFV6YfniG2pUzqdA+g30ptTK8Itcb/xy3U4/FIHQjMLL+0SmdQQ8yqH5CPE1 pK2uJbJUobrc2bL+faV+GAju1tnvQtccwuVjILAtR6tLzPb/Sr/j5+2BfAmolteb m4FxZEmwA+FWV9VX/ky554iXXz7QfMeEJEFRH9lAOaegBRYLykdXkWLTWZITZxDu b97mmfcD+MCgZETRmmfPH0/xed1CwrWp1A8hfub4O04EvSPTr47M5J8k3yAf8z/4 dsGi/KCddeHP7K+mQMvsl7jYWXGbhOZX/jUXB8UniDeDBN7i3XGK4whoxKY2E2I7 2ZLArji2obym1xy9KR7DYhhJUEbTxprMimV5K6BKAW2SGpFbZFAiJTbl80GWjIFb Xx3obOE7qA5LE74qwUY= =MxSr -----END PGP SIGNATURE----- Merge tag 'v4.10-next-dts32' of https://github.com/mbgg/linux-mediatek into next/dt Lots of updates for mt2701: Rearrange the dt nodes and fix unit address for pincontroler Add nodes for: - clock controller subsystems - scpsys controller - iommu and smi - spi - nand - auxadc - thermal controller and zones Email address updated for mt7623 devicetree files. * tag 'v4.10-next-dts32' of https://github.com/mbgg/linux-mediatek: arm: dts: mt2701: Add thermal device node. arm: dts: mt2701: Add auxadc device node. arm: dts: mt2701: Add nand device node arm: dts: mt2701: Add spi device node ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 ARM: dts: mediatek: update my email address arm: dts: mt2701: Add power domain controller device node arm: dts: mt2701: Add subsystem clock controller device nodes arm: dts: mt2701: Sort DT nodes by register address Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
1a0c4ca509
@ -24,6 +24,60 @@
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};
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};
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&auxadc {
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status = "okay";
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};
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&pio {
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spi_pins_a: spi0@0 {
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pins_spi {
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pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
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<MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
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<MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
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<MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
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bias-disable;
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};
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};
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spi_pins_b: spi1@0 {
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pins_spi {
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pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
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<MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
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<MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
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<MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
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bias-disable;
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};
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};
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spi_pins_c: spi2@0 {
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pins_spi {
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pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
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<MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
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<MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
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<MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
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bias-disable;
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins_a>;
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status = "disabled";
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins_b>;
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status = "disabled";
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};
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&spi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins_c>;
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status = "disabled";
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};
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&uart0 {
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status = "okay";
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};
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@ -13,6 +13,7 @@
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*/
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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@ -87,6 +88,36 @@
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clock-output-names = "rtc32k";
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};
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thermal-zones {
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <1000>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&thermal 0>;
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sustainable-power = <1000>;
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trips {
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threshold: trip-point@0 {
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temperature = <68000>;
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hysteresis = <2000>;
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type = "passive";
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};
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target: trip-point@1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit@0 {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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@ -96,24 +127,6 @@
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt2701-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt2701-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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@ -134,6 +147,22 @@
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#reset-cells = <1>;
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};
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt2701-scpsys", "syscon";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_MFG_SEL>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "mm", "mfg", "ethif";
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt2701-wdt",
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"mediatek,mt6589-wdt";
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@ -149,6 +178,29 @@
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clock-names = "system-clk", "rtc-clk";
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};
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pio: pinctrl@1000b000 {
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compatible = "mediatek,mt2701-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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smi_common: smi@1000c000 {
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compatible = "mediatek,mt2701-smi-common";
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reg = <0 0x1000c000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_SMI>,
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<&mmsys CLK_MM_SMI_COMMON>,
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<&infracfg CLK_INFRA_SMI>;
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt2701-sysirq",
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"mediatek,mt6577-sysirq";
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@ -158,6 +210,16 @@
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reg = <0 0x10200100 0 0x1c>;
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};
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iommu: mmsys_iommu@10205000 {
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compatible = "mediatek,mt2701-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2>;
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#iommu-cells = <1>;
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt2701-apmixedsys", "syscon";
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reg = <0 0x10209000 0 0x1000>;
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@ -175,6 +237,15 @@
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<0 0x10216000 0 0x2000>;
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};
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auxadc: adc@11001000 {
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compatible = "mediatek,mt2701-auxadc";
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reg = <0 0x11001000 0 0x1000>;
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clocks = <&pericfg CLK_PERI_AUXADC>;
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clock-names = "main";
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#io-channel-cells = <1>;
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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@ -214,4 +285,144 @@
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clock-names = "baud", "bus";
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI0_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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thermal: thermal@1100b000 {
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#thermal-sensor-cells = <0>;
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compatible = "mediatek,mt2701-thermal";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
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clock-names = "therm", "auxadc";
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resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
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reset-names = "therm";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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};
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nandc: nfi@1100d000 {
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compatible = "mediatek,mt2701-nfc";
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reg = <0 0x1100d000 0 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI>,
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<&pericfg CLK_PERI_NFI_PAD>;
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clock-names = "nfi_clk", "pad_clk";
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status = "disabled";
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ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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bch: ecc@1100e000 {
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compatible = "mediatek,mt2701-ecc";
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reg = <0 0x1100e000 0 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_ECC>;
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clock-names = "nfiecc_clk";
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status = "disabled";
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};
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spi1: spi@11016000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11016000 0 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI1_SEL>,
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<&pericfg CLK_PERI_SPI1>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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spi2: spi@11017000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11017000 0 0x1000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI2_SEL>,
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<&pericfg CLK_PERI_SPI2>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt2701-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb0: larb@14010000 {
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compatible = "mediatek,mt2701-smi-larb";
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reg = <0 0x14010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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clocks = <&mmsys CLK_MM_SMI_LARB0>,
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<&mmsys CLK_MM_SMI_LARB0>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt2701-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb2: larb@15001000 {
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compatible = "mediatek,mt2701-smi-larb";
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reg = <0 0x15001000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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clocks = <&imgsys CLK_IMG_SMI_COMM>,
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<&imgsys CLK_IMG_SMI_COMM>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt2701-vdecsys", "syscon";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb1: larb@16010000 {
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compatible = "mediatek,mt2701-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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clocks = <&vdecsys CLK_VDEC_CKGEN>,
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<&vdecsys CLK_VDEC_LARB>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
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||||
};
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hifsys: syscon@1a000000 {
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||||
compatible = "mediatek,mt2701-hifsys", "syscon";
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||||
reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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||||
};
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||||
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||||
ethsys: syscon@1b000000 {
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||||
compatible = "mediatek,mt2701-ethsys", "syscon";
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||||
reg = <0 0x1b000000 0 0x1000>;
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||||
#clock-cells = <1>;
|
||||
};
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||||
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||||
bdpsys: syscon@1c000000 {
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||||
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
||||
reg = <0 0x1c000000 0 0x1000>;
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||||
#clock-cells = <1>;
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||||
};
|
||||
};
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||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2016 MediaTek Inc.
|
||||
* Author: John Crispin <blogic@openwrt.org>
|
||||
* Author: John Crispin <john@phrozen.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
||||
@ -1,6 +1,6 @@
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||||
/*
|
||||
* Copyright (c) 2016 MediaTek Inc.
|
||||
* Author: John Crispin <blogic@openwrt.org>
|
||||
* Author: John Crispin <john@phrozen.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
||||
Loading…
Reference in New Issue
Block a user