forked from Minki/linux
serial: xuartps: Get rid of register access macros.
Get rid of cdns_uart_readl() and cdns_uart_writel() and just call readl() and writel() directly. Most of the patch was created by search-and-replace (I had to convert a few lines manually, and break some lines longer than 80 columns): * s/cdns_uart_readl(/readl(port->membase + /g * s/cdns_uart_writel(\([^,]*\),/writel(\1, port->membase +/g Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Thomas Betker
Greg Kroah-Hartman
parent
0c39a467e7
commit
19f22efdb6
@ -39,9 +39,6 @@
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#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
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#define CDNS_UART_REGISTER_SPACE 0x1000
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#define cdns_uart_readl(offset) ioread32(port->membase + offset)
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#define cdns_uart_writel(val, offset) iowrite32(val, port->membase + offset)
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/* Rx Trigger level */
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static int rx_trigger_level = 56;
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module_param(rx_trigger_level, uint, S_IRUGO);
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@ -195,7 +192,7 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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/* Read the interrupt status register to determine which
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* interrupt(s) is/are active.
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*/
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isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET);
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isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET);
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/*
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* There is no hardware break detection, so we interpret framing
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@ -203,14 +200,15 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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* there's another non-zero byte at the end of the sequence.
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*/
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if (isrstatus & CDNS_UART_IXR_FRAMING) {
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while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
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while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
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CDNS_UART_SR_RXEMPTY)) {
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if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) {
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if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) {
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port->read_status_mask |= CDNS_UART_IXR_BRK;
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isrstatus &= ~CDNS_UART_IXR_FRAMING;
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}
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}
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cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET);
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writel(CDNS_UART_IXR_FRAMING,
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port->membase + CDNS_UART_ISR_OFFSET);
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}
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/* drop byte with parity error if IGNPAR specified */
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@ -223,9 +221,9 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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if ((isrstatus & CDNS_UART_IXR_TOUT) ||
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(isrstatus & CDNS_UART_IXR_RXTRIG)) {
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/* Receive Timeout Interrupt */
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while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
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CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
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data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
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while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
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CDNS_UART_SR_RXEMPTY)) {
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data = readl(port->membase + CDNS_UART_FIFO_OFFSET);
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/* Non-NULL byte after BREAK is garbage (99%) */
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if (data && (port->read_status_mask &
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@ -275,8 +273,8 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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/* Dispatch an appropriate handler */
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if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
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if (uart_circ_empty(&port->state->xmit)) {
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cdns_uart_writel(CDNS_UART_IXR_TXEMPTY,
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CDNS_UART_IDR_OFFSET);
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writel(CDNS_UART_IXR_TXEMPTY,
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port->membase + CDNS_UART_IDR_OFFSET);
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} else {
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numbytes = port->fifosize;
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/* Break if no more data available in the UART buffer */
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@ -287,9 +285,9 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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* and write it to the cdns_uart's TX_FIFO
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* register.
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*/
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cdns_uart_writel(
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port->state->xmit.buf[port->state->xmit.
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tail], CDNS_UART_FIFO_OFFSET);
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writel(port->state->xmit.buf[
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port->state->xmit.tail],
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port->membase + CDNS_UART_FIFO_OFFSET);
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port->icount.tx++;
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@ -307,7 +305,7 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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}
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}
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cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET);
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writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET);
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/* be sure to release the lock and tty before leaving */
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spin_unlock_irqrestore(&port->lock, flags);
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@ -397,14 +395,14 @@ static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
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&div8);
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/* Write new divisors to hardware */
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mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
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mreg = readl(port->membase + CDNS_UART_MR_OFFSET);
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if (div8)
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mreg |= CDNS_UART_MR_CLKSEL;
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else
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mreg &= ~CDNS_UART_MR_CLKSEL;
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cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET);
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cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET);
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cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET);
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writel(mreg, port->membase + CDNS_UART_MR_OFFSET);
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writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET);
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writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET);
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cdns_uart->baud = baud;
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return calc_baud;
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@ -451,9 +449,9 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
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spin_lock_irqsave(&cdns_uart->port->lock, flags);
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/* Disable the TX and RX to set baud rate */
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ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
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cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
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@ -478,11 +476,11 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
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spin_lock_irqsave(&cdns_uart->port->lock, flags);
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/* Set TX/RX Reset */
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ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
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cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
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while (readl(port->membase + CDNS_UART_CR_OFFSET) &
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(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
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cpu_relax();
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@ -491,11 +489,11 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
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* enable bit and RX enable bit to enable the transmitter and
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* receiver.
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*/
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cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
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ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
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ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
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cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
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@ -517,14 +515,14 @@ static void cdns_uart_start_tx(struct uart_port *port)
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if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
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return;
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status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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status = readl(port->membase + CDNS_UART_CR_OFFSET);
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/* Set the TX enable bit and clear the TX disable bit to enable the
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* transmitter.
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*/
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cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
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CDNS_UART_CR_OFFSET);
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writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
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port->membase + CDNS_UART_CR_OFFSET);
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while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
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while (numbytes-- && ((readl(port->membase + CDNS_UART_SR_OFFSET) &
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CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
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/* Break if no more data available in the UART buffer */
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if (uart_circ_empty(&port->state->xmit))
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@ -533,9 +531,8 @@ static void cdns_uart_start_tx(struct uart_port *port)
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/* Get the data from the UART circular buffer and
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* write it to the cdns_uart's TX_FIFO register.
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*/
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cdns_uart_writel(
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port->state->xmit.buf[port->state->xmit.tail],
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CDNS_UART_FIFO_OFFSET);
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writel(port->state->xmit.buf[port->state->xmit.tail],
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port->membase + CDNS_UART_FIFO_OFFSET);
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port->icount.tx++;
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/* Adjust the tail of the UART buffer and wrap
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@ -544,9 +541,9 @@ static void cdns_uart_start_tx(struct uart_port *port)
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port->state->xmit.tail = (port->state->xmit.tail + 1) &
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(UART_XMIT_SIZE - 1);
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}
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cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET);
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writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET);
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/* Enable the TX Empty interrupt */
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cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET);
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writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET);
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if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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@ -560,10 +557,10 @@ static void cdns_uart_stop_tx(struct uart_port *port)
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{
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unsigned int regval;
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regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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regval = readl(port->membase + CDNS_UART_CR_OFFSET);
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regval |= CDNS_UART_CR_TX_DIS;
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/* Disable the transmitter */
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cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
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writel(regval, port->membase + CDNS_UART_CR_OFFSET);
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}
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/**
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@ -574,10 +571,10 @@ static void cdns_uart_stop_rx(struct uart_port *port)
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{
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unsigned int regval;
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regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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regval = readl(port->membase + CDNS_UART_CR_OFFSET);
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regval |= CDNS_UART_CR_RX_DIS;
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/* Disable the receiver */
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cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
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writel(regval, port->membase + CDNS_UART_CR_OFFSET);
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}
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/**
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@ -590,7 +587,8 @@ static unsigned int cdns_uart_tx_empty(struct uart_port *port)
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{
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unsigned int status;
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status = cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY;
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status = readl(port->membase + CDNS_UART_SR_OFFSET) &
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CDNS_UART_SR_TXEMPTY;
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return status ? TIOCSER_TEMT : 0;
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}
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@ -607,15 +605,15 @@ static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
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spin_lock_irqsave(&port->lock, flags);
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status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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status = readl(port->membase + CDNS_UART_CR_OFFSET);
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if (ctl == -1)
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cdns_uart_writel(CDNS_UART_CR_STARTBRK | status,
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CDNS_UART_CR_OFFSET);
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writel(CDNS_UART_CR_STARTBRK | status,
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port->membase + CDNS_UART_CR_OFFSET);
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else {
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if ((status & CDNS_UART_CR_STOPBRK) == 0)
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cdns_uart_writel(CDNS_UART_CR_STOPBRK | status,
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CDNS_UART_CR_OFFSET);
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writel(CDNS_UART_CR_STOPBRK | status,
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port->membase + CDNS_UART_CR_OFFSET);
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}
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@ -638,17 +636,18 @@ static void cdns_uart_set_termios(struct uart_port *port,
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spin_lock_irqsave(&port->lock, flags);
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/* Wait for the transmit FIFO to empty before making changes */
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if (!(cdns_uart_readl(CDNS_UART_CR_OFFSET) & CDNS_UART_CR_TX_DIS)) {
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while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
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if (!(readl(port->membase + CDNS_UART_CR_OFFSET) &
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CDNS_UART_CR_TX_DIS)) {
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while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
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CDNS_UART_SR_TXEMPTY)) {
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cpu_relax();
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}
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}
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/* Disable the TX and RX to set baud rate */
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ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
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cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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/*
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* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
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@ -667,20 +666,20 @@ static void cdns_uart_set_termios(struct uart_port *port,
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uart_update_timeout(port, termios->c_cflag, baud);
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/* Set TX/RX Reset */
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ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
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cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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/*
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* Clear the RX disable and TX disable bits and then set the TX enable
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* bit and RX enable bit to enable the transmitter and receiver.
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*/
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ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
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ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
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cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
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writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
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port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
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CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
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@ -700,7 +699,7 @@ static void cdns_uart_set_termios(struct uart_port *port,
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CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
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CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
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mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
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mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET);
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/* Handling Data Size */
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switch (termios->c_cflag & CSIZE) {
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@ -741,7 +740,7 @@ static void cdns_uart_set_termios(struct uart_port *port,
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cval |= CDNS_UART_MR_PARITY_NONE;
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}
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cval |= mode_reg & 1;
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cdns_uart_writel(cval, CDNS_UART_MR_OFFSET);
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writel(cval, port->membase + CDNS_UART_MR_OFFSET);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@ -762,52 +761,53 @@ static int cdns_uart_startup(struct uart_port *port)
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return retval;
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/* Disable the TX and RX */
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cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
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CDNS_UART_CR_OFFSET);
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writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
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port->membase + CDNS_UART_CR_OFFSET);
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/* Set the Control Register with TX/RX Enable, TX/RX Reset,
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* no break chars.
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*/
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cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
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CDNS_UART_CR_OFFSET);
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writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
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port->membase + CDNS_UART_CR_OFFSET);
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status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
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status = readl(port->membase + CDNS_UART_CR_OFFSET);
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/* Clear the RX disable and TX disable bits and then set the TX enable
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* bit and RX enable bit to enable the transmitter and receiver.
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*/
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cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS))
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writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS))
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| (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN |
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CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET);
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CDNS_UART_CR_STOPBRK),
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port->membase + CDNS_UART_CR_OFFSET);
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/* Set the Mode Register with normal mode,8 data bits,1 stop bit,
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* no parity.
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*/
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cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
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writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
|
||||
| CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
|
||||
CDNS_UART_MR_OFFSET);
|
||||
port->membase + CDNS_UART_MR_OFFSET);
|
||||
|
||||
/*
|
||||
* Set the RX FIFO Trigger level to use most of the FIFO, but it
|
||||
* can be tuned with a module parameter
|
||||
*/
|
||||
cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
|
||||
writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET);
|
||||
|
||||
/*
|
||||
* Receive Timeout register is enabled but it
|
||||
* can be tuned with a module parameter
|
||||
*/
|
||||
cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
|
||||
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
|
||||
|
||||
/* Clear out any pending interrupts before enabling them */
|
||||
cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET),
|
||||
CDNS_UART_ISR_OFFSET);
|
||||
writel(readl(port->membase + CDNS_UART_ISR_OFFSET),
|
||||
port->membase + CDNS_UART_ISR_OFFSET);
|
||||
|
||||
/* Set the Interrupt Registers with desired interrupts */
|
||||
cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
|
||||
writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
|
||||
CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN |
|
||||
CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT,
|
||||
CDNS_UART_IER_OFFSET);
|
||||
port->membase + CDNS_UART_IER_OFFSET);
|
||||
|
||||
return retval;
|
||||
}
|
||||
@ -821,12 +821,12 @@ static void cdns_uart_shutdown(struct uart_port *port)
|
||||
int status;
|
||||
|
||||
/* Disable interrupts */
|
||||
status = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
|
||||
cdns_uart_writel(status, CDNS_UART_IDR_OFFSET);
|
||||
status = readl(port->membase + CDNS_UART_IMR_OFFSET);
|
||||
writel(status, port->membase + CDNS_UART_IDR_OFFSET);
|
||||
|
||||
/* Disable the TX and RX */
|
||||
cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
|
||||
CDNS_UART_CR_OFFSET);
|
||||
writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
|
||||
port->membase + CDNS_UART_CR_OFFSET);
|
||||
free_irq(port->irq, port);
|
||||
}
|
||||
|
||||
@ -928,7 +928,7 @@ static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = cdns_uart_readl(CDNS_UART_MODEMCR_OFFSET);
|
||||
val = readl(port->membase + CDNS_UART_MODEMCR_OFFSET);
|
||||
|
||||
val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
|
||||
|
||||
@ -937,7 +937,7 @@ static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
if (mctrl & TIOCM_DTR)
|
||||
val |= CDNS_UART_MODEMCR_DTR;
|
||||
|
||||
cdns_uart_writel(val, CDNS_UART_MODEMCR_OFFSET);
|
||||
writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CONSOLE_POLL
|
||||
@ -947,17 +947,18 @@ static int cdns_uart_poll_get_char(struct uart_port *port)
|
||||
int c;
|
||||
|
||||
/* Disable all interrupts */
|
||||
imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
|
||||
cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
|
||||
imr = readl(port->membase + CDNS_UART_IMR_OFFSET);
|
||||
writel(imr, port->membase + CDNS_UART_IDR_OFFSET);
|
||||
|
||||
/* Check if FIFO is empty */
|
||||
if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
|
||||
if (readl(port->membase + CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
|
||||
c = NO_POLL_CHAR;
|
||||
else /* Read a character */
|
||||
c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
|
||||
c = (unsigned char) readl(
|
||||
port->membase + CDNS_UART_FIFO_OFFSET);
|
||||
|
||||
/* Enable interrupts */
|
||||
cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
|
||||
writel(imr, port->membase + CDNS_UART_IER_OFFSET);
|
||||
|
||||
return c;
|
||||
}
|
||||
@ -967,22 +968,24 @@ static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
|
||||
u32 imr;
|
||||
|
||||
/* Disable all interrupts */
|
||||
imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
|
||||
cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
|
||||
imr = readl(port->membase + CDNS_UART_IMR_OFFSET);
|
||||
writel(imr, port->membase + CDNS_UART_IDR_OFFSET);
|
||||
|
||||
/* Wait until FIFO is empty */
|
||||
while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
|
||||
while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
|
||||
CDNS_UART_SR_TXEMPTY))
|
||||
cpu_relax();
|
||||
|
||||
/* Write a character */
|
||||
cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET);
|
||||
writel(c, port->membase + CDNS_UART_FIFO_OFFSET);
|
||||
|
||||
/* Wait until FIFO is empty */
|
||||
while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
|
||||
while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
|
||||
CDNS_UART_SR_TXEMPTY))
|
||||
cpu_relax();
|
||||
|
||||
/* Enable interrupts */
|
||||
cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
|
||||
writel(imr, port->membase + CDNS_UART_IER_OFFSET);
|
||||
|
||||
return;
|
||||
}
|
||||
@ -1056,8 +1059,8 @@ static struct uart_port *cdns_uart_get_port(int id)
|
||||
*/
|
||||
static void cdns_uart_console_wait_tx(struct uart_port *port)
|
||||
{
|
||||
while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)
|
||||
!= CDNS_UART_SR_TXEMPTY)
|
||||
while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
|
||||
CDNS_UART_SR_TXEMPTY))
|
||||
barrier();
|
||||
}
|
||||
|
||||
@ -1069,7 +1072,7 @@ static void cdns_uart_console_wait_tx(struct uart_port *port)
|
||||
static void cdns_uart_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
cdns_uart_console_wait_tx(port);
|
||||
cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET);
|
||||
writel(ch, port->membase + CDNS_UART_FIFO_OFFSET);
|
||||
}
|
||||
|
||||
static void cdns_early_write(struct console *con, const char *s, unsigned n)
|
||||
@ -1111,24 +1114,24 @@ static void cdns_uart_console_write(struct console *co, const char *s,
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* save and disable interrupt */
|
||||
imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
|
||||
cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
|
||||
imr = readl(port->membase + CDNS_UART_IMR_OFFSET);
|
||||
writel(imr, port->membase + CDNS_UART_IDR_OFFSET);
|
||||
|
||||
/*
|
||||
* Make sure that the tx part is enabled. Set the TX enable bit and
|
||||
* clear the TX disable bit to enable the transmitter.
|
||||
*/
|
||||
ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET);
|
||||
cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
|
||||
CDNS_UART_CR_OFFSET);
|
||||
ctrl = readl(port->membase + CDNS_UART_CR_OFFSET);
|
||||
writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
|
||||
port->membase + CDNS_UART_CR_OFFSET);
|
||||
|
||||
uart_console_write(port, s, count, cdns_uart_console_putchar);
|
||||
cdns_uart_console_wait_tx(port);
|
||||
|
||||
cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET);
|
||||
writel(ctrl, port->membase + CDNS_UART_CR_OFFSET);
|
||||
|
||||
/* restore interrupt state */
|
||||
cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
|
||||
writel(imr, port->membase + CDNS_UART_IER_OFFSET);
|
||||
|
||||
if (locked)
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
@ -1240,13 +1243,14 @@ static int cdns_uart_suspend(struct device *device)
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
/* Empty the receive FIFO 1st before making changes */
|
||||
while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
|
||||
while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
|
||||
CDNS_UART_SR_RXEMPTY))
|
||||
cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
|
||||
readl(port->membase + CDNS_UART_FIFO_OFFSET);
|
||||
/* set RX trigger level to 1 */
|
||||
cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET);
|
||||
writel(1, port->membase + CDNS_UART_RXWM_OFFSET);
|
||||
/* disable RX timeout interrups */
|
||||
cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET);
|
||||
writel(CDNS_UART_IXR_TOUT,
|
||||
port->membase + CDNS_UART_IDR_OFFSET);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
@ -1285,28 +1289,30 @@ static int cdns_uart_resume(struct device *device)
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* Set TX/RX Reset */
|
||||
ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
|
||||
ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
|
||||
ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
|
||||
cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
|
||||
while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
|
||||
writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
|
||||
while (readl(port->membase + CDNS_UART_CR_OFFSET) &
|
||||
(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
|
||||
cpu_relax();
|
||||
|
||||
/* restore rx timeout value */
|
||||
cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
|
||||
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
|
||||
/* Enable Tx/Rx */
|
||||
ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
|
||||
ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
|
||||
ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
|
||||
ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
|
||||
cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
|
||||
writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
} else {
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
/* restore original rx trigger level */
|
||||
cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
|
||||
writel(rx_trigger_level,
|
||||
port->membase + CDNS_UART_RXWM_OFFSET);
|
||||
/* enable RX timeout interrupt */
|
||||
cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET);
|
||||
writel(CDNS_UART_IXR_TOUT,
|
||||
port->membase + CDNS_UART_IER_OFFSET);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user