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drm/amd/display: Set addressable region as active + border

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This ensures that we do not draw the blank region onscreen, and that we
do underscan instead.

Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2017-10-05 19:15:25 -04:00 committed by Alex Deucher
parent 215a6f05bc
commit 199e458aaf
1 changed files with 14 additions and 0 deletions
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14
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
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@ -850,6 +850,20 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
*/
pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
/**
* KMD sends us h and v_addressable without the borders, which causes us sometimes to draw
* the blank region on-screen. Correct for this by adding the borders back to their
* respective addressable values, and by shifting recout.
*/
timing->h_addressable += timing->h_border_left + timing->h_border_right;
timing->v_addressable += timing->v_border_top + timing->v_border_bottom;
pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
timing->v_border_top = 0;
timing->v_border_bottom = 0;
timing->h_border_left = 0;
timing->h_border_right = 0;
pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable;
pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable;