forked from Minki/linux
drm/amdgpu/gfx9: allow updating gfx cgpg state
Wire up the enable functions to enable coarse grained powegating. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1960,6 +1960,38 @@ static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
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}
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}
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static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t data, default_data;
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default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
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if (enable == true)
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data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
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else
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data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
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if(default_data != data)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
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}
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static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t data, default_data;
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default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
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if (enable == true)
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data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
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else
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data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
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if(default_data != data)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
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if (!enable)
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/* read any GFX register to wake up GFX */
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data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
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}
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static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
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{
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if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
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@ -3209,6 +3241,24 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
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}
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}
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static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
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bool enable)
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{
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/* TODO: double check if we need to perform under safe mdoe */
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/* gfx_v9_0_enter_rlc_safe_mode(adev); */
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if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
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gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
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if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
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gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
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} else {
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gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
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gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
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}
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/* gfx_v9_0_exit_rlc_safe_mode(adev); */
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}
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static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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@ -3400,6 +3450,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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@ -3415,6 +3466,9 @@ static int gfx_v9_0_set_powergating_state(void *handle,
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gfx_v9_0_enable_cp_power_gating(adev, true);
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else
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gfx_v9_0_enable_cp_power_gating(adev, false);
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/* update gfx cgpg state */
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gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
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break;
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default:
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break;
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