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ARM: dts: porter: Enable SCIF_CLK frequency and pins

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Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2016-01-29 11:17:24 +01:00 committed by Simon Horman
parent e50b5ac88d
commit 19417bd9c5
1 changed files with 13 additions and 0 deletions
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13
arch/arm/boot/dts/r8a7791-porter.dts
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@ -143,11 +143,19 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif0_pins: serial0 { scif0_pins: serial0 {
renesas,groups = "scif0_data_d"; renesas,groups = "scif0_data_d";
renesas,function = "scif0"; renesas,function = "scif0";
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether { ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth"; renesas,function = "eth";
@ -221,6 +229,11 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&ether { &ether {
pinctrl-0 = <&ether_pins &phy1_pins>; pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";