forked from Minki/linux
mtd: pxa3xx_nand: remove the flash info in driver structure
After probe, all info already transfer to driver structure. There is no need to keep the original flash info. So that we could safely free the flash info in memory, which may grows larger when more flash is suported. Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Lei Wen
David Woodhouse
parent
227a886c7e
commit
18c81b1828
@ -117,7 +117,7 @@ struct pxa3xx_nand_info {
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struct nand_chip nand_chip;
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struct platform_device *pdev;
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const struct pxa3xx_nand_flash *flash_info;
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struct pxa3xx_nand_cmdset *cmdset;
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struct clk *clk;
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void __iomem *mmio_base;
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@ -131,6 +131,7 @@ struct pxa3xx_nand_info {
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int drcmr_cmd;
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unsigned char *data_buff;
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unsigned char *oob_buff;
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dma_addr_t data_buff_phys;
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size_t data_buff_size;
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int data_dma_ch;
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@ -149,7 +150,8 @@ struct pxa3xx_nand_info {
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int use_ecc; /* use HW ECC ? */
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int use_dma; /* use DMA ? */
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size_t data_size; /* data size in FIFO */
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unsigned int page_size; /* page size of attached chip */
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unsigned int data_size; /* data size in FIFO */
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int retcode;
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struct completion cmd_complete;
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@ -158,6 +160,10 @@ struct pxa3xx_nand_info {
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uint32_t ndcb1;
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uint32_t ndcb2;
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/* timing calcuted from setting */
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uint32_t ndtr0cs0;
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uint32_t ndtr1cs0;
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/* calculated from pxa3xx_nand_flash data */
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size_t oob_size;
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size_t read_id_bytes;
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@ -174,8 +180,6 @@ MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
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* Default NAND flash controller configuration setup by the
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* bootloader. This configuration is used only when pdata->keep_config is set
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*/
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static struct pxa3xx_nand_timing default_timing;
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static struct pxa3xx_nand_flash default_flash;
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static struct pxa3xx_nand_cmdset default_cmdset = {
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.read1 = 0x3000,
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.read2 = 0x0050,
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@ -222,23 +226,9 @@ static struct pxa3xx_nand_flash builtin_flash_types[] = {
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#define NDTR1_tWHR(c) (min((c), 15) << 4)
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#define NDTR1_tAR(c) (min((c), 15) << 0)
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#define tCH_NDTR0(r) (((r) >> 19) & 0x7)
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#define tCS_NDTR0(r) (((r) >> 16) & 0x7)
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#define tWH_NDTR0(r) (((r) >> 11) & 0x7)
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#define tWP_NDTR0(r) (((r) >> 8) & 0x7)
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#define tRH_NDTR0(r) (((r) >> 3) & 0x7)
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#define tRP_NDTR0(r) (((r) >> 0) & 0x7)
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#define tR_NDTR1(r) (((r) >> 16) & 0xffff)
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#define tWHR_NDTR1(r) (((r) >> 4) & 0xf)
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#define tAR_NDTR1(r) (((r) >> 0) & 0xf)
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/* convert nano-seconds to nand flash controller clock cycles */
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#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
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/* convert nand flash controller clock cycles to nano-seconds */
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#define cycle2ns(c, clk) ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
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static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
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const struct pxa3xx_nand_timing *t)
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{
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@ -256,6 +246,8 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
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NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
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NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
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info->ndtr0cs0 = ndtr0;
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info->ndtr1cs0 = ndtr1;
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nand_writel(info, NDTR0CS0, ndtr0);
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nand_writel(info, NDTR1CS0, ndtr1);
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}
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@ -279,23 +271,24 @@ static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
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return -ETIMEDOUT;
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}
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static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
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uint16_t cmd, int column, int page_addr)
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static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
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{
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const struct pxa3xx_nand_flash *f = info->flash_info;
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const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
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/* calculate data size */
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switch (f->page_size) {
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switch (info->page_size) {
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case 2048:
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info->data_size = (info->use_ecc) ? 2088 : 2112;
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break;
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case 512:
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info->data_size = (info->use_ecc) ? 520 : 528;
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break;
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default:
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return -EINVAL;
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}
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}
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static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
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uint16_t cmd, int column, int page_addr)
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{
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const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
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pxa3xx_set_datasize(info);
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/* generate values for NDCBx registers */
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info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
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@ -334,7 +327,7 @@ static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
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static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
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{
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const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
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const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
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info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
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info->ndcb1 = 0;
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@ -571,8 +564,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
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int column, int page_addr)
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{
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struct pxa3xx_nand_info *info = mtd->priv;
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const struct pxa3xx_nand_flash *flash_info = info->flash_info;
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const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
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const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
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int ret;
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info->use_dma = (use_dma) ? 1 : 0;
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@ -796,8 +788,7 @@ static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
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static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
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{
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const struct pxa3xx_nand_flash *f = info->flash_info;
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const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
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const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
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uint32_t ndcr;
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uint8_t id_buff[8];
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@ -839,6 +830,9 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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return -EINVAL;
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/* calculate flash information */
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info->cmdset = f->cmdset;
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info->page_size = f->page_size;
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info->oob_buff = info->data_buff + f->page_size;
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info->oob_size = (f->page_size == 2048) ? 64 : 16;
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info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
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@ -863,44 +857,20 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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info->reg_ndcr = ndcr;
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pxa3xx_nand_set_timing(info, f->timing);
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info->flash_info = f;
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return 0;
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}
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static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
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struct pxa3xx_nand_timing *t)
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{
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unsigned long nand_clk = clk_get_rate(info->clk);
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uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
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uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
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t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
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t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
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t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
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t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
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t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
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t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
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t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
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t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
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t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
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}
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static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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{
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uint32_t ndcr = nand_readl(info, NDCR);
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struct nand_flash_dev *type = NULL;
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uint32_t id = -1;
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uint32_t id = -1, page_per_block, num_blocks;
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int i;
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default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
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default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
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default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
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default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
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page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
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info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
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/* set info fields needed to __readid */
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info->flash_info = &default_flash;
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info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
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info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
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info->reg_ndcr = ndcr;
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if (__readid(info, &id))
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@ -919,22 +889,22 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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return -ENODEV;
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/* fill the missing flash information */
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i = __ffs(default_flash.page_per_block * default_flash.page_size);
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default_flash.num_blocks = type->chipsize << (20 - i);
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i = __ffs(page_per_block * info->page_size);
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num_blocks = type->chipsize << (20 - i);
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info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
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info->oob_size = (info->page_size == 2048) ? 64 : 16;
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/* calculate addressing information */
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info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
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info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
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if (default_flash.num_blocks * default_flash.page_per_block > 65536)
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if (num_blocks * page_per_block > 65536)
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info->row_addr_cycles = 3;
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else
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info->row_addr_cycles = 2;
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pxa3xx_nand_detect_timing(info, &default_timing);
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default_flash.timing = &default_timing;
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default_flash.cmdset = &default_cmdset;
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info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
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info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
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info->cmdset = &default_cmdset;
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return 0;
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}
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@ -1035,10 +1005,9 @@ static struct nand_ecclayout hw_largepage_ecclayout = {
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static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
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struct pxa3xx_nand_info *info)
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{
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const struct pxa3xx_nand_flash *f = info->flash_info;
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struct nand_chip *this = &info->nand_chip;
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this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
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this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
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this->waitfunc = pxa3xx_nand_waitfunc;
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this->select_chip = pxa3xx_nand_select_chip;
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@ -1054,9 +1023,9 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
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this->ecc.hwctl = pxa3xx_nand_ecc_hwctl;
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this->ecc.calculate = pxa3xx_nand_ecc_calculate;
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this->ecc.correct = pxa3xx_nand_ecc_correct;
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this->ecc.size = f->page_size;
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this->ecc.size = info->page_size;
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if (f->page_size == 2048)
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if (info->page_size == 2048)
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this->ecc.layout = &hw_largepage_ecclayout;
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else
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this->ecc.layout = &hw_smallpage_ecclayout;
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@ -1269,9 +1238,11 @@ static int pxa3xx_nand_resume(struct platform_device *pdev)
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struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
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struct pxa3xx_nand_info *info = mtd->priv;
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nand_writel(info, NDTR0CS0, info->ndtr0cs0);
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nand_writel(info, NDTR1CS0, info->ndtr1cs0);
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clk_enable(info->clk);
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return pxa3xx_nand_config_flash(info, info->flash_info);
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return 0;
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}
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#else
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#define pxa3xx_nand_suspend NULL
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