forked from Minki/linux
cpufreq: s5pv210: use relaxed IO accesors
The use of __raw IO accesors is not endian safe and should be used sparingly. The relaxed variants should be as lightweight and also are endian safe. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This commit is contained in:
Ben Dooks
Krzysztof Kozlowski
parent
58f388bcf0
commit
187364b6fc
@ -220,7 +220,7 @@ static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
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tmp1 /= tmp;
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__raw_writel(tmp1, reg);
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writel_relaxed(tmp1, reg);
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}
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static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
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@ -301,29 +301,29 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
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* 1. Temporary Change divider for MFC and G3D
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* SCLKA2M(200/1=200)->(200/4=50)Mhz
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*/
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reg = __raw_readl(S5P_CLK_DIV2);
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reg = readl_relaxed(S5P_CLK_DIV2);
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reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
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reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
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(3 << S5P_CLKDIV2_MFC_SHIFT);
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__raw_writel(reg, S5P_CLK_DIV2);
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writel_relaxed(reg, S5P_CLK_DIV2);
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/* For MFC, G3D dividing */
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do {
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reg = __raw_readl(S5P_CLKDIV_STAT0);
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reg = readl_relaxed(S5P_CLKDIV_STAT0);
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} while (reg & ((1 << 16) | (1 << 17)));
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/*
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* 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
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* (200/4=50)->(667/4=166)Mhz
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*/
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reg = __raw_readl(S5P_CLK_SRC2);
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reg = readl_relaxed(S5P_CLK_SRC2);
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reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
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reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
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(1 << S5P_CLKSRC2_MFC_SHIFT);
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__raw_writel(reg, S5P_CLK_SRC2);
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writel_relaxed(reg, S5P_CLK_SRC2);
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do {
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reg = __raw_readl(S5P_CLKMUX_STAT1);
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reg = readl_relaxed(S5P_CLKMUX_STAT1);
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} while (reg & ((1 << 7) | (1 << 3)));
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/*
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@ -335,19 +335,19 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
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s5pv210_set_refresh(DMC1, 133000);
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/* 4. SCLKAPLL -> SCLKMPLL */
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reg = __raw_readl(S5P_CLK_SRC0);
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reg = readl_relaxed(S5P_CLK_SRC0);
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reg &= ~(S5P_CLKSRC0_MUX200_MASK);
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reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
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__raw_writel(reg, S5P_CLK_SRC0);
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writel_relaxed(reg, S5P_CLK_SRC0);
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do {
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reg = __raw_readl(S5P_CLKMUX_STAT0);
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reg = readl_relaxed(S5P_CLKMUX_STAT0);
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} while (reg & (0x1 << 18));
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}
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/* Change divider */
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reg = __raw_readl(S5P_CLK_DIV0);
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reg = readl_relaxed(S5P_CLK_DIV0);
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reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
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S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
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@ -363,25 +363,25 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
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(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
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(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
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__raw_writel(reg, S5P_CLK_DIV0);
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writel_relaxed(reg, S5P_CLK_DIV0);
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do {
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reg = __raw_readl(S5P_CLKDIV_STAT0);
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reg = readl_relaxed(S5P_CLKDIV_STAT0);
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} while (reg & 0xff);
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/* ARM MCS value changed */
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reg = __raw_readl(S5P_ARM_MCS_CON);
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reg = readl_relaxed(S5P_ARM_MCS_CON);
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reg &= ~0x3;
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if (index >= L3)
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reg |= 0x3;
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else
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reg |= 0x1;
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__raw_writel(reg, S5P_ARM_MCS_CON);
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writel_relaxed(reg, S5P_ARM_MCS_CON);
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if (pll_changing) {
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/* 5. Set Lock time = 30us*24Mhz = 0x2cf */
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__raw_writel(0x2cf, S5P_APLL_LOCK);
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writel_relaxed(0x2cf, S5P_APLL_LOCK);
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/*
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* 6. Turn on APLL
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@ -389,12 +389,12 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
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* 6-2. Wait untile the PLL is locked
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*/
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if (index == L0)
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__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
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writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);
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else
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__raw_writel(APLL_VAL_800, S5P_APLL_CON);
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writel_relaxed(APLL_VAL_800, S5P_APLL_CON);
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do {
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reg = __raw_readl(S5P_APLL_CON);
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reg = readl_relaxed(S5P_APLL_CON);
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} while (!(reg & (0x1 << 29)));
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/*
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@ -402,39 +402,39 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
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* to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
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* (667/4=166)->(200/4=50)Mhz
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*/
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reg = __raw_readl(S5P_CLK_SRC2);
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reg = readl_relaxed(S5P_CLK_SRC2);
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reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
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reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
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(0 << S5P_CLKSRC2_MFC_SHIFT);
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__raw_writel(reg, S5P_CLK_SRC2);
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writel_relaxed(reg, S5P_CLK_SRC2);
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do {
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reg = __raw_readl(S5P_CLKMUX_STAT1);
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reg = readl_relaxed(S5P_CLKMUX_STAT1);
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} while (reg & ((1 << 7) | (1 << 3)));
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/*
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* 8. Change divider for MFC and G3D
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* (200/4=50)->(200/1=200)Mhz
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*/
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reg = __raw_readl(S5P_CLK_DIV2);
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reg = readl_relaxed(S5P_CLK_DIV2);
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reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
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reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
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(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
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__raw_writel(reg, S5P_CLK_DIV2);
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writel_relaxed(reg, S5P_CLK_DIV2);
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/* For MFC, G3D dividing */
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do {
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reg = __raw_readl(S5P_CLKDIV_STAT0);
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reg = readl_relaxed(S5P_CLKDIV_STAT0);
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} while (reg & ((1 << 16) | (1 << 17)));
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/* 9. Change MPLL to APLL in MSYS_MUX */
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reg = __raw_readl(S5P_CLK_SRC0);
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reg = readl_relaxed(S5P_CLK_SRC0);
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reg &= ~(S5P_CLKSRC0_MUX200_MASK);
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reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
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__raw_writel(reg, S5P_CLK_SRC0);
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writel_relaxed(reg, S5P_CLK_SRC0);
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do {
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reg = __raw_readl(S5P_CLKMUX_STAT0);
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reg = readl_relaxed(S5P_CLKMUX_STAT0);
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} while (reg & (0x1 << 18));
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/*
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@ -451,13 +451,13 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
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* and memory refresh parameter should be changed
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*/
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if (bus_speed_changing) {
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reg = __raw_readl(S5P_CLK_DIV6);
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reg = readl_relaxed(S5P_CLK_DIV6);
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reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
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reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
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__raw_writel(reg, S5P_CLK_DIV6);
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writel_relaxed(reg, S5P_CLK_DIV6);
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do {
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reg = __raw_readl(S5P_CLKDIV_STAT1);
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reg = readl_relaxed(S5P_CLKDIV_STAT1);
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} while (reg & (1 << 15));
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/* Reconfigure DRAM refresh counter value */
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@ -497,7 +497,7 @@ static int check_mem_type(void __iomem *dmc_reg)
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{
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unsigned long val;
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val = __raw_readl(dmc_reg + 0x4);
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val = readl_relaxed(dmc_reg + 0x4);
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val = (val & (0xf << 8));
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return val >> 8;
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@ -542,10 +542,10 @@ static int s5pv210_cpu_init(struct cpufreq_policy *policy)
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}
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/* Find current refresh counter and frequency each DMC */
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s5pv210_dram_conf[0].refresh = (__raw_readl(dmc_base[0] + 0x30) * 1000);
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s5pv210_dram_conf[0].refresh = (readl_relaxed(dmc_base[0] + 0x30) * 1000);
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s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
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s5pv210_dram_conf[1].refresh = (__raw_readl(dmc_base[1] + 0x30) * 1000);
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s5pv210_dram_conf[1].refresh = (readl_relaxed(dmc_base[1] + 0x30) * 1000);
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s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
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policy->suspend_freq = SLEEP_FREQ;
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