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drm/i915: gen6_enable_rps() wants to be called after ring initialisation

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Currently we call gen6_enable_rps() (which writes into the per-ring
register mmio space) from intel_modeset_init_hw() which is called before
we initialise the rings. If we defer intel_modeset_init_hw() until
afterwards (in the intel_modeset_gem_init() phase) all is well.

v2: Rectify ordering of gem vs display HW init upon resume. (Daniel)

v3: Fix up locking. (Paulo)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Smash Paulo's locking fix onto Chris' patch.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson
2012-05-09 11:56:28 +01:00
committed by Daniel Vetter
parent 0e43406bcc
commit 1833b13445
3 changed files with 6 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/i915/i915_drv.c
View File

@@ -624,15 +624,16 @@ static int i915_drm_thaw(struct drm_device *dev)
/* KMS EnterVT equivalent */ /* KMS EnterVT equivalent */
if (drm_core_check_feature(dev, DRIVER_MODESET)) { if (drm_core_check_feature(dev, DRIVER_MODESET)) {
if (HAS_PCH_SPLIT(dev))
ironlake_init_pch_refclk(dev);
mutex_lock(&dev->struct_mutex); mutex_lock(&dev->struct_mutex);
dev_priv->mm.suspended = 0; dev_priv->mm.suspended = 0;
error = i915_gem_init_hw(dev); error = i915_gem_init_hw(dev);
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
if (HAS_PCH_SPLIT(dev)) intel_modeset_init_hw(dev);
ironlake_init_pch_refclk(dev);
drm_mode_config_reset(dev); drm_mode_config_reset(dev);
drm_irq_install(dev); drm_irq_install(dev);
@@ -640,9 +641,6 @@ static int i915_drm_thaw(struct drm_device *dev)
mutex_lock(&dev->mode_config.mutex); mutex_lock(&dev->mode_config.mutex);
drm_helper_resume_force_mode(dev); drm_helper_resume_force_mode(dev);
mutex_unlock(&dev->mode_config.mutex); mutex_unlock(&dev->mode_config.mutex);
if (IS_IRONLAKE_M(dev))
ironlake_enable_rc6(dev);
} }
intel_opregion_init(dev); intel_opregion_init(dev);

6
drivers/gpu/drm/i915/i915_suspend.c
View File

@@ -876,12 +876,6 @@ int i915_restore_state(struct drm_device *dev)
I915_WRITE(IER, dev_priv->saveIER); I915_WRITE(IER, dev_priv->saveIER);
I915_WRITE(IMR, dev_priv->saveIMR); I915_WRITE(IMR, dev_priv->saveIMR);
} }
mutex_unlock(&dev->struct_mutex);
if (drm_core_check_feature(dev, DRIVER_MODESET))
intel_modeset_init_hw(dev);
mutex_lock(&dev->struct_mutex);
/* Cache mode state */ /* Cache mode state */
I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);

6
drivers/gpu/drm/i915/intel_display.c
View File

@@ -6658,6 +6658,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
if (IS_IRONLAKE_M(dev)) { if (IS_IRONLAKE_M(dev)) {
ironlake_enable_drps(dev); ironlake_enable_drps(dev);
ironlake_enable_rc6(dev);
intel_init_emon(dev); intel_init_emon(dev);
} }
@@ -6719,8 +6720,6 @@ void intel_modeset_init(struct drm_device *dev)
i915_disable_vga(dev); i915_disable_vga(dev);
intel_setup_outputs(dev); intel_setup_outputs(dev);
intel_modeset_init_hw(dev);
INIT_WORK(&dev_priv->idle_work, intel_idle_update); INIT_WORK(&dev_priv->idle_work, intel_idle_update);
setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
(unsigned long)dev); (unsigned long)dev);
@@ -6728,8 +6727,7 @@ void intel_modeset_init(struct drm_device *dev)
void intel_modeset_gem_init(struct drm_device *dev) void intel_modeset_gem_init(struct drm_device *dev)
{ {
if (IS_IRONLAKE_M(dev)) intel_modeset_init_hw(dev);
ironlake_enable_rc6(dev);
intel_setup_overlay(dev); intel_setup_overlay(dev);
} }