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MIPS: OCTEON: Add model checking support for cn73xx, cnf75xx and cn78xx

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Follow on patchs need to be able to distinguish the new models.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12498/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
2016-02-09 11:00:09 -08:00
committed by Ralf Baechle
parent 2df11221bd
commit 182a6d1cd3
4 changed files with 125 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
arch/mips/include/asm/octeon/cvmx.h
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@@ -57,6 +57,7 @@ enum cvmx_mips_space {
#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-ciu-defs.h>
#include <asm/octeon/cvmx-ciu3-defs.h>
#include <asm/octeon/cvmx-gpio-defs.h>
#include <asm/octeon/cvmx-iob-defs.h>
#include <asm/octeon/cvmx-ipd-defs.h>
@@ -341,6 +342,21 @@ static inline unsigned int cvmx_get_core_num(void)
return core_num;
}
/* Maximum # of bits to define core in node */
#define CVMX_NODE_NO_SHIFT 7
#define CVMX_NODE_MASK 0x3
static inline unsigned int cvmx_get_node_num(void)
{
unsigned int core_num = cvmx_get_core_num();
return (core_num >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK;
}
static inline unsigned int cvmx_get_local_core_num(void)
{
return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
}
/**
* Returns the number of bits set in the provided value.
* Simple wrapper for POP instruction.
@@ -448,8 +464,15 @@ static inline uint64_t cvmx_get_cycle_global(void)
/* Return the number of cores available in the chip */
static inline uint32_t cvmx_octeon_num_cores(void)
{
uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
return cvmx_pop(ciu_fuse);
u64 ciu_fuse_reg;
u64 ciu_fuse;
if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))
ciu_fuse_reg = CVMX_CIU3_FUSE;
else
ciu_fuse_reg = CVMX_CIU_FUSE;
ciu_fuse = cvmx_read_csr(ciu_fuse_reg);
return cvmx_dpop(ciu_fuse);
}
#endif /* __CVMX_H__ */

19
arch/mips/include/asm/octeon/octeon-feature.h
View File

@@ -81,6 +81,10 @@ enum octeon_feature {
OCTEON_FEATURE_HFA,
OCTEON_FEATURE_DFM,
OCTEON_FEATURE_CIU2,
OCTEON_FEATURE_CIU3,
/* Octeon has FPA first seen on 78XX */
OCTEON_FEATURE_FPA3,
OCTEON_FEATURE_FAU,
OCTEON_MAX_FEATURE
};
@@ -110,7 +114,7 @@ static inline int octeon_has_crypto(void)
* Returns Non zero if the feature exists. Zero if the feature does not
* exist.
*/
static inline int octeon_has_feature(enum octeon_feature feature)
static inline bool octeon_has_feature(enum octeon_feature feature)
{
switch (feature) {
case OCTEON_FEATURE_SAAD:
@@ -122,7 +126,7 @@ static inline int octeon_has_feature(enum octeon_feature feature)
fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
} else {
return 0;
return false;
}
case OCTEON_FEATURE_PCIE:
@@ -190,11 +194,20 @@ static inline int octeon_has_feature(enum octeon_feature feature)
case OCTEON_FEATURE_CIU2:
return OCTEON_IS_MODEL(OCTEON_CN68XX);
case OCTEON_FEATURE_CIU3:
case OCTEON_FEATURE_FPA3:
return OCTEON_IS_MODEL(OCTEON_CN78XX)
|| OCTEON_IS_MODEL(OCTEON_CNF75XX)
|| OCTEON_IS_MODEL(OCTEON_CN73XX);
case OCTEON_FEATURE_FAU:
return !(OCTEON_IS_MODEL(OCTEON_CN78XX)
|| OCTEON_IS_MODEL(OCTEON_CNF75XX)
|| OCTEON_IS_MODEL(OCTEON_CN73XX));
default:
break;
}
return 0;
return false;
}
#endif /* __OCTEON_FEATURE_H__ */

5
arch/mips/include/asm/octeon/octeon-model.h
View File

@@ -74,7 +74,12 @@
* CN7XXX models with new revision encoding
*/
#define OCTEON_CNF75XX_PASS1_0 0x000d9800
#define OCTEON_CNF75XX (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_REVISION)
#define OCTEON_CNF75XX_PASS1_X (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
#define OCTEON_CN73XX_PASS1_0 0x000d9700
#define OCTEON_CN73XX_PASS1_1 0x000d9701
#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION)
#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \
OM_IGNORE_MINOR_REVISION)