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pinctrl: cannonlake: Fix community ordering for H variant

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The driver was written based on an assumption that BIOS provides
unordered communities in ACPI DSDT. Nevertheless, it seems that
BIOS getting fixed before being provisioned to OxM:s.
So does driver.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=199911
Reported-by: Marc Landolt <2009@marclandolt.ch>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Fixes: a663ccf0fe ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andy Shevchenko 2018-07-26 19:59:05 +03:00 committed by Linus Walleij
parent 3c94d2d08a
commit 17ac526824
1 changed files with 2 additions and 6 deletions
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8
drivers/pinctrl/intel/pinctrl-cannonlake.c
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@ -444,12 +444,8 @@ static const struct intel_function cnlh_functions[] = {
static const struct intel_community cnlh_communities[] = {
CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
/*
* ACPI MMIO resources are returned in reverse order for
* communities 3 and 4.
*/
CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps),
CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps),
CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
};
static const struct intel_pinctrl_soc_data cnlh_soc_data = {