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drm/amdgpu/psp11: simplify the ucode register logic

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Split it between navi10 and newer and everything before
navi10.

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2019-07-08 14:01:30 -05:00
parent f8a7976b75
commit 173da95d93
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
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@ -534,7 +534,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
case AMDGPU_UCODE_ID_RLC_G:
*sram_offset = 0x2000;
if (adev->asic_type != CHIP_NAVI10) {
if (adev->asic_type < CHIP_NAVI10) {
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
} else {
@ -545,7 +545,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
case AMDGPU_UCODE_ID_SDMA0:
*sram_offset = 0x0;
if (adev->asic_type != CHIP_NAVI10) {
if (adev->asic_type < CHIP_NAVI10) {
*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
} else {