clk: qcom: gdsc: Add support to enable retention of GSDCR
Add support for the RETAIN_FF_ENABLE feature which enables the usage of retention registers. These registers maintain their state after disabling and re-enabling a GDSC. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -30,6 +30,7 @@
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/* CFG_GDSCR */
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/* CFG_GDSCR */
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#define GDSC_POWER_UP_COMPLETE BIT(16)
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#define GDSC_POWER_UP_COMPLETE BIT(16)
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#define GDSC_POWER_DOWN_COMPLETE BIT(15)
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#define GDSC_POWER_DOWN_COMPLETE BIT(15)
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#define GDSC_RETAIN_FF_ENABLE BIT(11)
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#define CFG_GDSCR_OFFSET 0x4
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#define CFG_GDSCR_OFFSET 0x4
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/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
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/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
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@ -217,6 +218,14 @@ static inline void gdsc_assert_reset_aon(struct gdsc *sc)
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regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
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regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
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GMEM_RESET_MASK, 0);
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GMEM_RESET_MASK, 0);
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}
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}
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static void gdsc_retain_ff_on(struct gdsc *sc)
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{
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u32 mask = GDSC_RETAIN_FF_ENABLE;
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regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
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}
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static int gdsc_enable(struct generic_pm_domain *domain)
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static int gdsc_enable(struct generic_pm_domain *domain)
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{
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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struct gdsc *sc = domain_to_gdsc(domain);
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@ -269,6 +278,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
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udelay(1);
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udelay(1);
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}
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}
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if (sc->flags & RETAIN_FF_ENABLE)
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gdsc_retain_ff_on(sc);
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return 0;
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return 0;
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}
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}
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@ -50,6 +50,7 @@ struct gdsc {
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#define AON_RESET BIT(4)
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#define AON_RESET BIT(4)
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#define POLL_CFG_GDSCR BIT(5)
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#define POLL_CFG_GDSCR BIT(5)
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#define ALWAYS_ON BIT(6)
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#define ALWAYS_ON BIT(6)
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#define RETAIN_FF_ENABLE BIT(7)
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struct reset_controller_dev *rcdev;
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struct reset_controller_dev *rcdev;
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unsigned int *resets;
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unsigned int *resets;
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unsigned int reset_count;
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unsigned int reset_count;
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