Fix race conditions for read_c0_entryhi. Remove broken ASID masks in
tlb-sb1.c. Make tlb-r4k.c and tlb-sb1.c more similiar and more efficient. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thiemo Seufer
Ralf Baechle
parent
202d0388e7
commit
172546bf60
@ -21,6 +21,12 @@
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extern void build_tlb_refill_handler(void);
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/*
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* Make sure all entries differ. If they're not different
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* MIPS32 will take revenge ...
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*/
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#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
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/* CP0 hazard avoidance. */
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#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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@ -42,11 +48,8 @@ void local_flush_tlb_all(void)
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/* Blast 'em all away. */
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while (entry < current_cpu_data.tlbsize) {
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/*
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* Make sure all entries differ. If they're not different
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* MIPS32 will take revenge ...
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*/
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write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry));
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write_c0_index(entry);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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@ -57,12 +60,21 @@ void local_flush_tlb_all(void)
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local_irq_restore(flags);
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}
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/* All entries common to a mm share an asid. To effectively flush
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these entries, we just bump the asid. */
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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int cpu = smp_processor_id();
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int cpu;
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if (cpu_context(cpu, mm) != 0)
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drop_mmu_context(mm,cpu);
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preempt_disable();
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cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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drop_mmu_context(mm, cpu);
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}
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preempt_enable();
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}
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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@ -75,9 +87,9 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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local_irq_save(flags);
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if (size <= current_cpu_data.tlbsize/2) {
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int oldpid = read_c0_entryhi();
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int newpid = cpu_asid(cpu, mm);
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@ -99,8 +111,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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if (idx < 0)
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continue;
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/* Make sure all entries differ. */
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write_c0_entryhi(CKSEG0 +
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(idx << (PAGE_SHIFT + 1)));
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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}
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@ -118,9 +129,9 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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local_irq_save(flags);
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if (size <= current_cpu_data.tlbsize / 2) {
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int pid = read_c0_entryhi();
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@ -142,7 +153,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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if (idx < 0)
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continue;
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/* Make sure all entries differ. */
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write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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}
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@ -176,7 +187,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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if (idx < 0)
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goto finish;
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/* Make sure all entries differ. */
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write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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@ -197,8 +208,8 @@ void local_flush_tlb_one(unsigned long page)
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int oldpid, idx;
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local_irq_save(flags);
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page &= (PAGE_MASK << 1);
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oldpid = read_c0_entryhi();
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page &= (PAGE_MASK << 1);
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write_c0_entryhi(page);
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mtc0_tlbw_hazard();
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tlb_probe();
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@ -208,7 +219,7 @@ void local_flush_tlb_one(unsigned long page)
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write_c0_entrylo1(0);
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if (idx >= 0) {
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/* Make sure all entries differ. */
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write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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@ -238,9 +249,9 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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if (current->active_mm != vma->vm_mm)
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return;
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pid = read_c0_entryhi() & ASID_MASK;
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local_irq_save(flags);
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pid = read_c0_entryhi() & ASID_MASK;
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address &= (PAGE_MASK << 1);
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write_c0_entryhi(address | pid);
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pgdp = pgd_offset(vma->vm_mm, address);
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@ -260,14 +271,12 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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write_c0_entrylo0(pte_val(*ptep++) >> 6);
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write_c0_entrylo1(pte_val(*ptep) >> 6);
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#endif
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write_c0_entryhi(address | pid);
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mtc0_tlbw_hazard();
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if (idx < 0)
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tlb_write_random();
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else
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tlb_write_indexed();
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tlbw_use_hazard();
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write_c0_entryhi(pid);
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local_irq_restore(flags);
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}
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@ -94,7 +94,7 @@ void local_flush_tlb_all(void)
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local_irq_save(flags);
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi() & ASID_MASK;
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old_ctx = read_c0_entryhi();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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@ -144,17 +144,17 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long flags;
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int cpu;
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int cpu = smp_processor_id();
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local_irq_save(flags);
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cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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unsigned long flags;
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int size;
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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local_irq_save(flags);
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if (size <= (current_cpu_data.tlbsize/2)) {
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int oldpid = read_c0_entryhi() & ASID_MASK;
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int oldpid = read_c0_entryhi();
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int newpid = cpu_asid(cpu, mm);
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start &= (PAGE_MASK << 1);
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@ -169,17 +169,17 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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if (idx < 0)
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continue;
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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tlb_write_indexed();
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}
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write_c0_entryhi(oldpid);
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} else {
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drop_mmu_context(mm, cpu);
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}
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local_irq_restore(flags);
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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@ -189,7 +189,6 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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local_irq_save(flags);
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if (size <= (current_cpu_data.tlbsize/2)) {
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int pid = read_c0_entryhi();
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@ -207,9 +206,9 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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if (idx < 0)
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continue;
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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tlb_write_indexed();
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}
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write_c0_entryhi(pid);
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@ -221,15 +220,16 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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unsigned long flags;
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int cpu = smp_processor_id();
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local_irq_save(flags);
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if (cpu_context(cpu, vma->vm_mm) != 0) {
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unsigned long flags;
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int oldpid, newpid, idx;
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newpid = cpu_asid(cpu, vma->vm_mm);
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page &= (PAGE_MASK << 1);
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oldpid = read_c0_entryhi() & ASID_MASK;
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local_irq_save(flags);
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oldpid = read_c0_entryhi();
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write_c0_entryhi(page | newpid);
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tlb_probe();
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idx = read_c0_index();
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@ -240,10 +240,11 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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tlb_write_indexed();
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finish:
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write_c0_entryhi(oldpid);
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local_irq_restore(flags);
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}
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local_irq_restore(flags);
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}
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/*
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@ -255,18 +256,17 @@ void local_flush_tlb_one(unsigned long page)
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unsigned long flags;
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int oldpid, idx;
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page &= (PAGE_MASK << 1);
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oldpid = read_c0_entryhi() & ASID_MASK;
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local_irq_save(flags);
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oldpid = read_c0_entryhi();
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page &= (PAGE_MASK << 1);
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write_c0_entryhi(page);
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tlb_probe();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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if (idx >= 0) {
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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tlb_write_indexed();
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}
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@ -297,6 +297,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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unsigned long flags;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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int idx, pid;
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@ -311,19 +312,26 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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pid = read_c0_entryhi() & ASID_MASK;
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address &= (PAGE_MASK << 1);
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write_c0_entryhi(address | (pid));
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write_c0_entryhi(address | pid);
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pgdp = pgd_offset(vma->vm_mm, address);
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tlb_probe();
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pmdp = pmd_offset(pgdp, address);
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pudp = pud_offset(pgdp, address);
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pmdp = pmd_offset(pudp, address);
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idx = read_c0_index();
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ptep = pte_offset_map(pmdp, address);
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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write_c0_entrylo0(ptep->pte_high);
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ptep++;
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write_c0_entrylo1(ptep->pte_high);
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#else
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write_c0_entrylo0(pte_val(*ptep++) >> 6);
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write_c0_entrylo1(pte_val(*ptep) >> 6);
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if (idx < 0) {
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#endif
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if (idx < 0)
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tlb_write_random();
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} else {
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else
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tlb_write_indexed();
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}
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local_irq_restore(flags);
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}
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@ -336,7 +344,8 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long old_ctx;
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local_irq_save(flags);
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old_ctx = read_c0_entryhi() & 0xff;
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi();
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old_pagemask = read_c0_pagemask();
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wired = read_c0_wired();
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write_c0_wired(wired + 1);
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