drm/amdgpu: support atcs method powershift (v4)
add support to handle ATCS method for power shift control. used to communicate dGPU device state to SBIOS. V2: use defined acpi func for checking psc support (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling (Alex) V4: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1340,8 +1340,11 @@ struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
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int amdgpu_acpi_init(struct amdgpu_device *adev);
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void amdgpu_acpi_fini(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_power_shift_control_supported(void);
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int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
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u8 perf_req, bool advertise);
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int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state);
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int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
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void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
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@ -1352,6 +1355,9 @@ static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
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static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
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static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; }
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static inline void amdgpu_acpi_detect(void) { }
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static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
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static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state) { return 0; }
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#endif
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int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
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@ -76,6 +76,7 @@ struct amdgpu_atcs_functions {
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bool pcie_perf_req;
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bool pcie_dev_rdy;
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bool pcie_bus_width;
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bool power_shift_control;
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};
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struct amdgpu_atcs {
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@ -534,6 +535,7 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas
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f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED;
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f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED;
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f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED;
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f->power_shift_control = mask & ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED;
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}
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/**
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@ -598,6 +600,18 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade
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return false;
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}
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/**
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* amdgpu_acpi_is_power_shift_control_supported
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*
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* Check if the ATCS power shift control method
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* is supported.
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* returns true if supported, false if not.
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*/
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bool amdgpu_acpi_is_power_shift_control_supported(void)
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{
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return amdgpu_acpi_priv.atcs.functions.power_shift_control;
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}
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/**
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* amdgpu_acpi_pcie_notify_device_ready
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*
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@ -699,6 +713,47 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
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return 0;
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}
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/**
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* amdgpu_acpi_power_shift_control
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*
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* @adev: amdgpu_device pointer
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* @dev_state: device acpi state
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* @drv_state: driver state
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*
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* Executes the POWER_SHIFT_CONTROL method to
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* communicate current dGPU device state and
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* driver state to APU/SBIOS.
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* returns 0 on success, error on failure.
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*/
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int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state)
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{
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union acpi_object *info;
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struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;
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struct atcs_pwr_shift_input atcs_input;
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struct acpi_buffer params;
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if (!amdgpu_acpi_is_power_shift_control_supported())
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return -EINVAL;
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atcs_input.size = sizeof(struct atcs_pwr_shift_input);
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/* dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
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atcs_input.dgpu_id = adev->pdev->devfn | (adev->pdev->bus->number << 8);
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atcs_input.dev_acpi_state = dev_state;
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atcs_input.drv_state = drv_state;
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params.length = sizeof(struct atcs_pwr_shift_input);
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params.pointer = &atcs_input;
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info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_POWER_SHIFT_CONTROL, ¶ms);
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if (!info) {
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DRM_ERROR("ATCS PSC update failed\n");
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return -EIO;
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}
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return 0;
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}
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/**
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* amdgpu_acpi_event - handle notify events
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*
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@ -103,6 +103,13 @@ struct atcs_pref_req_output {
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u8 ret_val; /* return value */
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} __packed;
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struct atcs_pwr_shift_input {
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u16 size; /* structure size in bytes (includes size field) */
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u16 dgpu_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
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u8 dev_acpi_state; /* D0 = 0, D3 hot = 3 */
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u8 drv_state; /* 0 = operational, 1 = not operational */
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} __packed;
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/* AMD hw uses four ACPI control methods:
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* 1. ATIF
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* ARG0: (ACPI_INTEGER) function code
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@ -418,6 +425,7 @@ struct atcs_pref_req_output {
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# define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED (1 << 1)
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# define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED (1 << 2)
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# define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED (1 << 3)
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# define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7)
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#define ATCS_FUNCTION_GET_EXTERNAL_STATE 0x1
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/* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE
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* ARG1: none
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@ -472,4 +480,14 @@ struct atcs_pref_req_output {
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* BYTE - number of active lanes
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*/
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#define ATCS_FUNCTION_POWER_SHIFT_CONTROL 0x8
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/* ARG0: ATCS_FUNCTION_POWER_SHIFT_CONTROL
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* ARG1:
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* WORD - structure size in bytes (includes size field)
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* WORD - dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
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* BYTE - Device ACPI state
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* BYTE - Driver state
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* OUTPUT: none
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*/
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#endif
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