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irqchip/mips-gic: Add new DT property to reserve IPIs

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The new property will allow to specify the range of GIC hwirqs to use for IPIs.

This is an optinal property. We preserve the previous behaviour of allocating
the last 2 * gic_vpes if it's not specified or DT is not supported.

Signed-off-by: Qais Yousef <qais.yousef@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-20-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Qais Yousef 2015-12-08 13:20:30 +00:00 committed by Thomas Gleixner
parent 7eb8c99db2
commit 16a8083ced
2 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
View File

@ -23,6 +23,12 @@ Optional properties:
- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
to which the GIC may not route interrupts. Valid values are 2 - 7. to which the GIC may not route interrupts. Valid values are 2 - 7.
This property is ignored if the CPU is started in EIC mode. This property is ignored if the CPU is started in EIC mode.
- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
reserved for IPIs.
It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
of the reserved range.
If not specified, the driver will allocate the last 2 * number of VPEs in the
system.
Required properties for timer sub-node: Required properties for timer sub-node:
- compatible : Should be "mti,gic-timer". - compatible : Should be "mti,gic-timer".
@ -44,6 +50,7 @@ Example:
#interrupt-cells = <3>; #interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>; mti,reserved-cpu-vectors = <7>;
mti,reserved-ipi-vectors = <40 8>;
timer { timer {
compatible = "mti,gic-timer"; compatible = "mti,gic-timer";

12
drivers/irqchip/irq-mips-gic.c
View File

@ -957,6 +957,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
struct device_node *node) struct device_node *node)
{ {
unsigned int gicconfig; unsigned int gicconfig;
unsigned int v[2];
__gic_base_addr = gic_base_addr; __gic_base_addr = gic_base_addr;
@ -1027,8 +1028,15 @@ static void __init __gic_init(unsigned long gic_base_addr,
gic_ipi_domain->bus_token = DOMAIN_BUS_IPI; gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
/* Make the last 2 * gic_vpes available for IPIs */ if (node &&
bitmap_set(ipi_resrv, gic_shared_intrs - 2 * gic_vpes, 2 * gic_vpes); !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
bitmap_set(ipi_resrv, v[0], v[1]);
} else {
/* Make the last 2 * gic_vpes available for IPIs */
bitmap_set(ipi_resrv,
gic_shared_intrs - 2 * gic_vpes,
2 * gic_vpes);
}
gic_basic_init(); gic_basic_init();
} }