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drm/nouveau/disp: add common class handling between <nv50 and >=nv50

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About to expose head/output path/connector objects everywhere, so we will
need support for child classes prior to nv50 now.

Somewhat cleaner than the code >=nv50 used previously.

v2:
- use ?: (lyude)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Ben Skeggs 2022-06-01 20:46:27 +10:00 committed by Dave Airlie
parent 92fba5d3c8
commit 168c029943
48 changed files with 398 additions and 1074 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/gpu/drm/nouveau/include/nvif/class.h
View File

@ -32,6 +32,8 @@
#define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d
#define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
#define NVIF_CLASS_DISP /* if0010.h */ 0x80000010
/* the below match nvidia-assigned (either in hw, or sw) class numbers */
#define NV_NULL_CLASS 0x00000030
@ -73,21 +75,21 @@
#define TURING_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c46f
#define AMPERE_CHANNEL_GPFIFO_B /* clc36f.h */ 0x0000c76f
#define NV50_DISP /* cl5070.h */ 0x00005070
#define G82_DISP /* cl5070.h */ 0x00008270
#define GT200_DISP /* cl5070.h */ 0x00008370
#define GT214_DISP /* cl5070.h */ 0x00008570
#define GT206_DISP /* cl5070.h */ 0x00008870
#define GF110_DISP /* cl5070.h */ 0x00009070
#define GK104_DISP /* cl5070.h */ 0x00009170
#define GK110_DISP /* cl5070.h */ 0x00009270
#define GM107_DISP /* cl5070.h */ 0x00009470
#define GM200_DISP /* cl5070.h */ 0x00009570
#define GP100_DISP /* cl5070.h */ 0x00009770
#define GP102_DISP /* cl5070.h */ 0x00009870
#define GV100_DISP /* cl5070.h */ 0x0000c370
#define TU102_DISP /* cl5070.h */ 0x0000c570
#define GA102_DISP /* cl5070.h */ 0x0000c670
#define NV50_DISP /* if0010.h */ 0x00005070
#define G82_DISP /* if0010.h */ 0x00008270
#define GT200_DISP /* if0010.h */ 0x00008370
#define GT214_DISP /* if0010.h */ 0x00008570
#define GT206_DISP /* if0010.h */ 0x00008870
#define GF110_DISP /* if0010.h */ 0x00009070
#define GK104_DISP /* if0010.h */ 0x00009170
#define GK110_DISP /* if0010.h */ 0x00009270
#define GM107_DISP /* if0010.h */ 0x00009470
#define GM200_DISP /* if0010.h */ 0x00009570
#define GP100_DISP /* if0010.h */ 0x00009770
#define GP102_DISP /* if0010.h */ 0x00009870
#define GV100_DISP /* if0010.h */ 0x0000c370
#define TU102_DISP /* if0010.h */ 0x0000c570
#define GA102_DISP /* if0010.h */ 0x0000c670
#define GV100_DISP_CAPS 0x0000c373

11
drivers/gpu/drm/nouveau/include/nvif/if0010.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0010_H__
#define __NVIF_IF0010_H__
union nvif_disp_args {
struct nvif_disp_v0 {
__u8 version;
__u8 pad01[7];
} v0;
};
#endif

9
drivers/gpu/drm/nouveau/include/nvif/printf.h
View File

@ -17,4 +17,13 @@
#endif
#define NVIF_ERROR(o,f,a...) NVIF_PRINT(errorf, (o), f, ##a)
#define NVIF_ERRON(c,o,f,a...) do { \
struct nvif_object *_object = (o); \
int _cond = (c); \
if (_cond) { \
NVIF_ERROR(_object, f" (ret:%d)", ##a, _cond); \
} else { \
NVIF_DEBUG(_object, f, ##a); \
} \
} while(0)
#endif

3
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
View File

@ -3,6 +3,7 @@
#define __NVKM_DISP_H__
#define nvkm_disp(p) container_of((p), struct nvkm_disp, engine)
#include <core/engine.h>
#include <core/object.h>
#include <core/event.h>
struct nvkm_disp {
@ -47,7 +48,7 @@ struct nvkm_disp {
struct {
spinlock_t lock;
struct nvkm_oproxy *object;
struct nvkm_object object;
} client;
};

58
drivers/gpu/drm/nouveau/nvif/disp.c
View File

@ -21,8 +21,10 @@
*/
#include <nvif/disp.h>
#include <nvif/device.h>
#include <nvif/printf.h>
#include <nvif/class.h>
#include <nvif/if0010.h>
void
nvif_disp_dtor(struct nvif_disp *disp)
@ -31,33 +33,41 @@ nvif_disp_dtor(struct nvif_disp *disp)
}
int
nvif_disp_ctor(struct nvif_device *device, const char *name, s32 oclass,
struct nvif_disp *disp)
nvif_disp_ctor(struct nvif_device *device, const char *name, s32 oclass, struct nvif_disp *disp)
{
static const struct nvif_mclass disps[] = {
{ GA102_DISP, -1 },
{ TU102_DISP, -1 },
{ GV100_DISP, -1 },
{ GP102_DISP, -1 },
{ GP100_DISP, -1 },
{ GM200_DISP, -1 },
{ GM107_DISP, -1 },
{ GK110_DISP, -1 },
{ GK104_DISP, -1 },
{ GF110_DISP, -1 },
{ GT214_DISP, -1 },
{ GT206_DISP, -1 },
{ GT200_DISP, -1 },
{ G82_DISP, -1 },
{ NV50_DISP, -1 },
{ NV04_DISP, -1 },
{ GA102_DISP, 0 },
{ TU102_DISP, 0 },
{ GV100_DISP, 0 },
{ GP102_DISP, 0 },
{ GP100_DISP, 0 },
{ GM200_DISP, 0 },
{ GM107_DISP, 0 },
{ GK110_DISP, 0 },
{ GK104_DISP, 0 },
{ GF110_DISP, 0 },
{ GT214_DISP, 0 },
{ GT206_DISP, 0 },
{ GT200_DISP, 0 },
{ G82_DISP, 0 },
{ NV50_DISP, 0 },
{ NV04_DISP, 0 },
{}
};
int cid = nvif_sclass(&device->object, disps, oclass);
disp->object.client = NULL;
if (cid < 0)
return cid;
struct nvif_disp_v0 args;
int cid, ret;
return nvif_object_ctor(&device->object, name ? name : "nvifDisp", 0,
disps[cid].oclass, NULL, 0, &disp->object);
cid = nvif_sclass(&device->object, disps, oclass);
disp->object.client = NULL;
if (cid < 0) {
NVIF_ERRON(cid, &device->object, "[NEW disp%04x] not supported", oclass);
return cid;
}
args.version = 0;
ret = nvif_object_ctor(&device->object, name ?: "nvifDisp", 0,
disps[cid].oclass, &args, sizeof(args), &disp->object);
NVIF_ERRON(ret, &device->object, "[NEW disp%04x]", disps[cid].oclass);
return ret;
}

16
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
View File

@ -64,20 +64,6 @@ nvkm-y += nvkm/engine/disp/conn.o
nvkm-y += nvkm/engine/disp/rootnv04.o
nvkm-y += nvkm/engine/disp/rootnv50.o
nvkm-y += nvkm/engine/disp/rootg84.o
nvkm-y += nvkm/engine/disp/rootg94.o
nvkm-y += nvkm/engine/disp/rootgt200.o
nvkm-y += nvkm/engine/disp/rootgt215.o
nvkm-y += nvkm/engine/disp/rootgf119.o
nvkm-y += nvkm/engine/disp/rootgk104.o
nvkm-y += nvkm/engine/disp/rootgk110.o
nvkm-y += nvkm/engine/disp/rootgm107.o
nvkm-y += nvkm/engine/disp/rootgm200.o
nvkm-y += nvkm/engine/disp/rootgp100.o
nvkm-y += nvkm/engine/disp/rootgp102.o
nvkm-y += nvkm/engine/disp/rootgv100.o
nvkm-y += nvkm/engine/disp/roottu102.o
nvkm-y += nvkm/engine/disp/rootga102.o
nvkm-y += nvkm/engine/disp/capsgv100.o
@ -125,3 +111,5 @@ nvkm-y += nvkm/engine/disp/cursgv100.o
nvkm-y += nvkm/engine/disp/oimmnv50.o
nvkm-y += nvkm/engine/disp/oimmgf119.o
nvkm-y += nvkm/engine/disp/oimmgp102.o
nvkm-y += nvkm/engine/disp/udisp.o

39
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
View File

@ -30,7 +30,6 @@
#include <core/client.h>
#include <core/notify.h>
#include <core/oproxy.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
@ -145,45 +144,12 @@ nvkm_disp_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **event)
return -EINVAL;
}
static void
nvkm_disp_class_del(struct nvkm_oproxy *oproxy)
{
struct nvkm_disp *disp = nvkm_disp(oproxy->base.engine);
spin_lock(&disp->client.lock);
if (disp->client.object == oproxy)
disp->client.object = NULL;
spin_unlock(&disp->client.lock);
}
static const struct nvkm_oproxy_func
nvkm_disp_class = {
.dtor[1] = nvkm_disp_class_del,
};
static int
nvkm_disp_class_new(struct nvkm_device *device,
const struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
const struct nvkm_disp_oclass *sclass = oclass->engn;
struct nvkm_disp *disp = nvkm_disp(oclass->engine);
struct nvkm_oproxy *oproxy;
int ret;
ret = nvkm_oproxy_new_(&nvkm_disp_class, oclass, &oproxy);
if (ret)
return ret;
*pobject = &oproxy->base;
spin_lock(&disp->client.lock);
if (disp->client.object) {
spin_unlock(&disp->client.lock);
return -EBUSY;
}
disp->client.object = oproxy;
spin_unlock(&disp->client.lock);
return sclass->ctor(disp, oclass, data, size, &oproxy->object);
return nvkm_udisp_new(oclass, data, size, pobject);
}
static const struct nvkm_device_oclass
@ -197,8 +163,7 @@ nvkm_disp_class_get(struct nvkm_oclass *oclass, int index,
{
struct nvkm_disp *disp = nvkm_disp(oclass->engine);
if (index == 0) {
oclass->base = disp->func->root->base;
oclass->engn = disp->func->root;
oclass->base = disp->func->root;
*class = &nvkm_disp_sclass;
return 0;
}

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/capsgv100.c
View File

@ -20,7 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#define gv100_disp_caps(p) container_of((p), struct gv100_disp_caps, object)
#include "rootnv50.h"
#include "priv.h"
struct gv100_disp_caps {
struct nvkm_object object;

1
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
View File

@ -22,7 +22,6 @@
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <core/notify.h>

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
g84_disp = {
@ -39,7 +41,15 @@ g84_disp = {
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &g84_disp_root_oclass,
.root = { 0,0,G82_DISP },
.user = {
{{0,0,G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,G82_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,G82_DISP_CORE_CHANNEL_DMA }, g84_disp_core_new },
{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
g94_disp = {
@ -39,7 +41,15 @@ g94_disp = {
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = g94_sor_cnt, .new = g94_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &g94_disp_root_oclass,
.root = { 0,0,GT206_DISP },
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT206_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{}
},
};
int

13
drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c
View File

@ -23,7 +23,8 @@
#include "head.h"
#include "ior.h"
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
ga102_disp = {
@ -38,7 +39,15 @@ ga102_disp = {
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
.sor = { .cnt = gv100_sor_cnt, .new = ga102_sor_new },
.ramht_size = 0x2000,
.root = &ga102_disp_root_oclass,
.root = { 0, 0,GA102_DISP },
.user = {
{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
{{ 0, 0,GA102_DISP_CURSOR }, gv100_disp_curs_new },
{{ 0, 0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
{{ 0, 0,GA102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
{{ 0, 0,GA102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
{}
},
};
int

13
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
View File

@ -26,11 +26,12 @@
#include "ior.h"
#include "outp.h"
#include "channv50.h"
#include "rootnv50.h"
#include <core/ramht.h>
#include <subdev/timer.h>
#include <nvif/class.h>
void
gf119_disp_super(struct work_struct *work)
{
@ -264,7 +265,15 @@ gf119_disp = {
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gf119_sor_new },
.root = &gf119_disp_root_oclass,
.root = { 0,0,GF110_DISP },
.user = {
{{0,0,GF110_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GF110_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GF110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GF110_DISP_CORE_CHANNEL_DMA }, gf119_disp_core_new },
{{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
gk104_disp = {
@ -39,7 +41,15 @@ gk104_disp = {
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
.root = &gk104_disp_root_oclass,
.root = { 0,0,GK104_DISP },
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK104_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
gk110_disp = {
@ -39,7 +41,15 @@ gk110_disp = {
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
.root = &gk110_disp_root_oclass,
.root = { 0,0,GK110_DISP },
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK110_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
gm107_disp = {
@ -39,7 +41,15 @@ gm107_disp = {
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gm107_sor_new },
.root = &gm107_disp_root_oclass,
.root = { 0,0,GM107_DISP },
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GM107_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
gm200_disp = {
@ -39,7 +41,15 @@ gm200_disp = {
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new },
.root = &gm200_disp_root_oclass,
.root = { 0,0,GM200_DISP },
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GM200_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
gp100_disp = {
@ -38,7 +40,15 @@ gp100_disp = {
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new },
.root = &gp100_disp_root_oclass,
.root = { 0,0,GP100_DISP },
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GP100_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
int

13
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
View File

@ -25,7 +25,8 @@
#include "head.h"
#include "ior.h"
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static void
gp102_disp_intr_error(struct nvkm_disp *disp, int chid)
@ -65,7 +66,15 @@ gp102_disp = {
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new },
.root = &gp102_disp_root_oclass,
.root = { 0,0,GP102_DISP },
.user = {
{{0,0,GK104_DISP_CURSOR }, gp102_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gp102_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gp102_disp_base_new },
{{0,0,GP102_DISP_CORE_CHANNEL_DMA }, gp102_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
gt200_disp = {
@ -39,7 +41,15 @@ gt200_disp = {
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &gt200_disp_root_oclass,
.root = { 0,0,GT200_DISP },
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT200_DISP_CORE_CHANNEL_DMA }, g84_disp_core_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
View File

@ -24,7 +24,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
gt215_disp = {
@ -39,7 +41,15 @@ gt215_disp = {
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = g94_sor_cnt, .new = gt215_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &gt215_disp_root_oclass,
.root = { 0,0,GT214_DISP },
.user = {
{{0,0,GT214_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,GT214_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT214_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT214_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new },
{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{}
},
};
int

13
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
View File

@ -24,11 +24,12 @@
#include "ior.h"
#include "outp.h"
#include "channv50.h"
#include "rootnv50.h"
#include <core/gpuobj.h>
#include <subdev/timer.h>
#include <nvif/class.h>
int
gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask)
{
@ -439,7 +440,15 @@ gv100_disp = {
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
.sor = { .cnt = gv100_sor_cnt, .new = gv100_sor_new },
.ramht_size = 0x2000,
.root = &gv100_disp_root_oclass,
.root = { 0, 0,GV100_DISP },
.user = {
{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
{{ 0, 0,GV100_DISP_CURSOR }, gv100_disp_curs_new },
{{ 0, 0,GV100_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
{{ 0, 0,GV100_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
{{ 0, 0,GV100_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
View File

@ -22,7 +22,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
mcp77_disp = {
@ -37,7 +39,15 @@ mcp77_disp = {
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = g94_sor_cnt, .new = mcp77_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &g94_disp_root_oclass,
.root = { 0,0,GT206_DISP },
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT206_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{}
},
};
int

14
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
View File

@ -22,7 +22,9 @@
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nvkm_disp_func
mcp89_disp = {
@ -37,7 +39,15 @@ mcp89_disp = {
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = g94_sor_cnt, .new = mcp89_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &gt215_disp_root_oclass,
.root = { 0,0,GT214_DISP },
.user = {
{{0,0,GT214_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,GT214_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT214_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT214_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new },
{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{}
},
};
int

5
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
View File

@ -24,6 +24,8 @@
#include "priv.h"
#include "head.h"
#include <nvif/class.h>
static void
nv04_disp_intr(struct nvkm_disp *disp)
{
@ -54,7 +56,8 @@ nv04_disp_intr(struct nvkm_disp *disp)
static const struct nvkm_disp_func
nv04_disp = {
.intr = nv04_disp_intr,
.root = &nv04_disp_root_oclass,
.root = { 0, 0, NV04_DISP },
.user = { {} },
};
int

13
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
View File

@ -26,7 +26,6 @@
#include "ior.h"
#include "outp.h"
#include "channv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <core/ramht.h>
@ -37,6 +36,8 @@
#include <subdev/devinit.h>
#include <subdev/timer.h>
#include <nvif/class.h>
void *
nv50_disp_dtor_(struct nvkm_disp *disp)
{
@ -727,7 +728,15 @@ nv50_disp = {
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = nv50_sor_cnt, .new = nv50_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &nv50_disp_root_oclass,
.root = { 0, 0, NV50_DISP },
.user = {
{{0,0,NV50_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,NV50_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,NV50_DISP_BASE_CHANNEL_DMA }, nv50_disp_base_new },
{{0,0,NV50_DISP_CORE_CHANNEL_DMA }, nv50_disp_core_new },
{{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new },
{}
}
};
int

1
drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c
View File

@ -22,7 +22,6 @@
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <subdev/timer.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c
View File

@ -22,7 +22,6 @@
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <subdev/timer.h>

21
drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVKM_DISP_PRIV_H__
#define __NVKM_DISP_PRIV_H__
#define nvkm_udisp(p) container_of((p), struct nvkm_disp, client.object)
#include <engine/disp.h>
#include <core/enum.h>
struct nvkm_head;
@ -32,12 +33,18 @@ struct nvkm_disp_func {
u16 ramht_size;
const struct nvkm_disp_oclass *root;
const struct nvkm_sclass root;
struct nvkm_disp_user {
struct nvkm_sclass base;
int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc, struct nvkm_disp *,
struct nvkm_object **);
} user[];
};
int nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
extern const struct nvkm_disp_oclass nv04_disp_root_oclass;
int nv04_disp_mthd(struct nvkm_object *, u32, void *, u32);
int nv50_disp_root_mthd_(struct nvkm_object *, u32, void *, u32);
void *nv50_disp_dtor_(struct nvkm_disp *);
int nv50_disp_oneinit_(struct nvkm_disp *);
@ -71,6 +78,8 @@ void gv100_disp_fini(struct nvkm_disp *);
void gv100_disp_intr(struct nvkm_disp *);
void gv100_disp_super(struct work_struct *);
int gv100_disp_wndw_cnt(struct nvkm_disp *, unsigned long *);
int gv100_disp_caps_new(const struct nvkm_oclass *, void *, u32,
struct nvkm_disp *, struct nvkm_object **);
int tu102_disp_init(struct nvkm_disp *);
@ -86,9 +95,5 @@ void nv50_disp_chan_uevent_send(struct nvkm_disp *, int);
extern const struct nvkm_event_func gf119_disp_chan_uevent;
extern const struct nvkm_event_func gv100_disp_chan_uevent;
struct nvkm_disp_oclass {
int (*ctor)(struct nvkm_disp *, const struct nvkm_oclass *,
void *data, u32 size, struct nvkm_object **);
struct nvkm_sclass base;
};
int nvkm_udisp_new(const struct nvkm_oclass *, void *, u32, struct nvkm_object **);
#endif

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
g84_disp_root = {
.user = {
{{0,0,G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,G82_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,G82_DISP_CORE_CHANNEL_DMA }, g84_disp_core_new },
{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{}
},
};
static int
g84_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&g84_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
g84_disp_root_oclass = {
.base.oclass = G82_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = g84_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
g94_disp_root = {
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT206_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{}
},
};
static int
g94_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&g94_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
g94_disp_root_oclass = {
.base.oclass = GT206_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = g94_disp_root_new,
};

52
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootga102.c
View File

@ -1,52 +0,0 @@
/*
* Copyright 2021 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
ga102_disp_root = {
.user = {
{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
{{0,0,GA102_DISP_CURSOR }, gv100_disp_curs_new },
{{0,0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
{{0,0,GA102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
{{0,0,GA102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
{}
},
};
static int
ga102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&ga102_disp_root, disp, oclass, data, size, pobject);
}
const struct nvkm_disp_oclass
ga102_disp_root_oclass = {
.base.oclass = GA102_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = ga102_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gf119_disp_root = {
.user = {
{{0,0,GF110_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GF110_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GF110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GF110_DISP_CORE_CHANNEL_DMA }, gf119_disp_core_new },
{{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new },
{}
},
};
static int
gf119_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gf119_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gf119_disp_root_oclass = {
.base.oclass = GF110_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gf119_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gk104_disp_root = {
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK104_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
static int
gk104_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gk104_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gk104_disp_root_oclass = {
.base.oclass = GK104_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gk104_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gk110_disp_root = {
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK110_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
static int
gk110_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gk110_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gk110_disp_root_oclass = {
.base.oclass = GK110_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gk110_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gm107_disp_root = {
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GM107_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
static int
gm107_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gm107_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gm107_disp_root_oclass = {
.base.oclass = GM107_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gm107_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gm200_disp_root = {
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GM200_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
static int
gm200_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gm200_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gm200_disp_root_oclass = {
.base.oclass = GM200_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gm200_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gp100_disp_root = {
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GP100_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
};
static int
gp100_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gp100_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gp100_disp_root_oclass = {
.base.oclass = GP100_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gp100_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2016 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gp102_disp_root = {
.user = {
{{0,0,GK104_DISP_CURSOR }, gp102_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gp102_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gp102_disp_base_new },
{{0,0,GP102_DISP_CORE_CHANNEL_DMA }, gp102_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },
{}
},
};
static int
gp102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gp102_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gp102_disp_root_oclass = {
.base.oclass = GP102_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gp102_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gt200_disp_root = {
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT200_DISP_CORE_CHANNEL_DMA }, g84_disp_core_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{}
},
};
static int
gt200_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gt200_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gt200_disp_root_oclass = {
.base.oclass = GT200_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gt200_disp_root_new,
};

55
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c
View File

@ -1,55 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gt215_disp_root = {
.user = {
{{0,0,GT214_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,GT214_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT214_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT214_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new },
{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{}
},
};
static int
gt215_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gt215_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gt215_disp_root_oclass = {
.base.oclass = GT214_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gt215_disp_root_new,
};

53
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c
View File

@ -1,53 +0,0 @@
/*
* Copyright 2018 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gv100_disp_root = {
.user = {
{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
{{0,0,GV100_DISP_CURSOR }, gv100_disp_curs_new },
{{0,0,GV100_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
{{0,0,GV100_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
{{0,0,GV100_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
{}
},
};
static int
gv100_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&gv100_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
gv100_disp_root_oclass = {
.base.oclass = GV100_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = gv100_disp_root_new,
};

42
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c
View File

@ -21,25 +21,18 @@
*
* Authors: Ben Skeggs
*/
#define nv04_disp_root(p) container_of((p), struct nv04_disp_root, object)
#include "priv.h"
#include "head.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/cl0046.h>
#include <nvif/unpack.h>
struct nv04_disp_root {
struct nvkm_object object;
struct nvkm_disp *disp;
};
static int
int
nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
struct nv04_disp_root *root = nv04_disp_root(object);
struct nvkm_disp *disp = nvkm_disp(object->engine);
union {
struct nv04_disp_mthd_v0 v0;
} *args = data;
@ -55,7 +48,7 @@ nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
} else
return ret;
if (!(head = nvkm_head_find(root->disp, id)))
if (!(head = nvkm_head_find(disp, id)))
return -ENXIO;
switch (mthd) {
@ -67,32 +60,3 @@ nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
return -EINVAL;
}
static const struct nvkm_object_func
nv04_disp_root = {
.mthd = nv04_disp_mthd,
.ntfy = nvkm_disp_ntfy,
};
static int
nv04_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
struct nv04_disp_root *root;
if (!(root = kzalloc(sizeof(*root), GFP_KERNEL)))
return -ENOMEM;
root->disp = disp;
*pobject = &root->object;
nvkm_object_ctor(&nv04_disp_root, oclass, &root->object);
return 0;
}
const struct nvkm_disp_oclass
nv04_disp_root_oclass = {
.base.oclass = NV04_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = nv04_disp_root_new,
};

91
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
View File

@ -21,7 +21,6 @@
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "channv50.h"
#include "head.h"
#include "ior.h"
@ -33,15 +32,14 @@
#include <nvif/cl5070.h>
#include <nvif/unpack.h>
static int
int
nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
union {
struct nv50_disp_mthd_v0 v0;
struct nv50_disp_mthd_v1 v1;
} *args = data;
struct nv50_disp_root *root = nv50_disp_root(object);
struct nvkm_disp *disp = root->disp;
struct nvkm_disp *disp = nvkm_udisp(object);
struct nvkm_outp *temp, *outp = NULL;
struct nvkm_head *head;
u16 type, mask = 0;
@ -271,88 +269,3 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
return -EINVAL;
}
static int
nv50_disp_root_child_new_(const struct nvkm_oclass *oclass,
void *argv, u32 argc, struct nvkm_object **pobject)
{
struct nvkm_disp *disp = nv50_disp_root(oclass->parent)->disp;
const struct nv50_disp_user *user = oclass->priv;
return user->ctor(oclass, argv, argc, disp, pobject);
}
static int
nv50_disp_root_child_get_(struct nvkm_object *object, int index,
struct nvkm_oclass *sclass)
{
struct nv50_disp_root *root = nv50_disp_root(object);
if (root->func->user[index].ctor) {
sclass->base = root->func->user[index].base;
sclass->priv = root->func->user + index;
sclass->ctor = nv50_disp_root_child_new_;
return 0;
}
return -EINVAL;
}
static void *
nv50_disp_root_dtor_(struct nvkm_object *object)
{
struct nv50_disp_root *root = nv50_disp_root(object);
return root;
}
static const struct nvkm_object_func
nv50_disp_root_ = {
.dtor = nv50_disp_root_dtor_,
.mthd = nv50_disp_root_mthd_,
.ntfy = nvkm_disp_ntfy,
.sclass = nv50_disp_root_child_get_,
};
int
nv50_disp_root_new_(const struct nv50_disp_root_func *func,
struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
struct nv50_disp_root *root;
if (!(root = kzalloc(sizeof(*root), GFP_KERNEL)))
return -ENOMEM;
*pobject = &root->object;
nvkm_object_ctor(&nv50_disp_root_, oclass, &root->object);
root->func = func;
root->disp = disp;
return 0;
}
static const struct nv50_disp_root_func
nv50_disp_root = {
.user = {
{{0,0,NV50_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,NV50_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,NV50_DISP_BASE_CHANNEL_DMA }, nv50_disp_base_new },
{{0,0,NV50_DISP_CORE_CHANNEL_DMA }, nv50_disp_core_new },
{{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new },
{}
},
};
static int
nv50_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&nv50_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
nv50_disp_root_oclass = {
.base.oclass = NV50_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = nv50_disp_root_new,
};

45
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
View File

@ -1,45 +0,0 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NV50_DISP_ROOT_H__
#define __NV50_DISP_ROOT_H__
#define nv50_disp_root(p) container_of((p), struct nv50_disp_root, object)
#include <core/object.h>
#include "priv.h"
struct nv50_disp_root {
const struct nv50_disp_root_func *func;
struct nvkm_disp *disp;
struct nvkm_object object;
};
struct nv50_disp_root_func {
int blah;
struct nv50_disp_user {
struct nvkm_sclass base;
int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_disp *, struct nvkm_object **);
} user[];
};
int nv50_disp_root_new_(const struct nv50_disp_root_func *, struct nvkm_disp *,
const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
int gv100_disp_caps_new(const struct nvkm_oclass *, void *, u32,
struct nvkm_disp *, struct nvkm_object **);
extern const struct nvkm_disp_oclass nv50_disp_root_oclass;
extern const struct nvkm_disp_oclass g84_disp_root_oclass;
extern const struct nvkm_disp_oclass g94_disp_root_oclass;
extern const struct nvkm_disp_oclass gt200_disp_root_oclass;
extern const struct nvkm_disp_oclass gt215_disp_root_oclass;
extern const struct nvkm_disp_oclass gf119_disp_root_oclass;
extern const struct nvkm_disp_oclass gk104_disp_root_oclass;
extern const struct nvkm_disp_oclass gk110_disp_root_oclass;
extern const struct nvkm_disp_oclass gm107_disp_root_oclass;
extern const struct nvkm_disp_oclass gm200_disp_root_oclass;
extern const struct nvkm_disp_oclass gp100_disp_root_oclass;
extern const struct nvkm_disp_oclass gp102_disp_root_oclass;
extern const struct nvkm_disp_oclass gv100_disp_root_oclass;
extern const struct nvkm_disp_oclass tu102_disp_root_oclass;
extern const struct nvkm_disp_oclass ga102_disp_root_oclass;
#endif

53
drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c
View File

@ -1,53 +0,0 @@
/*
* Copyright 2018 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "rootnv50.h"
#include "channv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
tu102_disp_root = {
.user = {
{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
{{0,0,TU102_DISP_CURSOR }, gv100_disp_curs_new },
{{0,0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
{{0,0,TU102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
{{0,0,TU102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
{}
},
};
static int
tu102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nv50_disp_root_new_(&tu102_disp_root, disp, oclass,
data, size, pobject);
}
const struct nvkm_disp_oclass
tu102_disp_root_oclass = {
.base.oclass = TU102_DISP,
.base.minver = -1,
.base.maxver = -1,
.ctor = tu102_disp_root_new,
};

13
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
View File

@ -23,11 +23,12 @@
#include "head.h"
#include "ior.h"
#include "channv50.h"
#include "rootnv50.h"
#include <core/gpuobj.h>
#include <subdev/timer.h>
#include <nvif/class.h>
int
tu102_disp_init(struct nvkm_disp *disp)
{
@ -144,7 +145,15 @@ tu102_disp = {
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
.sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new },
.ramht_size = 0x2000,
.root = &tu102_disp_root_oclass,
.root = { 0, 0,TU102_DISP },
.user = {
{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
{{ 0, 0,TU102_DISP_CURSOR }, gv100_disp_curs_new },
{{ 0, 0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
{{ 0, 0,TU102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
{{ 0, 0,TU102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
{}
},
};
int

100
drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.c Normal file
View File

@ -0,0 +1,100 @@
/*
* Copyright 2021 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <nvif/if0010.h>
static int
nvkm_udisp_sclass_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
struct nvkm_disp *disp = nvkm_udisp(oclass->parent);
const struct nvkm_disp_user *user = oclass->priv;
return user->ctor(oclass, argv, argc, disp, pobject);
}
static int
nvkm_udisp_sclass(struct nvkm_object *object, int index, struct nvkm_oclass *sclass)
{
struct nvkm_disp *disp = nvkm_udisp(object);
if (disp->func->user[index].ctor) {
sclass->base = disp->func->user[index].base;
sclass->priv = disp->func->user + index;
sclass->ctor = nvkm_udisp_sclass_new;
return 0;
}
return -EINVAL;
}
static int
nvkm_udisp_mthd(struct nvkm_object *object, u32 mthd, void *argv, u32 argc)
{
struct nvkm_disp *disp = nvkm_udisp(object);
if (disp->engine.subdev.device->card_type >= NV_50)
return nv50_disp_root_mthd_(object, mthd, argv, argc);
return nv04_disp_mthd(object, mthd, argv, argc);
}
static void *
nvkm_udisp_dtor(struct nvkm_object *object)
{
struct nvkm_disp *disp = nvkm_udisp(object);
spin_lock(&disp->client.lock);
if (object == &disp->client.object)
disp->client.object.func = NULL;
spin_unlock(&disp->client.lock);
return NULL;
}
static const struct nvkm_object_func
nvkm_udisp = {
.dtor = nvkm_udisp_dtor,
.mthd = nvkm_udisp_mthd,
.ntfy = nvkm_disp_ntfy,
.sclass = nvkm_udisp_sclass,
};
int
nvkm_udisp_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, struct nvkm_object **pobject)
{
struct nvkm_disp *disp = nvkm_disp(oclass->engine);
union nvif_disp_args *args = argv;
if (argc != sizeof(args->v0) || args->v0.version != 0)
return -ENOSYS;
spin_lock(&disp->client.lock);
if (disp->client.object.func) {
spin_unlock(&disp->client.lock);
return -EBUSY;
}
nvkm_object_ctor(&nvkm_udisp, oclass, &disp->client.object);
*pobject = &disp->client.object;
spin_unlock(&disp->client.lock);
return 0;
}