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Renesas ARM Based SoC Cleanup for v4.7

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* Remove unnecessary clock-output-names properties from DT
 * Use generic pinctrl properties in DT
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Merge tag 'renesas-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC Cleanup for v4.7

* Remove unnecessary clock-output-names properties from DT
* Use generic pinctrl properties in DT

* tag 'renesas-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (26 commits)
  ARM: dts: sh73a0: Remove unnecessary clock-output-names properties
  ARM: dts: r8a73a4: Remove unnecessary clock-output-names properties
  ARM: dts: lager: Remove unnecessary clock-output-names properties
  ARM: dts: porter: Remove unnecessary clock-output-names properties
  ARM: dts: koelsch: Remove unnecessary clock-output-names properties
  ARM: dts: gose: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7794: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7793: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7791: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7779: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7778: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7740: Remove unnecessary clock-output-names properties
  ARM: dts: r7s72100: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7790: Remove unnecessary clock-output-names properties
  ARM: dts: kzm9d: use generic pinctrl properties
  ARM: dts: kzm9g: use generic pinctrl properties
  ARM: dts: silk: use generic pinctrl properties
  ARM: dts: alt: use generic pinctrl properties
  ARM: dts: gose: use generic pinctrl properties
  ARM: dts: porter: use generic pinctrl properties
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-04-13 12:15:09 -07:00
commit 16757cbcd4
22 changed files with 432 additions and 628 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/emev2-kzm9d.dts
View File

@ -105,8 +105,8 @@
&pfc {
uart1_pins: serial@e1030000 {
renesas,groups = "uart1_ctrl", "uart1_data";
renesas,function = "uart1";
groups = "uart1_ctrl", "uart1_data";
function = "uart1";
};
};

15
arch/arm/boot/dts/r7s72100.dtsi
View File

@ -37,46 +37,41 @@
#size-cells = <1>;
/* External clocks */
extal_clk: extal_clk {
extal_clk: extal {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
clock-output-names = "extal";
};
usb_x1_clk: usb_x1_clk {
usb_x1_clk: usb_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
clock-output-names = "usb_x1";
};
/* Fixed factor clocks */
b_clk: b_clk {
b_clk: b {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <3>;
clock-output-names = "b";
};
p1_clk: p1_clk {
p1_clk: p1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <6>;
clock-output-names = "p1";
};
p0_clk: p0_clk {
p0_clk: p0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <12>;
clock-output-names = "p0";
};
/* Special CPG clocks */

20
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View File

@ -189,28 +189,28 @@
&pfc {
scifa0_pins: serial0 {
renesas,groups = "scifa0_data";
renesas,function = "scifa0";
groups = "scifa0_data";
function = "scifa0";
};
mmc0_pins: mmc {
renesas,groups = "mmc0_data8", "mmc0_ctrl";
renesas,function = "mmc0";
groups = "mmc0_data8", "mmc0_ctrl";
function = "mmc0";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
function = "sdhi0";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
};
keyboard_pins: keyboard {
renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327",
"PORT328", "PORT329";
pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328",
"PORT329";
bias-pull-up;
};
};

75
arch/arm/boot/dts/r8a73a4.dtsi
View File

@ -486,37 +486,32 @@
ranges;
/* External root clocks */
extalr_clk: extalr_clk {
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "extalr";
};
extal1_clk: extal1_clk {
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "extal1";
};
extal2_clk: extal2_clk {
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "extal2";
};
fsiack_clk: fsiack_clk {
fsiack_clk: fsiack {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
clock-output-names = "fsiack";
};
fsibck_clk: fsibck_clk {
fsibck_clk: fsibck {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
clock-output-names = "fsibck";
};
/* Special CPG clocks */
@ -540,171 +535,151 @@
#clock-cells = <0>;
clock-output-names = "zb";
};
sdhi0_clk: sdhi0_clk@e6150074 {
sdhi0_clk: sdhi0ck@e6150074 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150074 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "sdhi0ck";
};
sdhi1_clk: sdhi1_clk@e6150078 {
sdhi1_clk: sdhi1ck@e6150078 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150078 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "sdhi1ck";
};
sdhi2_clk: sdhi2_clk@e615007c {
sdhi2_clk: sdhi2ck@e615007c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615007c 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "sdhi2ck";
};
mmc0_clk: mmc0_clk@e6150240 {
mmc0_clk: mmc0@e6150240 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150240 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc0";
};
mmc1_clk: mmc1_clk@e6150244 {
mmc1_clk: mmc1@e6150244 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150244 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc1";
};
vclk1_clk: vclk1_clk@e6150008 {
vclk1_clk: vclk1@e6150008 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150008 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk1";
};
vclk2_clk: vclk2_clk@e615000c {
vclk2_clk: vclk2@e615000c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615000c 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk2";
};
vclk3_clk: vclk3_clk@e615001c {
vclk3_clk: vclk3@e615001c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615001c 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk3";
};
vclk4_clk: vclk4_clk@e6150014 {
vclk4_clk: vclk4@e6150014 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150014 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk4";
};
vclk5_clk: vclk5_clk@e6150034 {
vclk5_clk: vclk5@e6150034 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150034 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk5";
};
fsia_clk: fsia_clk@e6150018 {
fsia_clk: fsia@e6150018 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150018 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<&fsiack_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "fsia";
};
fsib_clk: fsib_clk@e6150090 {
fsib_clk: fsib@e6150090 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150090 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<&fsibck_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "fsib";
};
mp_clk: mp_clk@e6150080 {
mp_clk: mp@e6150080 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150080 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "mp";
};
m4_clk: m4_clk@e6150098 {
m4_clk: m4@e6150098 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150098 0 4>;
clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
#clock-cells = <0>;
clock-output-names = "m4";
};
hsi_clk: hsi_clk@e615026c {
hsi_clk: hsi@e615026c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615026c 0 4>;
clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
#clock-cells = <0>;
clock-output-names = "hsi";
};
spuv_clk: spuv_clk@e6150094 {
spuv_clk: spuv@e6150094 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150094 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "spuv";
};
/* Fixed factor clocks */
main_div2_clk: main_div2_clk {
main_div2_clk: main_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "main_div2";
};
pll0_div2_clk: pll0_div2_clk {
pll0_div2_clk: pll0_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll0_div2";
};
pll1_div2_clk: pll1_div2_clk {
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll1_div2";
};
extal1_div2_clk: extal1_div2_clk {
extal1_div2_clk: extal1_div2 {
compatible = "fixed-factor-clock";
clocks = <&extal1_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "extal1_div2";
};
/* Gate clocks */

34
arch/arm/boot/dts/r8a7740-armadillo800eva.dts
View File

@ -228,44 +228,44 @@
pinctrl-names = "default";
ether_pins: ether {
renesas,groups = "gether_mii", "gether_int";
renesas,function = "gether";
groups = "gether_mii", "gether_int";
function = "gether";
};
scifa1_pins: serial1 {
renesas,groups = "scifa1_data";
renesas,function = "scifa1";
groups = "scifa1_data";
function = "scifa1";
};
st1232_pins: touchscreen {
renesas,groups = "intc_irq10";
renesas,function = "intc";
groups = "intc_irq10";
function = "intc";
};
backlight_pins: backlight {
renesas,groups = "tpu0_to2_1";
renesas,function = "tpu0";
groups = "tpu0_to2_1";
function = "tpu0";
};
mmc0_pins: mmc0 {
renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
renesas,function = "mmc0";
groups = "mmc0_data8_1", "mmc0_ctrl_1";
function = "mmc0";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
function = "sdhi0";
};
fsia_pins: sounda {
renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
"fsia_data_in_1", "fsia_data_out_0";
renesas,function = "fsia";
groups = "fsia_sclk_in", "fsia_mclk_out",
"fsia_data_in_1", "fsia_data_out_0";
function = "fsia";
};
lcd0_pins: lcd0 {
renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
renesas,function = "lcd0";
groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
function = "lcd0";
/* DBGMD/LCDC0/FSIA MUX */
gpio-hog;

57
arch/arm/boot/dts/r8a7740.dtsi
View File

@ -422,53 +422,45 @@
ranges;
/* External root clock */
extalr_clk: extalr_clk {
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "extalr";
};
extal1_clk: extal1_clk {
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "extal1";
};
extal2_clk: extal2_clk {
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "extal2";
};
dv_clk: dv_clk {
dv_clk: dv {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "dv";
};
fmsick_clk: fmsick_clk {
fmsick_clk: fmsick {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fmsick";
};
fmsock_clk: fmsock_clk {
fmsock_clk: fmsock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fmsock";
};
fsiack_clk: fsiack_clk {
fsiack_clk: fsiack {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsiack";
};
fsibck_clk: fsibck_clk {
fsibck_clk: fsibck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsibck";
};
/* Special CPG clocks */
@ -486,7 +478,7 @@
};
/* Variable factor clocks (DIV6) */
vclk1_clk: vclk1_clk@e6150008 {
vclk1_clk: vclk1@e6150008 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150008 4>;
clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
@ -494,9 +486,8 @@
<&extal1_div2_clk>, <&extalr_clk>, <0>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk1";
};
vclk2_clk: vclk2_clk@e615000c {
vclk2_clk: vclk2@e615000c {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615000c 4>;
clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
@ -504,77 +495,67 @@
<&extal1_div2_clk>, <&extalr_clk>, <0>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk2";
};
fmsi_clk: fmsi_clk@e6150010 {
fmsi_clk: fmsi@e6150010 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150010 4>;
clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "fmsi";
};
fmso_clk: fmso_clk@e6150014 {
fmso_clk: fmso@e6150014 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150014 4>;
clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "fmso";
};
fsia_clk: fsia_clk@e6150018 {
fsia_clk: fsia@e6150018 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150018 4>;
clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "fsia";
};
sub_clk: sub_clk@e6150080 {
sub_clk: sub@e6150080 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150080 4>;
clocks = <&pllc1_div2_clk>,
<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "sub";
};
spu_clk: spu_clk@e6150084 {
spu_clk: spu@e6150084 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150084 4>;
clocks = <&pllc1_div2_clk>,
<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "spu";
};
vou_clk: vou_clk@e6150088 {
vou_clk: vou@e6150088 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150088 4>;
clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
<0>;
#clock-cells = <0>;
clock-output-names = "vou";
};
stpro_clk: stpro_clk@e615009c {
stpro_clk: stpro@e615009c {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615009c 4>;
clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
#clock-cells = <0>;
clock-output-names = "stpro";
};
/* Fixed factor clocks */
pllc1_div2_clk: pllc1_div2_clk {
pllc1_div2_clk: pllc1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pllc1_div2";
};
extal1_div2_clk: extal1_div2_clk {
extal1_div2_clk: extal1_div2 {
compatible = "fixed-factor-clock";
clocks = <&extal1_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "extal1_div2";
};
/* Gate clocks */

40
arch/arm/boot/dts/r8a7778-bockw.dts
View File

@ -130,53 +130,53 @@
pinctrl-names = "default";
scif0_pins: serial0 {
renesas,groups = "scif0_data_a", "scif0_ctrl";
renesas,function = "scif0";
groups = "scif0_data_a", "scif0_ctrl";
function = "scif0";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
mmc_pins: mmc {
renesas,groups = "mmc_data8", "mmc_ctrl";
renesas,function = "mmc";
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi0_pup_pins: sd0_pup {
renesas,groups = "sdhi0_cd", "sdhi0_wp";
renesas,function = "sdhi0";
groups = "sdhi0_cd", "sdhi0_wp";
function = "sdhi0";
bias-pull-up;
};
hspi0_pins: hspi0 {
renesas,groups = "hspi0_a";
renesas,function = "hspi0";
groups = "hspi0_a";
function = "hspi0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
vin1_pins: vin1 {
renesas,groups = "vin1_data8", "vin1_clk";
renesas,function = "vin1";
groups = "vin1_data8", "vin1_clk";
function = "vin1";
};
};

21
arch/arm/boot/dts/r8a7778.dtsi
View File

@ -443,11 +443,10 @@
ranges;
/* External input clock */
extal_clk: extal_clk {
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "extal";
};
/* External SCIF clock */
@ -474,59 +473,51 @@
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "audio_clk_a";
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "audio_clk_b";
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "audio_clk_c";
};
/* Fixed ratio clocks */
g_clk: g_clk {
g_clk: g {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "g";
};
i_clk: i_clk {
i_clk: i {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clock-output-names = "i";
};
s3_clk: s3_clk {
s3_clk: s3 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clock-output-names = "s3";
};
s4_clk: s4_clk {
s4_clk: s4 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "s4";
};
z_clk: z_clk {
z_clk: z {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clock-output-names = "z";
};
/* Gate clocks */

36
arch/arm/boot/dts/r8a7779-marzen.dts
View File

@ -170,49 +170,49 @@
du_pins: du {
du0 {
renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
renesas,function = "du0";
groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
function = "du0";
};
du1 {
renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
renesas,function = "du1";
groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
function = "du1";
};
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk_b";
renesas,function = "scif_clk";
groups = "scif_clk_b";
function = "scif_clk";
};
ethernet_pins: ethernet {
intc {
renesas,groups = "intc_irq1_b";
renesas,function = "intc";
groups = "intc_irq1_b";
function = "intc";
};
lbsc {
renesas,groups = "lbsc_ex_cs0";
renesas,function = "lbsc";
groups = "lbsc_ex_cs0";
function = "lbsc";
};
};
scif2_pins: serial2 {
renesas,groups = "scif2_data_c";
renesas,function = "scif2";
groups = "scif2_data_c";
function = "scif2";
};
scif4_pins: serial4 {
renesas,groups = "scif4_data";
renesas,function = "scif4";
groups = "scif4_data";
function = "scif4";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
function = "sdhi0";
};
hspi0_pins: hspi0 {
renesas,groups = "hspi0";
renesas,function = "hspi0";
groups = "hspi0";
function = "hspi0";
};
};

15
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -445,12 +445,11 @@
ranges;
/* External root clock */
extal_clk: extal_clk {
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overriden by the board. */
clock-frequency = <0>;
clock-output-names = "extal";
};
/* External SCIF clock */
@ -474,37 +473,33 @@
};
/* Fixed factor clocks */
i_clk: i_clk {
i_clk: i {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "i";
};
s3_clk: s3_clk {
s3_clk: s3 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "s3";
};
s4_clk: s4_clk {
s4_clk: s4 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <16>;
clock-mult = <1>;
clock-output-names = "s4";
};
g_clk: g_clk {
g_clk: g {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
clock-output-names = "g";
};
/* Gate clocks */

95
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -176,11 +176,10 @@
1800000 0>;
};
audio_clock: clock {
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
rsnd_ak4643: sound {
@ -314,119 +313,119 @@
pinctrl-names = "default";
du_pins: du {
renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
renesas,function = "du";
groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
function = "du";
};
scif0_pins: serial0 {
renesas,groups = "scif0_data";
renesas,function = "scif0";
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq0";
renesas,function = "intc";
groups = "intc_irq0";
function = "intc";
};
scifa1_pins: serial1 {
renesas,groups = "scifa1_data";
renesas,function = "scifa1";
groups = "scifa1_data";
function = "scifa1";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
};
mmc1_pins: mmc1 {
renesas,groups = "mmc1_data8", "mmc1_ctrl";
renesas,function = "mmc1";
groups = "mmc1_data8", "mmc1_ctrl";
function = "mmc1";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
msiof1_pins: spi2 {
renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
"msiof1_tx";
renesas,function = "msiof1";
function = "msiof1";
};
i2c0_pins: i2c0 {
renesas,groups = "i2c0";
renesas,function = "i2c0";
groups = "i2c0";
function = "i2c0";
};
iic0_pins: iic0 {
renesas,groups = "iic0";
renesas,function = "iic0";
groups = "iic0";
function = "iic0";
};
iic1_pins: iic1 {
renesas,groups = "iic1";
renesas,function = "iic1";
groups = "iic1";
function = "iic1";
};
iic2_pins: iic2 {
renesas,groups = "iic2";
renesas,function = "iic2";
groups = "iic2";
function = "iic2";
};
iic3_pins: iic3 {
renesas,groups = "iic3";
renesas,function = "iic3";
groups = "iic3";
function = "iic3";
};
hsusb_pins: hsusb {
renesas,groups = "usb0_ovc_vbus";
renesas,function = "usb0";
groups = "usb0_ovc_vbus";
function = "usb0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
usb2_pins: usb2 {
renesas,groups = "usb2";
renesas,function = "usb2";
groups = "usb2";
function = "usb2";
};
vin1_pins: vin {
renesas,groups = "vin1_data8", "vin1_clk";
renesas,function = "vin1";
groups = "vin1_data8", "vin1_clk";
function = "vin1";
};
sound_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
groups = "audio_clk_a";
function = "audio_clk";
};
};

88
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -1003,20 +1003,18 @@
ranges;
/* External root clock */
extal_clk: extal_clk {
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overriden by the board. */
clock-frequency = <0>;
clock-output-names = "extal";
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus_clk {
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "pcie_bus";
status = "disabled";
};
@ -1028,19 +1026,16 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_a";
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_b";
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_c";
};
/* External SCIF clock */
@ -1053,11 +1048,10 @@
};
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal_clk {
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "usb_extal";
};
/* External CAN clock */
@ -1066,7 +1060,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
clock-output-names = "can_clk";
status = "disabled";
};
@ -1084,201 +1077,176 @@
};
/* Variable factor clocks */
sd2_clk: sd2_clk@e6150078 {
sd2_clk: sd2@e6150078 {
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150078 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd2";
};
sd3_clk: sd3_clk@e615026c {
sd3_clk: sd3@e615026c {
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615026c 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd3";
};
mmc0_clk: mmc0_clk@e6150240 {
mmc0_clk: mmc0@e6150240 {
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150240 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc0";
};
mmc1_clk: mmc1_clk@e6150244 {
mmc1_clk: mmc1@e6150244 {
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150244 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc1";
};
ssp_clk: ssp_clk@e6150248 {
ssp_clk: ssp@e6150248 {
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150248 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "ssp";
};
ssprs_clk: ssprs_clk@e615024c {
ssprs_clk: ssprs@e615024c {
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615024c 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "ssprs";
};
/* Fixed factor clocks */
pll1_div2_clk: pll1_div2_clk {
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll1_div2";
};
z2_clk: z2_clk {
z2_clk: z2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "z2";
};
zg_clk: zg_clk {
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <3>;
clock-mult = <1>;
clock-output-names = "zg";
};
zx_clk: zx_clk {
zx_clk: zx {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <3>;
clock-mult = <1>;
clock-output-names = "zx";
};
zs_clk: zs_clk {
zs_clk: zs {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <6>;
clock-mult = <1>;
clock-output-names = "zs";
};
hp_clk: hp_clk {
hp_clk: hp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "hp";
};
i_clk: i_clk {
i_clk: i {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "i";
};
b_clk: b_clk {
b_clk: b {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "b";
};
p_clk: p_clk {
p_clk: p {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
clock-output-names = "p";
};
cl_clk: cl_clk {
cl_clk: cl {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <48>;
clock-mult = <1>;
clock-output-names = "cl";
};
m2_clk: m2_clk {
m2_clk: m2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "m2";
};
imp_clk: imp_clk {
imp_clk: imp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clock-output-names = "imp";
};
rclk_clk: rclk_clk {
rclk_clk: rclk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <(48 * 1024)>;
clock-mult = <1>;
clock-output-names = "rclk";
};
oscclk_clk: oscclk_clk {
oscclk_clk: oscclk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <(12 * 1024)>;
clock-mult = <1>;
clock-output-names = "oscclk";
};
zb3_clk: zb3_clk {
zb3_clk: zb3 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clock-output-names = "zb3";
};
zb3d2_clk: zb3d2_clk {
zb3d2_clk: zb3d2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "zb3d2";
};
ddr_clk: ddr_clk {
ddr_clk: ddr {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "ddr";
};
mp_clk: mp_clk {
mp_clk: mp {
compatible = "fixed-factor-clock";
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-div = <15>;
clock-mult = <1>;
clock-output-names = "mp";
};
cp_clk: cp_clk {
cp_clk: cp {
compatible = "fixed-factor-clock";
clocks = <&extal_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "cp";
};
/* Gate clocks */

71
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@ -242,11 +242,10 @@
1800000 0>;
};
audio_clock: clock {
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
rsnd_ak4643: sound {
@ -324,89 +323,89 @@
pinctrl-names = "default";
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
groups = "i2c2";
function = "i2c2";
};
du_pins: du {
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du";
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
scif0_pins: serial0 {
renesas,groups = "scif0_data_d";
renesas,function = "scif0";
groups = "scif0_data_d";
function = "scif0";
};
scif1_pins: serial1 {
renesas,groups = "scif1_data_d";
renesas,function = "scif1";
groups = "scif1_data_d";
function = "scif1";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq0";
renesas,function = "intc";
groups = "intc_irq0";
function = "intc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
msiof0_pins: spi1 {
renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
"msiof0_tx";
renesas,function = "msiof0";
function = "msiof0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
vin1_pins: vin1 {
renesas,groups = "vin1_data8", "vin1_clk";
renesas,function = "vin1";
groups = "vin1_data8", "vin1_clk";
function = "vin1";
};
sound_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
groups = "audio_clk_a";
function = "audio_clk";
};
};

63
arch/arm/boot/dts/r8a7791-porter.dts
View File

@ -113,11 +113,10 @@
clock-frequency = <74250000>;
};
x14_clk: x14-clock {
x14_clk: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
sound {
@ -147,78 +146,78 @@
pinctrl-names = "default";
scif0_pins: serial0 {
renesas,groups = "scif0_data_d";
renesas,function = "scif0";
groups = "scif0_data_d";
function = "scif0";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq0";
renesas,function = "intc";
groups = "intc_irq0";
function = "intc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
groups = "i2c2";
function = "i2c2";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
can0_pins: can0 {
renesas,groups = "can0_data";
renesas,function = "can0";
groups = "can0_data";
function = "can0";
};
du_pins: du {
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du";
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
ssi_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
audio_clk_pins: audio_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
groups = "audio_clk_a";
function = "audio_clk";
};
};

79
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -1048,12 +1048,11 @@
ranges;
/* External root clock */
extal_clk: extal_clk {
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overriden by the board. */
clock-frequency = <0>;
clock-output-names = "extal";
};
/*
@ -1064,27 +1063,23 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_a";
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_b";
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_c";
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus_clk {
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "pcie_bus";
status = "disabled";
};
@ -1098,11 +1093,10 @@
};
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal_clk {
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "usb_extal";
};
/* External CAN clock */
@ -1111,7 +1105,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
clock-output-names = "can_clk";
status = "disabled";
};
@ -1129,178 +1122,156 @@
};
/* Variable factor clocks */
sd2_clk: sd2_clk@e6150078 {
sd2_clk: sd2@e6150078 {
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150078 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd2";
};
sd3_clk: sd3_clk@e615026c {
sd3_clk: sd3@e615026c {
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615026c 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd3";
};
mmc0_clk: mmc0_clk@e6150240 {
mmc0_clk: mmc0@e6150240 {
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150240 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc0";
};
ssp_clk: ssp_clk@e6150248 {
ssp_clk: ssp@e6150248 {
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150248 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "ssp";
};
ssprs_clk: ssprs_clk@e615024c {
ssprs_clk: ssprs@e615024c {
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615024c 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "ssprs";
};
/* Fixed factor clocks */
pll1_div2_clk: pll1_div2_clk {
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll1_div2";
};
zg_clk: zg_clk {
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <3>;
clock-mult = <1>;
clock-output-names = "zg";
};
zx_clk: zx_clk {
zx_clk: zx {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <3>;
clock-mult = <1>;
clock-output-names = "zx";
};
zs_clk: zs_clk {
zs_clk: zs {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <6>;
clock-mult = <1>;
clock-output-names = "zs";
};
hp_clk: hp_clk {
hp_clk: hp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "hp";
};
i_clk: i_clk {
i_clk: i {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "i";
};
b_clk: b_clk {
b_clk: b {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "b";
};
p_clk: p_clk {
p_clk: p {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
clock-output-names = "p";
};
cl_clk: cl_clk {
cl_clk: cl {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <48>;
clock-mult = <1>;
clock-output-names = "cl";
};
m2_clk: m2_clk {
m2_clk: m2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "m2";
};
rclk_clk: rclk_clk {
rclk_clk: rclk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <(48 * 1024)>;
clock-mult = <1>;
clock-output-names = "rclk";
};
oscclk_clk: oscclk_clk {
oscclk_clk: oscclk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <(12 * 1024)>;
clock-mult = <1>;
clock-output-names = "oscclk";
};
zb3_clk: zb3_clk {
zb3_clk: zb3 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clock-output-names = "zb3";
};
zb3d2_clk: zb3d2_clk {
zb3d2_clk: zb3d2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "zb3d2";
};
ddr_clk: ddr_clk {
ddr_clk: ddr {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "ddr";
};
mp_clk: mp_clk {
mp_clk: mp {
compatible = "fixed-factor-clock";
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-div = <15>;
clock-mult = <1>;
clock-output-names = "mp";
};
cp_clk: cp_clk {
cp_clk: cp {
compatible = "fixed-factor-clock";
clocks = <&extal_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "cp";
};
/* Gate clocks */

43
arch/arm/boot/dts/r8a7793-gose.dts
View File

@ -158,11 +158,10 @@
};
};
audio_clock: clock {
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
rsnd_ak4643: sound {
@ -240,53 +239,53 @@
pinctrl-names = "default";
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
groups = "i2c2";
function = "i2c2";
};
du_pins: du {
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du";
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
scif0_pins: serial0 {
renesas,groups = "scif0_data_d";
renesas,function = "scif0";
groups = "scif0_data_d";
function = "scif0";
};
scif1_pins: serial1 {
renesas,groups = "scif1_data_d";
renesas,function = "scif1";
groups = "scif1_data_d";
function = "scif1";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq0";
renesas,function = "intc";
groups = "intc_irq0";
function = "intc";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
sound_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
groups = "audio_clk_a";
function = "audio_clk";
};
};

45
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -812,12 +812,11 @@
ranges;
/* External root clock */
extal_clk: extal_clk {
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
clock-output-names = "extal";
};
/*
@ -828,19 +827,16 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_a";
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_b";
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "audio_clk_c";
};
/* External SCIF clock */
@ -866,111 +862,98 @@
};
/* Variable factor clocks */
sd2_clk: sd2_clk@e6150078 {
sd2_clk: sd2@e6150078 {
compatible = "renesas,r8a7793-div6-clock",
"renesas,cpg-div6-clock";
reg = <0 0xe6150078 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd2";
};
sd3_clk: sd3_clk@e615026c {
sd3_clk: sd3@e615026c {
compatible = "renesas,r8a7793-div6-clock",
"renesas,cpg-div6-clock";
reg = <0 0xe615026c 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd3";
};
mmc0_clk: mmc0_clk@e6150240 {
mmc0_clk: mmc0@e6150240 {
compatible = "renesas,r8a7793-div6-clock",
"renesas,cpg-div6-clock";
reg = <0 0xe6150240 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc0";
};
/* Fixed factor clocks */
pll1_div2_clk: pll1_div2_clk {
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll1_div2";
};
zg_clk: zg_clk {
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <5>;
clock-mult = <1>;
clock-output-names = "zg";
};
zx_clk: zx_clk {
zx_clk: zx {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <3>;
clock-mult = <1>;
clock-output-names = "zx";
};
zs_clk: zs_clk {
zs_clk: zs {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <6>;
clock-mult = <1>;
clock-output-names = "zs";
};
hp_clk: hp_clk {
hp_clk: hp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "hp";
};
p_clk: p_clk {
p_clk: p {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
clock-output-names = "p";
};
m2_clk: m2_clk {
m2_clk: m2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "m2";
};
rclk_clk: rclk_clk {
rclk_clk: rclk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <(48 * 1024)>;
clock-mult = <1>;
clock-output-names = "rclk";
};
mp_clk: mp_clk {
mp_clk: mp {
compatible = "fixed-factor-clock";
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-div = <15>;
clock-mult = <1>;
clock-output-names = "mp";
};
cp_clk: cp_clk {
cp_clk: cp {
compatible = "fixed-factor-clock";
clocks = <&extal_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "cp";
};
/* Gate clocks */

32
arch/arm/boot/dts/r8a7794-alt.dts
View File

@ -107,38 +107,38 @@
pinctrl-names = "default";
du_pins: du {
renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
renesas,function = "du";
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
function = "du";
};
scif2_pins: serial2 {
renesas,groups = "scif2_data";
renesas,function = "scif2";
groups = "scif2_data";
function = "scif2";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq8";
renesas,function = "intc";
groups = "intc_irq8";
function = "intc";
};
i2c1_pins: i2c1 {
renesas,groups = "i2c1";
renesas,function = "i2c1";
groups = "i2c1";
function = "i2c1";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
};
@ -148,8 +148,8 @@
&pfc {
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
};

44
arch/arm/boot/dts/r8a7794-silk.dts
View File

@ -130,58 +130,58 @@
pinctrl-names = "default";
scif2_pins: serial2 {
renesas,groups = "scif2_data";
renesas,function = "scif2";
groups = "scif2_data";
function = "scif2";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq8";
renesas,function = "intc";
groups = "intc_irq8";
function = "intc";
};
i2c1_pins: i2c1 {
renesas,groups = "i2c1";
renesas,function = "i2c1";
groups = "i2c1";
function = "i2c1";
};
mmcif0_pins: mmcif0 {
renesas,groups = "mmc_data8", "mmc_ctrl";
renesas,function = "mmc";
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
};

66
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -836,12 +836,11 @@
ranges;
/* External root clock */
extal_clk: extal_clk {
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overriden by the board. */
clock-frequency = <0>;
clock-output-names = "extal";
};
/* External SCIF clock */
@ -865,173 +864,152 @@
#power-domain-cells = <0>;
};
/* Variable factor clocks */
sd2_clk: sd2_clk@e6150078 {
sd2_clk: sd2@e6150078 {
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150078 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd2";
};
sd3_clk: sd3_clk@e615026c {
sd3_clk: sd3@e615026c {
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615026c 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd3";
};
mmc0_clk: mmc0_clk@e6150240 {
mmc0_clk: mmc0@e6150240 {
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150240 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc0";
};
/* Fixed factor clocks */
pll1_div2_clk: pll1_div2_clk {
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll1_div2";
};
zg_clk: zg_clk {
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <6>;
clock-mult = <1>;
clock-output-names = "zg";
};
zx_clk: zx_clk {
zx_clk: zx {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <3>;
clock-mult = <1>;
clock-output-names = "zx";
};
zs_clk: zs_clk {
zs_clk: zs {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <6>;
clock-mult = <1>;
clock-output-names = "zs";
};
hp_clk: hp_clk {
hp_clk: hp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "hp";
};
i_clk: i_clk {
i_clk: i {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "i";
};
b_clk: b_clk {
b_clk: b {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "b";
};
p_clk: p_clk {
p_clk: p {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
clock-output-names = "p";
};
cl_clk: cl_clk {
cl_clk: cl {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <48>;
clock-mult = <1>;
clock-output-names = "cl";
};
m2_clk: m2_clk {
m2_clk: m2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "m2";
};
rclk_clk: rclk_clk {
rclk_clk: rclk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <(48 * 1024)>;
clock-mult = <1>;
clock-output-names = "rclk";
};
oscclk_clk: oscclk_clk {
oscclk_clk: oscclk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <(12 * 1024)>;
clock-mult = <1>;
clock-output-names = "oscclk";
};
zb3_clk: zb3_clk {
zb3_clk: zb3 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clock-output-names = "zb3";
};
zb3d2_clk: zb3d2_clk {
zb3d2_clk: zb3d2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "zb3d2";
};
ddr_clk: ddr_clk {
ddr_clk: ddr {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "ddr";
};
mp_clk: mp_clk {
mp_clk: mp {
compatible = "fixed-factor-clock";
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-div = <15>;
clock-mult = <1>;
clock-output-names = "mp";
};
cp_clk: cp_clk {
cp_clk: cp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <48>;
clock-mult = <1>;
clock-output-names = "cp";
};
acp_clk: acp_clk {
acp_clk: acp {
compatible = "fixed-factor-clock";
clocks = <&extal_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "acp";
};
/* Gate clocks */

30
arch/arm/boot/dts/sh73a0-kzm9g.dts
View File

@ -329,41 +329,41 @@
&pfc {
i2c3_pins: i2c3 {
renesas,groups = "i2c3_1";
renesas,function = "i2c3";
groups = "i2c3_1";
function = "i2c3";
};
mmcif_pins: mmc {
mux {
renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
renesas,function = "mmc0";
groups = "mmc0_data8_0", "mmc0_ctrl_0";
function = "mmc0";
};
cfg {
renesas,groups = "mmc0_data8_0";
renesas,pins = "PORT279";
groups = "mmc0_data8_0";
pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: serial4 {
renesas,groups = "scifa4_data", "scifa4_ctrl";
renesas,function = "scifa4";
groups = "scifa4_data", "scifa4_ctrl";
function = "scifa4";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
function = "sdhi0";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
};
fsia_pins: sounda {
renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
"fsia_data_in", "fsia_data_out";
renesas,function = "fsia";
groups = "fsia_mclk_in", "fsia_sclk_in",
"fsia_data_in", "fsia_data_out";
function = "fsia";
};
};

87
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -602,39 +602,33 @@
ranges;
/* External root clocks */
extalr_clk: extalr_clk {
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "extalr";
};
extal1_clk: extal1_clk {
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "extal1";
};
extal2_clk: extal2_clk {
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "extal2";
};
extcki_clk: extcki_clk {
extcki_clk: extcki {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "extcki";
};
fsiack_clk: fsiack_clk {
fsiack_clk: fsiack {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsiack";
};
fsibck_clk: fsibck_clk {
fsibck_clk: fsibck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsibck";
};
/* Special CPG clocks */
@ -650,7 +644,7 @@
};
/* Variable factor clocks (DIV6) */
vclk1_clk: vclk1_clk@e6150008 {
vclk1_clk: vclk1@e6150008 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150008 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
@ -658,9 +652,8 @@
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk1";
};
vclk2_clk: vclk2_clk@e615000c {
vclk2_clk: vclk2@e615000c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615000c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
@ -668,9 +661,8 @@
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk2";
};
vclk3_clk: vclk3_clk@e615001c {
vclk3_clk: vclk3@e615001c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615001c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
@ -678,7 +670,6 @@
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk3";
};
zb_clk: zb_clk@e6150010 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
@ -688,168 +679,148 @@
#clock-cells = <0>;
clock-output-names = "zb";
};
flctl_clk: flctl_clk@e6150014 {
flctl_clk: flctlck@e6150014 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150014 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "flctlck";
};
sdhi0_clk: sdhi0_clk@e6150074 {
sdhi0_clk: sdhi0ck@e6150074 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150074 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&pll1_div13_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "sdhi0ck";
};
sdhi1_clk: sdhi1_clk@e6150078 {
sdhi1_clk: sdhi1ck@e6150078 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150078 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&pll1_div13_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "sdhi1ck";
};
sdhi2_clk: sdhi2_clk@e615007c {
sdhi2_clk: sdhi2ck@e615007c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615007c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&pll1_div13_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "sdhi2ck";
};
fsia_clk: fsia_clk@e6150018 {
fsia_clk: fsia@e6150018 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150018 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&fsiack_clk>, <&fsiack_clk>;
#clock-cells = <0>;
clock-output-names = "fsia";
};
fsib_clk: fsib_clk@e6150090 {
fsib_clk: fsib@e6150090 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150090 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&fsibck_clk>, <&fsibck_clk>;
#clock-cells = <0>;
clock-output-names = "fsib";
};
sub_clk: sub_clk@e6150080 {
sub_clk: sub@e6150080 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150080 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "sub";
};
spua_clk: spua_clk@e6150084 {
spua_clk: spua@e6150084 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150084 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "spua";
};
spuv_clk: spuv_clk@e6150094 {
spuv_clk: spuv@e6150094 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150094 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "spuv";
};
msu_clk: msu_clk@e6150088 {
msu_clk: msu@e6150088 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150088 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "msu";
};
hsi_clk: hsi_clk@e615008c {
hsi_clk: hsi@e615008c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615008c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&pll1_div7_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "hsi";
};
mfg1_clk: mfg1_clk@e6150098 {
mfg1_clk: mfg1@e6150098 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150098 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "mfg1";
};
mfg2_clk: mfg2_clk@e615009c {
mfg2_clk: mfg2@e615009c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615009c 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "mfg2";
};
dsit_clk: dsit_clk@e6150060 {
dsit_clk: dsit@e6150060 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150060 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "dsit";
};
dsi0p_clk: dsi0p_clk@e6150064 {
dsi0p_clk: dsi0pck@e6150064 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150064 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
<&extcki_clk>, <0>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "dsi0pck";
};
/* Fixed factor clocks */
main_div2_clk: main_div2_clk {
main_div2_clk: main_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "main_div2";
};
pll1_div2_clk: pll1_div2_clk {
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll1_div2";
};
pll1_div7_clk: pll1_div7_clk {
pll1_div7_clk: pll1_div7 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <7>;
clock-mult = <1>;
clock-output-names = "pll1_div7";
};
pll1_div13_clk: pll1_div13_clk {
pll1_div13_clk: pll1_div13 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <13>;
clock-mult = <1>;
clock-output-names = "pll1_div13";
};
twd_clk: twd_clk {
twd_clk: twd {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_Z>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clock-output-names = "twd";
};
/* Gate clocks */