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tg3: Add read accessor for AUX CTRL phy reg

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This patch adds a read accessor for the aux ctrl register.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson 2011-04-20 07:57:40 +00:00 committed by David S. Miller
parent b0988c15c1
commit 15ee95c36d
2 changed files with 38 additions and 18 deletions
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39
drivers/net/tg3.c
View File

@ -949,6 +949,19 @@ static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
return err; return err;
} }
static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
{
int err;
err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
(reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
MII_TG3_AUXCTL_SHDWSEL_MISC);
if (!err)
err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
return err;
}
static int tg3_bmcr_reset(struct tg3 *tp) static int tg3_bmcr_reset(struct tg3 *tp)
{ {
u32 phy_control; u32 phy_control;
@ -1679,10 +1692,11 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
tg3_writephy(tp, MII_TG3_FET_TEST, ephy); tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
} }
} else { } else {
phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | int ret;
MII_TG3_AUXCTL_SHDWSEL_MISC;
if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && ret = tg3_phy_auxctl_read(tp,
!tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
if (!ret) {
if (enable) if (enable)
phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
else else
@ -1695,13 +1709,14 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
static void tg3_phy_set_wirespeed(struct tg3 *tp) static void tg3_phy_set_wirespeed(struct tg3 *tp)
{ {
int ret;
u32 val; u32 val;
if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
return; return;
if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
!tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) if (!ret)
tg3_writephy(tp, MII_TG3_AUX_CTRL, tg3_writephy(tp, MII_TG3_AUX_CTRL,
(val | (1 << 15) | (1 << 4))); (val | (1 << 15) | (1 << 4)));
} }
@ -2092,8 +2107,9 @@ out:
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
} else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
/* Set bit 14 with read-modify-write to preserve other bits */ /* Set bit 14 with read-modify-write to preserve other bits */
if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && err = tg3_phy_auxctl_read(tp,
!tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
if (!err)
tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000); tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
} }
@ -3263,9 +3279,10 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
current_duplex = DUPLEX_INVALID; current_duplex = DUPLEX_INVALID;
if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); err = tg3_phy_auxctl_read(tp,
tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
if (!(val & (1 << 10))) { &val);
if (!err && !(val & (1 << 10))) {
val |= (1 << 10); val |= (1 << 10);
tg3_writephy(tp, MII_TG3_AUX_CTRL, val); tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
goto relink; goto relink;

17
drivers/net/tg3.h
View File

@ -2194,19 +2194,22 @@
#define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */ #define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */
#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
#define MII_TG3_AUXCTL_MISC_WREN 0x8000 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
#define MII_TG3_AUXCTL_MISC_WREN 0x8000
#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
#define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */ #define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */
#define MII_TG3_AUX_STAT_LPASS 0x0004 #define MII_TG3_AUX_STAT_LPASS 0x0004