From 81c93798ef3ebd2109dc24371db3cc14cdf77777 Mon Sep 17 00:00:00 2001 From: Elia Devito Date: Sun, 4 Oct 2020 23:13:05 +0200 Subject: [PATCH 01/15] platform/x86: hp-wmi: add support for thermal policy HP Spectre notebooks (and probably other model as well) support up to 4 thermal policy: - HP Recommended - Performance - Cool - Quiet at least on HP Spectre x360 Convertible 15-df0xxx the firmware sets the thermal policy to default but hardcode the odvp0 variable to 1, this causes thermald to choose the wrong DPTF profile witch result in low performance when notebook is on AC, calling thermal policy write command allow firmware to correctly set the odvp0 variable. Signed-off-by: Elia Devito Link: https://lore.kernel.org/r/20201004211305.11628-1-eliadevito@gmail.com Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- drivers/platform/x86/hp-wmi.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/platform/x86/hp-wmi.c b/drivers/platform/x86/hp-wmi.c index 1762f335bac9..ecd477964d11 100644 --- a/drivers/platform/x86/hp-wmi.c +++ b/drivers/platform/x86/hp-wmi.c @@ -81,6 +81,7 @@ enum hp_wmi_commandtype { HPWMI_FEATURE2_QUERY = 0x0d, HPWMI_WIRELESS2_QUERY = 0x1b, HPWMI_POSTCODEERROR_QUERY = 0x2a, + HPWMI_THERMAL_POLICY_QUERY = 0x4c, }; enum hp_wmi_command { @@ -861,6 +862,26 @@ fail: return err; } +static int thermal_policy_setup(struct platform_device *device) +{ + int err, tp; + + tp = hp_wmi_read_int(HPWMI_THERMAL_POLICY_QUERY); + if (tp < 0) + return tp; + + /* + * call thermal policy write command to ensure that the firmware correctly + * sets the OEM variables for the DPTF + */ + err = hp_wmi_perform_query(HPWMI_THERMAL_POLICY_QUERY, HPWMI_WRITE, &tp, + sizeof(tp), 0); + if (err) + return err; + + return 0; +} + static int __init hp_wmi_bios_setup(struct platform_device *device) { /* clear detected rfkill devices */ @@ -872,6 +893,8 @@ static int __init hp_wmi_bios_setup(struct platform_device *device) if (hp_wmi_rfkill_setup(device)) hp_wmi_rfkill2_setup(device); + thermal_policy_setup(device); + return 0; } From 7566616fb968dcc9f11d3f6b57132d33acab4e35 Mon Sep 17 00:00:00 2001 From: Jonathan Doman Date: Wed, 30 Sep 2020 15:26:36 -0700 Subject: [PATCH 02/15] tools/power/x86/intel-speed-select: Fix missing base-freq core IDs The reported base-freq high-priority-cpu-list was potentially omitting some cpus, due to incorrectly using a logical core count to constrain the size of a physical punit core ID mask. We may need to read both high and low PBF CORE_MASK values regardless of the logical core count. Signed-off-by: Jonathan Doman Signed-off-by: Srinivas Pandruvada Signed-off-by: Hans de Goede --- .../x86/intel-speed-select/isst-config.c | 21 +++++++++++-------- .../power/x86/intel-speed-select/isst-core.c | 8 +++---- tools/power/x86/intel-speed-select/isst.h | 2 +- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/tools/power/x86/intel-speed-select/isst-config.c b/tools/power/x86/intel-speed-select/isst-config.c index 9f4b190f1d74..0bba5be8d1fd 100644 --- a/tools/power/x86/intel-speed-select/isst-config.c +++ b/tools/power/x86/intel-speed-select/isst-config.c @@ -545,20 +545,23 @@ static void set_cpu_present_cpu_mask(void) } } -int get_core_count(int pkg_id, int die_id) +int get_max_punit_core_id(int pkg_id, int die_id) { - int cnt = 0; + int max_id = 0; + int i; - if (pkg_id < MAX_PACKAGE_COUNT && die_id < MAX_DIE_PER_PACKAGE) { - int i; + for (i = 0; i < topo_max_cpus; ++i) + { + if (!CPU_ISSET_S(i, present_cpumask_size, present_cpumask)) + continue; - for (i = 0; i < sizeof(long long) * 8; ++i) { - if (core_mask[pkg_id][die_id] & (1ULL << i)) - cnt++; - } + if (cpu_map[i].pkg_id == pkg_id && + cpu_map[i].die_id == die_id && + cpu_map[i].punit_cpu_core > max_id) + max_id = cpu_map[i].punit_cpu_core; } - return cnt; + return max_id; } int get_cpu_count(int pkg_id, int die_id) diff --git a/tools/power/x86/intel-speed-select/isst-core.c b/tools/power/x86/intel-speed-select/isst-core.c index a7f4337c5777..1d7ecb54352e 100644 --- a/tools/power/x86/intel-speed-select/isst-core.c +++ b/tools/power/x86/intel-speed-select/isst-core.c @@ -396,7 +396,7 @@ int isst_get_pbf_info(int cpu, int level, struct isst_pbf_info *pbf_info) { struct isst_pkg_ctdp_level_info ctdp_level; struct isst_pkg_ctdp pkg_dev; - int i, ret, core_cnt, max; + int i, ret, max_punit_core, max_mask_index; unsigned int req, resp; ret = isst_get_ctdp_levels(cpu, &pkg_dev); @@ -421,10 +421,10 @@ int isst_get_pbf_info(int cpu, int level, struct isst_pbf_info *pbf_info) pbf_info->core_cpumask_size = alloc_cpu_set(&pbf_info->core_cpumask); - core_cnt = get_core_count(get_physical_package_id(cpu), get_physical_die_id(cpu)); - max = core_cnt > 32 ? 2 : 1; + max_punit_core = get_max_punit_core_id(get_physical_package_id(cpu), get_physical_die_id(cpu)); + max_mask_index = max_punit_core > 32 ? 2 : 1; - for (i = 0; i < max; ++i) { + for (i = 0; i < max_mask_index; ++i) { unsigned long long mask; int count; diff --git a/tools/power/x86/intel-speed-select/isst.h b/tools/power/x86/intel-speed-select/isst.h index 094ba4589a9c..29715e9c2e06 100644 --- a/tools/power/x86/intel-speed-select/isst.h +++ b/tools/power/x86/intel-speed-select/isst.h @@ -170,7 +170,7 @@ struct isst_pkg_ctdp { extern int get_topo_max_cpus(void); extern int get_cpu_count(int pkg_id, int die_id); -extern int get_core_count(int pkg_id, int die_id); +extern int get_max_punit_core_id(int pkg_id, int die_id); /* Common interfaces */ FILE *get_output_file(void); From e529412f3211071b4787a8e7e153c8ced3c22a28 Mon Sep 17 00:00:00 2001 From: Srinivas Pandruvada Date: Tue, 6 Oct 2020 06:26:31 -0700 Subject: [PATCH 03/15] tools/power/x86/intel-speed-select: Update version for v5.10 Update version for changes released with v5.10 kernel release. Signed-off-by: Srinivas Pandruvada Signed-off-by: Hans de Goede --- tools/power/x86/intel-speed-select/isst-config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/power/x86/intel-speed-select/isst-config.c b/tools/power/x86/intel-speed-select/isst-config.c index 0bba5be8d1fd..cd089a505859 100644 --- a/tools/power/x86/intel-speed-select/isst-config.c +++ b/tools/power/x86/intel-speed-select/isst-config.c @@ -15,7 +15,7 @@ struct process_cmd_struct { int arg; }; -static const char *version_str = "v1.5"; +static const char *version_str = "v1.6"; static const int supported_api_ver = 1; static struct isst_if_platform_info isst_platform_info; static char *progname; From e973f1d372dca5ac1d107ec6134f72e566fdf968 Mon Sep 17 00:00:00 2001 From: "David E. Box" Date: Tue, 6 Oct 2020 15:47:00 -0700 Subject: [PATCH 04/15] platform/x86: pmc_core: Use descriptive names for LPM registers TigerLake Lower Power Mode (LPM) registers are grouped by functionality but were given simple enumerated names in the code (lpm0, lpm1, ...). Instead, give the register blocks names that describe their usage. Suggested-by: Andy Shevchenko Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20201006224702.12697-2-david.e.box@linux.intel.com Signed-off-by: Hans de Goede --- drivers/platform/x86/intel_pmc_core.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 338ea5222555..ed9fdf7c8928 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -409,7 +409,7 @@ static const struct pmc_reg_map icl_reg_map = { .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED, }; -static const struct pmc_bit_map tgl_lpm0_map[] = { +static const struct pmc_bit_map tgl_clocksource_status_map[] = { {"USB2PLL_OFF_STS", BIT(18)}, {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)}, {"PCIe_Gen3PLL_OFF_STS", BIT(20)}, @@ -425,7 +425,7 @@ static const struct pmc_bit_map tgl_lpm0_map[] = { {} }; -static const struct pmc_bit_map tgl_lpm1_map[] = { +static const struct pmc_bit_map tgl_power_gating_status_map[] = { {"SPI_PG_STS", BIT(2)}, {"xHCI_PG_STS", BIT(3)}, {"PCIe_Ctrller_A_PG_STS", BIT(4)}, @@ -453,7 +453,7 @@ static const struct pmc_bit_map tgl_lpm1_map[] = { {} }; -static const struct pmc_bit_map tgl_lpm2_map[] = { +static const struct pmc_bit_map tgl_d3_status_map[] = { {"ADSP_D3_STS", BIT(0)}, {"SATA_D3_STS", BIT(1)}, {"xHCI0_D3_STS", BIT(2)}, @@ -468,7 +468,7 @@ static const struct pmc_bit_map tgl_lpm2_map[] = { {} }; -static const struct pmc_bit_map tgl_lpm3_map[] = { +static const struct pmc_bit_map tgl_vnn_req_status_map[] = { {"GPIO_COM0_VNN_REQ_STS", BIT(1)}, {"GPIO_COM1_VNN_REQ_STS", BIT(2)}, {"GPIO_COM2_VNN_REQ_STS", BIT(3)}, @@ -493,7 +493,7 @@ static const struct pmc_bit_map tgl_lpm3_map[] = { {} }; -static const struct pmc_bit_map tgl_lpm4_map[] = { +static const struct pmc_bit_map tgl_vnn_misc_status_map[] = { {"CPU_C10_REQ_STS_0", BIT(0)}, {"PCIe_LPM_En_REQ_STS_3", BIT(3)}, {"ITH_REQ_STS_5", BIT(5)}, @@ -509,7 +509,7 @@ static const struct pmc_bit_map tgl_lpm4_map[] = { {} }; -static const struct pmc_bit_map tgl_lpm5_map[] = { +static const struct pmc_bit_map tgl_signal_status_map[] = { {"LSX_Wake0_En_STS", BIT(0)}, {"LSX_Wake0_Pol_STS", BIT(1)}, {"LSX_Wake1_En_STS", BIT(2)}, @@ -546,12 +546,12 @@ static const struct pmc_bit_map tgl_lpm5_map[] = { }; static const struct pmc_bit_map *tgl_lpm_maps[] = { - tgl_lpm0_map, - tgl_lpm1_map, - tgl_lpm2_map, - tgl_lpm3_map, - tgl_lpm4_map, - tgl_lpm5_map, + tgl_clocksource_status_map, + tgl_power_gating_status_map, + tgl_d3_status_map, + tgl_vnn_req_status_map, + tgl_vnn_misc_status_map, + tgl_signal_status_map, NULL }; From 652036bd5be0ac94fd1db851d72ece8ee133c74d Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 6 Oct 2020 15:47:01 -0700 Subject: [PATCH 05/15] platform/x86: intel_pmc_core: Fix TigerLake power gating status map TigerLake's LPM power gating status register has errors in the bit-to-name mapping as well as with the marked reserved bits according to the actual implementation. Hence, update the right bit-to-name mapping and the reserved bits in accordance with actual implementation. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20201006224702.12697-3-david.e.box@linux.intel.com Signed-off-by: Hans de Goede --- drivers/platform/x86/intel_pmc_core.c | 48 +++++++++++++-------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index ed9fdf7c8928..cf4006e08c69 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -426,30 +426,30 @@ static const struct pmc_bit_map tgl_clocksource_status_map[] = { }; static const struct pmc_bit_map tgl_power_gating_status_map[] = { - {"SPI_PG_STS", BIT(2)}, - {"xHCI_PG_STS", BIT(3)}, - {"PCIe_Ctrller_A_PG_STS", BIT(4)}, - {"PCIe_Ctrller_B_PG_STS", BIT(5)}, - {"PCIe_Ctrller_C_PG_STS", BIT(6)}, - {"GBE_PG_STS", BIT(7)}, - {"SATA_PG_STS", BIT(8)}, - {"HDA0_PG_STS", BIT(9)}, - {"HDA1_PG_STS", BIT(10)}, - {"HDA2_PG_STS", BIT(11)}, - {"HDA3_PG_STS", BIT(12)}, - {"PCIe_Ctrller_D_PG_STS", BIT(13)}, - {"ISIO_PG_STS", BIT(14)}, - {"SMB_PG_STS", BIT(16)}, - {"ISH_PG_STS", BIT(17)}, - {"ITH_PG_STS", BIT(19)}, - {"SDX_PG_STS", BIT(20)}, - {"xDCI_PG_STS", BIT(25)}, - {"DCI_PG_STS", BIT(26)}, - {"CSME0_PG_STS", BIT(27)}, - {"CSME_KVM_PG_STS", BIT(28)}, - {"CSME1_PG_STS", BIT(29)}, - {"CSME_CLINK_PG_STS", BIT(30)}, - {"CSME2_PG_STS", BIT(31)}, + {"CSME_PG_STS", BIT(0)}, + {"SATA_PG_STS", BIT(1)}, + {"xHCI_PG_STS", BIT(2)}, + {"UFSX2_PG_STS", BIT(3)}, + {"OTG_PG_STS", BIT(5)}, + {"SPA_PG_STS", BIT(6)}, + {"SPB_PG_STS", BIT(7)}, + {"SPC_PG_STS", BIT(8)}, + {"SPD_PG_STS", BIT(9)}, + {"SPE_PG_STS", BIT(10)}, + {"SPF_PG_STS", BIT(11)}, + {"LSX_PG_STS", BIT(13)}, + {"P2SB_PG_STS", BIT(14)}, + {"PSF_PG_STS", BIT(15)}, + {"SBR_PG_STS", BIT(16)}, + {"OPIDMI_PG_STS", BIT(17)}, + {"THC0_PG_STS", BIT(18)}, + {"THC1_PG_STS", BIT(19)}, + {"GBETSN_PG_STS", BIT(20)}, + {"GBE_PG_STS", BIT(21)}, + {"LPSS_PG_STS", BIT(22)}, + {"MMP_UFSX2_PG_STS", BIT(23)}, + {"MMP_UFSX2B_PG_STS", BIT(24)}, + {"FIA_PG_STS", BIT(25)}, {} }; From 025f26de7fa0fc40c8baf6c19fb273500f3321f0 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 6 Oct 2020 15:47:02 -0700 Subject: [PATCH 06/15] platform/x86: intel_pmc_core: Fix the slp_s0 counter displayed value slp_s0 counter value displayed via debugfs interface is calculated by multiplying the granularity for crystal oscillator tick as 100us with the value read from using slp_s0 offset. But the granularity of the tick varies from platform to platform and it needs to be fixed. Hence, specify granularity of the tick for each platform, so that the value of the slp_s0 counter is accurate. Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20201006224702.12697-4-david.e.box@linux.intel.com Signed-off-by: Hans de Goede --- drivers/platform/x86/intel_pmc_core.c | 10 +++++++--- drivers/platform/x86/intel_pmc_core.h | 5 ++++- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index cf4006e08c69..122eb53eb595 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -154,6 +154,7 @@ static const struct pmc_reg_map spt_reg_map = { .ltr_show_sts = spt_ltr_show_map, .msr_sts = msr_map, .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET, + .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP, .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET, .regmap_length = SPT_PMC_MMIO_REG_LEN, .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A, @@ -380,6 +381,7 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { static const struct pmc_reg_map cnp_reg_map = { .pfear_sts = ext_cnp_pfear_map, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, + .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP, .slps0_dbg_maps = cnp_slps0_dbg_maps, .ltr_show_sts = cnp_ltr_show_map, .msr_sts = msr_map, @@ -396,6 +398,7 @@ static const struct pmc_reg_map cnp_reg_map = { static const struct pmc_reg_map icl_reg_map = { .pfear_sts = ext_icl_pfear_map, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, + .slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP, .slps0_dbg_maps = cnp_slps0_dbg_maps, .ltr_show_sts = cnp_ltr_show_map, .msr_sts = msr_map, @@ -558,6 +561,7 @@ static const struct pmc_bit_map *tgl_lpm_maps[] = { static const struct pmc_reg_map tgl_reg_map = { .pfear_sts = ext_tgl_pfear_map, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, + .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, .ltr_show_sts = cnp_ltr_show_map, .msr_sts = msr_map, .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, @@ -586,9 +590,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset, writel(val, pmcdev->regbase + reg_offset); } -static inline u64 pmc_core_adjust_slp_s0_step(u32 value) +static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value) { - return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP; + return (u64)value * pmcdev->map->slp_s0_res_counter_step; } static int pmc_core_dev_state_get(void *data, u64 *val) @@ -598,7 +602,7 @@ static int pmc_core_dev_state_get(void *data, u64 *val) u32 value; value = pmc_core_reg_read(pmcdev, map->slp_s0_offset); - *val = pmc_core_adjust_slp_s0_step(value); + *val = pmc_core_adjust_slp_s0_step(pmcdev, value); return 0; } diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 5eae55d80226..f33cd2c34835 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -30,7 +30,7 @@ #define SPT_PMC_MPHY_CORE_STS_1 0x1142 #define SPT_PMC_MPHY_COM_STS_0 0x1155 #define SPT_PMC_MMIO_REG_LEN 0x1000 -#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 +#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68 #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) #define MTPMC_MASK 0xffff0000 #define PPFEAR_MAX_NUM_ENTRIES 12 @@ -185,8 +185,10 @@ enum ppfear_regs { #define ICL_PPFEAR_NUM_ENTRIES 9 #define ICL_NUM_IP_IGN_ALLOWED 20 #define ICL_PMC_LTR_WIGIG 0x1BFC +#define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 #define TGL_NUM_IP_IGN_ALLOWED 22 +#define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A /* * Tigerlake Power Management Controller register offsets @@ -245,6 +247,7 @@ struct pmc_reg_map { const struct pmc_bit_map *msr_sts; const struct pmc_bit_map **lpm_sts; const u32 slp_s0_offset; + const int slp_s0_res_counter_step; const u32 ltr_ignore_offset; const int regmap_length; const u32 ppfear0_offset; From 3976c6e365d7d50cbc96e92b0c537f5e8c744373 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 6 Oct 2020 20:51:05 -0700 Subject: [PATCH 07/15] platform/x86: intel_pmc_core: Clean up: Remove the duplicate comments and reorganize Some of the Cannon Lake PCH IPs are reused by most of the platforms such as Ice Lake, Tiger Lake, Elkhart Lake, Jasper Lake and can be reused by future platforms as well. The same was mentioned via comments not once but twice in an array of bit map structs for Cannon Lake (cnp_pfear_map). Hence, remove the duplicate comments and reorganize them. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Cc: Tony Luck Cc: Rui Zhang Suggested-by: Dave Hansen Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20201007035108.31078-2-david.e.box@linux.intel.com Signed-off-by: Hans de Goede --- drivers/platform/x86/intel_pmc_core.c | 32 +++++++++++++++++---------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 122eb53eb595..c6d71662d398 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -118,6 +118,10 @@ static const struct pmc_bit_map spt_pfear_map[] = { }; static const struct pmc_bit_map *ext_spt_pfear_map[] = { + /* + * Check intel_pmc_core_ids[] users of spt_reg_map for + * a list of core SoCs using this. + */ spt_pfear_map, NULL }; @@ -167,7 +171,6 @@ static const struct pmc_reg_map spt_reg_map = { /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */ static const struct pmc_bit_map cnp_pfear_map[] = { - /* Reserved for Cannon Lake but valid for Comet Lake */ {"PMC", BIT(0)}, {"OPI-DMI", BIT(1)}, {"SPI/eSPI", BIT(2)}, @@ -193,10 +196,6 @@ static const struct pmc_bit_map cnp_pfear_map[] = { {"SDX", BIT(4)}, {"SPE", BIT(5)}, {"Fuse", BIT(6)}, - /* - * Reserved for Cannon Lake but valid for Ice Lake, Comet Lake, - * Tiger Lake, Elkhart Lake and Jasper Lake. - */ {"SBR8", BIT(7)}, {"CSME_FSC", BIT(0)}, @@ -240,10 +239,6 @@ static const struct pmc_bit_map cnp_pfear_map[] = { {"HDA_PGD4", BIT(2)}, {"HDA_PGD5", BIT(3)}, {"HDA_PGD6", BIT(4)}, - /* - * Reserved for Cannon Lake but valid for Ice Lake, Comet Lake, - * Tiger Lake, ELkhart Lake and Jasper Lake. - */ {"PSF6", BIT(5)}, {"PSF7", BIT(6)}, {"PSF8", BIT(7)}, @@ -251,12 +246,15 @@ static const struct pmc_bit_map cnp_pfear_map[] = { }; static const struct pmc_bit_map *ext_cnp_pfear_map[] = { + /* + * Check intel_pmc_core_ids[] users of cnp_reg_map for + * a list of core SoCs using this. + */ cnp_pfear_map, NULL }; static const struct pmc_bit_map icl_pfear_map[] = { - /* Ice Lake and Jasper Lake generation onwards only */ {"RES_65", BIT(0)}, {"RES_66", BIT(1)}, {"RES_67", BIT(2)}, @@ -269,13 +267,16 @@ static const struct pmc_bit_map icl_pfear_map[] = { }; static const struct pmc_bit_map *ext_icl_pfear_map[] = { + /* + * Check intel_pmc_core_ids[] users of icl_reg_map for + * a list of core SoCs using this. + */ cnp_pfear_map, icl_pfear_map, NULL }; static const struct pmc_bit_map tgl_pfear_map[] = { - /* Tiger Lake and Elkhart Lake generation onwards only */ {"PSF9", BIT(0)}, {"RES_66", BIT(1)}, {"RES_67", BIT(2)}, @@ -287,6 +288,10 @@ static const struct pmc_bit_map tgl_pfear_map[] = { }; static const struct pmc_bit_map *ext_tgl_pfear_map[] = { + /* + * Check intel_pmc_core_ids[] users of tgl_reg_map for + * a list of core SoCs using this. + */ cnp_pfear_map, tgl_pfear_map, NULL @@ -370,7 +375,10 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { {"ISH", CNP_PMC_LTR_ISH}, {"UFSX2", CNP_PMC_LTR_UFSX2}, {"EMMC", CNP_PMC_LTR_EMMC}, - /* Reserved for Cannon Lake but valid for Ice Lake */ + /* + * Check intel_pmc_core_ids[] users of cnp_reg_map for + * a list of core SoCs using this. + */ {"WIGIG", ICL_PMC_LTR_WIGIG}, /* Below two cannot be used for LTR_IGNORE */ {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, From 68cb1a977e5e8b9531e7bf4fbfbde5ce1d19537b Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 6 Oct 2020 20:51:06 -0700 Subject: [PATCH 08/15] platform/x86: intel_pmc_core: Add Intel RocketLake (RKL) support Add RocketLake to the list of the platforms that intel_pmc_core driver supports for pmc_core device. RocketLake reuses all the TigerLake PCH IPs. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Cc: Tony Luck Cc: Rui Zhang Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20201007035108.31078-3-david.e.box@linux.intel.com Signed-off-by: Hans de Goede --- drivers/platform/x86/intel_pmc_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index c6d71662d398..da316000785e 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -1159,6 +1159,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map), + X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map), {} }; From 46461f8709ed1998bdfae35296ba63ab12ec50a9 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 6 Oct 2020 20:51:07 -0700 Subject: [PATCH 09/15] platform/x86: intel_pmc_core: fix: Replace dev_dbg macro with dev_info() dev_dbg macro is used to dump the debug registers in resume from an S0ix failure. However, when CONFIG_DYNAMIC_DEBUG is not set, the user may not be able to find the debug dump on an S0ix failure which defeats the purpose. The output of these messages is already controlled by a module parameter, warn_on_s0ix_failures, making it a 2 step process to enable anyway when CONFIG_DYNAMIC_DEBUG is set. Hence, replace dev_dbg with dev_info, allowing the control of the messages solely through the module parameter which is N by default. Fixes commit 913f984a8347 ("platform/x86: intel_pmc_core: Add an additional parameter to pmc_core_lpm_display()") Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20201007035108.31078-4-david.e.box@linux.intel.com Signed-off-by: Hans de Goede --- drivers/platform/x86/intel_pmc_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index da316000785e..3e5fe66333f1 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -640,7 +640,7 @@ static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev, offset += 4; while (map->name) { if (dev) - dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n", + dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n", map->name, data & map->bit_mask ? "Yes" : "No"); if (s) @@ -683,7 +683,7 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev, for (idx = 0; idx < arr_size; idx++) { if (dev) - dev_dbg(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx, + dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx, lpm_regs[idx]); if (s) seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx, @@ -691,7 +691,7 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev, for (index = 0; maps[idx][index].name && index < len; index++) { bit_mask = maps[idx][index].bit_mask; if (dev) - dev_dbg(dev, "%-30s %-30d\n", + dev_info(dev, "%-30s %-30d\n", maps[idx][index].name, lpm_regs[idx] & bit_mask ? 1 : 0); if (s) From d0e21c24de71f0c46491d2ccf3d511447a74d2c7 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 6 Oct 2020 20:51:08 -0700 Subject: [PATCH 10/15] MAINTAINERS: Update maintainers for pmc_core driver Update MAINTAINERS file for pmc_core driver to reflect the current maintainers. Cc: Vishwanath Somayaji Cc: Andy Shevchenko Cc: Srinivas Pandruvada Cc: David E. Box Acked-by: David E. Box Acked-by: Vishwanath Somayaji Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20201007035108.31078-5-david.e.box@linux.intel.com Signed-off-by: Hans de Goede --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b1c97a16b6ce..edd2b19c240f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8905,8 +8905,8 @@ F: arch/x86/include/asm/intel_punit_ipc.h F: drivers/platform/x86/intel_punit_ipc.c INTEL PMC CORE DRIVER -M: Rajneesh Bhardwaj -M: Vishwanath Somayaji +M: Rajneesh Bhardwaj +M: David E Box L: platform-driver-x86@vger.kernel.org S: Maintained F: drivers/platform/x86/intel_pmc_core* From c071afcea6ecf24a3c119f25ce9f71ffd55b5dc2 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 23 Sep 2020 20:20:49 +0300 Subject: [PATCH 11/15] platform/x86: mlx-platform: Remove PSU EEPROM configuration Remove PSU EEPROM configuration for systems class equipped with Mellanox chip Spectrume-2. Till now all the systems from this class used few types of power units, all equipped with EEPROM device with address space two bytes. Thus, all these devices have been handled by EEPROM driver "24c32". There is a new requirement is to support power unit replacement by "off the shelf" device, matching electrical required parameters. Such device could be equipped with different EEPROM type, which could be one byte address space addressing or even could be not equipped with EEPROM. In such case "24c32" will not work. Fixes: 1bd42d94ccab ("platform/x86: mlx-platform: Add support for new 200G IB and Ethernet systems") Signed-off-by: Vadim Pasternak Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20200923172053.26296-2-vadimp@nvidia.com Signed-off-by: Hans de Goede --- drivers/platform/x86/mlx-platform.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 1506ec0a4777..04a745095c37 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -328,15 +328,6 @@ static struct i2c_board_info mlxplat_mlxcpld_psu[] = { }, }; -static struct i2c_board_info mlxplat_mlxcpld_ng_psu[] = { - { - I2C_BOARD_INFO("24c32", 0x51), - }, - { - I2C_BOARD_INFO("24c32", 0x50), - }, -}; - static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { { I2C_BOARD_INFO("dps460", 0x59), @@ -770,15 +761,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { .label = "psu1", .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, .mask = BIT(0), - .hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[0], - .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, { .label = "psu2", .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, .mask = BIT(1), - .hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[1], - .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, }; From 638eae9bc7eb1012d1e0f5a8fd4db46447f822e9 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 23 Sep 2020 20:20:51 +0300 Subject: [PATCH 12/15] platform_data/mlxreg: Update module license Update license to SPDX-License. Signed-off-by: Vadim Pasternak Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20200923172053.26296-4-vadimp@nvidia.com Signed-off-by: Hans de Goede --- include/linux/platform_data/mlxreg.h | 32 ++-------------------------- 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 1af9c01563f9..0a727d405a7a 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -1,34 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ /* - * Copyright (c) 2017 Mellanox Technologies. All rights reserved. - * Copyright (c) 2017 Vadim Pasternak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the names of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Copyright (C) 2017-2020 Mellanox Technologies Ltd. */ #ifndef __LINUX_PLATFORM_DATA_MLXREG_H From d2f3ab5b6b05f67817f3bd3f2fda5f0126e95a62 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 23 Sep 2020 20:20:52 +0300 Subject: [PATCH 13/15] platform_data/mlxreg: Extend core platform structure Add 'capability' field to structure 'mlxreg_core_platform_data'. The purpose of this filed to indicate the actual number of the components within the particular group. Such components could be, for example the number of the FAN drawers. Some systems are equipped with FAN drawers with one tachometer inside, others with FAN drawers with several tachometers inside. Signed-off-by: Vadim Pasternak Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20200923172053.26296-5-vadimp@nvidia.com Signed-off-by: Hans de Goede --- include/linux/platform_data/mlxreg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 0a727d405a7a..101333fe2b8d 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -109,6 +109,7 @@ struct mlxreg_core_item { * @features: supported features of device; * @version: implementation version; * @identity: device identity name; + * @capability: device capability register; */ struct mlxreg_core_platform_data { struct mlxreg_core_data *data; @@ -117,6 +118,7 @@ struct mlxreg_core_platform_data { u32 features; u32 version; char identity[MLXREG_CORE_LABEL_MAX_SIZE]; + u32 capability; }; /** From 47a514b642cf144d6067e219474f08cde562b840 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 23 Sep 2020 20:20:53 +0300 Subject: [PATCH 14/15] platform/x86: mlx-platform: Add capability field to platform FAN description Set 'capability' field to FAN core platform data.. The content of 'capability' register allows to set the mapping between the drawers and tachometers. The motivation is to avoid adding a new code in the future in order to distinct between the systems types supporting a different kinds of the FAN drawers. Signed-off-by: Vadim Pasternak Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20200923172053.26296-6-vadimp@nvidia.com Signed-off-by: Hans de Goede --- drivers/platform/x86/mlx-platform.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 04a745095c37..986ad3dda1c1 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -1939,6 +1939,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { static struct mlxreg_core_platform_data mlxplat_default_fan_data = { .data = mlxplat_mlxcpld_default_fan_data, .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, }; /* Watchdog type1: hardware implementation version1 From 1a3f7813f38e400b0b63492b626b425f0a043d0b Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 8 Oct 2020 21:38:30 +0200 Subject: [PATCH 15/15] MAINTAINERS: update X86 PLATFORM DRIVERS entry with new kernel.org git repo The pdx86 maintainers have moved their git tree from infradead.org to kernel.org, update the X86 PLATFORM DRIVERS MAINTAINERS entry for this. Signed-off-by: Hans de Goede --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index edd2b19c240f..2a2170ff3a91 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18861,7 +18861,7 @@ M: Hans de Goede M: Mark Gross L: platform-driver-x86@vger.kernel.org S: Maintained -T: git git://git.infradead.org/linux-platform-drivers-x86.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git F: drivers/platform/olpc/ F: drivers/platform/x86/