drm/radeon: Only flush HDP cache for indirect buffers from userspace
It isn't necessary for command streams generated by the kernel (at least not while we aren't storing ring or indirect buffers in VRAM). Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
701e1e7891
commit
1538a9e0e0
@@ -925,7 +925,7 @@ int r100_copy_blit(struct radeon_device *rdev,
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if (fence) {
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r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
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}
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radeon_ring_unlock_commit(rdev, ring);
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radeon_ring_unlock_commit(rdev, ring, false);
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return r;
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}
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@@ -958,7 +958,7 @@ void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
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RADEON_ISYNC_ANY3D_IDLE2D |
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RADEON_ISYNC_WAIT_IDLEGUI |
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RADEON_ISYNC_CPSCRATCH_IDLEGUI);
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radeon_ring_unlock_commit(rdev, ring);
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radeon_ring_unlock_commit(rdev, ring, false);
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}
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@@ -3638,7 +3638,7 @@ int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
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}
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radeon_ring_write(ring, PACKET0(scratch, 0));
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radeon_ring_write(ring, 0xDEADBEEF);
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radeon_ring_unlock_commit(rdev, ring);
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radeon_ring_unlock_commit(rdev, ring, false);
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = RREG32(scratch);
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if (tmp == 0xDEADBEEF) {
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@@ -3700,7 +3700,7 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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ib.ptr[6] = PACKET2(0);
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ib.ptr[7] = PACKET2(0);
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ib.length_dw = 8;
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r = radeon_ib_schedule(rdev, &ib, NULL);
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r = radeon_ib_schedule(rdev, &ib, NULL, false);
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if (r) {
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DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
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goto free_ib;
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