forked from Minki/linux
ath9k: remove ah->mask_reg, it's never used properly
ah->mask_reg was used to hold different data throughout the driver. ath9k_hw_init_interrupt_masks() used it to save the value written to AR_IMR. ath9k_hw_set_interrupts() used it to hold the interrupt mask as defined in enum ath9k_int. Those masks differ in many bits. Use ah->imask instead of ah->mask_reg in ath9k_hw_set_interrupts() and ath9k_hw_updatetxtriglevel(). That's what the code was meant to do. ah->imask is initialized in ath9k_start(), so we don't need to initialize it from ah->mask_reg. Once it's done, ah->mask_reg becomes write-only, so it's replaced with a local variable in ath9k_hw_init_interrupt_masks(). Signed-off-by: Pavel Roskin <proski@gnu.org> Reported-by: Julia Lawall <julia@diku.dk> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1120,23 +1120,23 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
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static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
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enum nl80211_iftype opmode)
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{
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ah->mask_reg = AR_IMR_TXERR |
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u32 imr_reg = AR_IMR_TXERR |
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AR_IMR_TXURN |
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AR_IMR_RXERR |
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AR_IMR_RXORN |
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AR_IMR_BCNMISC;
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if (ah->config.rx_intr_mitigation)
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ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
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imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
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else
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ah->mask_reg |= AR_IMR_RXOK;
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imr_reg |= AR_IMR_RXOK;
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ah->mask_reg |= AR_IMR_TXOK;
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imr_reg |= AR_IMR_TXOK;
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if (opmode == NL80211_IFTYPE_AP)
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ah->mask_reg |= AR_IMR_MIB;
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imr_reg |= AR_IMR_MIB;
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REG_WRITE(ah, AR_IMR, ah->mask_reg);
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REG_WRITE(ah, AR_IMR, imr_reg);
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ah->imrs2_reg |= AR_IMR_S2_GTT;
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REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
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@ -2839,7 +2839,7 @@ EXPORT_SYMBOL(ath9k_hw_getisr);
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enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
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{
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u32 omask = ah->mask_reg;
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enum ath9k_int omask = ah->imask;
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u32 mask, mask2;
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struct ath9k_hw_capabilities *pCap = &ah->caps;
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struct ath_common *common = ath9k_hw_common(ah);
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@ -2911,7 +2911,6 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
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AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
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ah->imrs2_reg |= mask2;
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REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
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ah->mask_reg = ints;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
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if (ints & ATH9K_INT_TIM_TIMER)
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@ -479,7 +479,6 @@ struct ath_hw {
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int16_t curchan_rad_index;
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enum ath9k_int imask;
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u32 mask_reg;
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u32 imrs2_reg;
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u32 txok_interrupt_mask;
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u32 txerr_interrupt_mask;
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@ -105,7 +105,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
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if (ah->tx_trig_level >= ah->config.max_txtrig_level)
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return false;
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omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL);
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omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
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txcfg = REG_READ(ah, AR_TXCFG);
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curLevel = MS(txcfg, AR_FTRIG);
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