clk: pxa: declare init function and data __init
As the clock descriptions are constant and only usefull at init time, mark them as such by : - spliting clock description (desc) and clock private data (dynamic) - mark __initdata clock descriptions This makes all the register and descriptions of the clocks to go after kernel init phase. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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@ -26,12 +26,20 @@ static struct clk_onecell_data onecell_data = {
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.clk_num = CLK_MAX,
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};
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#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
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struct pxa_clk {
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struct clk_hw hw;
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struct clk_fixed_factor lp;
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struct clk_fixed_factor hp;
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struct clk_gate gate;
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bool (*is_in_low_power)(void);
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};
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#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
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static unsigned long cken_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pxa_clk_cken *pclk = to_pxa_clk(hw);
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struct pxa_clk *pclk = to_pxa_clk(hw);
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struct clk_fixed_factor *fix;
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if (!pclk->is_in_low_power || pclk->is_in_low_power())
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@ -48,7 +56,7 @@ static struct clk_ops cken_rate_ops = {
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static u8 cken_get_parent(struct clk_hw *hw)
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{
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struct pxa_clk_cken *pclk = to_pxa_clk(hw);
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struct pxa_clk *pclk = to_pxa_clk(hw);
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if (!pclk->is_in_low_power)
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return 0;
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@ -69,23 +77,27 @@ void __init clkdev_pxa_register(int ckid, const char *con_id,
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clk_register_clkdev(clk, con_id, dev_id);
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}
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int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
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int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks)
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{
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int i;
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struct pxa_clk_cken *pclk;
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struct pxa_clk *pxa_clk;
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struct clk *clk;
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for (i = 0; i < nb_clks; i++) {
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pclk = clks + i;
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pclk->gate.lock = &lock;
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clk = clk_register_composite(NULL, pclk->name,
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pclk->parent_names, 2,
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&pclk->hw, &cken_mux_ops,
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&pclk->hw, &cken_rate_ops,
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&pclk->gate.hw, &clk_gate_ops,
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pclk->flags);
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clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id,
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clk);
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pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
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pxa_clk->is_in_low_power = clks[i].is_in_low_power;
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pxa_clk->lp = clks[i].lp;
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pxa_clk->hp = clks[i].hp;
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pxa_clk->gate = clks[i].gate;
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pxa_clk->gate.lock = &lock;
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clk = clk_register_composite(NULL, clks[i].name,
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clks[i].parent_names, 2,
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&pxa_clk->hw, &cken_mux_ops,
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&pxa_clk->hw, &cken_rate_ops,
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&pxa_clk->gate.hw, &clk_gate_ops,
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clks[i].flags);
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clkdev_pxa_register(clks[i].ckid, clks[i].con_id,
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clks[i].dev_id, clk);
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}
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return 0;
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}
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@ -25,7 +25,7 @@
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk *clk_register_ ## name(void) \
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static struct clk * __init clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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@ -40,7 +40,7 @@
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk *clk_register_ ## name(void) \
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static struct clk * __init clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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@ -66,7 +66,7 @@
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* | Clock | --- | / div_hp |
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* +------------+ +-----------+
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*/
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struct pxa_clk_cken {
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struct desc_clk_cken {
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struct clk_hw hw;
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int ckid;
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const char *name;
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@ -102,6 +102,6 @@ static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
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extern void clkdev_pxa_register(int ckid, const char *con_id,
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const char *dev_id, struct clk *clk);
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extern int clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks);
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extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
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#endif
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@ -111,7 +111,7 @@ PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
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&CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
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static struct pxa_clk_cken pxa27x_clocks[] = {
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static struct desc_clk_cken pxa27x_clocks[] __initdata = {
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PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
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PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
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PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
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