powerpc/8xx: Convert CPM1 interrupt controller to platform_device
In the same logic as commit be7ecbd240
("soc: fsl: qe: convert QE
interrupt controller to platform_device"), convert CPM1 interrupt
controller to platform_device.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/fb80d0b2077312079c49da0296e25591578771cd.1649226186.git.christophe.leroy@csgroup.eu
This commit is contained in:
parent
22add2a20e
commit
14d893fc68
@ -7,7 +7,6 @@
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <asm/cpm1.h>
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#include <asm/cpm1.h>
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@ -43,7 +42,7 @@ static struct irq_chip cpm_pic = {
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.irq_eoi = cpm_end_irq,
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.irq_eoi = cpm_end_irq,
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};
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};
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int cpm_get_irq(void)
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static int cpm_get_irq(void)
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{
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{
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int cpm_vec;
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int cpm_vec;
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@ -58,11 +57,14 @@ int cpm_get_irq(void)
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return irq_linear_revmap(cpm_pic_host, cpm_vec);
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return irq_linear_revmap(cpm_pic_host, cpm_vec);
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}
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}
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static void cpm_cascade(struct irq_desc *desc)
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{
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generic_handle_irq(cpm_get_irq());
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}
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static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
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static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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irq_hw_number_t hw)
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{
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{
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pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
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irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
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return 0;
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return 0;
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@ -72,57 +74,65 @@ static const struct irq_domain_ops cpm_pic_host_ops = {
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.map = cpm_pic_host_map,
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.map = cpm_pic_host_map,
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};
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};
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unsigned int __init cpm_pic_init(void)
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static int cpm_pic_probe(struct platform_device *pdev)
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{
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{
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struct device_node *np = NULL;
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struct device *dev = &pdev->dev;
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struct resource res;
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struct resource *res;
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unsigned int sirq = 0, hwirq;
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int irq;
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int ret;
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pr_debug("cpm_pic_init\n");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
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cpic_reg = devm_ioremap(dev, res->start, resource_size(res));
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if (np == NULL)
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if (!cpic_reg)
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np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
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return -ENODEV;
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if (np == NULL) {
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printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
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return sirq;
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}
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ret = of_address_to_resource(np, 0, &res);
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irq = platform_get_irq(pdev, 0);
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if (ret)
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if (irq < 0)
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goto end;
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return irq;
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cpic_reg = ioremap(res.start, resource_size(&res));
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if (cpic_reg == NULL)
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goto end;
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sirq = irq_of_parse_and_map(np, 0);
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if (!sirq)
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goto end;
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/* Initialize the CPM interrupt controller. */
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/* Initialize the CPM interrupt controller. */
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hwirq = (unsigned int)virq_to_hw(sirq);
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out_be32(&cpic_reg->cpic_cicr,
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out_be32(&cpic_reg->cpic_cicr,
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(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
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(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
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((hwirq/2) << 13) | CICR_HP_MASK);
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((virq_to_hw(irq) / 2) << 13) | CICR_HP_MASK);
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out_be32(&cpic_reg->cpic_cimr, 0);
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out_be32(&cpic_reg->cpic_cimr, 0);
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cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
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cpm_pic_host = irq_domain_add_linear(dev->of_node, 64, &cpm_pic_host_ops, NULL);
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if (cpm_pic_host == NULL) {
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if (!cpm_pic_host)
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printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
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return -ENODEV;
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sirq = 0;
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goto end;
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irq_set_chained_handler(irq, cpm_cascade);
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}
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setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
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setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
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end:
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return 0;
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of_node_put(np);
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return sirq;
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}
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}
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static const struct of_device_id cpm_pic_match[] = {
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{
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.compatible = "fsl,cpm1-pic",
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}, {
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.type = "cpm-pic",
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.compatible = "CPM",
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}, {},
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};
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static struct platform_driver cpm_pic_driver = {
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.driver = {
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.name = "cpm-pic",
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.of_match_table = cpm_pic_match,
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},
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.probe = cpm_pic_probe,
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};
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static int __init cpm_pic_init(void)
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{
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return platform_driver_register(&cpm_pic_driver);
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}
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arch_initcall(cpm_pic_init);
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/*
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/*
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* The CPM can generate the error interrupt when there is a race condition
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* The CPM can generate the error interrupt when there is a race condition
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* between generating and masking interrupts. All we have to do is ACK it
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* between generating and masking interrupts. All we have to do is ACK it
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@ -29,9 +29,6 @@
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#include "mpc8xx.h"
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#include "mpc8xx.h"
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extern int cpm_pic_init(void);
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extern int cpm_get_irq(void);
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/* A place holder for time base interrupts, if they are ever enabled. */
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/* A place holder for time base interrupts, if they are ever enabled. */
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static irqreturn_t timebase_interrupt(int irq, void *dev)
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static irqreturn_t timebase_interrupt(int irq, void *dev)
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{
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{
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@ -209,11 +206,6 @@ void __noreturn mpc8xx_restart(char *cmd)
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panic("Restart failed\n");
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panic("Restart failed\n");
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}
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}
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static void cpm_cascade(struct irq_desc *desc)
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{
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generic_handle_irq(cpm_get_irq());
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}
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/* Initialize the internal interrupt controllers. The number of
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/* Initialize the internal interrupt controllers. The number of
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* interrupts supported can vary with the processor type, and the
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* interrupts supported can vary with the processor type, and the
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* 82xx family can have up to 64.
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* 82xx family can have up to 64.
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@ -222,14 +214,8 @@ static void cpm_cascade(struct irq_desc *desc)
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*/
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*/
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void __init mpc8xx_pics_init(void)
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void __init mpc8xx_pics_init(void)
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{
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{
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int irq;
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if (mpc8xx_pic_init()) {
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if (mpc8xx_pic_init()) {
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printk(KERN_ERR "Failed interrupt 8xx controller initialization\n");
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printk(KERN_ERR "Failed interrupt 8xx controller initialization\n");
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return;
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return;
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}
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}
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irq = cpm_pic_init();
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if (irq)
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irq_set_chained_handler(irq, cpm_cascade);
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}
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}
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@ -15,8 +15,6 @@
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#define PIC_VEC_SPURRIOUS 15
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#define PIC_VEC_SPURRIOUS 15
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extern int cpm_get_irq(struct pt_regs *regs);
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static struct irq_domain *mpc8xx_pic_host;
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static struct irq_domain *mpc8xx_pic_host;
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static unsigned long mpc8xx_cached_irq_mask;
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static unsigned long mpc8xx_cached_irq_mask;
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static sysconf8xx_t __iomem *siu_reg;
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static sysconf8xx_t __iomem *siu_reg;
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