Merge tag 'drm-misc-next-2019-04-04' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.2: UAPI Changes: -syncobj: Add TIMELINE_WAIT|QUERY|TRANSFER|TIMELINE_SIGNAL ioctls (Chunming) -Clarify that 1.0 can be represented by drm_color_lut (Daniel) Cross-subsystem Changes: -dt-bindings: Add binding for rk3066 hdmi (Johan) -dt-bindings: Add binding for Feiyang FY07024DI26A30-D panel (Jagan) -dt-bindings: Add Rocktech vendor prefix and jh057n00900 panel bindings (Guido) -MAINTAINERS: Add lima and ASPEED entries (Joel & Qiang) Core Changes: -memory: use dma_alloc_coherent when mem encryption is active (Christian) -dma_buf: add support for a dma_fence chain (Christian) -shmem_gem: fix off-by-one bug in new shmem gem helpers (Dan) Driver Changes: -rockchip: Add support for rk3066 hdmi (Johan) -ASPEED: Add driver supporting ASPEED BMC display controller to drm (Joel) -lima: Add driver supporting Arm Mali4xx gpus to drm (Qiang) -vc4/v3d: Various cleanups and improved error handling (Eric) -panel: Add support for Feiyang FY07024DI26A30-D MIPI-DSI panel (Jagan) -panel: Add support for Rocktech jh057n00900 MIPI-DSI panel (Guido) Cc: Johan Jonker <jbx6244@gmail.com> Cc: Christian König <christian.koenig@amd.com> Cc: Chunming Zhou <david1.zhou@amd.com> Cc: Dan Carpenter <dan.carpenter@oracle.com> Cc: Eric Anholt <eric@anholt.net> Cc: Qiang Yu <yuq825@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Guido Günther <agx@sigxcpu.org> Cc: Joel Stanley <joel@jms.id.au> [airlied: fixed XA limit build breakage, Rodrigo also submitted the same patch, but I squashed it in the merge.] Signed-off-by: Dave Airlie <airlied@redhat.com> From: Sean Paul <sean@poorly.run> Link: https://patchwork.freedesktop.org/patch/msgid/20190404201016.GA139524@art_vandelay
This commit is contained in:
Dave Airlie
@@ -735,8 +735,18 @@ struct drm_syncobj_handle {
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__u32 pad;
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};
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struct drm_syncobj_transfer {
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__u32 src_handle;
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__u32 dst_handle;
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__u64 src_point;
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__u64 dst_point;
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__u32 flags;
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__u32 pad;
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};
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
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struct drm_syncobj_wait {
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__u64 handles;
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/* absolute timeout */
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@@ -747,12 +757,33 @@ struct drm_syncobj_wait {
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__u32 pad;
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};
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struct drm_syncobj_timeline_wait {
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__u64 handles;
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/* wait on specific timeline point for every handles*/
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__u64 points;
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/* absolute timeout */
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__s64 timeout_nsec;
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__u32 count_handles;
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__u32 flags;
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__u32 first_signaled; /* only valid when not waiting all */
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__u32 pad;
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};
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struct drm_syncobj_array {
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__u64 handles;
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__u32 count_handles;
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__u32 pad;
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};
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struct drm_syncobj_timeline_array {
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__u64 handles;
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__u64 points;
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__u32 count_handles;
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__u32 pad;
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};
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/* Query current scanout sequence number */
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struct drm_crtc_get_sequence {
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__u32 crtc_id; /* requested crtc_id */
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@@ -909,6 +940,11 @@ extern "C" {
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#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
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#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
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#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
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#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
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#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
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#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
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/**
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* Device specific ioctls should only be in their respective headers
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* The device specific ioctl range is from 0x40 to 0x9f.
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@@ -621,7 +621,8 @@ struct drm_color_ctm {
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struct drm_color_lut {
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/*
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* Data is U0.16 fixed point format.
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* Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
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* 0xffff == 1.0.
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*/
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__u16 red;
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__u16 green;
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169
include/uapi/drm/lima_drm.h
Normal file
169
include/uapi/drm/lima_drm.h
Normal file
@@ -0,0 +1,169 @@
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/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
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/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
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#ifndef __LIMA_DRM_H__
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#define __LIMA_DRM_H__
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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enum drm_lima_param_gpu_id {
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DRM_LIMA_PARAM_GPU_ID_UNKNOWN,
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DRM_LIMA_PARAM_GPU_ID_MALI400,
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DRM_LIMA_PARAM_GPU_ID_MALI450,
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};
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enum drm_lima_param {
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DRM_LIMA_PARAM_GPU_ID,
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DRM_LIMA_PARAM_NUM_PP,
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DRM_LIMA_PARAM_GP_VERSION,
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DRM_LIMA_PARAM_PP_VERSION,
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};
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/**
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* get various information of the GPU
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*/
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struct drm_lima_get_param {
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__u32 param; /* in, value in enum drm_lima_param */
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__u32 pad; /* pad, must be zero */
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__u64 value; /* out, parameter value */
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};
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/**
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* create a buffer for used by GPU
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*/
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struct drm_lima_gem_create {
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__u32 size; /* in, buffer size */
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__u32 flags; /* in, currently no flags, must be zero */
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__u32 handle; /* out, GEM buffer handle */
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__u32 pad; /* pad, must be zero */
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};
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/**
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* get information of a buffer
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*/
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struct drm_lima_gem_info {
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__u32 handle; /* in, GEM buffer handle */
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__u32 va; /* out, virtual address mapped into GPU MMU */
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__u64 offset; /* out, used to mmap this buffer to CPU */
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};
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#define LIMA_SUBMIT_BO_READ 0x01
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#define LIMA_SUBMIT_BO_WRITE 0x02
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/* buffer information used by one task */
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struct drm_lima_gem_submit_bo {
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__u32 handle; /* in, GEM buffer handle */
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__u32 flags; /* in, buffer read/write by GPU */
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};
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#define LIMA_GP_FRAME_REG_NUM 6
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/* frame used to setup GP for each task */
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struct drm_lima_gp_frame {
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__u32 frame[LIMA_GP_FRAME_REG_NUM];
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};
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#define LIMA_PP_FRAME_REG_NUM 23
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#define LIMA_PP_WB_REG_NUM 12
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/* frame used to setup mali400 GPU PP for each task */
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struct drm_lima_m400_pp_frame {
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__u32 frame[LIMA_PP_FRAME_REG_NUM];
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__u32 num_pp;
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__u32 wb[3 * LIMA_PP_WB_REG_NUM];
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__u32 plbu_array_address[4];
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__u32 fragment_stack_address[4];
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};
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/* frame used to setup mali450 GPU PP for each task */
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struct drm_lima_m450_pp_frame {
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__u32 frame[LIMA_PP_FRAME_REG_NUM];
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__u32 num_pp;
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__u32 wb[3 * LIMA_PP_WB_REG_NUM];
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__u32 use_dlbu;
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__u32 _pad;
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union {
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__u32 plbu_array_address[8];
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__u32 dlbu_regs[4];
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};
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__u32 fragment_stack_address[8];
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};
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#define LIMA_PIPE_GP 0x00
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#define LIMA_PIPE_PP 0x01
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#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
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/**
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* submit a task to GPU
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*
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* User can always merge multi sync_file and drm_syncobj
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* into one drm_syncobj as in_sync[0], but we reserve
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* in_sync[1] for another task's out_sync to avoid the
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* export/import/merge pass when explicit sync.
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*/
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struct drm_lima_gem_submit {
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__u32 ctx; /* in, context handle task is submitted to */
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__u32 pipe; /* in, which pipe to use, GP/PP */
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__u32 nr_bos; /* in, array length of bos field */
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__u32 frame_size; /* in, size of frame field */
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__u64 bos; /* in, array of drm_lima_gem_submit_bo */
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__u64 frame; /* in, GP/PP frame */
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__u32 flags; /* in, submit flags */
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__u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */
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__u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */
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};
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#define LIMA_GEM_WAIT_READ 0x01
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#define LIMA_GEM_WAIT_WRITE 0x02
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/**
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* wait pending GPU task finish of a buffer
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*/
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struct drm_lima_gem_wait {
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__u32 handle; /* in, GEM buffer handle */
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__u32 op; /* in, CPU want to read/write this buffer */
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__s64 timeout_ns; /* in, wait timeout in absulute time */
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};
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/**
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* create a context
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*/
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struct drm_lima_ctx_create {
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__u32 id; /* out, context handle */
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__u32 _pad; /* pad, must be zero */
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};
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/**
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* free a context
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*/
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struct drm_lima_ctx_free {
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__u32 id; /* in, context handle */
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__u32 _pad; /* pad, must be zero */
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};
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#define DRM_LIMA_GET_PARAM 0x00
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#define DRM_LIMA_GEM_CREATE 0x01
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#define DRM_LIMA_GEM_INFO 0x02
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#define DRM_LIMA_GEM_SUBMIT 0x03
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#define DRM_LIMA_GEM_WAIT 0x04
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#define DRM_LIMA_CTX_CREATE 0x05
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#define DRM_LIMA_CTX_FREE 0x06
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#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param)
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#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
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#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
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#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit)
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#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
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#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create)
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#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __LIMA_DRM_H__ */
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