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net: ethernet: use phylink_set_10g_modes()

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Update three drivers to use the new phylink_set_10g_modes() helper:
Cadence macb, Freescale DPAA2 and Marvell PP2.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King (Oracle) 2021-10-04 12:03:33 +01:00 committed by David S. Miller
parent a2c27a61b4
commit 14ad41c74f
3 changed files with 3 additions and 18 deletions
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7
drivers/net/ethernet/cadence/macb_main.c
View File

@ -547,13 +547,8 @@ static void macb_validate(struct phylink_config *config,
if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE && if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
(state->interface == PHY_INTERFACE_MODE_NA || (state->interface == PHY_INTERFACE_MODE_NA ||
state->interface == PHY_INTERFACE_MODE_10GBASER)) { state->interface == PHY_INTERFACE_MODE_10GBASER)) {
phylink_set(mask, 10000baseCR_Full); phylink_set_10g_modes(mask);
phylink_set(mask, 10000baseER_Full);
phylink_set(mask, 10000baseKR_Full); phylink_set(mask, 10000baseKR_Full);
phylink_set(mask, 10000baseLR_Full);
phylink_set(mask, 10000baseLRM_Full);
phylink_set(mask, 10000baseSR_Full);
phylink_set(mask, 10000baseT_Full);
if (state->interface != PHY_INTERFACE_MODE_NA) if (state->interface != PHY_INTERFACE_MODE_NA)
goto out; goto out;
} }

7
drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
View File

@ -139,12 +139,7 @@ static void dpaa2_mac_validate(struct phylink_config *config,
case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_NA:
case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_USXGMII:
phylink_set(mask, 10000baseT_Full); phylink_set_10g_modes(mask);
phylink_set(mask, 10000baseCR_Full);
phylink_set(mask, 10000baseSR_Full);
phylink_set(mask, 10000baseLR_Full);
phylink_set(mask, 10000baseLRM_Full);
phylink_set(mask, 10000baseER_Full);
if (state->interface == PHY_INTERFACE_MODE_10GBASER) if (state->interface == PHY_INTERFACE_MODE_10GBASER)
break; break;
phylink_set(mask, 5000baseT_Full); phylink_set(mask, 5000baseT_Full);

7
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
View File

@ -6301,12 +6301,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_XAUI:
case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_NA:
if (mvpp2_port_supports_xlg(port)) { if (mvpp2_port_supports_xlg(port)) {
phylink_set(mask, 10000baseT_Full); phylink_set_10g_modes(mask);
phylink_set(mask, 10000baseCR_Full);
phylink_set(mask, 10000baseSR_Full);
phylink_set(mask, 10000baseLR_Full);
phylink_set(mask, 10000baseLRM_Full);
phylink_set(mask, 10000baseER_Full);
phylink_set(mask, 10000baseKR_Full); phylink_set(mask, 10000baseKR_Full);
} }
if (state->interface != PHY_INTERFACE_MODE_NA) if (state->interface != PHY_INTERFACE_MODE_NA)