ARM: SoC fix for 5.17, part 4
Here is one last regression fix for 5.17, reverting a patch that went into 5.16 as a cleanup that ended up breaking external interrupts on Layerscape chips. The revert makes it work again, but also reintroduces a build time warning about the nonstandard DT binding that will have to be dealt with in the future. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmI2ZjkACgkQmmx57+YA GNkNgg//eTPKd0JH0GbxCKDt2afKMKsBmI71/a2z6M4fWsT9s53Sn+4eG+RO+Q1J y+yaXJTnOEHh9FTXDxDxL/+5Xn/URxL1mzqMxM6LMQRu2b1fe53jC9GzOC779s17 pLyAHvRuwhDxvBUOVRWNZz4OoLQ5ap0aVDFTwuuEkjB9DBxdGzxhAuKJMGMHEKeH NBySAkJKa3xFSHCrPYI/T+MpoCizQwhehYT8OSzRgme2dtSmQ7jj10io1k3GAz0G mzS3BkOVIFMjif/s/Qci35UnQE9P1S/wN2Eg65Z2X1Z/sosuwUzP9uM2lBtTp59V c7LwTDkQhhEnyGWJeEwvNx3iJw5kJjxuZlvNVwUFmK4ckEzQss7jD3+oe+/3wO8Q zAantKWF87POOnie06cSbVfxeb5Iwbam6UQq+YRJQb5ybNNyt8akcINReSizqRHI qFKLDXYmewdJWwI6JuvHW+tBRH++O48Gzq71UANgPJYD8Km4T6YdpzKkfhATisZZ OpV7XqajVRWXqn5AdB8aA+MlKNMUBgkXKdZLxsoBaAkmhB+RvptHZBEaIS5Lt7Lj KaIS5KxaHTuZ8n1nZXlkUAnZ22wG1us8njM+iiaAnuhdFO45L9ZikvHrQWiJVYtB 9XUa9WHg95DNYbmA0ZS/p/7Dm2gu9lWoCjKrMjy7sWPnOtzA1M8= =GWWD -----END PGP SIGNATURE----- Merge tag 'soc-fixes-5.17-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fix from Arnd Bergmann: "Here is one last regression fix for 5.17, reverting a patch that went into 5.16 as a cleanup that ended up breaking external interrupts on Layerscape chips. The revert makes it work again, but also reintroduces a build time warning about the nonstandard DT binding that will have to be dealt with in the future" * tag 'soc-fixes-5.17-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: Revert "arm64: dts: freescale: Fix 'interrupt-map' parent address cells"
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commit
14702b3b24
@ -253,18 +253,18 @@
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interrupt-controller;
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reg = <0x14 4>;
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interrupt-map =
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<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0xffffffff 0x0>;
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};
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};
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@ -293,18 +293,18 @@
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interrupt-controller;
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reg = <0x14 4>;
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interrupt-map =
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<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0xffffffff 0x0>;
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};
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};
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@ -680,18 +680,18 @@
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interrupt-controller;
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reg = <0x14 4>;
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interrupt-map =
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<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0xffffffff 0x0>;
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};
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};
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