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drm/i915: Use adjusted_mode->clock in lpt_program_iclkip

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lpt_program_iclkip() wants to know the pixel clock. It should get that
information from adjusted_mode, not crtc->mode.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-09-04 18:25:19 +03:00 committed by Daniel Vetter
parent a2b076b6e4
commit 12d7ceed52
1 changed files with 5 additions and 4 deletions
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9
drivers/gpu/drm/i915/intel_display.c
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@ -2897,6 +2897,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
u32 divsel, phaseinc, auxdiv, phasedir = 0; u32 divsel, phaseinc, auxdiv, phasedir = 0;
u32 temp; u32 temp;
@ -2914,13 +2915,13 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
SBI_ICLK); SBI_ICLK);
/* 20MHz is a corner case which is out of range for the 7-bit divisor */ /* 20MHz is a corner case which is out of range for the 7-bit divisor */
if (crtc->mode.clock == 20000) { if (clock == 20000) {
auxdiv = 1; auxdiv = 1;
divsel = 0x41; divsel = 0x41;
phaseinc = 0x20; phaseinc = 0x20;
} else { } else {
/* The iCLK virtual clock root frequency is in MHz, /* The iCLK virtual clock root frequency is in MHz,
* but the crtc->mode.clock in in KHz. To get the divisors, * but the adjusted_mode->clock in in KHz. To get the divisors,
* it is necessary to divide one by another, so we * it is necessary to divide one by another, so we
* convert the virtual clock precision to KHz here for higher * convert the virtual clock precision to KHz here for higher
* precision. * precision.
@ -2929,7 +2930,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
u32 iclk_pi_range = 64; u32 iclk_pi_range = 64;
u32 desired_divisor, msb_divisor_value, pi_value; u32 desired_divisor, msb_divisor_value, pi_value;
desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); desired_divisor = (iclk_virtual_root_freq / clock);
msb_divisor_value = desired_divisor / iclk_pi_range; msb_divisor_value = desired_divisor / iclk_pi_range;
pi_value = desired_divisor % iclk_pi_range; pi_value = desired_divisor % iclk_pi_range;
@ -2945,7 +2946,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
~SBI_SSCDIVINTPHASE_INCVAL_MASK); ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
crtc->mode.clock, clock,
auxdiv, auxdiv,
divsel, divsel,
phasedir, phasedir,