ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_SPI
Cosmetic change of integer value "0" in the first field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Frank Rowand
Andy Gross
parent
b0a627b409
commit
12d2de2e50
@ -243,7 +243,7 @@
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adsp-pil {
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compatible = "qcom,msm8974-adsp-pil";
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interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
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interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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@ -275,7 +275,7 @@
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qcom,smem = <443>, <429>;
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interrupt-parent = <&intc>;
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interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 10>;
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@ -300,7 +300,7 @@
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qcom,smem = <435>, <428>;
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interrupt-parent = <&intc>;
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interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 14>;
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@ -325,7 +325,7 @@
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qcom,smem = <451>, <431>;
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interrupt-parent = <&intc>;
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interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 18>;
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@ -364,7 +364,7 @@
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modem_smsm: modem@1 {
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reg = <1>;
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interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -372,7 +372,7 @@
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adsp_smsm: adsp@2 {
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reg = <2>;
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interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -380,7 +380,7 @@
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wcnss_smsm: wcnss@7 {
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reg = <7>;
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interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -445,50 +445,50 @@
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frame@f9021000 {
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frame-number = <0>;
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interrupts = <0 8 0x4>,
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<0 7 0x4>;
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interrupts = <GIC_SPI 8 0x4>,
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<GIC_SPI 7 0x4>;
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reg = <0xf9021000 0x1000>,
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<0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <1>;
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interrupts = <0 9 0x4>;
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interrupts = <GIC_SPI 9 0x4>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <2>;
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interrupts = <0 10 0x4>;
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interrupts = <GIC_SPI 10 0x4>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <3>;
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interrupts = <0 11 0x4>;
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interrupts = <GIC_SPI 11 0x4>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <4>;
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interrupts = <0 12 0x4>;
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interrupts = <GIC_SPI 12 0x4>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <5>;
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interrupts = <0 13 0x4>;
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interrupts = <GIC_SPI 13 0x4>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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};
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frame@f9028000 {
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frame-number = <6>;
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interrupts = <0 14 0x4>;
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interrupts = <GIC_SPI 14 0x4>;
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reg = <0xf9028000 0x1000>;
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status = "disabled";
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};
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@ -586,7 +586,7 @@
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blsp1_uart1: serial@f991d000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991d000 0x1000>;
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interrupts = <0 107 0x0>;
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interrupts = <GIC_SPI 107 0x0>;
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -595,7 +595,7 @@
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blsp1_uart2: serial@f991e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991e000 0x1000>;
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interrupts = <0 108 0x0>;
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interrupts = <GIC_SPI 108 0x0>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -605,7 +605,8 @@
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 123 0>, <0 138 0>;
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interrupts = <GIC_SPI 123 0>,
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<GIC_SPI 138 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>,
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@ -632,7 +633,8 @@
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 125 0>, <0 221 0>;
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interrupts = <GIC_SPI 125 0>,
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<GIC_SPI 221 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_APPS_CLK>,
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<&gcc GCC_SDCC2_AHB_CLK>,
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@ -699,14 +701,14 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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interrupts = <GIC_SPI 208 0>;
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};
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i2c@f9924000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9924000 0x1000>;
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interrupts = <0 96 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>;
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clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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@ -717,7 +719,7 @@
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9964000 0x1000>;
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interrupts = <0 102 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>;
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clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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@ -728,7 +730,7 @@
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9967000 0x1000>;
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interrupts = <0 105 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_NONE>;
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clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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@ -744,7 +746,7 @@
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<0xfc4cb000 0x1000>,
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<0xfc4ca000 0x1000>;
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interrupt-names = "periph_irq";
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interrupts = <0 190 0>;
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interrupts = <GIC_SPI 190 0>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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@ -1040,21 +1042,21 @@
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compatible = "qcom,smd";
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adsp {
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interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 8>;
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qcom,smd-edge = <1>;
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};
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modem {
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interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 12>;
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qcom,smd-edge = <0>;
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};
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rpm {
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interrupts = <0 168 1>;
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interrupts = <GIC_SPI 168 1>;
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qcom,ipc = <&apcs 8 0>;
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qcom,smd-edge = <15>;
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