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media updates for v5.20-rc1

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Merge tag 'media/v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

Pull media updates from Mauro Carvalho Chehab:

 - New driver for Semi AR0521 sensor

 - rkisp1 CSI code was split into a separate file

 - sun6i has gained support for the A31 MIPI CSI-2 controller

 - sun8i has gained support for the A83T MIPI CSI-2 controller

 - vimc driver got support for virtual lens

 - HEVC uAPI has gained its final form and got added to public headers

 - hantro and cedrus got updates on H-265 support

 - stkwebcam was promoted from staging

 - atomisp staging driver got cleanups on its hmm and kmap related logic

 - ov5640 gained support for more modes and got some rework

 - imx7-media-csi staging driver got several improvements related to mc
   API support

 - uvcvideo now handles better power line control

 - mediatec vcodec gained support for new hardware and got some codec
   updates

 - Lots of other bug fixes, improvements and cleanups.

* tag 'media/v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (446 commits)
  media: hantro: Remove dedicated control documentation
  hantro: Remove incorrect HEVC SPS validation
  media: cedrus: hevc: Add check for invalid timestamp
  media: sunxi: sun6i_mipi_csi2.c/sun8i_a83t_mipi_csi2.c: clarify error handling
  media: uvcvideo: Fix invalid pointer in uvc_ctrl_init_ctrl()
  media: Documentation: mc-core: Fix typo
  media: videodev2.h.rst.exceptions: add missing exceptions
  media: vimc: wrong pointer is used with PTR_ERR
  media: rkisp1: debug: Add dump file in debugfs for MI main path registers
  media: rkisp1: Make the internal CSI-2 receiver optional
  media: rkisp1: Add infrastructure to support ISP features
  media: rkisp1: Support the ISP parallel input
  media: dt-bindings: media: rkisp1: Add port for parallel interface
  media: rkisp1: Use fwnode_graph_for_each_endpoint
  media: rkisp1: csi: Plumb the CSI RX subdev
  media: rkisp1: csi: Implement a V4L2 subdev for the CSI receiver
  media: rkisp1: isp: Disallow multiple active sources
  media: rkisp1: isp: Rename rkisp1_get_remote_source()
  media: rkisp1: isp: Constify various local variables
  media: rkisp1: isp: Fix whitespace issues
  ...
This commit is contained in:
Linus Torvalds 2022-08-03 19:29:28 -07:00
commit 12b68040a5
355 changed files with 14697 additions and 8341 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/admin-guide/media/vimc.dot
View File

@ -5,9 +5,13 @@ digraph board {
n00000001 [label="{{} | Sensor A\n/dev/v4l-subdev0 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
n00000001:port0 -> n00000005:port0 [style=bold]
n00000001:port0 -> n0000000b [style=bold]
n00000001 -> n00000002
n00000002 [label="{{} | Lens A\n/dev/v4l-subdev5 | {<port0>}}", shape=Mrecord, style=filled, fillcolor=green]
n00000003 [label="{{} | Sensor B\n/dev/v4l-subdev1 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
n00000003:port0 -> n00000008:port0 [style=bold]
n00000003:port0 -> n0000000f [style=bold]
n00000003 -> n00000004
n00000004 [label="{{} | Lens B\n/dev/v4l-subdev6 | {<port0>}}", shape=Mrecord, style=filled, fillcolor=green]
n00000005 [label="{{<port0> 0} | Debayer A\n/dev/v4l-subdev2 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
n00000005:port1 -> n00000015:port0
n00000008 [label="{{<port0> 0} | Debayer B\n/dev/v4l-subdev3 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]

19
Documentation/admin-guide/media/vimc.rst
View File

@ -53,6 +53,25 @@ vimc-sensor:
* 1 Pad source
vimc-lens:
Ancillary lens for a sensor. Supports auto focus control. Linked to
a vimc-sensor using an ancillary link. The lens supports FOCUS_ABSOLUTE
control.
.. code-block:: bash
media-ctl -p
...
- entity 28: Lens A (0 pad, 0 link)
type V4L2 subdev subtype Lens flags 0
device node name /dev/v4l-subdev6
- entity 29: Lens B (0 pad, 0 link)
type V4L2 subdev subtype Lens flags 0
device node name /dev/v4l-subdev7
v4l2-ctl -d /dev/v4l-subdev7 -C focus_absolute
focus_absolute: 0
vimc-debayer:
Transforms images in bayer format into a non-bayer format.
Exposes:

14
Documentation/admin-guide/media/vivid.rst
View File

@ -714,6 +714,20 @@ The Test Pattern Controls are all specific to video capture.
does the same for the EAV (End of Active Video) code.
- Insert Video Guard Band
adds 4 columns of pixels with the HDMI Video Guard Band code at the
left hand side of the image. This only works with 3 or 4 byte RGB pixel
formats. The RGB pixel value 0xab/0x55/0xab turns out to be equivalent
to the HDMI Video Guard Band code that precedes each active video line
(see section 5.2.2.1 in the HDMI 1.3 Specification). To test if a video
receiver has correct HDMI Video Guard Band processing, enable this
control and then move the image to the left hand side of the screen.
That will result in video lines that start with multiple pixels that
have the same value as the Video Guard Band that precedes them.
Receivers that will just keep skipping Video Guard Band values will
now fail and either loose sync or these video lines will shift.
Capture Feature Selection Controls
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

56
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
View File

@ -42,6 +42,7 @@ properties:
port:
$ref: /schemas/graph.yaml#/$defs/port-base
description: Parallel input port, connect to a parallel sensor
properties:
endpoint:
@ -59,7 +60,24 @@ properties:
required:
- bus-width
additionalProperties: false
unevaluatedProperties: false
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: "#/properties/port"
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: MIPI CSI-2 bridge input port
anyOf:
- required:
- port@0
- required:
- port@1
required:
- compatible
@ -69,6 +87,12 @@ required:
- clock-names
- resets
oneOf:
- required:
- ports
- required:
- port
additionalProperties: false
examples:
@ -89,19 +113,25 @@ examples:
"ram";
resets = <&ccu RST_BUS_CSI>;
port {
/* Parallel bus endpoint */
csi1_ep: endpoint {
remote-endpoint = <&adv7611_ep>;
bus-width = <16>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/*
* If hsync-active/vsync-active are missing,
* embedded BT.656 sync is used.
*/
hsync-active = <0>; /* Active low */
vsync-active = <0>; /* Active low */
pclk-sample = <1>; /* Rising */
port@0 {
reg = <0>;
/* Parallel bus endpoint */
csi1_ep: endpoint {
remote-endpoint = <&adv7611_ep>;
bus-width = <16>;
/*
* If hsync-active/vsync-active are missing,
* embedded BT.656 sync is used.
*/
hsync-active = <0>; /* Active low */
vsync-active = <0>; /* Active low */
pclk-sample = <1>; /* Rising */
};
};
};
};

137
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml Normal file
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@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
maintainers:
- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
properties:
compatible:
oneOf:
- const: allwinner,sun6i-a31-mipi-csi2
- items:
- const: allwinner,sun8i-v3s-mipi-csi2
- const: allwinner,sun6i-a31-mipi-csi2
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: bus
- const: mod
phys:
maxItems: 1
description: MIPI D-PHY
phy-names:
items:
- const: dphy
resets:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
description: Input port, connect to a MIPI CSI-2 sensor
properties:
reg:
const: 0
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
unevaluatedProperties: false
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output port, connect to a CSI controller
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- phys
- phy-names
- resets
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
mipi_csi2: csi@1cb1000 {
compatible = "allwinner,sun8i-v3s-mipi-csi2",
"allwinner,sun6i-a31-mipi-csi2";
reg = <0x01cb1000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI1_SCLK>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_CSI>;
phys = <&dphy>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_in: port@0 {
reg = <0>;
mipi_csi2_in_ov5648: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&ov5648_out_mipi_csi2>;
};
};
mipi_csi2_out: port@1 {
reg = <1>;
mipi_csi2_out_csi0: endpoint {
remote-endpoint = <&csi0_in_mipi_csi2>;
};
};
};
};
...

125
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml Normal file
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@ -0,0 +1,125 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
maintainers:
- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
properties:
compatible:
const: allwinner,sun8i-a83t-mipi-csi2
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
- description: MIPI-specific Clock
- description: Misc CSI Clock
clock-names:
items:
- const: bus
- const: mod
- const: mipi
- const: misc
resets:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
description: Input port, connect to a MIPI CSI-2 sensor
properties:
reg:
const: 0
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
unevaluatedProperties: false
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output port, connect to a CSI controller
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
mipi_csi2: csi@1cb1000 {
compatible = "allwinner,sun8i-a83t-mipi-csi2";
reg = <0x01cb1000 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI_SCLK>,
<&ccu CLK_MIPI_CSI>,
<&ccu CLK_CSI_MISC>;
clock-names = "bus", "mod", "mipi", "misc";
resets = <&ccu RST_BUS_CSI>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_in: port@0 {
reg = <0>;
mipi_csi2_in_ov8865: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&ov8865_out_mipi_csi2>;
};
};
mipi_csi2_out: port@1 {
reg = <1>;
mipi_csi2_out_csi: endpoint {
remote-endpoint = <&csi_in_mipi_csi2>;
};
};
};
};
...

16
Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt
View File

@ -1,16 +0,0 @@
Samsung S5P/Exynos SoC series JPEG codec
Required properties:
- compatible : should be one of:
"samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg",
"samsung,exynos3250-jpeg", "samsung,exynos5420-jpeg",
"samsung,exynos5433-jpeg";
- reg : address and length of the JPEG codec IP register set;
- interrupts : specifies the JPEG codec IP interrupt;
- clock-names : should contain:
- "jpeg" for the core gate clock,
- "sclk" for the special clock (optional).
- clocks : should contain the clock specifier and clock ID list
matching entries in the clock-names property; from
the common clock bindings.

1
Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml
View File

@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- aptina,mt9p006
- aptina,mt9p031
- aptina,mt9p031m

112
Documentation/devicetree/bindings/media/i2c/onnn,ar0521.yaml Normal file
View File

@ -0,0 +1,112 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/onnn,ar0521.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ON Semiconductor AR0521 MIPI CSI-2 sensor
maintainers:
- Krzysztof Hałasa <khalasa@piap.pl>
description: |-
The AR0521 is a raw CMOS image sensor with MIPI CSI-2 and
I2C-compatible control interface.
properties:
compatible:
const: onnn,ar0521
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: extclk
vaa-supply:
description:
Definition of the regulator used as analog (2.7 V) voltage supply.
vdd-supply:
description:
Definition of the regulator used as digital core (1.2 V) voltage supply.
vdd_io-supply:
description:
Definition of the regulator used as digital I/O (1.8 V) voltage supply.
reset-gpios:
description: reset GPIO, usually active low
maxItems: 1
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: |
Video output port.
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
bus-type:
const: 4
data-lanes:
anyOf:
- items:
- const: 1
- items:
- const: 1
- const: 2
- items:
- const: 1
- const: 2
- const: 3
- const: 4
required:
- compatible
- reg
- clocks
- clock-names
- vaa-supply
- vdd-supply
- vdd_io-supply
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
ar0521: camera-sensor@36 {
compatible = "onnn,ar0521";
reg = <0x36>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_camera>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "extclk";
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
vaa-supply = <&reg_2p7v>;
vdd-supply = <&reg_1p2v>;
vdd_io-supply = <&reg_1p8v>;
port {
mipi_camera_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
data-lanes = <1 2 3 4>;
};
};
};
};

124
Documentation/devicetree/bindings/media/i2c/ovti,ov5693.yaml Normal file
View File

@ -0,0 +1,124 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2022 Amarulasolutions
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/ovti,ov5693.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Omnivision OV5693 CMOS Sensor
maintainers:
- Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
description: |
The Omnivision OV5693 is a high performance, 1/4-inch, 5 megapixel, CMOS
image sensor that delivers 2592x1944 at 30fps. It provides full-frame,
sub-sampled, and windowed 10-bit MIPI images in various formats via the
Serial Camera Control Bus (SCCB) interface.
OV5693 is controlled via I2C and two-wire Serial Camera Control Bus (SCCB).
The sensor output is available via CSI-2 serial data output (up to 2-lane).
allOf:
- $ref: /schemas/media/video-interface-devices.yaml#
properties:
compatible:
const: ovti,ov5693
reg:
maxItems: 1
clocks:
description:
System input clock (aka XVCLK). From 6 to 27 MHz.
maxItems: 1
dovdd-supply:
description:
Digital I/O voltage supply, 1.8V.
avdd-supply:
description:
Analog voltage supply, 2.8V.
dvdd-supply:
description:
Digital core voltage supply, 1.2V.
reset-gpios:
description:
The phandle and specifier for the GPIO that controls sensor reset.
This corresponds to the hardware pin XSHUTDN which is physically
active low.
maxItems: 1
port:
description: MIPI CSI-2 transmitter port
$ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
link-frequencies: true
data-lanes:
minItems: 1
maxItems: 2
required:
- data-lanes
- link-frequencies
required:
- compatible
- reg
- clocks
- port
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/px30-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
ov5693: camera@36 {
compatible = "ovti,ov5693";
reg = <0x36>;
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clkout_m0>;
clocks = <&cru SCLK_CIF_OUT>;
assigned-clocks = <&cru SCLK_CIF_OUT>;
assigned-clock-rates = <19200000>;
avdd-supply = <&vcc_1v8>;
dvdd-supply = <&vcc_1v2>;
dovdd-supply = <&vcc_2v8>;
rotation = <90>;
orientation = <0>;
port {
ucam_out: endpoint {
remote-endpoint = <&mipi_in_ucam>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <450000000>;
};
};
};
};
...

52
Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
View File

@ -17,20 +17,20 @@ description: |
About the Decoder Hardware Block Diagram, please check below:
+---------------------------------+------------------------------------+
| | |
| input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
| || | || |
+------------||-------------------+---------------------||-------------+
lat workqueue | core workqueue <parent>
-------------||-----------------------------------------||------------------
|| || <child>
\/ <----------------HW index-------------->\/
+------------------------------------------------------+
| enable/disable |
| clk power irq iommu |
| (lat/lat soc/core0/core1) |
+------------------------------------------------------+
+------------------------------------------------+-------------------------------------+
| | |
| input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
| || || | || |
+------------||-------------||-------------------+---------------------||--------------+
|| lat || | core workqueue <parent>
-------------||-------------||-------------------|---------------------||---------------
||<------------||----------------HW index---------------->|| <child>
\/ \/ \/
+-------------------------------------------------------------+
| enable/disable |
| clk power irq iommu |
| (lat/lat soc/core0/core1) |
+-------------------------------------------------------------+
As above, there are parent and child devices, child mean each hardware. The child device
controls the information of each hardware independent which include clk/power/irq.
@ -45,11 +45,19 @@ description: |
For the smi common may not the same for each hardware, can't combine all hardware in one node,
or leading to iommu fault when access dram data.
Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
clock when lat start to work, don't have interrupt.
mt8195: lat soc HW + lat HW + core HW
mt8192: lat HW + core HW
properties:
compatible:
enum:
- mediatek,mt8192-vcodec-dec
- mediatek,mt8186-vcodec-dec
- mediatek,mt8195-vcodec-dec
reg:
maxItems: 1
@ -87,7 +95,9 @@ patternProperties:
properties:
compatible:
const: mediatek,mtk-vcodec-lat
enum:
- mediatek,mtk-vcodec-lat
- mediatek,mtk-vcodec-lat-soc
reg:
maxItems: 1
@ -125,7 +135,6 @@ patternProperties:
required:
- compatible
- reg
- interrupts
- iommus
- clocks
- clock-names
@ -196,6 +205,17 @@ required:
- dma-ranges
- ranges
if:
properties:
compatible:
contains:
enum:
- mediatek,mtk-vcodec-lat
then:
required:
- interrupts
additionalProperties: false
examples:

6
Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
View File

@ -18,6 +18,7 @@ properties:
- enum:
- mediatek,mt2701-jpgenc
- mediatek,mt8183-jpgenc
- mediatek,mt8186-jpgenc
- const: mediatek,mtk-jpgenc
reg:
maxItems: 1
@ -42,6 +43,11 @@ properties:
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
required:
- compatible
- reg

11
Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
View File

@ -22,9 +22,14 @@ description: |-
properties:
compatible:
enum:
- fsl,imx7-mipi-csi2
- fsl,imx8mm-mipi-csi2
oneOf:
- enum:
- fsl,imx7-mipi-csi2
- fsl,imx8mm-mipi-csi2
- items:
- enum:
- fsl,imx8mp-mipi-csi2
- const: fsl,imx8mm-mipi-csi2
reg:
maxItems: 1

7
Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml
View File

@ -84,6 +84,13 @@ properties:
- const: vfe0
- const: vfe1
interconnects:
maxItems: 1
interconnect-names:
items:
- const: vfe-mem
iommus:
maxItems: 4

69
Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml Normal file
View File

@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/rockchip,rk3568-vepu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Hantro G1 VPU encoders implemented on Rockchip SoCs
maintainers:
- Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
description:
Hantro G1 video encode-only accelerators present on Rockchip SoCs.
properties:
compatible:
enum:
- rockchip,rk3568-vepu
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: aclk
- const: hclk
power-domains:
maxItems: 1
iommus:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3568-power.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
vepu: video-codec@fdee0000 {
compatible = "rockchip,rk3568-vepu";
reg = <0x0 0xfdee0000 0x0 0x800>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
clock-names = "aclk", "hclk";
iommus = <&vepu_mmu>;
power-domains = <&power RK3568_PD_RGA>;
};
};

23
Documentation/devicetree/bindings/media/rockchip-isp1.yaml
View File

@ -84,8 +84,27 @@ properties:
minItems: 1
maxItems: 4
required:
- port@0
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: connection point for input on the parallel interface
properties:
bus-type:
enum: [5, 6]
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
required:
- bus-type
anyOf:
- required:
- port@0
- required:
- port@1
required:
- compatible

123
Documentation/devicetree/bindings/media/samsung,s5pv210-jpeg.yaml Normal file
View File

@ -0,0 +1,123 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/samsung,s5pv210-jpeg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5PV210 and Exynos SoC JPEG codec
maintainers:
- Jacek Anaszewski <jacek.anaszewski@gmail.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Andrzej Pietrasiewicz <andrzejtp2010@gmail.com>
properties:
compatible:
enum:
- samsung,s5pv210-jpeg
- samsung,exynos3250-jpeg
- samsung,exynos4210-jpeg
- samsung,exynos4212-jpeg
- samsung,exynos5420-jpeg
- samsung,exynos5433-jpeg
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
interrupts:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,s5pv210-jpeg
- samsung,exynos4210-jpeg
- samsung,exynos4212-jpeg
- samsung,exynos5420-jpeg
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: jpeg
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos3250-jpeg
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: jpeg
- const: sclk
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5433-jpeg
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: pclk
- const: aclk
- const: aclk_xiu
- const: sclk
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
codec@15020000 {
compatible = "samsung,exynos5433-jpeg";
reg = <0x15020000 0x10000>;
interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
clocks = <&cmu_mscl CLK_PCLK_JPEG>,
<&cmu_mscl CLK_ACLK_JPEG>,
<&cmu_mscl CLK_ACLK_XIU_MSCLX>,
<&cmu_mscl CLK_SCLK_JPEG>;
iommus = <&sysmmu_jpeg>;
power-domains = <&pd_mscl>;
};

5
Documentation/driver-api/media/mc-core.rst
View File

@ -186,8 +186,9 @@ is required and the graph structure can be freed normally.
Helper functions can be used to find a link between two given pads, or a pad
connected to another pad through an enabled link
:c:func:`media_entity_find_link()` and
:c:func:`media_entity_remote_pad()`.
(:c:func:`media_entity_find_link()`, :c:func:`media_pad_remote_pad_first()`,
:c:func:`media_entity_remote_source_pad_unique()` and
:c:func:`media_pad_remote_pad_unique()`).
Use count and power handling
^^^^^^^^^^^^^^^^^^^^^^^^^^^^

6
Documentation/driver-api/media/v4l2-subdev.rst
View File

@ -243,6 +243,12 @@ notifier callback is called. After all subdevices have been located the
.complete() callback is called. When a subdevice is removed from the
system the .unbind() method is called. All three callbacks are optional.
Drivers can store any type of custom data in their driver-specific
:c:type:`v4l2_async_subdev` wrapper. If any of that data requires special
handling when the structure is freed, drivers must implement the ``.destroy()``
notifier callback. The framework will call it right before freeing the
:c:type:`v4l2_async_subdev`.
Calling subdev operations
~~~~~~~~~~~~~~~~~~~~~~~~~

19
Documentation/userspace-api/media/drivers/hantro.rst
View File

@ -1,19 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0
Hantro video decoder driver
===========================
The Hantro video decoder driver implements the following driver-specific controls:
``V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP (integer)``
Specifies to Hantro HEVC video decoder driver the number of data (in bits) to
skip in the slice segment header.
If non-IDR, the bits to be skipped go from syntax element "pic_output_flag"
to before syntax element "slice_temporal_mvp_enabled_flag".
If IDR, the skipped bits are just "pic_output_flag"
(separate_colour_plane_flag is not supported).
.. note::
This control is not yet part of the public kernel API and
it is expected to change.

1
Documentation/userspace-api/media/drivers/index.rst
View File

@ -33,7 +33,6 @@ For more details see the file COPYING in the source distribution of Linux.
ccs
cx2341x-uapi
hantro
imx-uapi
max2175
meye-uapi

4
Documentation/userspace-api/media/v4l/control.rst
View File

@ -461,10 +461,10 @@ Example: Changing controls
perror("VIDIOC_QUERYCTRL");
exit(EXIT_FAILURE);
} else {
printf("V4L2_CID_BRIGHTNESS is not supportedn");
printf("V4L2_CID_BRIGHTNESS is not supported\n");
}
} else if (queryctrl.flags & V4L2_CTRL_FLAG_DISABLED) {
printf("V4L2_CID_BRIGHTNESS is not supportedn");
printf("V4L2_CID_BRIGHTNESS is not supported\n");
} else {
memset(&control, 0, sizeof (control));
control.id = V4L2_CID_BRIGHTNESS;

902
Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst
View File

@ -2048,3 +2048,905 @@ This structure contains all loop filter related parameters. See sections
- 0x2
- When set, the bitstream contains additional syntax elements that
specify which mode and reference frame deltas are to be updated.
.. _v4l2-codec-stateless-hevc:
``V4L2_CID_STATELESS_HEVC_SPS (struct)``
Specifies the Sequence Parameter Set fields (as extracted from the
bitstream) for the associated HEVC slice data.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.3.2 "Sequence parameter set RBSP
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_sps
.. raw:: latex
\small
.. tabularcolumns:: |p{1.2cm}|p{9.2cm}|p{6.9cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_sps
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``video_parameter_set_id``
- Specifies the value of the vps_video_parameter_set_id of the active VPS
as described in section "7.4.3.2.1 General sequence parameter set RBSP semantics"
of H.265 specifications.
* - __u8
- ``seq_parameter_set_id``
- Provides an identifier for the SPS for reference by other syntax elements
as described in section "7.4.3.2.1 General sequence parameter set RBSP semantics"
of H.265 specifications.
* - __u16
- ``pic_width_in_luma_samples``
- Specifies the width of each decoded picture in units of luma samples.
* - __u16
- ``pic_height_in_luma_samples``
- Specifies the height of each decoded picture in units of luma samples.
* - __u8
- ``bit_depth_luma_minus8``
- This value plus 8 specifies the bit depth of the samples of the luma array.
* - __u8
- ``bit_depth_chroma_minus8``
- This value plus 8 specifies the bit depth of the samples of the chroma arrays.
* - __u8
- ``log2_max_pic_order_cnt_lsb_minus4``
- Specifies the value of the variable MaxPicOrderCntLsb.
* - __u8
- ``sps_max_dec_pic_buffering_minus1``
- This value plus 1 specifies the maximum required size of the decoded picture buffer for
the coded video sequence (CVS).
* - __u8
- ``sps_max_num_reorder_pics``
- Indicates the maximum allowed number of pictures.
* - __u8
- ``sps_max_latency_increase_plus1``
- Used to signal MaxLatencyPictures, which indicates the maximum number of
pictures that can precede any picture in output order and follow that
picture in decoding order.
* - __u8
- ``log2_min_luma_coding_block_size_minus3``
- This value plus 3 specifies the minimum luma coding block size.
* - __u8
- ``log2_diff_max_min_luma_coding_block_size``
- Specifies the difference between the maximum and minimum luma coding block size.
* - __u8
- ``log2_min_luma_transform_block_size_minus2``
- This value plus 2 specifies the minimum luma transform block size.
* - __u8
- ``log2_diff_max_min_luma_transform_block_size``
- Specifies the difference between the maximum and minimum luma transform block size.
* - __u8
- ``max_transform_hierarchy_depth_inter``
- Specifies the maximum hierarchy depth for transform units of coding units coded
in inter prediction mode.
* - __u8
- ``max_transform_hierarchy_depth_intra``
- Specifies the maximum hierarchy depth for transform units of coding units coded in
intra prediction mode.
* - __u8
- ``pcm_sample_bit_depth_luma_minus1``
- This value plus 1 specifies the number of bits used to represent each of PCM sample values of the
luma component.
* - __u8
- ``pcm_sample_bit_depth_chroma_minus1``
- Specifies the number of bits used to represent each of PCM sample values of
the chroma components.
* - __u8
- ``log2_min_pcm_luma_coding_block_size_minus3``
- Plus 3 specifies the minimum size of coding blocks.
* - __u8
- ``log2_diff_max_min_pcm_luma_coding_block_size``
- Specifies the difference between the maximum and minimum size of coding blocks.
* - __u8
- ``num_short_term_ref_pic_sets``
- Specifies the number of st_ref_pic_set() syntax structures included in the SPS.
* - __u8
- ``num_long_term_ref_pics_sps``
- Specifies the number of candidate long-term reference pictures that are
specified in the SPS.
* - __u8
- ``chroma_format_idc``
- Specifies the chroma sampling.
* - __u8
- ``sps_max_sub_layers_minus1``
- This value plus 1 specifies the maximum number of temporal sub-layers.
* - __u64
- ``flags``
- See :ref:`Sequence Parameter Set Flags <hevc_sps_flags>`
.. raw:: latex
\normalsize
.. _hevc_sps_flags:
``Sequence Parameter Set Flags``
.. raw:: latex
\small
.. cssclass:: longtable
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE``
- 0x00000001
-
* - ``V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED``
- 0x00000002
-
* - ``V4L2_HEVC_SPS_FLAG_AMP_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET``
- 0x00000008
-
* - ``V4L2_HEVC_SPS_FLAG_PCM_ENABLED``
- 0x00000010
-
* - ``V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED``
- 0x00000020
-
* - ``V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT``
- 0x00000040
-
* - ``V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED``
- 0x00000080
-
* - ``V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED``
- 0x00000100
-
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_PPS (struct)``
Specifies the Picture Parameter Set fields (as extracted from the
bitstream) for the associated HEVC slice data.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.3.3 "Picture parameter set RBSP
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_pps
.. tabularcolumns:: |p{1.2cm}|p{8.6cm}|p{7.5cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_pps
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``pic_parameter_set_id``
- Identifies the PPS for reference by other syntax elements.
* - __u8
- ``num_extra_slice_header_bits``
- Specifies the number of extra slice header bits that are present
in the slice header RBSP for coded pictures referring to the PPS.
* - __u8
- ``num_ref_idx_l0_default_active_minus1``
- This value plus 1 specifies the inferred value of num_ref_idx_l0_active_minus1.
* - __u8
- ``num_ref_idx_l1_default_active_minus1``
- This value plus 1 specifies the inferred value of num_ref_idx_l1_active_minus1.
* - __s8
- ``init_qp_minus26``
- This value plus 26 specifies the initial value of SliceQp Y for each slice
referring to the PPS.
* - __u8
- ``diff_cu_qp_delta_depth``
- Specifies the difference between the luma coding tree block size
and the minimum luma coding block size of coding units that
convey cu_qp_delta_abs and cu_qp_delta_sign_flag.
* - __s8
- ``pps_cb_qp_offset``
- Specifies the offsets to the luma quantization parameter Cb.
* - __s8
- ``pps_cr_qp_offset``
- Specifies the offsets to the luma quantization parameter Cr.
* - __u8
- ``num_tile_columns_minus1``
- This value plus 1 specifies the number of tile columns partitioning the picture.
* - __u8
- ``num_tile_rows_minus1``
- This value plus 1 specifies the number of tile rows partitioning the picture.
* - __u8
- ``column_width_minus1[20]``
- This value plus 1 specifies the width of the i-th tile column in units of
coding tree blocks.
* - __u8
- ``row_height_minus1[22]``
- This value plus 1 specifies the height of the i-th tile row in units of coding
tree blocks.
* - __s8
- ``pps_beta_offset_div2``
- Specifies the default deblocking parameter offsets for beta divided by 2.
* - __s8
- ``pps_tc_offset_div2``
- Specifies the default deblocking parameter offsets for tC divided by 2.
* - __u8
- ``log2_parallel_merge_level_minus2``
- This value plus 2 specifies the value of the variable Log2ParMrgLevel.
* - __u8
- ``padding[4]``
- Applications and drivers must set this to zero.
* - __u64
- ``flags``
- See :ref:`Picture Parameter Set Flags <hevc_pps_flags>`
.. _hevc_pps_flags:
``Picture Parameter Set Flags``
.. raw:: latex
\small
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED``
- 0x00000001
-
* - ``V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT``
- 0x00000002
-
* - ``V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT``
- 0x00000008
-
* - ``V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED``
- 0x00000010
-
* - ``V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED``
- 0x00000020
-
* - ``V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED``
- 0x00000040
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT``
- 0x00000080
-
* - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED``
- 0x00000100
-
* - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED``
- 0x00000200
-
* - ``V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED``
- 0x00000400
-
* - ``V4L2_HEVC_PPS_FLAG_TILES_ENABLED``
- 0x00000800
-
* - ``V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED``
- 0x00001000
-
* - ``V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED``
- 0x00002000
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED``
- 0x00004000
-
* - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED``
- 0x00008000
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER``
- 0x00010000
-
* - ``V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT``
- 0x00020000
-
* - ``V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT``
- 0x00040000
-
* - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT``
- 0x00080000
- Specifies the presence of deblocking filter control syntax elements in
the PPS
* - ``V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING``
- 0x00100000
- Specifies that tile column boundaries and likewise tile row boundaries
are distributed uniformly across the picture
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_SLICE_PARAMS (struct)``
Specifies various slice-specific parameters, especially from the NAL unit
header, general slice segment header and weighted prediction parameter
parts of the bitstream.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.7 "General slice segment header
semantics" of the specification.
This control is a dynamically sized 1-dimensional array,
V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it.
.. c:type:: v4l2_ctrl_hevc_slice_params
.. raw:: latex
\scriptsize
.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_slice_params
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u32
- ``bit_size``
- Size (in bits) of the current slice data.
* - __u32
- ``data_byte_offset``
- Offset (in byte) to the video data in the current slice data.
* - __u32
- ``num_entry_point_offsets``
- Specifies the number of entry point offset syntax elements in the slice header.
When the driver supports it, the ``V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS``
must be set.
* - __u8
- ``nal_unit_type``
- Specifies the coding type of the slice (B, P or I).
* - __u8
- ``nuh_temporal_id_plus1``
- Minus 1 specifies a temporal identifier for the NAL unit.
* - __u8
- ``slice_type``
-
(V4L2_HEVC_SLICE_TYPE_I, V4L2_HEVC_SLICE_TYPE_P or
V4L2_HEVC_SLICE_TYPE_B).
* - __u8
- ``colour_plane_id``
- Specifies the colour plane associated with the current slice.
* - __s32
- ``slice_pic_order_cnt``
- Specifies the picture order count.
* - __u8
- ``num_ref_idx_l0_active_minus1``
- This value plus 1 specifies the maximum reference index for reference picture list 0
that may be used to decode the slice.
* - __u8
- ``num_ref_idx_l1_active_minus1``
- This value plus 1 specifies the maximum reference index for reference picture list 1
that may be used to decode the slice.
* - __u8
- ``collocated_ref_idx``
- Specifies the reference index of the collocated picture used for
temporal motion vector prediction.
* - __u8
- ``five_minus_max_num_merge_cand``
- Specifies the maximum number of merging motion vector prediction
candidates supported in the slice subtracted from 5.
* - __s8
- ``slice_qp_delta``
- Specifies the initial value of QpY to be used for the coding blocks in the slice.
* - __s8
- ``slice_cb_qp_offset``
- Specifies a difference to be added to the value of pps_cb_qp_offset.
* - __s8
- ``slice_cr_qp_offset``
- Specifies a difference to be added to the value of pps_cr_qp_offset.
* - __s8
- ``slice_act_y_qp_offset``
- Specifies the offset to the luma of quantization parameter qP derived in section 8.6.2
* - __s8
- ``slice_act_cb_qp_offset``
- Specifies the offset to the cb of quantization parameter qP derived in section 8.6.2
* - __s8
- ``slice_act_cr_qp_offset``
- Specifies the offset to the cr of quantization parameter qP derived in section 8.6.2
* - __s8
- ``slice_beta_offset_div2``
- Specifies the deblocking parameter offsets for beta divided by 2.
* - __s8
- ``slice_tc_offset_div2``
- Specifies the deblocking parameter offsets for tC divided by 2.
* - __u8
- ``pic_struct``
- Indicates whether a picture should be displayed as a frame or as one or more fields.
* - __u32
- ``slice_segment_addr``
- Specifies the address of the first coding tree block in the slice segment.
* - __u8
- ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The list of L0 reference elements as indices in the DPB.
* - __u8
- ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The list of L1 reference elements as indices in the DPB.
* - __u16
- ``short_term_ref_pic_set_size``
- Specifies the size, in bits, of the short-term reference picture set, described as st_ref_pic_set()
in the specification, included in the slice header or SPS (section 7.3.6.1).
* - __u16
- ``long_term_ref_pic_set_size``
- Specifies the size, in bits, of the long-term reference picture set include in the slice header
or SPS. It is the number of bits in the conditional block if(long_term_ref_pics_present_flag)
in section 7.3.6.1 of the specification.
* - __u8
- ``padding``
- Applications and drivers must set this to zero.
* - struct :c:type:`v4l2_hevc_pred_weight_table`
- ``pred_weight_table``
- The prediction weight coefficients for inter-picture prediction.
* - __u64
- ``flags``
- See :ref:`Slice Parameters Flags <hevc_slice_params_flags>`
.. raw:: latex
\normalsize
.. _hevc_slice_params_flags:
``Slice Parameters Flags``
.. raw:: latex
\scriptsize
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA``
- 0x00000001
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA``
- 0x00000002
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO``
- 0x00000008
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT``
- 0x00000010
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0``
- 0x00000020
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV``
- 0x00000040
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED``
- 0x00000080
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED``
- 0x00000100
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT``
- 0x00000200
-
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (integer)``
Specifies entry point offsets in bytes.
This control is a dynamically sized array. The number of entry point
offsets is reported by the ``elems`` field.
This bitstream parameter is defined according to :ref:`hevc`.
They are described in section 7.4.7.1 "General slice segment header
semantics" of the specification.
When multiple slices are submitted in a request, the length of
this array must be the sum of num_entry_point_offsets of all the
slices in the request.
``V4L2_CID_STATELESS_HEVC_SCALING_MATRIX (struct)``
Specifies the HEVC scaling matrix parameters used for the scaling process
for transform coefficients.
These matrix and parameters are defined according to :ref:`hevc`.
They are described in section 7.4.5 "Scaling list data semantics" of
the specification.
.. c:type:: v4l2_ctrl_hevc_scaling_matrix
.. raw:: latex
\scriptsize
.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``scaling_list_4x4[6][16]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_8x8[6][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_16x16[6][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_32x32[2][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_dc_coef_16x16[6]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_dc_coef_32x32[2]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
.. raw:: latex
\normalsize
.. c:type:: v4l2_hevc_dpb_entry
.. raw:: latex
\small
.. tabularcolumns:: |p{1.0cm}|p{4.2cm}|p{12.1cm}|
.. flat-table:: struct v4l2_hevc_dpb_entry
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u64
- ``timestamp``
- Timestamp of the V4L2 capture buffer to use as reference, used
with B-coded and P-coded frames. The timestamp refers to the
``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the
:c:func:`v4l2_timeval_to_ns()` function to convert the struct
:c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64.
* - __u8
- ``flags``
- Long term flag for the reference frame
(V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE). The flag is set as
described in the ITU HEVC specification chapter "8.3.2 Decoding
process for reference picture set".
* - __u8
- ``field_pic``
- Whether the reference is a field picture or a frame.
See :ref:`HEVC dpb field pic Flags <hevc_dpb_field_pic_flags>`
* - __s32
- ``pic_order_cnt_val``
- The picture order count of the current picture.
* - __u8
- ``padding[2]``
- Applications and drivers must set this to zero.
.. raw:: latex
\normalsize
.. _hevc_dpb_field_pic_flags:
``HEVC dpb field pic Flags``
.. raw:: latex
\scriptsize
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SEI_PIC_STRUCT_FRAME``
- 0
- (progressive) Frame
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_FIELD``
- 1
- Top field
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_FIELD``
- 2
- Bottom field
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_BOTTOM``
- 3
- Top field, bottom field, in that order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_TOP``
- 4
- Bottom field, top field, in that order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_BOTTOM_TOP``
- 5
- Top field, bottom field, top field repeated, in that order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_TOP_BOTTOM``
- 6
- Bottom field, top field, bottom field repeated, in that order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_FRAME_DOUBLING``
- 7
- Frame doubling
* - ``V4L2_HEVC_SEI_PIC_STRUCT_FRAME_TRIPLING``
- 8
- Frame tripling
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_PAIRED_PREVIOUS_BOTTOM``
- 9
- Top field paired with previous bottom field in output order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_PAIRED_PREVIOUS_TOP``
- 10
- Bottom field paired with previous top field in output order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_PAIRED_NEXT_BOTTOM``
- 11
- Top field paired with next bottom field in output order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_PAIRED_NEXT_TOP``
- 12
- Bottom field paired with next top field in output order
.. c:type:: v4l2_hevc_pred_weight_table
.. raw:: latex
\footnotesize
.. tabularcolumns:: |p{0.8cm}|p{10.6cm}|p{5.9cm}|
.. flat-table:: struct v4l2_hevc_pred_weight_table
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __s8
- ``delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The difference of the weighting factor applied to the luma
prediction value for list 0.
* - __s8
- ``luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The additive offset applied to the luma prediction value for list 0.
* - __s8
- ``delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
- The difference of the weighting factor applied to the chroma
prediction value for list 0.
* - __s8
- ``chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
- The difference of the additive offset applied to the chroma
prediction values for list 0.
* - __s8
- ``delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The difference of the weighting factor applied to the luma
prediction value for list 1.
* - __s8
- ``luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The additive offset applied to the luma prediction value for list 1.
* - __s8
- ``delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
- The difference of the weighting factor applied to the chroma
prediction value for list 1.
* - __s8
- ``chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
- The difference of the additive offset applied to the chroma
prediction values for list 1.
* - __u8
- ``luma_log2_weight_denom``
- The base 2 logarithm of the denominator for all luma weighting
factors.
* - __s8
- ``delta_chroma_log2_weight_denom``
- The difference of the base 2 logarithm of the denominator for
all chroma weighting factors.
* - __u8
- ``padding[6]``
- Applications and drivers must set this to zero.
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_DECODE_MODE (enum)``
Specifies the decoding mode to use. Currently exposes slice-based and
frame-based decoding but new modes might be added later on.
This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE
pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE
are required to set this control in order to specify the decoding mode
that is expected for the buffer.
Drivers may expose a single or multiple decoding modes, depending
on what they can support.
.. c:type:: v4l2_stateless_hevc_decode_mode
.. raw:: latex
\small
.. tabularcolumns:: |p{9.4cm}|p{0.6cm}|p{7.3cm}|
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED``
- 0
- Decoding is done at the slice granularity.
The OUTPUT buffer must contain a single slice.
* - ``V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED``
- 1
- Decoding is done at the frame granularity.
The OUTPUT buffer must contain all slices needed to decode the
frame.
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_START_CODE (enum)``
Specifies the HEVC slice start code expected for each slice.
This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE
pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE
are required to set this control in order to specify the start code
that is expected for the buffer.
Drivers may expose a single or multiple start codes, depending
on what they can support.
.. c:type:: v4l2_stateless_hevc_start_code
.. tabularcolumns:: |p{9.2cm}|p{0.6cm}|p{7.5cm}|
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_STATELESS_HEVC_START_CODE_NONE``
- 0
- Selecting this value specifies that HEVC slices are passed
to the driver without any start code. The bitstream data should be
according to :ref:`hevc` 7.3.1.1 General NAL unit syntax, hence
contains emulation prevention bytes when required.
* - ``V4L2_STATELESS_HEVC_START_CODE_ANNEX_B``
- 1
- Selecting this value specifies that HEVC slices are expected
to be prefixed by Annex B start codes. According to :ref:`hevc`
valid start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001.
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID (integer)``
Specifies a priority identifier for the NAL unit, which will be applied to
the base layer. By default this value is set to 0 for the base layer,
and the next layer will have the priority ID assigned as 1, 2, 3 and so on.
The video encoder can't decide the priority id to be applied to a layer,
so this has to come from client.
This is applicable to H264 and valid Range is from 0 to 63.
Source Rec. ITU-T H.264 (06/2019); G.7.4.1.1, G.8.8.1.
``V4L2_CID_MPEG_VIDEO_LTR_COUNT (integer)``
Specifies the maximum number of Long Term Reference (LTR) frames at any
given time that the encoder can keep.
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX (integer)``
After setting this control the frame that will be queued next
will be marked as a Long Term Reference (LTR) frame
and given this LTR index which ranges from 0 to LTR_COUNT-1.
This is applicable to the H264 and HEVC encoders.
Source Rec. ITU-T H.264 (06/2019); Table 7.9
``V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES (bitmask)``
Specifies the Long Term Reference (LTR) frame(s) to be used for
encoding the next frame queued after setting this control.
This provides a bitmask which consists of bits [0, LTR_COUNT-1].
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_STATELESS_HEVC_DECODE_PARAMS (struct)``
Specifies various decode parameters, especially the references picture order
count (POC) for all the lists (short, long, before, current, after) and the
number of entries for each of them.
These parameters are defined according to :ref:`hevc`.
They are described in section 8.3 "Slice decoding process" of the
specification.
.. c:type:: v4l2_ctrl_hevc_decode_params
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_decode_params
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __s32
- ``pic_order_cnt_val``
- PicOrderCntVal as described in section 8.3.1 "Decoding process
for picture order count" of the specification.
* - __u16
- ``short_term_ref_pic_set_size``
- Specifies the size, in bits, of the short-term reference picture set, of the first slice
described as st_ref_pic_set() in the specification, included in the slice header
or SPS (section 7.3.6.1).
* - __u16
- ``long_term_ref_pic_set_size``
- Specifies the size, in bits, of the long-term reference picture set, of the first slice
included in the slice header or SPS. It is the number of bits in the conditional block
if(long_term_ref_pics_present_flag) in section 7.3.6.1 of the specification.
* - __u8
- ``num_active_dpb_entries``
- The number of entries in ``dpb``.
* - __u8
- ``num_poc_st_curr_before``
- The number of reference pictures in the short-term set that come before
the current frame.
* - __u8
- ``num_poc_st_curr_after``
- The number of reference pictures in the short-term set that come after
the current frame.
* - __u8
- ``num_poc_lt_curr``
- The number of reference pictures in the long-term set.
* - __u8
- ``poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocStCurrBefore as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the short term before references in DPB array.
* - __u8
- ``poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocStCurrAfter as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the short term after references in DPB array.
* - __u8
- ``poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocLtCurr as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the long term references in DPB array.
* - struct :c:type:`v4l2_hevc_dpb_entry`
- ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The decoded picture buffer, for meta-data about reference frames.
* - __u64
- ``flags``
- See :ref:`Decode Parameters Flags <hevc_decode_params_flags>`
.. _hevc_decode_params_flags:
``Decode Parameters Flags``
.. cssclass:: longtable
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC``
- 0x00000001
-
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC``
- 0x00000002
-
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR``
- 0x00000004
-

780
Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
View File

@ -2658,783 +2658,3 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
Indicates whether to generate SPS and PPS at every IDR. Setting it to 0
disables generating SPS and PPS at every IDR. Setting it to one enables
generating SPS and PPS at every IDR.
.. _v4l2-mpeg-hevc:
``V4L2_CID_MPEG_VIDEO_HEVC_SPS (struct)``
Specifies the Sequence Parameter Set fields (as extracted from the
bitstream) for the associated HEVC slice data.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.3.2 "Sequence parameter set RBSP
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_sps
.. raw:: latex
\small
.. tabularcolumns:: |p{1.2cm}|p{9.2cm}|p{6.9cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_sps
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u16
- ``pic_width_in_luma_samples``
-
* - __u16
- ``pic_height_in_luma_samples``
-
* - __u8
- ``bit_depth_luma_minus8``
-
* - __u8
- ``bit_depth_chroma_minus8``
-
* - __u8
- ``log2_max_pic_order_cnt_lsb_minus4``
-
* - __u8
- ``sps_max_dec_pic_buffering_minus1``
-
* - __u8
- ``sps_max_num_reorder_pics``
-
* - __u8
- ``sps_max_latency_increase_plus1``
-
* - __u8
- ``log2_min_luma_coding_block_size_minus3``
-
* - __u8
- ``log2_diff_max_min_luma_coding_block_size``
-
* - __u8
- ``log2_min_luma_transform_block_size_minus2``
-
* - __u8
- ``log2_diff_max_min_luma_transform_block_size``
-
* - __u8
- ``max_transform_hierarchy_depth_inter``
-
* - __u8
- ``max_transform_hierarchy_depth_intra``
-
* - __u8
- ``pcm_sample_bit_depth_luma_minus1``
-
* - __u8
- ``pcm_sample_bit_depth_chroma_minus1``
-
* - __u8
- ``log2_min_pcm_luma_coding_block_size_minus3``
-
* - __u8
- ``log2_diff_max_min_pcm_luma_coding_block_size``
-
* - __u8
- ``num_short_term_ref_pic_sets``
-
* - __u8
- ``num_long_term_ref_pics_sps``
-
* - __u8
- ``chroma_format_idc``
-
* - __u8
- ``sps_max_sub_layers_minus1``
-
* - __u64
- ``flags``
- See :ref:`Sequence Parameter Set Flags <hevc_sps_flags>`
.. raw:: latex
\normalsize
.. _hevc_sps_flags:
``Sequence Parameter Set Flags``
.. raw:: latex
\small
.. cssclass:: longtable
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE``
- 0x00000001
-
* - ``V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED``
- 0x00000002
-
* - ``V4L2_HEVC_SPS_FLAG_AMP_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET``
- 0x00000008
-
* - ``V4L2_HEVC_SPS_FLAG_PCM_ENABLED``
- 0x00000010
-
* - ``V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED``
- 0x00000020
-
* - ``V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT``
- 0x00000040
-
* - ``V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED``
- 0x00000080
-
* - ``V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED``
- 0x00000100
-
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_PPS (struct)``
Specifies the Picture Parameter Set fields (as extracted from the
bitstream) for the associated HEVC slice data.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.3.3 "Picture parameter set RBSP
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_pps
.. tabularcolumns:: |p{1.2cm}|p{8.6cm}|p{7.5cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_pps
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``num_extra_slice_header_bits``
-
* - __u8
- ``num_ref_idx_l0_default_active_minus1``
- Specifies the inferred value of num_ref_idx_l0_active_minus1
* - __u8
- ``num_ref_idx_l1_default_active_minus1``
- Specifies the inferred value of num_ref_idx_l1_active_minus1
* - __s8
- ``init_qp_minus26``
-
* - __u8
- ``diff_cu_qp_delta_depth``
-
* - __s8
- ``pps_cb_qp_offset``
-
* - __s8
- ``pps_cr_qp_offset``
-
* - __u8
- ``num_tile_columns_minus1``
-
* - __u8
- ``num_tile_rows_minus1``
-
* - __u8
- ``column_width_minus1[20]``
-
* - __u8
- ``row_height_minus1[22]``
-
* - __s8
- ``pps_beta_offset_div2``
-
* - __s8
- ``pps_tc_offset_div2``
-
* - __u8
- ``log2_parallel_merge_level_minus2``
-
* - __u8
- ``padding[4]``
- Applications and drivers must set this to zero.
* - __u64
- ``flags``
- See :ref:`Picture Parameter Set Flags <hevc_pps_flags>`
.. _hevc_pps_flags:
``Picture Parameter Set Flags``
.. raw:: latex
\small
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED``
- 0x00000001
-
* - ``V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT``
- 0x00000002
-
* - ``V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT``
- 0x00000008
-
* - ``V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED``
- 0x00000010
-
* - ``V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED``
- 0x00000020
-
* - ``V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED``
- 0x00000040
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT``
- 0x00000080
-
* - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED``
- 0x00000100
-
* - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED``
- 0x00000200
-
* - ``V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED``
- 0x00000400
-
* - ``V4L2_HEVC_PPS_FLAG_TILES_ENABLED``
- 0x00000800
-
* - ``V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED``
- 0x00001000
-
* - ``V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED``
- 0x00002000
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED``
- 0x00004000
-
* - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED``
- 0x00008000
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER``
- 0x00010000
-
* - ``V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT``
- 0x00020000
-
* - ``V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT``
- 0x00040000
-
* - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT``
- 0x00080000
- Specifies the presence of deblocking filter control syntax elements in
the PPS
* - ``V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING``
- 0x00100000
- Specifies that tile column boundaries and likewise tile row boundaries
are distributed uniformly across the picture
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (struct)``
Specifies various slice-specific parameters, especially from the NAL unit
header, general slice segment header and weighted prediction parameter
parts of the bitstream.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.7 "General slice segment header
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_slice_params
.. raw:: latex
\scriptsize
.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_slice_params
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u32
- ``bit_size``
- Size (in bits) of the current slice data.
* - __u32
- ``data_bit_offset``
- Offset (in bits) to the video data in the current slice data.
* - __u8
- ``nal_unit_type``
-
* - __u8
- ``nuh_temporal_id_plus1``
-
* - __u8
- ``slice_type``
-
(V4L2_HEVC_SLICE_TYPE_I, V4L2_HEVC_SLICE_TYPE_P or
V4L2_HEVC_SLICE_TYPE_B).
* - __u8
- ``colour_plane_id``
-
* - __u16
- ``slice_pic_order_cnt``
-
* - __u8
- ``num_ref_idx_l0_active_minus1``
-
* - __u8
- ``num_ref_idx_l1_active_minus1``
-
* - __u8
- ``collocated_ref_idx``
-
* - __u8
- ``five_minus_max_num_merge_cand``
-
* - __s8
- ``slice_qp_delta``
-
* - __s8
- ``slice_cb_qp_offset``
-
* - __s8
- ``slice_cr_qp_offset``
-
* - __s8
- ``slice_act_y_qp_offset``
-
* - __s8
- ``slice_act_cb_qp_offset``
-
* - __s8
- ``slice_act_cr_qp_offset``
-
* - __s8
- ``slice_beta_offset_div2``
-
* - __s8
- ``slice_tc_offset_div2``
-
* - __u8
- ``pic_struct``
-
* - __u32
- ``slice_segment_addr``
-
* - __u8
- ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The list of L0 reference elements as indices in the DPB.
* - __u8
- ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The list of L1 reference elements as indices in the DPB.
* - __u8
- ``padding``
- Applications and drivers must set this to zero.
* - struct :c:type:`v4l2_hevc_pred_weight_table`
- ``pred_weight_table``
- The prediction weight coefficients for inter-picture prediction.
* - __u64
- ``flags``
- See :ref:`Slice Parameters Flags <hevc_slice_params_flags>`
.. raw:: latex
\normalsize
.. _hevc_slice_params_flags:
``Slice Parameters Flags``
.. raw:: latex
\scriptsize
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA``
- 0x00000001
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA``
- 0x00000002
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO``
- 0x00000008
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT``
- 0x00000010
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0``
- 0x00000020
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV``
- 0x00000040
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED``
- 0x00000080
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED``
- 0x00000100
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT``
- 0x00000200
-
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)``
Specifies the HEVC scaling matrix parameters used for the scaling process
for transform coefficients.
These matrix and parameters are defined according to :ref:`hevc`.
They are described in section 7.4.5 "Scaling list data semantics" of
the specification.
.. c:type:: v4l2_ctrl_hevc_scaling_matrix
.. raw:: latex
\scriptsize
.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``scaling_list_4x4[6][16]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_8x8[6][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_16x16[6][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_32x32[2][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_dc_coef_16x16[6]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_dc_coef_32x32[2]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
.. raw:: latex
\normalsize
.. c:type:: v4l2_hevc_dpb_entry
.. raw:: latex
\small
.. tabularcolumns:: |p{1.0cm}|p{4.2cm}|p{12.1cm}|
.. flat-table:: struct v4l2_hevc_dpb_entry
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u64
- ``timestamp``
- Timestamp of the V4L2 capture buffer to use as reference, used
with B-coded and P-coded frames. The timestamp refers to the
``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the
:c:func:`v4l2_timeval_to_ns()` function to convert the struct
:c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64.
* - __u8
- ``flags``
- Long term flag for the reference frame
(V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE). The flag is set as
described in the ITU HEVC specification chapter "8.3.2 Decoding
process for reference picture set".
* - __u8
- ``field_pic``
- Whether the reference is a field picture or a frame.
* - __u16
- ``pic_order_cnt[2]``
- The picture order count of the reference. Only the first element of the
array is used for frame pictures, while the first element identifies the
top field and the second the bottom field in field-coded pictures.
* - __u8
- ``padding[2]``
- Applications and drivers must set this to zero.
.. raw:: latex
\normalsize
.. c:type:: v4l2_hevc_pred_weight_table
.. raw:: latex
\footnotesize
.. tabularcolumns:: |p{0.8cm}|p{10.6cm}|p{5.9cm}|
.. flat-table:: struct v4l2_hevc_pred_weight_table
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``luma_log2_weight_denom``
-
* - __s8
- ``delta_chroma_log2_weight_denom``
-
* - __s8
- ``delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
-
* - __s8
- ``luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
-
* - __s8
- ``delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
-
* - __s8
- ``chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
-
* - __s8
- ``delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
-
* - __s8
- ``luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
-
* - __s8
- ``delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
-
* - __s8
- ``chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
-
* - __u8
- ``padding[6]``
- Applications and drivers must set this to zero.
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)``
Specifies the decoding mode to use. Currently exposes slice-based and
frame-based decoding but new modes might be added later on.
This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE
pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE
are required to set this control in order to specify the decoding mode
that is expected for the buffer.
Drivers may expose a single or multiple decoding modes, depending
on what they can support.
.. note::
This menu control is not yet part of the public kernel API and
it is expected to change.
.. c:type:: v4l2_mpeg_video_hevc_decode_mode
.. raw:: latex
\small
.. tabularcolumns:: |p{9.4cm}|p{0.6cm}|p{7.3cm}|
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED``
- 0
- Decoding is done at the slice granularity.
The OUTPUT buffer must contain a single slice.
* - ``V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED``
- 1
- Decoding is done at the frame granularity.
The OUTPUT buffer must contain all slices needed to decode the
frame. The OUTPUT buffer must also contain both fields.
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (enum)``
Specifies the HEVC slice start code expected for each slice.
This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE
pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE
are required to set this control in order to specify the start code
that is expected for the buffer.
Drivers may expose a single or multiple start codes, depending
on what they can support.
.. note::
This menu control is not yet part of the public kernel API and
it is expected to change.
.. c:type:: v4l2_mpeg_video_hevc_start_code
.. tabularcolumns:: |p{9.2cm}|p{0.6cm}|p{7.5cm}|
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE``
- 0
- Selecting this value specifies that HEVC slices are passed
to the driver without any start code. The bitstream data should be
according to :ref:`hevc` 7.3.1.1 General NAL unit syntax, hence
contains emulation prevention bytes when required.
* - ``V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B``
- 1
- Selecting this value specifies that HEVC slices are expected
to be prefixed by Annex B start codes. According to :ref:`hevc`
valid start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001.
``V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID (integer)``
Specifies a priority identifier for the NAL unit, which will be applied to
the base layer. By default this value is set to 0 for the base layer,
and the next layer will have the priority ID assigned as 1, 2, 3 and so on.
The video encoder can't decide the priority id to be applied to a layer,
so this has to come from client.
This is applicable to H264 and valid Range is from 0 to 63.
Source Rec. ITU-T H.264 (06/2019); G.7.4.1.1, G.8.8.1.
``V4L2_CID_MPEG_VIDEO_LTR_COUNT (integer)``
Specifies the maximum number of Long Term Reference (LTR) frames at any
given time that the encoder can keep.
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX (integer)``
After setting this control the frame that will be queued next
will be marked as a Long Term Reference (LTR) frame
and given this LTR index which ranges from 0 to LTR_COUNT-1.
This is applicable to the H264 and HEVC encoders.
Source Rec. ITU-T H.264 (06/2019); Table 7.9
``V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES (bitmask)``
Specifies the Long Term Reference (LTR) frame(s) to be used for
encoding the next frame queued after setting this control.
This provides a bitmask which consists of bits [0, LTR_COUNT-1].
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (struct)``
Specifies various decode parameters, especially the references picture order
count (POC) for all the lists (short, long, before, current, after) and the
number of entries for each of them.
These parameters are defined according to :ref:`hevc`.
They are described in section 8.3 "Slice decoding process" of the
specification.
.. c:type:: v4l2_ctrl_hevc_decode_params
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_decode_params
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __s32
- ``pic_order_cnt_val``
- PicOrderCntVal as described in section 8.3.1 "Decoding process
for picture order count" of the specification.
* - __u8
- ``num_active_dpb_entries``
- The number of entries in ``dpb``.
* - struct :c:type:`v4l2_hevc_dpb_entry`
- ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The decoded picture buffer, for meta-data about reference frames.
* - __u8
- ``num_poc_st_curr_before``
- The number of reference pictures in the short-term set that come before
the current frame.
* - __u8
- ``num_poc_st_curr_after``
- The number of reference pictures in the short-term set that come after
the current frame.
* - __u8
- ``num_poc_lt_curr``
- The number of reference pictures in the long-term set.
* - __u8
- ``poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocStCurrBefore as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the short term before references in DPB array.
* - __u8
- ``poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocStCurrAfter as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the short term after references in DPB array.
* - __u8
- ``poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocLtCurr as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the long term references in DPB array.
* - __u64
- ``flags``
- See :ref:`Decode Parameters Flags <hevc_decode_params_flags>`
.. _hevc_decode_params_flags:
``Decode Parameters Flags``
.. cssclass:: longtable
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC``
- 0x00000001
-
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC``
- 0x00000002
-
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR``
- 0x00000004
-

2
Documentation/userspace-api/media/v4l/mmap.rst
View File

@ -232,7 +232,7 @@ In the write loop, when the application runs out of free buffers, it
must wait until an empty buffer can be dequeued and reused.
To enqueue and dequeue a buffer applications use the
:ref:`VIVIOC_QBUF <VIDIOC_QBUF>` and :ref:`VIDIOC_DQBUF <VIDIOC_QBUF>`
:ref:`VIDIOC_QBUF <VIDIOC_QBUF>` and :ref:`VIDIOC_DQBUF <VIDIOC_QBUF>`
ioctl. The status of a buffer being mapped, enqueued, full or empty can
be determined at any time using the :ref:`VIDIOC_QUERYBUF` ioctl. Two
methods exist to suspend execution of the application until one or more

7
Documentation/userspace-api/media/v4l/pixfmt-compressed.rst
View File

@ -212,14 +212,9 @@ Compressed Formats
``V4L2_CID_MPEG_VIDEO_HEVC_SPS``,
``V4L2_CID_MPEG_VIDEO_HEVC_PPS``, and
``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS``.
See the :ref:`associated Codec Control IDs <v4l2-mpeg-hevc>`.
See the :ref:`associated Codec Control IDs <v4l2-codec-stateless-hevc>`.
Buffers associated with this pixel format must contain the appropriate
number of macroblocks to decode a full corresponding frame.
.. note::
This format is not yet part of the public kernel API and it
is expected to change.
* .. _V4L2-PIX-FMT-FWHT:
- ``V4L2_PIX_FMT_FWHT``

20
Documentation/userspace-api/media/v4l/pixfmt-packed-yuv.rst
View File

@ -220,6 +220,26 @@ the second byte and Y'\ :sub:`7-0` in the third byte.
- Y'\ :sub:`7-0`
- X\ :sub:`7-0`
* .. _V4L2-PIX-FMT-YUVA32:
- ``V4L2_PIX_FMT_YUVA32``
- 'YUVA'
- Y'\ :sub:`7-0`
- Cb\ :sub:`7-0`
- Cr\ :sub:`7-0`
- A\ :sub:`7-0`
* .. _V4L2-PIX-FMT-YUVX32:
- ``V4L2_PIX_FMT_YUVX32``
- 'YUVX'
- Y'\ :sub:`7-0`
- Cb\ :sub:`7-0`
- Cr\ :sub:`7-0`
- X\ :sub:`7-0`
* .. _V4L2-PIX-FMT-YUV24:
- ``V4L2_PIX_FMT_YUV24``

63
Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
View File

@ -109,6 +109,20 @@ All components are stored with the same number of bits per component.
- Cb, Cr
- No
- 16x16 tiles
* - V4L2_PIX_FMT_P010
- 'P010'
- 10
- 4:2:0
- Cb, Cr
- Yes
- Linear
* - V4L2_PIX_FMT_P010_4L4
- 'T010'
- 10
- 4:2:0
- Cb, Cr
- Yes
- 4x4 tiles
* - V4L2_PIX_FMT_NV16
- 'NV16'
- 8
@ -171,6 +185,7 @@ horizontally.
.. _V4L2-PIX-FMT-NV21:
.. _V4L2-PIX-FMT-NV12M:
.. _V4L2-PIX-FMT-NV21M:
.. _V4L2-PIX-FMT-P010:
NV12, NV21, NV12M and NV21M
---------------------------
@ -519,6 +534,50 @@ number of lines as the luma plane.
- Cb\ :sub:`33`
- Cr\ :sub:`33`
.. _V4L2_PIX_FMT_P010:
.. _V4L2-PIX-FMT-P010-4L4:
P010 and tiled P010
-------------------
P010 is like NV12 with 10 bits per component, expanded to 16 bits.
Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian order.
.. flat-table:: Sample 4x4 P010 Image
:header-rows: 0
:stub-columns: 0
* - start + 0:
- Y'\ :sub:`00`
- Y'\ :sub:`01`
- Y'\ :sub:`02`
- Y'\ :sub:`03`
* - start + 8:
- Y'\ :sub:`10`
- Y'\ :sub:`11`
- Y'\ :sub:`12`
- Y'\ :sub:`13`
* - start + 16:
- Y'\ :sub:`20`
- Y'\ :sub:`21`
- Y'\ :sub:`22`
- Y'\ :sub:`23`
* - start + 24:
- Y'\ :sub:`30`
- Y'\ :sub:`31`
- Y'\ :sub:`32`
- Y'\ :sub:`33`
* - start + 32:
- Cb\ :sub:`00`
- Cr\ :sub:`00`
- Cb\ :sub:`01`
- Cr\ :sub:`01`
* - start + 40:
- Cb\ :sub:`10`
- Cr\ :sub:`10`
- Cb\ :sub:`11`
- Cr\ :sub:`11`
Fully Planar YUV Formats
========================
@ -538,6 +597,10 @@ relationship between the luma and chroma line padding and stride.
All components are stored with the same number of bits per component.
``V4L2_PIX_FMT_P010_4L4`` stores pixels in 4x4 tiles, and stores tiles linearly
in memory. The line stride must be aligned to multiple of 8 and image height to
a multiple of 4. The layouts of the luma and chroma planes are identical.
.. raw:: latex
\small

20
Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst
View File

@ -249,6 +249,26 @@ still cause this situation.
- ``p_hdr10_mastering``
- A pointer to a struct :c:type:`v4l2_ctrl_hdr10_mastering_display`. Valid if this control is
of type ``V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY``.
* - struct :c:type:`v4l2_ctrl_hevc_sps` *
- ``p_hevc_sps``
- A pointer to a struct :c:type:`v4l2_ctrl_hevc_sps`. Valid if this
control is of type ``V4L2_CTRL_TYPE_HEVC_SPS``.
* - struct :c:type:`v4l2_ctrl_hevc_pps` *
- ``p_hevc_pps``
- A pointer to a struct :c:type:`v4l2_ctrl_hevc_pps`. Valid if this
control is of type ``V4L2_CTRL_TYPE_HEVC_PPS``.
* - struct :c:type:`v4l2_ctrl_hevc_slice_params` *
- ``p_hevc_slice_params``
- A pointer to a struct :c:type:`v4l2_ctrl_hevc_slice_params`. Valid if this
control is of type ``V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS``.
* - struct :c:type:`v4l2_ctrl_hevc_scaling_matrix` *
- ``p_hevc_scaling_matrix``
- A pointer to a struct :c:type:`v4l2_ctrl_hevc_scaling_matrix`. Valid if this
control is of type ``V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX``.
* - struct :c:type:`v4l2_ctrl_hevc_decode_params` *
- ``p_hevc_decode_params``
- A pointer to a struct :c:type:`v4l2_ctrl_hevc_decode_params`. Valid if this
control is of type ``V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS``.
* - void *
- ``ptr``
- A pointer to a compound type which can be an N-dimensional array

8
Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst
View File

@ -625,6 +625,14 @@ See also the examples in :ref:`control`.
``V4L2_CTRL_FLAG_GRABBED`` flag when buffers are allocated or
streaming is in progress since most drivers do not support changing
the format in that case.
* - ``V4L2_CTRL_FLAG_DYNAMIC_ARRAY``
- 0x0800
- This control is a dynamically sized 1-dimensional array. It
behaves the same as a regular array, except that the number
of elements as reported by the ``elems`` field is between 1 and
``dims[0]``. So setting the control with a differently sized
array will change the ``elems`` field when the control is
queried afterwards.
Return Value
============

9
Documentation/userspace-api/media/videodev2.h.rst.exceptions
View File

@ -70,6 +70,7 @@ replace symbol V4L2_COLORSPACE_REC709 :c:type:`v4l2_colorspace`
replace symbol V4L2_COLORSPACE_SMPTE170M :c:type:`v4l2_colorspace`
replace symbol V4L2_COLORSPACE_SMPTE240M :c:type:`v4l2_colorspace`
replace symbol V4L2_COLORSPACE_SRGB :c:type:`v4l2_colorspace`
replace symbol V4L2_COLORSPACE_LAST :c:type:`v4l2_colorspace`
# Documented enum v4l2_xfer_func
replace symbol V4L2_XFER_FUNC_709 :c:type:`v4l2_xfer_func`
@ -81,6 +82,7 @@ replace symbol V4L2_XFER_FUNC_NONE :c:type:`v4l2_xfer_func`
replace symbol V4L2_XFER_FUNC_SMPTE2084 :c:type:`v4l2_xfer_func`
replace symbol V4L2_XFER_FUNC_SMPTE240M :c:type:`v4l2_xfer_func`
replace symbol V4L2_XFER_FUNC_SRGB :c:type:`v4l2_xfer_func`
replace symbol V4L2_XFER_FUNC_LAST :c:type:`v4l2_xfer_func`
# Documented enum v4l2_ycbcr_encoding
replace symbol V4L2_YCBCR_ENC_601 :c:type:`v4l2_ycbcr_encoding`
@ -92,6 +94,7 @@ replace symbol V4L2_YCBCR_ENC_SYCC :c:type:`v4l2_ycbcr_encoding`
replace symbol V4L2_YCBCR_ENC_XV601 :c:type:`v4l2_ycbcr_encoding`
replace symbol V4L2_YCBCR_ENC_XV709 :c:type:`v4l2_ycbcr_encoding`
replace symbol V4L2_YCBCR_ENC_SMPTE240M :c:type:`v4l2_ycbcr_encoding`
replace symbol V4L2_YCBCR_ENC_LAST :c:type:`v4l2_ycbcr_encoding`
# Documented enum v4l2_hsv_encoding
replace symbol V4L2_HSV_ENC_180 :c:type:`v4l2_hsv_encoding`
@ -153,6 +156,11 @@ replace symbol V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_VP9_FRAME :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HDR10_CLL_INFO :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HEVC_SPS :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HEVC_PPS :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS :c:type:`v4l2_ctrl_type`
# V4L2 capability defines
replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities
@ -379,6 +387,7 @@ replace define V4L2_CTRL_FLAG_VOLATILE control-flags
replace define V4L2_CTRL_FLAG_HAS_PAYLOAD control-flags
replace define V4L2_CTRL_FLAG_EXECUTE_ON_WRITE control-flags
replace define V4L2_CTRL_FLAG_MODIFY_LAYOUT control-flags
replace define V4L2_CTRL_FLAG_DYNAMIC_ARRAY control-flags
replace define V4L2_CTRL_FLAG_NEXT_CTRL control
replace define V4L2_CTRL_FLAG_NEXT_COMPOUND control

20
MAINTAINERS
View File

@ -766,6 +766,14 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
F: drivers/media/platform/sunxi/sun4i-csi/
ALLWINNER A31 MIPI CSI-2 BRIDGE DRIVER
M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
F: drivers/media/platform/sunxi/sun6i-mipi-csi2/
ALLWINNER CPUFREQ DRIVER
M: Yangtao Li <tiny.windzz@gmail.com>
L: linux-pm@vger.kernel.org
@ -1473,6 +1481,13 @@ S: Supported
W: http://www.aquantia.com
F: drivers/net/ethernet/aquantia/atlantic/aq_ptp*
AR0521 ON SEMICONDUCTOR CAMERA SENSOR DRIVER
M: Krzysztof Hałasa <khalasa@piap.pl>
L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/i2c/onnn,ar0521.yaml
F: drivers/media/i2c/ar0521.c
ARASAN NAND CONTROLLER DRIVER
M: Miquel Raynal <miquel.raynal@bootlin.com>
M: Naga Sureshkumar Relli <nagasure@xilinx.com>
@ -2726,6 +2741,7 @@ M: Sylwester Nawrocki <s.nawrocki@samsung.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/samsung,s5pv210-jpeg.yaml
F: drivers/media/platform/samsung/s5p-jpeg/
ARM/SAMSUNG S5P SERIES Multi Format Codec (MFC) SUPPORT
@ -8811,6 +8827,7 @@ L: linux-media@vger.kernel.org
L: linux-rockchip@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
F: Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
F: Documentation/devicetree/bindings/media/rockchip-vpu.yaml
F: drivers/staging/media/hantro/
@ -12630,6 +12647,7 @@ F: Documentation/driver-api/media/
F: Documentation/userspace-api/media/
F: drivers/media/
F: drivers/staging/media/
F: include/dt-bindings/media/
F: include/linux/platform_data/media/
F: include/media/
F: include/uapi/linux/dvb/
@ -12712,6 +12730,7 @@ F: drivers/media/platform/mediatek/vpu/
MEDIATEK MEDIA DRIVER
M: Tiffany Lin <tiffany.lin@mediatek.com>
M: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
M: Yunfei Dong <yunfei.dong@mediatek.com>
S: Supported
F: Documentation/devicetree/bindings/media/mediatek,vcodec*.yaml
F: Documentation/devicetree/bindings/media/mediatek-vpu.txt
@ -14915,6 +14934,7 @@ M: Daniel Scally <djrscally@gmail.com>
L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/ovti,ov5693.yaml
F: drivers/media/i2c/ov5693.c
OMNIVISION OV5695 SENSOR DRIVER

5
drivers/media/cec/core/cec-adap.c
View File

@ -1309,8 +1309,11 @@ static int cec_config_log_addr(struct cec_adapter *adap,
* we assume that something is really weird and that it is not a
* good idea to try and claim this logical address.
*/
if (i == max_retries)
if (i == max_retries) {
dprintk(0, "polling for LA %u failed with tx_status=0x%04x\n",
log_addr, msg.tx_status);
return 0;
}
/*
* Message not acknowledged, so this logical

4
drivers/media/cec/platform/cros-ec/cros-ec-cec.c
View File

@ -217,6 +217,10 @@ static const struct cec_dmi_match cec_dmi_match_table[] = {
{ "Google", "Fizz", "0000:00:02.0", "Port B" },
/* Google Brask */
{ "Google", "Brask", "0000:00:02.0", "Port B" },
/* Google Moli */
{ "Google", "Moli", "0000:00:02.0", "Port B" },
/* Google Kinox */
{ "Google", "Kinox", "0000:00:02.0", "Port B" },
};
static struct device *cros_ec_cec_find_hdmi_dev(struct device *dev,

44
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
View File

@ -266,6 +266,8 @@ bool tpg_s_fourcc(struct tpg_data *tpg, u32 fourcc)
case V4L2_PIX_FMT_XYUV32:
case V4L2_PIX_FMT_VUYA32:
case V4L2_PIX_FMT_VUYX32:
case V4L2_PIX_FMT_YUVA32:
case V4L2_PIX_FMT_YUVX32:
tpg->color_enc = TGP_COLOR_ENC_YCBCR;
break;
case V4L2_PIX_FMT_YUV420M:
@ -412,6 +414,8 @@ bool tpg_s_fourcc(struct tpg_data *tpg, u32 fourcc)
case V4L2_PIX_FMT_XYUV32:
case V4L2_PIX_FMT_VUYA32:
case V4L2_PIX_FMT_VUYX32:
case V4L2_PIX_FMT_YUVA32:
case V4L2_PIX_FMT_YUVX32:
case V4L2_PIX_FMT_HSV32:
tpg->twopixelsize[0] = 2 * 4;
break;
@ -1376,9 +1380,11 @@ static void gen_twopix(struct tpg_data *tpg,
buf[0][offset + 3] = b_v;
break;
case V4L2_PIX_FMT_RGBX32:
case V4L2_PIX_FMT_YUVX32:
alpha = 0;
fallthrough;
case V4L2_PIX_FMT_RGBA32:
case V4L2_PIX_FMT_YUVA32:
buf[0][offset] = r_y_h;
buf[0][offset + 1] = g_u_s;
buf[0][offset + 2] = b_v;
@ -2402,6 +2408,44 @@ static void tpg_fill_plane_extras(const struct tpg_data *tpg,
((params->sav_eav_f ^ vact) << 1) |
(hact ^ vact ^ params->sav_eav_f);
}
if (tpg->insert_hdmi_video_guard_band) {
unsigned int i;
switch (tpg->fourcc) {
case V4L2_PIX_FMT_BGR24:
case V4L2_PIX_FMT_RGB24:
for (i = 0; i < 3 * 4; i += 3) {
vbuf[i] = 0xab;
vbuf[i + 1] = 0x55;
vbuf[i + 2] = 0xab;
}
break;
case V4L2_PIX_FMT_RGB32:
case V4L2_PIX_FMT_ARGB32:
case V4L2_PIX_FMT_XRGB32:
case V4L2_PIX_FMT_BGRX32:
case V4L2_PIX_FMT_BGRA32:
for (i = 0; i < 4 * 4; i += 4) {
vbuf[i] = 0x00;
vbuf[i + 1] = 0xab;
vbuf[i + 2] = 0x55;
vbuf[i + 3] = 0xab;
}
break;
case V4L2_PIX_FMT_BGR32:
case V4L2_PIX_FMT_XBGR32:
case V4L2_PIX_FMT_ABGR32:
case V4L2_PIX_FMT_RGBX32:
case V4L2_PIX_FMT_RGBA32:
for (i = 0; i < 4 * 4; i += 4) {
vbuf[i] = 0xab;
vbuf[i + 1] = 0x55;
vbuf[i + 2] = 0xab;
vbuf[i + 3] = 0x00;
}
break;
}
}
}
static void tpg_fill_plane_pattern(const struct tpg_data *tpg,

12
drivers/media/common/videobuf2/videobuf2-v4l2.c
View File

@ -638,6 +638,18 @@ int vb2_find_timestamp(const struct vb2_queue *q, u64 timestamp,
}
EXPORT_SYMBOL_GPL(vb2_find_timestamp);
struct vb2_buffer *vb2_find_buffer(struct vb2_queue *q, u64 timestamp)
{
unsigned int i;
for (i = 0; i < q->num_buffers; i++)
if (q->bufs[i]->copied_timestamp &&
q->bufs[i]->timestamp == timestamp)
return vb2_get_buffer(q, i);
return NULL;
}
EXPORT_SYMBOL_GPL(vb2_find_buffer);
/*
* vb2_querybuf() - query video buffer information
* @q: videobuf queue

18
drivers/media/i2c/Kconfig
View File

@ -34,6 +34,19 @@ config VIDEO_APTINA_PLL
config VIDEO_CCS_PLL
tristate
config VIDEO_AR0521
tristate "ON Semiconductor AR0521 sensor support"
depends on I2C && VIDEO_DEV
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
This is a Video4Linux2 sensor driver for the ON Semiconductor
AR0521 camera.
To compile this driver as a module, choose M here: the
module will be called ar0521.
config VIDEO_HI556
tristate "Hynix Hi-556 sensor support"
depends on I2C && VIDEO_DEV
@ -75,8 +88,10 @@ config VIDEO_HI847
config VIDEO_IMX208
tristate "Sony IMX208 sensor support"
depends on I2C && VIDEO_DEV && VIDEO_V4L2_SUBDEV_API
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
help
This is a Video4Linux2 sensor driver for the Sony
IMX208 camera.
@ -1178,6 +1193,7 @@ config VIDEO_ISL7998X
depends on OF_GPIO
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for Intersil ISL7998x analog to MIPI-CSI2 or
BT.656 decoder.

1
drivers/media/i2c/Makefile
View File

@ -19,6 +19,7 @@ obj-$(CONFIG_VIDEO_ADV7842) += adv7842.o
obj-$(CONFIG_VIDEO_AK7375) += ak7375.o
obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
obj-$(CONFIG_VIDEO_APTINA_PLL) += aptina-pll.o
obj-$(CONFIG_VIDEO_AR0521) += ar0521.o
obj-$(CONFIG_VIDEO_BT819) += bt819.o
obj-$(CONFIG_VIDEO_BT856) += bt856.o
obj-$(CONFIG_VIDEO_BT866) += bt866.o

5
drivers/media/i2c/adv7180.c
View File

@ -43,6 +43,7 @@
#define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
#define ADV7182_REG_INPUT_VIDSEL 0x0002
#define ADV7182_REG_INPUT_RESERVED BIT(2)
#define ADV7180_REG_OUTPUT_CONTROL 0x0003
#define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
@ -1060,7 +1061,9 @@ static int adv7182_init(struct adv7180_state *state)
static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
{
return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
/* Failing to set the reserved bit can result in increased video noise */
return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,
(std << 4) | ADV7182_REG_INPUT_RESERVED);
}
enum adv7182_input_type {

2
drivers/media/i2c/adv748x/adv748x.h
View File

@ -417,7 +417,7 @@ int adv748x_write_block(struct adv748x_state *state, int client_page,
static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
{
pad = media_entity_remote_pad(pad);
pad = media_pad_remote_pad_first(pad);
if (!pad)
return NULL;

5
drivers/media/i2c/adv7604.c
View File

@ -2505,9 +2505,8 @@ static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
union hdmi_infoframe frame;
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (adv76xx_read_infoframe(sd, i, &frame))
return;
hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
if (!adv76xx_read_infoframe(sd, i, &frame))
hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
}
}

1061
drivers/media/i2c/ar0521.c Normal file
View File

File diff suppressed because it is too large Load Diff

93
drivers/media/i2c/mt9p031.c
View File

@ -623,12 +623,22 @@ static int mt9p031_get_selection(struct v4l2_subdev *subdev,
{
struct mt9p031 *mt9p031 = to_mt9p031(subdev);
if (sel->target != V4L2_SEL_TGT_CROP)
return -EINVAL;
switch (sel->target) {
case V4L2_SEL_TGT_CROP_BOUNDS:
sel->r.left = MT9P031_COLUMN_START_MIN;
sel->r.top = MT9P031_ROW_START_MIN;
sel->r.width = MT9P031_WINDOW_WIDTH_MAX;
sel->r.height = MT9P031_WINDOW_HEIGHT_MAX;
return 0;
sel->r = *__mt9p031_get_pad_crop(mt9p031, sd_state, sel->pad,
sel->which);
return 0;
case V4L2_SEL_TGT_CROP:
sel->r = *__mt9p031_get_pad_crop(mt9p031, sd_state,
sel->pad, sel->which);
return 0;
default:
return -EINVAL;
}
}
static int mt9p031_set_selection(struct v4l2_subdev *subdev,
@ -682,6 +692,37 @@ static int mt9p031_set_selection(struct v4l2_subdev *subdev,
return 0;
}
static int mt9p031_init_cfg(struct v4l2_subdev *subdev,
struct v4l2_subdev_state *sd_state)
{
struct mt9p031 *mt9p031 = to_mt9p031(subdev);
struct v4l2_mbus_framefmt *format;
struct v4l2_rect *crop;
const int which = sd_state == NULL ? V4L2_SUBDEV_FORMAT_ACTIVE :
V4L2_SUBDEV_FORMAT_TRY;
crop = __mt9p031_get_pad_crop(mt9p031, sd_state, 0, which);
v4l2_subdev_get_try_crop(subdev, sd_state, 0);
crop->left = MT9P031_COLUMN_START_DEF;
crop->top = MT9P031_ROW_START_DEF;
crop->width = MT9P031_WINDOW_WIDTH_DEF;
crop->height = MT9P031_WINDOW_HEIGHT_DEF;
format = __mt9p031_get_pad_format(mt9p031, sd_state, 0, which);
if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
format->code = MEDIA_BUS_FMT_Y12_1X12;
else
format->code = MEDIA_BUS_FMT_SGRBG12_1X12;
format->width = MT9P031_WINDOW_WIDTH_DEF;
format->height = MT9P031_WINDOW_HEIGHT_DEF;
format->field = V4L2_FIELD_NONE;
format->colorspace = V4L2_COLORSPACE_SRGB;
return 0;
}
/* -----------------------------------------------------------------------------
* V4L2 subdev control operations
*/
@ -980,28 +1021,6 @@ static int mt9p031_registered(struct v4l2_subdev *subdev)
static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
{
struct mt9p031 *mt9p031 = to_mt9p031(subdev);
struct v4l2_mbus_framefmt *format;
struct v4l2_rect *crop;
crop = v4l2_subdev_get_try_crop(subdev, fh->state, 0);
crop->left = MT9P031_COLUMN_START_DEF;
crop->top = MT9P031_ROW_START_DEF;
crop->width = MT9P031_WINDOW_WIDTH_DEF;
crop->height = MT9P031_WINDOW_HEIGHT_DEF;
format = v4l2_subdev_get_try_format(subdev, fh->state, 0);
if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
format->code = MEDIA_BUS_FMT_Y12_1X12;
else
format->code = MEDIA_BUS_FMT_SGRBG12_1X12;
format->width = MT9P031_WINDOW_WIDTH_DEF;
format->height = MT9P031_WINDOW_HEIGHT_DEF;
format->field = V4L2_FIELD_NONE;
format->colorspace = V4L2_COLORSPACE_SRGB;
return mt9p031_set_power(subdev, 1);
}
@ -1019,6 +1038,7 @@ static const struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = {
};
static const struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = {
.init_cfg = mt9p031_init_cfg,
.enum_mbus_code = mt9p031_enum_mbus_code,
.enum_frame_size = mt9p031_enum_frame_size,
.get_fmt = mt9p031_get_format,
@ -1166,20 +1186,9 @@ static int mt9p031_probe(struct i2c_client *client,
mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF;
mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF;
mt9p031->crop.left = MT9P031_COLUMN_START_DEF;
mt9p031->crop.top = MT9P031_ROW_START_DEF;
if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
mt9p031->format.code = MEDIA_BUS_FMT_Y12_1X12;
else
mt9p031->format.code = MEDIA_BUS_FMT_SGRBG12_1X12;
mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF;
mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF;
mt9p031->format.field = V4L2_FIELD_NONE;
mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB;
ret = mt9p031_init_cfg(&mt9p031->subdev, NULL);
if (ret)
goto done;
mt9p031->reset = devm_gpiod_get_optional(&client->dev, "reset",
GPIOD_OUT_HIGH);
@ -1214,6 +1223,7 @@ static int mt9p031_remove(struct i2c_client *client)
}
static const struct i2c_device_id mt9p031_id[] = {
{ "mt9p006", MT9P031_MODEL_COLOR },
{ "mt9p031", MT9P031_MODEL_COLOR },
{ "mt9p031m", MT9P031_MODEL_MONOCHROME },
{ }
@ -1222,6 +1232,7 @@ MODULE_DEVICE_TABLE(i2c, mt9p031_id);
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id mt9p031_of_match[] = {
{ .compatible = "aptina,mt9p006", },
{ .compatible = "aptina,mt9p031", },
{ .compatible = "aptina,mt9p031m", },
{ /* sentinel */ },

1650
drivers/media/i2c/ov5640.c
View File

File diff suppressed because it is too large Load Diff

57
drivers/media/i2c/ov5693.c
View File

@ -127,11 +127,16 @@
#define OV5693_LINK_FREQ_419_2MHZ 419200000
#define OV5693_PIXEL_RATE 167680000
/* Miscellaneous */
#define OV5693_NUM_SUPPLIES 2
#define to_ov5693_sensor(x) container_of(x, struct ov5693_device, sd)
static const char * const ov5693_supply_names[] = {
"avdd", /* Analog power */
"dovdd", /* Digital I/O power */
"dvdd", /* Digital circuit power */
};
#define OV5693_NUM_SUPPLIES ARRAY_SIZE(ov5693_supply_names)
struct ov5693_reg {
u32 reg;
u8 val;
@ -152,7 +157,7 @@ struct ov5693_device {
struct gpio_desc *reset;
struct gpio_desc *powerdown;
struct regulator_bulk_data supplies[OV5693_NUM_SUPPLIES];
struct clk *clk;
struct clk *xvclk;
struct ov5693_mode {
struct v4l2_rect crop;
@ -352,11 +357,6 @@ static const s64 link_freq_menu_items[] = {
OV5693_LINK_FREQ_419_2MHZ
};
static const char * const ov5693_supply_names[] = {
"avdd",
"dovdd",
};
static const char * const ov5693_test_pattern_menu[] = {
"Disabled",
"Random Data",
@ -794,7 +794,7 @@ static void ov5693_sensor_powerdown(struct ov5693_device *ov5693)
regulator_bulk_disable(OV5693_NUM_SUPPLIES, ov5693->supplies);
clk_disable_unprepare(ov5693->clk);
clk_disable_unprepare(ov5693->xvclk);
}
static int ov5693_sensor_powerup(struct ov5693_device *ov5693)
@ -804,7 +804,7 @@ static int ov5693_sensor_powerup(struct ov5693_device *ov5693)
gpiod_set_value_cansleep(ov5693->reset, 1);
gpiod_set_value_cansleep(ov5693->powerdown, 1);
ret = clk_prepare_enable(ov5693->clk);
ret = clk_prepare_enable(ov5693->xvclk);
if (ret) {
dev_err(ov5693->dev, "Failed to enable clk\n");
goto fail_power;
@ -1390,7 +1390,7 @@ out_free_bus_cfg:
static int ov5693_probe(struct i2c_client *client)
{
struct ov5693_device *ov5693;
u32 clk_rate;
u32 xvclk_rate;
int ret = 0;
ov5693 = devm_kzalloc(&client->dev, sizeof(*ov5693), GFP_KERNEL);
@ -1408,16 +1408,28 @@ static int ov5693_probe(struct i2c_client *client)
v4l2_i2c_subdev_init(&ov5693->sd, client, &ov5693_ops);
ov5693->clk = devm_clk_get(&client->dev, "xvclk");
if (IS_ERR(ov5693->clk)) {
dev_err(&client->dev, "Error getting clock\n");
return PTR_ERR(ov5693->clk);
ov5693->xvclk = devm_clk_get_optional(&client->dev, "xvclk");
if (IS_ERR(ov5693->xvclk))
return dev_err_probe(&client->dev, PTR_ERR(ov5693->xvclk),
"failed to get xvclk: %ld\n",
PTR_ERR(ov5693->xvclk));
if (ov5693->xvclk) {
xvclk_rate = clk_get_rate(ov5693->xvclk);
} else {
ret = fwnode_property_read_u32(dev_fwnode(&client->dev),
"clock-frequency",
&xvclk_rate);
if (ret) {
dev_err(&client->dev, "can't get clock frequency");
return ret;
}
}
clk_rate = clk_get_rate(ov5693->clk);
if (clk_rate != OV5693_XVCLK_FREQ)
if (xvclk_rate != OV5693_XVCLK_FREQ)
dev_warn(&client->dev, "Found clk freq %u, expected %u\n",
clk_rate, OV5693_XVCLK_FREQ);
xvclk_rate, OV5693_XVCLK_FREQ);
ret = ov5693_configure_gpios(ov5693);
if (ret)
@ -1521,10 +1533,17 @@ static const struct acpi_device_id ov5693_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, ov5693_acpi_match);
static const struct of_device_id ov5693_of_match[] = {
{ .compatible = "ovti,ov5693", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, ov5693_of_match);
static struct i2c_driver ov5693_driver = {
.driver = {
.name = "ov5693",
.acpi_match_table = ov5693_acpi_match,
.of_match_table = ov5693_of_match,
.pm = &ov5693_pm_ops,
},
.probe_new = ov5693_probe,

7
drivers/media/i2c/ov7251.c
View File

@ -934,6 +934,8 @@ static int ov7251_set_power_on(struct device *dev)
ARRAY_SIZE(ov7251_global_init_setting));
if (ret < 0) {
dev_err(ov7251->dev, "error during global init\n");
gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
clk_disable_unprepare(ov7251->xclk);
ov7251_regulators_disable(ov7251);
return ret;
}
@ -1340,7 +1342,7 @@ static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
if (enable) {
ret = pm_runtime_get_sync(ov7251->dev);
if (ret < 0)
goto unlock_out;
goto err_power_down;
ret = ov7251_pll_configure(ov7251);
if (ret) {
@ -1372,12 +1374,11 @@ static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
pm_runtime_put(ov7251->dev);
}
unlock_out:
mutex_unlock(&ov7251->lock);
return ret;
err_power_down:
pm_runtime_put_noidle(ov7251->dev);
pm_runtime_put(ov7251->dev);
mutex_unlock(&ov7251->lock);
return ret;
}

30
drivers/media/i2c/st-mipid02.c
View File

@ -50,6 +50,7 @@
/* Bits definition for MIPID02_MODE_REG2 */
#define MODE_HSYNC_ACTIVE_HIGH BIT(1)
#define MODE_VSYNC_ACTIVE_HIGH BIT(2)
#define MODE_PCLK_SAMPLE_RISING BIT(3)
/* Bits definition for MIPID02_DATA_SELECTION_CTRL */
#define SELECTION_MANUAL_DATA BIT(2)
#define SELECTION_MANUAL_WIDTH BIT(3)
@ -61,9 +62,12 @@ static const u32 mipid02_supported_fmt_codes[] = {
MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10,
MEDIA_BUS_FMT_SBGGR12_1X12, MEDIA_BUS_FMT_SGBRG12_1X12,
MEDIA_BUS_FMT_SGRBG12_1X12, MEDIA_BUS_FMT_SRGGB12_1X12,
MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_BGR888_1X24,
MEDIA_BUS_FMT_YUYV8_1X16, MEDIA_BUS_FMT_YVYU8_1X16,
MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_VYUY8_1X16,
MEDIA_BUS_FMT_RGB565_1X16, MEDIA_BUS_FMT_BGR888_1X24,
MEDIA_BUS_FMT_RGB565_2X8_LE, MEDIA_BUS_FMT_RGB565_2X8_BE,
MEDIA_BUS_FMT_YUYV8_2X8, MEDIA_BUS_FMT_UYVY8_2X8,
MEDIA_BUS_FMT_YUYV8_2X8, MEDIA_BUS_FMT_YVYU8_2X8,
MEDIA_BUS_FMT_UYVY8_2X8, MEDIA_BUS_FMT_VYUY8_2X8,
MEDIA_BUS_FMT_JPEG_1X8
};
@ -130,9 +134,15 @@ static int bpp_from_code(__u32 code)
case MEDIA_BUS_FMT_SGRBG12_1X12:
case MEDIA_BUS_FMT_SRGGB12_1X12:
return 12;
case MEDIA_BUS_FMT_YUYV8_1X16:
case MEDIA_BUS_FMT_YVYU8_1X16:
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_VYUY8_1X16:
case MEDIA_BUS_FMT_RGB565_1X16:
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YVYU8_2X8:
case MEDIA_BUS_FMT_UYVY8_2X8:
case MEDIA_BUS_FMT_VYUY8_2X8:
case MEDIA_BUS_FMT_RGB565_2X8_LE:
case MEDIA_BUS_FMT_RGB565_2X8_BE:
return 16;
@ -161,12 +171,18 @@ static u8 data_type_from_code(__u32 code)
case MEDIA_BUS_FMT_SGRBG12_1X12:
case MEDIA_BUS_FMT_SRGGB12_1X12:
return 0x2c;
case MEDIA_BUS_FMT_YUYV8_1X16:
case MEDIA_BUS_FMT_YVYU8_1X16:
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_VYUY8_1X16:
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YVYU8_2X8:
case MEDIA_BUS_FMT_UYVY8_2X8:
case MEDIA_BUS_FMT_VYUY8_2X8:
return 0x1e;
case MEDIA_BUS_FMT_BGR888_1X24:
return 0x24;
case MEDIA_BUS_FMT_RGB565_1X16:
case MEDIA_BUS_FMT_RGB565_2X8_LE:
case MEDIA_BUS_FMT_RGB565_2X8_BE:
return 0x22;
@ -201,8 +217,16 @@ static __u32 get_fmt_code(__u32 code)
static __u32 serial_to_parallel_code(__u32 serial)
{
if (serial == MEDIA_BUS_FMT_RGB565_1X16)
return MEDIA_BUS_FMT_RGB565_2X8_LE;
if (serial == MEDIA_BUS_FMT_YUYV8_1X16)
return MEDIA_BUS_FMT_YUYV8_2X8;
if (serial == MEDIA_BUS_FMT_YVYU8_1X16)
return MEDIA_BUS_FMT_YVYU8_2X8;
if (serial == MEDIA_BUS_FMT_UYVY8_1X16)
return MEDIA_BUS_FMT_UYVY8_2X8;
if (serial == MEDIA_BUS_FMT_VYUY8_1X16)
return MEDIA_BUS_FMT_VYUY8_2X8;
if (serial == MEDIA_BUS_FMT_BGR888_1X24)
return MEDIA_BUS_FMT_BGR888_3X8;
@ -494,6 +518,8 @@ static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING;
return 0;
}

1
drivers/media/i2c/tda1997x.c
View File

@ -2798,6 +2798,7 @@ err_free_mutex:
cancel_delayed_work(&state->delayed_work_enable_hpd);
mutex_destroy(&state->page_lock);
mutex_destroy(&state->lock);
tda1997x_set_power(state, 0);
err_free_state:
kfree(state);
dev_err(&client->dev, "%s failed: %d\n", __func__, ret);

2
drivers/media/i2c/tvp5150.c
View File

@ -1285,7 +1285,7 @@ static int tvp5150_disable_all_input_links(struct tvp5150 *decoder)
int err;
for (i = 0; i < TVP5150_NUM_PADS - 1; i++) {
connector_pad = media_entity_remote_pad(&decoder->pads[i]);
connector_pad = media_pad_remote_pad_first(&decoder->pads[i]);
if (!connector_pad)
continue;

96
drivers/media/mc/mc-entity.c
View File

@ -9,6 +9,7 @@
*/
#include <linux/bitmap.h>
#include <linux/list.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <media/media-entity.h>
@ -449,7 +450,7 @@ __must_check int __media_pipeline_start(struct media_entity *entity,
bitmap_zero(active, entity->num_pads);
bitmap_fill(has_no_links, entity->num_pads);
list_for_each_entry(link, &entity->links, list) {
for_each_media_entity_data_link(entity, link) {
struct media_pad *pad = link->sink->entity == entity
? link->sink : link->source;
@ -888,7 +889,7 @@ media_entity_find_link(struct media_pad *source, struct media_pad *sink)
{
struct media_link *link;
list_for_each_entry(link, &source->entity->links, list) {
for_each_media_entity_data_link(source->entity, link) {
if (link->source->entity == source->entity &&
link->source->index == source->index &&
link->sink->entity == sink->entity &&
@ -900,11 +901,11 @@ media_entity_find_link(struct media_pad *source, struct media_pad *sink)
}
EXPORT_SYMBOL_GPL(media_entity_find_link);
struct media_pad *media_entity_remote_pad(const struct media_pad *pad)
struct media_pad *media_pad_remote_pad_first(const struct media_pad *pad)
{
struct media_link *link;
list_for_each_entry(link, &pad->entity->links, list) {
for_each_media_entity_data_link(pad->entity, link) {
if (!(link->flags & MEDIA_LNK_FL_ENABLED))
continue;
@ -918,7 +919,77 @@ struct media_pad *media_entity_remote_pad(const struct media_pad *pad)
return NULL;
}
EXPORT_SYMBOL_GPL(media_entity_remote_pad);
EXPORT_SYMBOL_GPL(media_pad_remote_pad_first);
struct media_pad *
media_entity_remote_pad_unique(const struct media_entity *entity,
unsigned int type)
{
struct media_pad *pad = NULL;
struct media_link *link;
list_for_each_entry(link, &entity->links, list) {
struct media_pad *local_pad;
struct media_pad *remote_pad;
if (((link->flags & MEDIA_LNK_FL_LINK_TYPE) !=
MEDIA_LNK_FL_DATA_LINK) ||
!(link->flags & MEDIA_LNK_FL_ENABLED))
continue;
if (type == MEDIA_PAD_FL_SOURCE) {
local_pad = link->sink;
remote_pad = link->source;
} else {
local_pad = link->source;
remote_pad = link->sink;
}
if (local_pad->entity == entity) {
if (pad)
return ERR_PTR(-ENOTUNIQ);
pad = remote_pad;
}
}
if (!pad)
return ERR_PTR(-ENOLINK);
return pad;
}
EXPORT_SYMBOL_GPL(media_entity_remote_pad_unique);
struct media_pad *media_pad_remote_pad_unique(const struct media_pad *pad)
{
struct media_pad *found_pad = NULL;
struct media_link *link;
list_for_each_entry(link, &pad->entity->links, list) {
struct media_pad *remote_pad;
if (!(link->flags & MEDIA_LNK_FL_ENABLED))
continue;
if (link->sink == pad)
remote_pad = link->source;
else if (link->source == pad)
remote_pad = link->sink;
else
continue;
if (found_pad)
return ERR_PTR(-ENOTUNIQ);
found_pad = remote_pad;
}
if (!found_pad)
return ERR_PTR(-ENOLINK);
return found_pad;
}
EXPORT_SYMBOL_GPL(media_pad_remote_pad_unique);
static void media_interface_init(struct media_device *mdev,
struct media_interface *intf,
@ -1051,3 +1122,18 @@ struct media_link *media_create_ancillary_link(struct media_entity *primary,
return link;
}
EXPORT_SYMBOL_GPL(media_create_ancillary_link);
struct media_link *__media_entity_next_link(struct media_entity *entity,
struct media_link *link,
unsigned long link_type)
{
link = link ? list_next_entry(link, list)
: list_first_entry(&entity->links, typeof(*link), list);
list_for_each_entry_from(link, &entity->links, list)
if ((link->flags & MEDIA_LNK_FL_LINK_TYPE) == link_type)
return link;
return NULL;
}
EXPORT_SYMBOL_GPL(__media_entity_next_link);

2
drivers/media/pci/cx18/cx18-av-core.c
View File

@ -180,7 +180,7 @@ static void cx18_av_initialize(struct v4l2_subdev *sd)
*/
cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000);
/* Setup the Video and and Aux/Audio PLLs */
/* Setup the Video and Aux/Audio PLLs */
cx18_av_init(cx);
/* set video to auto-detect */

22
drivers/media/pci/cx88/cx88-core.c
View File

@ -618,12 +618,24 @@ EXPORT_SYMBOL(cx88_reset);
static inline unsigned int norm_swidth(v4l2_std_id norm)
{
return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M))
return 754;
if (norm & V4L2_STD_PAL_Nc)
return 745;
return 922;
}
static inline unsigned int norm_hdelay(v4l2_std_id norm)
{
return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 135 : 186;
if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M))
return 135;
if (norm & V4L2_STD_PAL_Nc)
return 149;
return 186;
}
static inline unsigned int norm_vdelay(v4l2_std_id norm)
@ -636,7 +648,7 @@ static inline unsigned int norm_fsc8(v4l2_std_id norm)
if (norm & V4L2_STD_PAL_M)
return 28604892; // 3.575611 MHz
if (norm & (V4L2_STD_PAL_Nc))
if (norm & V4L2_STD_PAL_Nc)
return 28656448; // 3.582056 MHz
if (norm & V4L2_STD_NTSC) // All NTSC/M and variants
@ -841,8 +853,8 @@ static int set_tvaudio(struct cx88_core *core)
} else if (V4L2_STD_SECAM_DK & norm) {
core->tvaudio = WW_DK;
} else if ((V4L2_STD_NTSC_M & norm) ||
(V4L2_STD_PAL_M & norm)) {
} else if ((V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL_Nc) &
norm) {
core->tvaudio = WW_BTSC;
} else if (V4L2_STD_NTSC_M_JP & norm) {

9
drivers/media/pci/ddbridge/ddbridge-ci.c
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Marcus Metzler <mocm@metzlerbros.de>
* Ralph Metzler <rjkm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "ddbridge.h"

9
drivers/media/pci/ddbridge/ddbridge-ci.h
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Marcus Metzler <mocm@metzlerbros.de>
* Ralph Metzler <rjkm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DDBRIDGE_CI_H__

9
drivers/media/pci/ddbridge/ddbridge-core.c
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Marcus Metzler <mocm@metzlerbros.de>
* Ralph Metzler <rjkm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>

9
drivers/media/pci/ddbridge/ddbridge-hw.c
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "ddbridge.h"

11
drivers/media/pci/ddbridge/ddbridge-hw.h
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DDBRIDGE_HW_H_
@ -40,4 +31,4 @@ struct ddb_device_id {
const struct ddb_info *get_ddb_info(u16 vendor, u16 device,
u16 subvendor, u16 subdevice);
#endif /* _DDBRIDGE_HW_H */
#endif /* _DDBRIDGE_HW_H_ */

9
drivers/media/pci/ddbridge/ddbridge-i2c.c
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>

9
drivers/media/pci/ddbridge/ddbridge-i2c.h
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DDBRIDGE_I2C_H__

9
drivers/media/pci/ddbridge/ddbridge-io.h
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DDBRIDGE_IO_H__

9
drivers/media/pci/ddbridge/ddbridge-main.c
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

9
drivers/media/pci/ddbridge/ddbridge-max.c
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>

11
drivers/media/pci/ddbridge/ddbridge-max.h
View File

@ -5,15 +5,6 @@
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DDBRIDGE_MAX_H_
@ -27,4 +18,4 @@ int ddb_lnb_init_fmode(struct ddb *dev, struct ddb_link *link, u32 fm);
int ddb_fe_attach_mxl5xx(struct ddb_input *input);
int ddb_fe_attach_mci(struct ddb_input *input, u32 type);
#endif /* _DDBRIDGE_MAX_H */
#endif /* _DDBRIDGE_MAX_H_ */

9
drivers/media/pci/ddbridge/ddbridge-mci.c
View File

@ -5,15 +5,6 @@
* Copyright (C) 2017-2018 Digital Devices GmbH
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "ddbridge.h"

9
drivers/media/pci/ddbridge/ddbridge-mci.h
View File

@ -5,15 +5,6 @@
* Copyright (C) 2017-2018 Digital Devices GmbH
* Marcus Metzler <mocm@metzlerbros.de>
* Ralph Metzler <rjkm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DDBRIDGE_MCI_H_

9
drivers/media/pci/ddbridge/ddbridge-regs.h
View File

@ -3,15 +3,6 @@
* ddbridge-regs.h: Digital Devices PCIe bridge driver
*
* Copyright (C) 2010-2017 Digital Devices GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DDBRIDGE_REGS_H__

9
drivers/media/pci/ddbridge/ddbridge-sx8.c
View File

@ -5,15 +5,6 @@
* Copyright (C) 2018 Digital Devices GmbH
* Marcus Metzler <mocm@metzlerbros.de>
* Ralph Metzler <rjkm@metzlerbros.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "ddbridge.h"

11
drivers/media/pci/ddbridge/ddbridge.h
View File

@ -4,15 +4,6 @@
*
* Copyright (C) 2010-2017 Digital Devices GmbH
* Ralph Metzler <rmetzler@digitaldevices.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DDBRIDGE_H_
@ -379,4 +370,4 @@ void ddb_unmap(struct ddb *dev);
int ddb_exit_ddbridge(int stage, int error);
int ddb_init_ddbridge(void);
#endif /* DDBRIDGE_H */
#endif /* _DDBRIDGE_H_ */

2
drivers/media/pci/intel/ipu3/ipu3-cio2-main.c
View File

@ -1323,7 +1323,7 @@ static int cio2_video_link_validate(struct media_link *link)
struct v4l2_subdev_format source_fmt;
int ret;
if (!media_entity_remote_pad(entity->pads)) {
if (!media_pad_remote_pad_first(entity->pads)) {
dev_info(dev, "video node %s pad not connected\n", vd->name);
return -ENOTCONN;
}

2
drivers/media/pci/saa7164/saa7164-api.c
View File

@ -801,7 +801,7 @@ int saa7164_api_read_eeprom(struct saa7164_dev *dev, u8 *buf, int buflen)
if (buflen < 128)
return -ENOMEM;
/* Assumption: Hauppauge eeprom is at 0xa0 on on bus 0 */
/* Assumption: Hauppauge eeprom is at 0xa0 on bus 0 */
/* TODO: Pull the details from the boards struct */
return saa7164_api_i2c_read(&dev->i2c_bus[0], 0xa0 >> 1, sizeof(reg),
&reg[0], 128, buf);

2
drivers/media/pci/sta2x11/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config STA2X11_VIP
tristate "STA2X11 VIP Video For Linux"
depends on PCI && VIDEO_DEV && VIRT_TO_BUS && I2C
depends on PCI && VIDEO_DEV && I2C
depends on STA2X11 || COMPILE_TEST
select GPIOLIB if MEDIA_SUBDRV_AUTOSELECT
select VIDEO_ADV7180 if MEDIA_SUBDRV_AUTOSELECT

30
drivers/media/pci/tw5864/tw5864-core.c
View File

@ -254,9 +254,9 @@ static int tw5864_initdev(struct pci_dev *pci_dev,
/* pci init */
dev->pci = pci_dev;
err = pci_enable_device(pci_dev);
err = pcim_enable_device(pci_dev);
if (err) {
dev_err(&dev->pci->dev, "pci_enable_device() failed\n");
dev_err(&dev->pci->dev, "pcim_enable_device() failed\n");
goto unreg_v4l2;
}
@ -265,21 +265,16 @@ static int tw5864_initdev(struct pci_dev *pci_dev,
err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32));
if (err) {
dev_err(&dev->pci->dev, "32 bit PCI DMA is not supported\n");
goto disable_pci;
goto unreg_v4l2;
}
/* get mmio */
err = pci_request_regions(pci_dev, dev->name);
err = pcim_iomap_regions(pci_dev, BIT(0), dev->name);
if (err) {
dev_err(&dev->pci->dev, "Cannot request regions for MMIO\n");
goto disable_pci;
}
dev->mmio = pci_ioremap_bar(pci_dev, 0);
if (!dev->mmio) {
err = -EIO;
dev_err(&dev->pci->dev, "can't ioremap() MMIO memory\n");
goto release_mmio;
goto unreg_v4l2;
}
dev->mmio = pcim_iomap_table(pci_dev)[0];
spin_lock_init(&dev->slock);
@ -291,7 +286,7 @@ static int tw5864_initdev(struct pci_dev *pci_dev,
err = tw5864_video_init(dev, video_nr);
if (err)
goto unmap_mmio;
goto unreg_v4l2;
/* get irq */
err = devm_request_irq(&pci_dev->dev, pci_dev->irq, tw5864_isr,
@ -308,12 +303,6 @@ static int tw5864_initdev(struct pci_dev *pci_dev,
fini_video:
tw5864_video_fini(dev);
unmap_mmio:
iounmap(dev->mmio);
release_mmio:
pci_release_regions(pci_dev);
disable_pci:
pci_disable_device(pci_dev);
unreg_v4l2:
v4l2_device_unregister(&dev->v4l2_dev);
return err;
@ -331,11 +320,6 @@ static void tw5864_finidev(struct pci_dev *pci_dev)
/* unregister */
tw5864_video_fini(dev);
/* release resources */
iounmap(dev->mmio);
pci_release_regions(pci_dev);
pci_disable_device(pci_dev);
v4l2_device_unregister(&dev->v4l2_dev);
}

21
drivers/media/pci/tw686x/tw686x-core.c
View File

@ -315,13 +315,6 @@ static int tw686x_probe(struct pci_dev *pci_dev,
spin_lock_init(&dev->lock);
err = request_irq(pci_dev->irq, tw686x_irq, IRQF_SHARED,
dev->name, dev);
if (err < 0) {
dev_err(&pci_dev->dev, "unable to request interrupt\n");
goto iounmap;
}
timer_setup(&dev->dma_delay_timer, tw686x_dma_delay, 0);
/*
@ -333,18 +326,26 @@ static int tw686x_probe(struct pci_dev *pci_dev,
err = tw686x_video_init(dev);
if (err) {
dev_err(&pci_dev->dev, "can't register video\n");
goto free_irq;
goto iounmap;
}
err = tw686x_audio_init(dev);
if (err)
dev_warn(&pci_dev->dev, "can't register audio\n");
err = request_irq(pci_dev->irq, tw686x_irq, IRQF_SHARED,
dev->name, dev);
if (err < 0) {
dev_err(&pci_dev->dev, "unable to request interrupt\n");
goto tw686x_free;
}
pci_set_drvdata(pci_dev, dev);
return 0;
free_irq:
free_irq(pci_dev->irq, dev);
tw686x_free:
tw686x_video_free(dev);
tw686x_audio_free(dev);
iounmap:
pci_iounmap(pci_dev, dev->mmio);
free_region:

4
drivers/media/pci/tw686x/tw686x-video.c
View File

@ -1280,8 +1280,10 @@ int tw686x_video_init(struct tw686x_dev *dev)
video_set_drvdata(vdev, vc);
err = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
if (err < 0)
if (err < 0) {
video_device_release(vdev);
goto error;
}
vc->num = vdev->num;
}

50
drivers/media/platform/amphion/vdec.c
View File

@ -63,6 +63,7 @@ struct vdec_t {
bool is_source_changed;
u32 source_change;
u32 drain;
bool aborting;
};
static const struct vpu_format vdec_formats[] = {
@ -104,7 +105,6 @@ static const struct vpu_format vdec_formats[] = {
.pixfmt = V4L2_PIX_FMT_VC1_ANNEX_L,
.num_planes = 1,
.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION
},
{
.pixfmt = V4L2_PIX_FMT_MPEG2,
@ -178,16 +178,6 @@ static int vdec_ctrl_init(struct vpu_inst *inst)
return 0;
}
static void vdec_set_last_buffer_dequeued(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
if (vdec->eos_received) {
if (!vpu_set_last_buffer_dequeued(inst))
vdec->eos_received--;
}
}
static void vdec_handle_resolution_change(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
@ -234,6 +224,21 @@ static int vdec_update_state(struct vpu_inst *inst, enum vpu_codec_state state,
return 0;
}
static void vdec_set_last_buffer_dequeued(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
return;
if (vdec->eos_received) {
if (!vpu_set_last_buffer_dequeued(inst)) {
vdec->eos_received--;
vdec_update_state(inst, VPU_CODEC_STATE_DRAIN, 0);
}
}
}
static int vdec_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
{
strscpy(cap->driver, "amphion-vpu", sizeof(cap->driver));
@ -493,6 +498,8 @@ static int vdec_drain(struct vpu_inst *inst)
static int vdec_cmd_start(struct vpu_inst *inst)
{
struct vdec_t *vdec = inst->priv;
switch (inst->state) {
case VPU_CODEC_STATE_STARTED:
case VPU_CODEC_STATE_DRAIN:
@ -503,6 +510,8 @@ static int vdec_cmd_start(struct vpu_inst *inst)
break;
}
vpu_process_capture_buffer(inst);
if (vdec->eos_received)
vdec_set_last_buffer_dequeued(inst);
return 0;
}
@ -731,6 +740,7 @@ static void vdec_stop_done(struct vpu_inst *inst)
vdec->eos_received = 0;
vdec->is_source_changed = false;
vdec->source_change = 0;
inst->total_input_count = 0;
vpu_inst_unlock(inst);
}
@ -939,6 +949,9 @@ static int vdec_response_frame(struct vpu_inst *inst, struct vb2_v4l2_buffer *vb
if (inst->state != VPU_CODEC_STATE_ACTIVE)
return -EINVAL;
if (vdec->aborting)
return -EINVAL;
if (!vdec->req_frame_count)
return -EINVAL;
@ -1048,6 +1061,8 @@ static void vdec_clear_slots(struct vpu_inst *inst)
vpu_buf = vdec->slots[i];
vbuf = &vpu_buf->m2m_buf.vb;
vpu_trace(inst->dev, "clear slot %d\n", i);
vdec_response_fs_release(inst, i, vpu_buf->tag);
vdec_recycle_buffer(inst, vbuf);
vdec->slots[i]->state = VPU_BUF_STATE_IDLE;
vdec->slots[i] = NULL;
@ -1203,7 +1218,6 @@ static void vdec_event_eos(struct vpu_inst *inst)
vdec->eos_received++;
vdec->fixed_fmt = false;
inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP;
vdec_update_state(inst, VPU_CODEC_STATE_DRAIN, 0);
vdec_set_last_buffer_dequeued(inst);
vpu_inst_unlock(inst);
}
@ -1310,6 +1324,8 @@ static void vdec_abort(struct vpu_inst *inst)
int ret;
vpu_trace(inst->dev, "[%d] state = %d\n", inst->id, inst->state);
vdec->aborting = true;
vpu_iface_add_scode(inst, SCODE_PADDING_ABORT);
vdec->params.end_flag = 1;
vpu_iface_set_decode_params(inst, &vdec->params, 1);
@ -1333,6 +1349,7 @@ static void vdec_abort(struct vpu_inst *inst)
vdec->decoded_frame_count = 0;
vdec->display_frame_count = 0;
vdec->sequence = 0;
vdec->aborting = false;
}
static void vdec_stop(struct vpu_inst *inst, bool free)
@ -1369,8 +1386,7 @@ static void vdec_cleanup(struct vpu_inst *inst)
return;
vdec = inst->priv;
if (vdec)
vfree(vdec);
vfree(vdec);
inst->priv = NULL;
vfree(inst);
}
@ -1480,10 +1496,10 @@ static int vdec_stop_session(struct vpu_inst *inst, u32 type)
vdec_update_state(inst, VPU_CODEC_STATE_SEEK, 0);
vdec->drain = 0;
} else {
if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) {
vdec_abort(inst);
vdec->eos_received = 0;
vdec->eos_received = 0;
}
vdec_clear_slots(inst);
}

3
drivers/media/platform/amphion/venc.c
View File

@ -919,8 +919,7 @@ static void venc_cleanup(struct vpu_inst *inst)
return;
venc = inst->priv;
if (venc)
vfree(venc);
vfree(venc);
inst->priv = NULL;
vfree(inst);
}

1
drivers/media/platform/amphion/vpu.h
View File

@ -258,6 +258,7 @@ struct vpu_inst {
struct vpu_format cap_format;
u32 min_buffer_cap;
u32 min_buffer_out;
u32 total_input_count;
struct v4l2_rect crop;
u32 colorspace;

3
drivers/media/platform/amphion/vpu_cmds.c
View File

@ -117,8 +117,7 @@ static void vpu_free_cmd(struct vpu_cmd_t *cmd)
{
if (!cmd)
return;
if (cmd->pkt)
vfree(cmd->pkt);
vfree(cmd->pkt);
vfree(cmd);
}

18
drivers/media/platform/amphion/vpu_core.c
View File

@ -257,14 +257,8 @@ static int vpu_core_register(struct device *dev, struct vpu_core *core)
}
list_add_tail(&core->list, &vpu->cores);
vpu_core_get_vpu(core);
if (vpu_iface_get_power_state(core))
ret = vpu_core_restore(core);
if (ret)
goto error;
return 0;
error:
if (core->msg_buffer) {
@ -362,7 +356,10 @@ struct vpu_core *vpu_request_core(struct vpu_dev *vpu, enum vpu_core_type type)
pm_runtime_resume_and_get(core->dev);
if (core->state == VPU_CORE_DEINIT) {
ret = vpu_core_boot(core, true);
if (vpu_iface_get_power_state(core))
ret = vpu_core_restore(core);
else
ret = vpu_core_boot(core, true);
if (ret) {
pm_runtime_put_sync(core->dev);
mutex_unlock(&core->lock);
@ -455,8 +452,13 @@ int vpu_inst_unregister(struct vpu_inst *inst)
}
vpu_core_check_hang(core);
if (core->state == VPU_CORE_HANG && !core->instance_mask) {
int err;
dev_info(core->dev, "reset hang core\n");
if (!vpu_core_sw_reset(core)) {
mutex_unlock(&core->lock);
err = vpu_core_sw_reset(core);
mutex_lock(&core->lock);
if (!err) {
core->state = VPU_CORE_ACTIVE;
core->hang_mask = 0;
}

2
drivers/media/platform/amphion/vpu_dbg.c
View File

@ -27,7 +27,7 @@ struct print_buf_desc {
u32 bytes;
u32 read;
u32 write;
char buffer[0];
char buffer[];
};
static char *vb2_stat_name[] = {

20
drivers/media/platform/amphion/vpu_malone.c
View File

@ -309,6 +309,7 @@ struct malone_padding_scode {
struct malone_fmt_mapping {
u32 pixelformat;
enum vpu_malone_format malone_format;
u32 is_disabled;
};
struct malone_scode_t {
@ -568,6 +569,8 @@ static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
u32 i;
for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
if (fmt_mappings[i].is_disabled)
continue;
if (pixelformat == fmt_mappings[i].pixelformat)
return fmt_mappings[i].malone_format;
}
@ -575,6 +578,19 @@ static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
return MALONE_FMT_NULL;
}
bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt)
{
if (!vpu_imx8q_check_fmt(type, pixelfmt))
return false;
if (pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128)
return true;
if (vpu_malone_format_remap(pixelfmt) == MALONE_FMT_NULL)
return false;
return true;
}
static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
u32 instance,
enum vpu_malone_format malone_format)
@ -610,6 +626,8 @@ static int vpu_malone_set_params(struct vpu_shared_addr *shared,
enum vpu_malone_format malone_format;
malone_format = vpu_malone_format_remap(params->codec_format);
if (WARN_ON(malone_format == MALONE_FMT_NULL))
return -EINVAL;
iface->udata_buffer[instance].base = params->udata.base;
iface->udata_buffer[instance].slot_size = params->udata.size;
@ -1296,6 +1314,8 @@ static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)
int size = 0;
u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];
if (scode->inst->total_input_count)
return 0;
scode->need_data = 0;
ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr));

1
drivers/media/platform/amphion/vpu_malone.h
View File

@ -40,5 +40,6 @@ int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance);
int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance);
int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance);
u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared);
bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt);
#endif

7
drivers/media/platform/amphion/vpu_msgs.c
View File

@ -150,7 +150,12 @@ static void vpu_session_handle_eos(struct vpu_inst *inst, struct vpu_rpc_event *
static void vpu_session_handle_error(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
{
dev_err(inst->dev, "unsupported stream\n");
char *str = (char *)pkt->data;
if (strlen(str))
dev_err(inst->dev, "instance %d firmware error : %s\n", inst->id, str);
else
dev_err(inst->dev, "instance %d is unsupported stream\n", inst->id);
call_void_vop(inst, event_notify, VPU_MSG_ID_UNSUPPORTED, NULL);
vpu_v4l2_set_error(inst);
}

2
drivers/media/platform/amphion/vpu_rpc.c
View File

@ -195,7 +195,7 @@ static struct vpu_iface_ops imx8q_rpc_ops[] = {
},
[VPU_CORE_TYPE_DEC] = {
.check_codec = vpu_imx8q_check_codec,
.check_fmt = vpu_imx8q_check_fmt,
.check_fmt = vpu_malone_check_fmt,
.boot_core = vpu_imx8q_boot_core,
.get_power_state = vpu_imx8q_get_power_state,
.on_firmware_loaded = vpu_imx8q_on_firmware_loaded,

7
drivers/media/platform/amphion/vpu_rpc.h
View File

@ -312,11 +312,16 @@ static inline int vpu_iface_input_frame(struct vpu_inst *inst,
struct vb2_buffer *vb)
{
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
int ret;
if (!ops || !ops->input_frame)
return -EINVAL;
return ops->input_frame(inst->core->iface, inst, vb);
ret = ops->input_frame(inst->core->iface, inst, vb);
if (ret < 0)
return ret;
inst->total_input_count++;
return ret;
}
static inline int vpu_iface_config_memory_resource(struct vpu_inst *inst,

6
drivers/media/platform/amphion/vpu_v4l2.c
View File

@ -500,10 +500,12 @@ static int vpu_vb2_start_streaming(struct vb2_queue *q, unsigned int count)
fmt->sizeimage[1], fmt->bytesperline[1],
fmt->sizeimage[2], fmt->bytesperline[2],
q->num_buffers);
call_void_vop(inst, start, q->type);
vb2_clear_last_buffer_dequeued(q);
ret = call_vop(inst, start, q->type);
if (ret)
vpu_vb2_buffers_return(inst, q->type, VB2_BUF_STATE_QUEUED);
return 0;
return ret;
}
static void vpu_vb2_stop_streaming(struct vb2_queue *q)

4
drivers/media/platform/atmel/Kconfig
View File

@ -20,12 +20,14 @@ config VIDEO_ATMEL_ISC
config VIDEO_ATMEL_XISC
tristate "ATMEL eXtended Image Sensor Controller (XISC) support"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV && COMMON_CLK && VIDEO_V4L2_SUBDEV_API
depends on VIDEO_DEV && COMMON_CLK
depends on ARCH_AT91 || COMPILE_TEST
select VIDEOBUF2_DMA_CONTIG
select REGMAP_MMIO
select V4L2_FWNODE
select VIDEO_ATMEL_ISC_BASE
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
help
This module makes the ATMEL eXtended Image Sensor Controller
available as a v4l2 device.

20
drivers/media/platform/atmel/atmel-isc-base.c
View File

@ -132,12 +132,9 @@ static int isc_buffer_prepare(struct vb2_buffer *vb)
return 0;
}
static void isc_start_dma(struct isc_device *isc)
static void isc_crop_pfe(struct isc_device *isc)
{
struct regmap *regmap = isc->regmap;
u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
u32 dctrl_dview;
dma_addr_t addr0;
u32 h, w;
h = isc->fmt.fmt.pix.height;
@ -172,6 +169,14 @@ static void isc_start_dma(struct isc_device *isc)
regmap_update_bits(regmap, ISC_PFE_CFG0,
ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
}
static void isc_start_dma(struct isc_device *isc)
{
struct regmap *regmap = isc->regmap;
u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
u32 dctrl_dview;
dma_addr_t addr0;
addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
@ -369,6 +374,7 @@ static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
struct isc_buffer, list);
list_del(&isc->cur_frm->list);
isc_crop_pfe(isc);
isc_start_dma(isc);
spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
@ -1466,7 +1472,7 @@ static void isc_awb_work(struct work_struct *w)
if (isc->stop) {
mutex_unlock(&isc->awb_mutex);
return;
};
}
isc_update_profile(isc);
@ -1525,10 +1531,6 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
else
ctrls->awb = ISC_WB_NONE;
/* we did not configure ISC yet */
if (!isc->config.sd_format)
break;
/* configure the controls with new values from v4l2 */
if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;

2
drivers/media/platform/atmel/atmel-sama7g5-isc.c
View File

@ -591,11 +591,13 @@ static const struct dev_pm_ops microchip_xisc_dev_pm_ops = {
SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL)
};
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id microchip_xisc_of_match[] = {
{ .compatible = "microchip,sama7g5-isc" },
{ }
};
MODULE_DEVICE_TABLE(of, microchip_xisc_of_match);
#endif
static struct platform_driver microchip_xisc_driver = {
.probe = microchip_xisc_probe,

3
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
View File

@ -1369,6 +1369,9 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
jpeg->vdev->device_caps = V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_M2M_MPLANE;
if (of_get_property(pdev->dev.of_node, "dma-ranges", NULL))
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));
ret = video_register_device(jpeg->vdev, VFL_TYPE_VIDEO, -1);
if (ret) {
v4l2_err(&jpeg->v4l2_dev, "Failed to register video device\n");

2
drivers/media/platform/mediatek/mdp/mtk_mdp_ipi.h
View File

@ -40,12 +40,14 @@ struct mdp_ipi_init {
* @ipi_id : IPI_MDP
* @ap_inst : AP mtk_mdp_vpu address
* @vpu_inst_addr : VPU MDP instance address
* @padding : Alignment padding
*/
struct mdp_ipi_comm {
uint32_t msg_id;
uint32_t ipi_id;
uint64_t ap_inst;
uint32_t vpu_inst_addr;
uint32_t padding;
};
/**

135
drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c
View File

@ -35,6 +35,44 @@ mtk_vdec_find_format(struct v4l2_format *f,
return NULL;
}
static bool mtk_vdec_get_cap_fmt(struct mtk_vcodec_ctx *ctx, int format_index)
{
const struct mtk_vcodec_dec_pdata *dec_pdata = ctx->dev->vdec_pdata;
const struct mtk_video_fmt *fmt;
struct mtk_q_data *q_data;
int num_frame_count = 0, i;
bool ret = true;
for (i = 0; i < *dec_pdata->num_formats; i++) {
if (dec_pdata->vdec_formats[i].type != MTK_FMT_FRAME)
continue;
num_frame_count++;
}
if (num_frame_count == 1)
return true;
fmt = &dec_pdata->vdec_formats[format_index];
q_data = &ctx->q_data[MTK_Q_DATA_SRC];
switch (q_data->fmt->fourcc) {
case V4L2_PIX_FMT_VP8_FRAME:
if (fmt->fourcc == V4L2_PIX_FMT_MM21)
ret = true;
break;
case V4L2_PIX_FMT_H264_SLICE:
case V4L2_PIX_FMT_VP9_FRAME:
if (fmt->fourcc == V4L2_PIX_FMT_MM21)
ret = false;
break;
default:
ret = true;
break;
}
return ret;
}
static struct mtk_q_data *mtk_vdec_get_q_data(struct mtk_vcodec_ctx *ctx,
enum v4l2_buf_type type)
{
@ -112,8 +150,6 @@ void mtk_vcodec_dec_set_default_params(struct mtk_vcodec_ctx *ctx)
{
struct mtk_q_data *q_data;
ctx->dev->vdec_pdata->init_vdec_params(ctx);
ctx->m2m_ctx->q_lock = &ctx->dev->dev_mutex;
ctx->fh.m2m_ctx = ctx->m2m_ctx;
ctx->fh.ctrl_handler = &ctx->ctrl_hdl;
@ -141,15 +177,6 @@ void mtk_vcodec_dec_set_default_params(struct mtk_vcodec_ctx *ctx)
q_data->coded_height = DFT_CFG_HEIGHT;
q_data->fmt = ctx->dev->vdec_pdata->default_cap_fmt;
q_data->field = V4L2_FIELD_NONE;
ctx->max_width = MTK_VDEC_MAX_W;
ctx->max_height = MTK_VDEC_MAX_H;
v4l_bound_align_image(&q_data->coded_width,
MTK_VDEC_MIN_W,
ctx->max_width, 4,
&q_data->coded_height,
MTK_VDEC_MIN_H,
ctx->max_height, 5, 6);
q_data->sizeimage[0] = q_data->coded_width * q_data->coded_height;
q_data->bytesperline[0] = q_data->coded_width;
@ -185,12 +212,34 @@ static int vidioc_vdec_dqbuf(struct file *file, void *priv,
return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
}
static int mtk_vcodec_dec_get_chip_name(void *priv)
{
struct mtk_vcodec_ctx *ctx = fh_to_ctx(priv);
struct device *dev = &ctx->dev->plat_dev->dev;
if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-dec"))
return 8173;
else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-dec"))
return 8183;
else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-dec"))
return 8192;
else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-dec"))
return 8195;
else if (of_device_is_compatible(dev->of_node, "mediatek,mt8186-vcodec-dec"))
return 8186;
else
return 8173;
}
static int vidioc_vdec_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->driver, MTK_VCODEC_DEC_NAME, sizeof(cap->driver));
strscpy(cap->bus_info, MTK_PLATFORM_STR, sizeof(cap->bus_info));
strscpy(cap->card, MTK_PLATFORM_STR, sizeof(cap->card));
struct mtk_vcodec_ctx *ctx = fh_to_ctx(priv);
struct device *dev = &ctx->dev->plat_dev->dev;
int platform_name = mtk_vcodec_dec_get_chip_name(priv);
strscpy(cap->driver, dev->driver->name, sizeof(cap->driver));
snprintf(cap->card, sizeof(cap->card), "MT%d video decoder", platform_name);
return 0;
}
@ -198,6 +247,11 @@ static int vidioc_vdec_querycap(struct file *file, void *priv,
static int vidioc_vdec_subscribe_evt(struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub)
{
struct mtk_vcodec_ctx *ctx = fh_to_ctx(fh);
if (ctx->dev->vdec_pdata->uses_stateless_api)
return v4l2_ctrl_subscribe_event(fh, sub);
switch (sub->type) {
case V4L2_EVENT_EOS:
return v4l2_event_subscribe(fh, sub, 2, NULL);
@ -212,13 +266,18 @@ static int vidioc_try_fmt(struct mtk_vcodec_ctx *ctx, struct v4l2_format *f,
const struct mtk_video_fmt *fmt)
{
struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
const struct v4l2_frmsize_stepwise *frmsize;
pix_fmt_mp->field = V4L2_FIELD_NONE;
pix_fmt_mp->width =
clamp(pix_fmt_mp->width, MTK_VDEC_MIN_W, ctx->max_width);
pix_fmt_mp->height =
clamp(pix_fmt_mp->height, MTK_VDEC_MIN_H, ctx->max_height);
/* Always apply frame size constraints from the coded side */
if (V4L2_TYPE_IS_OUTPUT(f->type))
frmsize = &fmt->frmsize;
else
frmsize = &ctx->q_data[MTK_Q_DATA_SRC].fmt->frmsize;
pix_fmt_mp->width = clamp(pix_fmt_mp->width, MTK_VDEC_MIN_W, frmsize->max_width);
pix_fmt_mp->height = clamp(pix_fmt_mp->height, MTK_VDEC_MIN_H, frmsize->max_height);
if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
pix_fmt_mp->num_planes = 1;
@ -234,18 +293,15 @@ static int vidioc_try_fmt(struct mtk_vcodec_ctx *ctx, struct v4l2_format *f,
*/
tmp_w = pix_fmt_mp->width;
tmp_h = pix_fmt_mp->height;
v4l_bound_align_image(&pix_fmt_mp->width,
MTK_VDEC_MIN_W,
ctx->max_width, 6,
&pix_fmt_mp->height,
MTK_VDEC_MIN_H,
ctx->max_height, 6, 9);
v4l_bound_align_image(&pix_fmt_mp->width, MTK_VDEC_MIN_W, frmsize->max_width, 6,
&pix_fmt_mp->height, MTK_VDEC_MIN_H, frmsize->max_height, 6,
9);
if (pix_fmt_mp->width < tmp_w &&
(pix_fmt_mp->width + 64) <= ctx->max_width)
(pix_fmt_mp->width + 64) <= frmsize->max_width)
pix_fmt_mp->width += 64;
if (pix_fmt_mp->height < tmp_h &&
(pix_fmt_mp->height + 64) <= ctx->max_height)
(pix_fmt_mp->height + 64) <= frmsize->max_height)
pix_fmt_mp->height += 64;
mtk_v4l2_debug(0,
@ -435,13 +491,6 @@ static int vidioc_vdec_s_fmt(struct file *file, void *priv,
if (fmt == NULL)
return -EINVAL;
if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED) &&
fmt->fourcc != V4L2_PIX_FMT_VP8_FRAME) {
mtk_v4l2_debug(3, "4K is enabled");
ctx->max_width = VCODEC_DEC_4K_CODED_WIDTH;
ctx->max_height = VCODEC_DEC_4K_CODED_HEIGHT;
}
q_data->fmt = fmt;
vidioc_try_fmt(ctx, f, q_data->fmt);
if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
@ -526,15 +575,17 @@ static int vidioc_enum_framesizes(struct file *file, void *priv,
if (fsize->index != 0)
return -EINVAL;
for (i = 0; i < *dec_pdata->num_framesizes; ++i) {
if (fsize->pixel_format != dec_pdata->vdec_framesizes[i].fourcc)
for (i = 0; i < *dec_pdata->num_formats; i++) {
if (fsize->pixel_format != dec_pdata->vdec_formats[i].fourcc)
continue;
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
fsize->stepwise = dec_pdata->vdec_framesizes[i].stepwise;
/* Only coded formats have frame sizes set */
if (!dec_pdata->vdec_formats[i].frmsize.max_width)
return -ENOTTY;
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
fsize->stepwise = dec_pdata->vdec_formats[i].frmsize;
fsize->stepwise.max_width = ctx->max_width;
fsize->stepwise.max_height = ctx->max_height;
mtk_v4l2_debug(1, "%x, %d %d %d %d %d %d",
ctx->dev->dec_capability,
fsize->stepwise.min_width,
@ -566,6 +617,9 @@ static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, void *priv,
dec_pdata->vdec_formats[i].type != MTK_FMT_FRAME)
continue;
if (!output_queue && !mtk_vdec_get_cap_fmt(ctx, i))
continue;
if (j == f->index)
break;
++j;
@ -735,6 +789,7 @@ int vb2ops_vdec_buf_prepare(struct vb2_buffer *vb)
mtk_v4l2_err("data will not fit into plane %d (%lu < %d)",
i, vb2_plane_size(vb, i),
q_data->sizeimage[i]);
return -EINVAL;
}
if (!V4L2_TYPE_IS_OUTPUT(vb->type))
vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
@ -938,6 +993,7 @@ int mtk_vcodec_dec_queue_init(void *priv, struct vb2_queue *src_vq,
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
src_vq->lock = &ctx->dev->dev_mutex;
src_vq->dev = &ctx->dev->plat_dev->dev;
src_vq->allow_cache_hints = 1;
ret = vb2_queue_init(src_vq);
if (ret) {
@ -953,6 +1009,7 @@ int mtk_vcodec_dec_queue_init(void *priv, struct vb2_queue *src_vq,
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
dst_vq->lock = &ctx->dev->dev_mutex;
dst_vq->dev = &ctx->dev->plat_dev->dev;
dst_vq->allow_cache_hints = 1;
ret = vb2_queue_init(dst_vq);
if (ret)

13
drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c
View File

@ -208,9 +208,12 @@ static int fops_vcodec_open(struct file *file)
dev->dec_capability =
mtk_vcodec_fw_get_vdec_capa(dev->fw_handler);
mtk_v4l2_debug(0, "decoder capability %x", dev->dec_capability);
}
ctx->dev->vdec_pdata->init_vdec_params(ctx);
list_add(&ctx->list, &dev->ctx_list);
mutex_unlock(&dev->dev_mutex);
@ -386,8 +389,14 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
mtk_v4l2_err("Main device of_platform_populate failed.");
goto err_reg_cont;
}
} else {
set_bit(MTK_VDEC_CORE, dev->subdev_bitmap);
}
atomic_set(&dev->dec_active_cnt, 0);
memset(dev->vdec_racing_info, 0, sizeof(dev->vdec_racing_info));
mutex_init(&dev->dec_racing_info_mutex);
ret = video_register_device(vfd_dec, VFL_TYPE_VIDEO, -1);
if (ret) {
mtk_v4l2_err("Failed to register video device");
@ -465,6 +474,10 @@ static const struct of_device_id mtk_vcodec_match[] = {
.compatible = "mediatek,mt8186-vcodec-dec",
.data = &mtk_vdec_single_core_pdata,
},
{
.compatible = "mediatek,mt8195-vcodec-dec",
.data = &mtk_lat_sig_core_pdata,
},
{},
};

12
drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c
View File

@ -28,6 +28,10 @@ static const struct of_device_id mtk_vdec_hw_match[] = {
.compatible = "mediatek,mtk-vcodec-core",
.data = (void *)MTK_VDEC_CORE,
},
{
.compatible = "mediatek,mtk-vcodec-lat-soc",
.data = (void *)MTK_VDEC_LAT_SOC,
},
{},
};
MODULE_DEVICE_TABLE(of, mtk_vdec_hw_match);
@ -166,9 +170,11 @@ static int mtk_vdec_hw_probe(struct platform_device *pdev)
subdev_dev->reg_base[VDEC_HW_SYS] = main_dev->reg_base[VDEC_HW_SYS];
set_bit(subdev_dev->hw_idx, main_dev->subdev_bitmap);
ret = mtk_vdec_hw_init_irq(subdev_dev);
if (ret)
goto err;
if (IS_SUPPORT_VDEC_HW_IRQ(hw_idx)) {
ret = mtk_vdec_hw_init_irq(subdev_dev);
if (ret)
goto err;
}
subdev_dev->reg_base[VDEC_HW_MISC] =
devm_platform_ioremap_resource(pdev, 0);

2
drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h
View File

@ -17,6 +17,8 @@
#define VDEC_IRQ_CLR 0x10
#define VDEC_IRQ_CFG_REG 0xa4
#define IS_SUPPORT_VDEC_HW_IRQ(hw_idx) ((hw_idx) != MTK_VDEC_LAT_SOC)
/**
* enum mtk_vdec_hw_reg_idx - subdev hardware register base index
* @VDEC_HW_SYS : vdec soc register index

50
drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c
View File

@ -144,6 +144,34 @@ static void mtk_vcodec_dec_disable_irq(struct mtk_vcodec_dev *vdec_dev, int hw_i
}
}
static void mtk_vcodec_load_racing_info(struct mtk_vcodec_ctx *ctx)
{
void __iomem *vdec_racing_addr;
int j;
mutex_lock(&ctx->dev->dec_racing_info_mutex);
if (atomic_inc_return(&ctx->dev->dec_active_cnt) == 1) {
vdec_racing_addr = ctx->dev->reg_base[VDEC_MISC] + 0x100;
for (j = 0; j < 132; j++)
writel(ctx->dev->vdec_racing_info[j], vdec_racing_addr + j * 4);
}
mutex_unlock(&ctx->dev->dec_racing_info_mutex);
}
static void mtk_vcodec_record_racing_info(struct mtk_vcodec_ctx *ctx)
{
void __iomem *vdec_racing_addr;
int j;
mutex_lock(&ctx->dev->dec_racing_info_mutex);
if (atomic_dec_and_test(&ctx->dev->dec_active_cnt)) {
vdec_racing_addr = ctx->dev->reg_base[VDEC_MISC] + 0x100;
for (j = 0; j < 132; j++)
ctx->dev->vdec_racing_info[j] = readl(vdec_racing_addr + j * 4);
}
mutex_unlock(&ctx->dev->dec_racing_info_mutex);
}
static struct mtk_vcodec_pm *mtk_vcodec_dec_get_pm(struct mtk_vcodec_dev *vdec_dev,
int hw_idx)
{
@ -174,6 +202,14 @@ static void mtk_vcodec_dec_child_dev_on(struct mtk_vcodec_dev *vdec_dev,
mtk_vcodec_dec_pw_on(pm);
mtk_vcodec_dec_clock_on(pm);
}
if (hw_idx == MTK_VDEC_LAT0) {
pm = mtk_vcodec_dec_get_pm(vdec_dev, MTK_VDEC_LAT_SOC);
if (pm) {
mtk_vcodec_dec_pw_on(pm);
mtk_vcodec_dec_clock_on(pm);
}
}
}
static void mtk_vcodec_dec_child_dev_off(struct mtk_vcodec_dev *vdec_dev,
@ -186,6 +222,14 @@ static void mtk_vcodec_dec_child_dev_off(struct mtk_vcodec_dev *vdec_dev,
mtk_vcodec_dec_clock_off(pm);
mtk_vcodec_dec_pw_off(pm);
}
if (hw_idx == MTK_VDEC_LAT0) {
pm = mtk_vcodec_dec_get_pm(vdec_dev, MTK_VDEC_LAT_SOC);
if (pm) {
mtk_vcodec_dec_clock_off(pm);
mtk_vcodec_dec_pw_off(pm);
}
}
}
void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx)
@ -198,11 +242,17 @@ void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx)
mtk_vcodec_dec_child_dev_on(ctx->dev, hw_idx);
mtk_vcodec_dec_enable_irq(ctx->dev, hw_idx);
if (IS_VDEC_INNER_RACING(ctx->dev->dec_capability))
mtk_vcodec_load_racing_info(ctx);
}
EXPORT_SYMBOL_GPL(mtk_vcodec_dec_enable_hardware);
void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx)
{
if (IS_VDEC_INNER_RACING(ctx->dev->dec_capability))
mtk_vcodec_record_racing_info(ctx);
mtk_vcodec_dec_disable_irq(ctx->dev, hw_idx);
mtk_vcodec_dec_child_dev_off(ctx->dev, hw_idx);

29
drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c
View File

@ -17,18 +17,24 @@ static const struct mtk_video_fmt mtk_video_formats[] = {
.type = MTK_FMT_DEC,
.num_planes = 1,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION,
.frmsize = { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16,
MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 },
},
{
.fourcc = V4L2_PIX_FMT_VP8,
.type = MTK_FMT_DEC,
.num_planes = 1,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION,
.frmsize = { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16,
MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 },
},
{
.fourcc = V4L2_PIX_FMT_VP9,
.type = MTK_FMT_DEC,
.num_planes = 1,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION,
.frmsize = { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16,
MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 },
},
{
.fourcc = V4L2_PIX_FMT_MT21C,
@ -43,27 +49,6 @@ static const unsigned int num_supported_formats =
#define DEFAULT_OUT_FMT_IDX 0
#define DEFAULT_CAP_FMT_IDX 3
static const struct mtk_codec_framesizes mtk_vdec_framesizes[] = {
{
.fourcc = V4L2_PIX_FMT_H264,
.stepwise = { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16,
MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 },
},
{
.fourcc = V4L2_PIX_FMT_VP8,
.stepwise = { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16,
MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 },
},
{
.fourcc = V4L2_PIX_FMT_VP9,
.stepwise = { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16,
MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 },
},
};
static const unsigned int num_supported_framesize =
ARRAY_SIZE(mtk_vdec_framesizes);
/*
* This function tries to clean all display buffers, the buffers will return
* in display order.
@ -618,8 +603,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = {
.num_formats = &num_supported_formats,
.default_out_fmt = &mtk_video_formats[DEFAULT_OUT_FMT_IDX],
.default_cap_fmt = &mtk_video_formats[DEFAULT_CAP_FMT_IDX],
.vdec_framesizes = mtk_vdec_framesizes,
.num_framesizes = &num_supported_framesize,
.worker = mtk_vdec_worker,
.flush_decoder = mtk_vdec_flush_decoder,
.is_subdev_supported = false,

28
drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c
View File

@ -112,14 +112,12 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = {
#define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls)
static struct mtk_video_fmt mtk_video_formats[5];
static struct mtk_codec_framesizes mtk_vdec_framesizes[3];
static struct mtk_video_fmt default_out_format;
static struct mtk_video_fmt default_cap_format;
static unsigned int num_formats;
static unsigned int num_framesizes;
static struct v4l2_frmsize_stepwise stepwise_fhd = {
static const struct v4l2_frmsize_stepwise stepwise_fhd = {
.min_width = MTK_VDEC_MIN_W,
.max_width = MTK_VDEC_MAX_W,
.step_width = 16,
@ -348,7 +346,6 @@ static void mtk_vcodec_add_formats(unsigned int fourcc,
struct mtk_vcodec_dev *dev = ctx->dev;
const struct mtk_vcodec_dec_pdata *pdata = dev->vdec_pdata;
int count_formats = *pdata->num_formats;
int count_framesizes = *pdata->num_framesizes;
switch (fourcc) {
case V4L2_PIX_FMT_H264_SLICE:
@ -357,10 +354,15 @@ static void mtk_vcodec_add_formats(unsigned int fourcc,
mtk_video_formats[count_formats].fourcc = fourcc;
mtk_video_formats[count_formats].type = MTK_FMT_DEC;
mtk_video_formats[count_formats].num_planes = 1;
mtk_video_formats[count_formats].frmsize = stepwise_fhd;
mtk_vdec_framesizes[count_framesizes].fourcc = fourcc;
mtk_vdec_framesizes[count_framesizes].stepwise = stepwise_fhd;
num_framesizes++;
if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED) &&
fourcc != V4L2_PIX_FMT_VP8_FRAME) {
mtk_video_formats[count_formats].frmsize.max_width =
VCODEC_DEC_4K_CODED_WIDTH;
mtk_video_formats[count_formats].frmsize.max_height =
VCODEC_DEC_4K_CODED_HEIGHT;
}
break;
case V4L2_PIX_FMT_MM21:
case V4L2_PIX_FMT_MT21C:
@ -374,15 +376,15 @@ static void mtk_vcodec_add_formats(unsigned int fourcc,
}
num_formats++;
mtk_v4l2_debug(3, "num_formats: %d num_frames:%d dec_capability: 0x%x",
count_formats, count_framesizes, ctx->dev->dec_capability);
mtk_v4l2_debug(3, "num_formats: %d dec_capability: 0x%x",
count_formats, ctx->dev->dec_capability);
}
static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_ctx *ctx)
{
int cap_format_count = 0, out_format_count = 0;
if (num_formats && num_framesizes)
if (num_formats)
return;
if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) {
@ -461,8 +463,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = {
.num_formats = &num_formats,
.default_out_fmt = &default_out_format,
.default_cap_fmt = &default_cap_format,
.vdec_framesizes = mtk_vdec_framesizes,
.num_framesizes = &num_framesizes,
.uses_stateless_api = true,
.worker = mtk_vdec_worker,
.flush_decoder = mtk_vdec_flush_decoder,
@ -481,8 +481,6 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata = {
.num_formats = &num_formats,
.default_out_fmt = &default_out_format,
.default_cap_fmt = &default_cap_format,
.vdec_framesizes = mtk_vdec_framesizes,
.num_framesizes = &num_framesizes,
.uses_stateless_api = true,
.worker = mtk_vdec_worker,
.flush_decoder = mtk_vdec_flush_decoder,
@ -500,8 +498,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = {
.num_formats = &num_formats,
.default_out_fmt = &default_out_format,
.default_cap_fmt = &default_cap_format,
.vdec_framesizes = mtk_vdec_framesizes,
.num_framesizes = &num_framesizes,
.uses_stateless_api = true,
.worker = mtk_vdec_worker,
.flush_decoder = mtk_vdec_flush_decoder,

36
drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h
View File

@ -19,15 +19,14 @@
#include "mtk_vcodec_util.h"
#include "vdec_msg_queue.h"
#define MTK_VCODEC_DRV_NAME "mtk_vcodec_drv"
#define MTK_VCODEC_DEC_NAME "mtk-vcodec-dec"
#define MTK_VCODEC_ENC_NAME "mtk-vcodec-enc"
#define MTK_PLATFORM_STR "platform:mt8173"
#define MTK_VCODEC_MAX_PLANES 3
#define MTK_V4L2_BENCHMARK 0
#define WAIT_INTR_TIMEOUT_MS 1000
#define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >= MTK_VDEC_LAT_SINGLE_CORE)
#define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_RACING)
/*
* enum mtk_hw_reg_idx - MTK hw register base index
@ -104,6 +103,7 @@ enum mtk_vdec_hw_id {
MTK_VDEC_CORE,
MTK_VDEC_LAT0,
MTK_VDEC_LAT1,
MTK_VDEC_LAT_SOC,
MTK_VDEC_HW_MAX,
};
@ -125,15 +125,7 @@ struct mtk_video_fmt {
enum mtk_fmt_type type;
u32 num_planes;
u32 flags;
};
/*
* struct mtk_codec_framesizes - Structure used to store information about
* framesizes
*/
struct mtk_codec_framesizes {
u32 fourcc;
struct v4l2_frmsize_stepwise stepwise;
struct v4l2_frmsize_stepwise frmsize;
};
/*
@ -255,7 +247,7 @@ struct vdec_pic_info {
* @param_change: indicate encode parameter type
* @enc_params: encoding parameters
* @dec_if: hooked decoder driver interface
* @enc_if: hoooked encoder driver interface
* @enc_if: hooked encoder driver interface
* @drv_handle: driver handle for specific decode/encode instance
*
* @picinfo: store picture info after header parsing
@ -285,8 +277,6 @@ struct vdec_pic_info {
* mtk_video_dec_buf.
* @hw_id: hardware index used to identify different hardware.
*
* @max_width: hardware supported max width
* @max_height: hardware supported max height
* @msg_queue: msg queue used to store lat buffer information.
*/
struct mtk_vcodec_ctx {
@ -333,8 +323,6 @@ struct mtk_vcodec_ctx {
struct mutex lock;
int hw_id;
unsigned int max_width;
unsigned int max_height;
struct vdec_msg_queue msg_queue;
};
@ -356,6 +344,7 @@ enum mtk_vdec_format_types {
MTK_VDEC_FORMAT_H264_SLICE = 0x100,
MTK_VDEC_FORMAT_VP8_FRAME = 0x200,
MTK_VDEC_FORMAT_VP9_FRAME = 0x400,
MTK_VCODEC_INNER_RACING = 0x20000,
};
/**
@ -373,9 +362,6 @@ enum mtk_vdec_format_types {
* @default_out_fmt: default output buffer format
* @default_cap_fmt: default capture buffer format
*
* @vdec_framesizes: supported video decoder frame sizes
* @num_framesizes: count of video decoder frame sizes
*
* @hw_arch: hardware arch is used to separate pure_sin_core and lat_sin_core
*
* @is_subdev_supported: whether support parent-node architecture(subdev)
@ -398,9 +384,6 @@ struct mtk_vcodec_dec_pdata {
const struct mtk_video_fmt *default_out_fmt;
const struct mtk_video_fmt *default_cap_fmt;
const struct mtk_codec_framesizes *vdec_framesizes;
const int *num_framesizes;
enum mtk_vdec_hw_arch hw_arch;
bool is_subdev_supported;
@ -477,6 +460,10 @@ struct mtk_vcodec_enc_pdata {
* @subdev_dev: subdev hardware device
* @subdev_prob_done: check whether all used hw device is prob done
* @subdev_bitmap: used to record hardware is ready or not
*
* @dec_active_cnt: used to mark whether need to record register value
* @vdec_racing_info: record register value
* @dec_racing_info_mutex: mutex lock used for inner racing mode
*/
struct mtk_vcodec_dev {
struct v4l2_device v4l2_dev;
@ -522,6 +509,11 @@ struct mtk_vcodec_dev {
void *subdev_dev[MTK_VDEC_HW_MAX];
int (*subdev_prob_done)(struct mtk_vcodec_dev *vdec_dev);
DECLARE_BITMAP(subdev_bitmap, MTK_VDEC_HW_MAX);
atomic_t dec_active_cnt;
u32 vdec_racing_info[132];
/* Protects access to vdec_racing_info data */
struct mutex dec_racing_info_mutex;
};
static inline struct mtk_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)

37
drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c
View File

@ -50,6 +50,14 @@ static int vidioc_venc_s_ctrl(struct v4l2_ctrl *ctrl)
int ret = 0;
switch (ctrl->id) {
case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
mtk_v4l2_debug(2, "V4L2_CID_MPEG_VIDEO_BITRATE_MODE val= %d",
ctrl->val);
if (ctrl->val != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) {
mtk_v4l2_err("Unsupported bitrate mode =%d", ctrl->val);
ret = -EINVAL;
}
break;
case V4L2_CID_MPEG_VIDEO_BITRATE:
mtk_v4l2_debug(2, "V4L2_CID_MPEG_VIDEO_BITRATE val = %d",
ctrl->val);
@ -204,12 +212,32 @@ static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
pdata->num_output_formats);
}
static int mtk_vcodec_enc_get_chip_name(void *priv)
{
struct mtk_vcodec_ctx *ctx = fh_to_ctx(priv);
struct device *dev = &ctx->dev->plat_dev->dev;
if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-enc"))
return 8173;
else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-enc"))
return 8183;
else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-enc"))
return 8192;
else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-enc"))
return 8195;
else
return 8173;
}
static int vidioc_venc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
strscpy(cap->driver, MTK_VCODEC_ENC_NAME, sizeof(cap->driver));
strscpy(cap->bus_info, MTK_PLATFORM_STR, sizeof(cap->bus_info));
strscpy(cap->card, MTK_PLATFORM_STR, sizeof(cap->card));
struct mtk_vcodec_ctx *ctx = fh_to_ctx(priv);
struct device *dev = &ctx->dev->plat_dev->dev;
int platform_name = mtk_vcodec_enc_get_chip_name(priv);
strscpy(cap->driver, dev->driver->name, sizeof(cap->driver));
snprintf(cap->card, sizeof(cap->card), "MT%d video encoder", platform_name);
return 0;
}
@ -1373,6 +1401,9 @@ int mtk_vcodec_enc_ctrls_setup(struct mtk_vcodec_ctx *ctx)
0, V4L2_MPEG_VIDEO_H264_LEVEL_4_0);
v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_MPEG_VIDEO_VP8_PROFILE,
V4L2_MPEG_VIDEO_VP8_PROFILE_0, 0, V4L2_MPEG_VIDEO_VP8_PROFILE_0);
v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
0, V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
if (handler->error) {

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