forked from Minki/linux
x86: cpu make amd.c more like amd_64.c v2
1. make 32bit have early_init_amd_mc and amd_detect_cmp 2. seperate init_amd_k5/k6/k7 ... v2: fix compiling for !CONFIG_SMP Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
parent
2d9cd6c27f
commit
11fdd252bb
@ -24,8 +24,200 @@
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extern void vide(void);
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__asm__(".align 4\nvide: ret");
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static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
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{
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/*
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* General Systems BIOSen alias the cpu frequency registers
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* of the Elan at 0x000df000. Unfortuantly, one of the Linux
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* drivers subsequently pokes it, and changes the CPU speed.
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* Workaround : Remove the unneeded alias.
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*/
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#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
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#define CBAR_ENB (0x80000000)
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#define CBAR_KEY (0X000000CB)
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if (c->x86_model == 9 || c->x86_model == 10) {
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if (inl (CBAR) & CBAR_ENB)
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outl (0 | CBAR_KEY, CBAR);
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}
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}
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static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int mbytes = num_physpages >> (20-PAGE_SHIFT);
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if (c->x86_model < 6) {
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/* Based on AMD doc 20734R - June 2000 */
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if (c->x86_model == 0) {
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clear_cpu_cap(c, X86_FEATURE_APIC);
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set_cpu_cap(c, X86_FEATURE_PGE);
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}
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return;
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}
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if (c->x86_model == 6 && c->x86_mask == 1) {
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const int K6_BUG_LOOP = 1000000;
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int n;
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void (*f_vide)(void);
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unsigned long d, d2;
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printk(KERN_INFO "AMD K6 stepping B detected - ");
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/*
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* It looks like AMD fixed the 2.6.2 bug and improved indirect
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* calls at the same time.
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*/
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n = K6_BUG_LOOP;
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f_vide = vide;
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rdtscl(d);
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while (n--)
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f_vide();
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rdtscl(d2);
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d = d2-d;
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if (d > 20*K6_BUG_LOOP)
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printk("system stability may be impaired when more than 32 MB are used.\n");
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else
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printk("probably OK (after B9730xxxx).\n");
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printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
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}
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/* K6 with old style WHCR */
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if (c->x86_model < 8 ||
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(c->x86_model == 8 && c->x86_mask < 8)) {
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/* We can only write allocate on the low 508Mb */
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if (mbytes > 508)
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mbytes = 508;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0x0000FFFF) == 0) {
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unsigned long flags;
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l = (1<<0)|((mbytes/4)<<1);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
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mbytes);
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}
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return;
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}
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if ((c->x86_model == 8 && c->x86_mask > 7) ||
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c->x86_model == 9 || c->x86_model == 13) {
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/* The more serious chips .. */
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if (mbytes > 4092)
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mbytes = 4092;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0xFFFF0000) == 0) {
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unsigned long flags;
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l = ((mbytes>>2)<<22)|(1<<16);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
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mbytes);
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}
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return;
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}
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if (c->x86_model == 10) {
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/* AMD Geode LX is model 10 */
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/* placeholder for any needed mods */
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return;
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}
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}
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static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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/*
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* Bit 15 of Athlon specific MSR 15, needs to be 0
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* to enable SSE on Palomino/Morgan/Barton CPU's.
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* If the BIOS didn't enable it already, enable it here.
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*/
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if (c->x86_model >= 6 && c->x86_model <= 10) {
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if (!cpu_has(c, X86_FEATURE_XMM)) {
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printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
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rdmsr(MSR_K7_HWCR, l, h);
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l &= ~0x00008000;
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wrmsr(MSR_K7_HWCR, l, h);
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set_cpu_cap(c, X86_FEATURE_XMM);
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}
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}
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/*
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* It's been determined by AMD that Athlons since model 8 stepping 1
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* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
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* As per AMD technical note 27212 0.2
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*/
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if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
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rdmsr(MSR_K7_CLK_CTL, l, h);
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if ((l & 0xfff00000) != 0x20000000) {
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printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
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((l & 0x000fffff)|0x20000000));
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wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
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}
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}
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set_cpu_cap(c, X86_FEATURE_K7);
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}
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/*
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* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
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* Assumes number of cores is a power of two.
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*/
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static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_HT
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unsigned bits;
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bits = c->x86_coreid_bits;
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/* Low order bits define the core id (index of core in socket) */
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c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
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/* Convert the initial APIC ID into the socket ID */
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c->phys_proc_id = c->initial_apicid >> bits;
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#endif
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}
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static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_HT
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unsigned bits, ecx;
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/* Multi core CPU? */
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if (c->extended_cpuid_level < 0x80000008)
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return;
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ecx = cpuid_ecx(0x80000008);
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c->x86_max_cores = (ecx & 0xff) + 1;
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/* CPU telling us the core id bits shift? */
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bits = (ecx >> 12) & 0xF;
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/* Otherwise recompute */
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if (bits == 0) {
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while ((1 << bits) < c->x86_max_cores)
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bits++;
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}
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c->x86_coreid_bits = bits;
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#endif
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}
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static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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{
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early_init_amd_mc(c);
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if (c->x86_power & (1<<8))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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@ -37,9 +229,6 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int mbytes = num_physpages >> (20-PAGE_SHIFT);
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#ifdef CONFIG_SMP
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unsigned long long value;
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@ -50,7 +239,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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* Errata 63 for SH-B3 steppings
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* Errata 122 for all steppings (F+ have it disabled by default)
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*/
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if (c->x86 == 15) {
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if (c->x86 == 0xf) {
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rdmsrl(MSR_K7_HWCR, value);
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value |= 1 << 6;
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wrmsrl(MSR_K7_HWCR, value);
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@ -73,192 +262,55 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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switch (c->x86) {
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case 4:
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/*
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* General Systems BIOSen alias the cpu frequency registers
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* of the Elan at 0x000df000. Unfortuantly, one of the Linux
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* drivers subsequently pokes it, and changes the CPU speed.
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* Workaround : Remove the unneeded alias.
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*/
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#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
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#define CBAR_ENB (0x80000000)
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#define CBAR_KEY (0X000000CB)
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if (c->x86_model == 9 || c->x86_model == 10) {
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if (inl (CBAR) & CBAR_ENB)
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outl (0 | CBAR_KEY, CBAR);
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}
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break;
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init_amd_k5(c);
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break;
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case 5:
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if (c->x86_model < 6) {
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/* Based on AMD doc 20734R - June 2000 */
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if (c->x86_model == 0) {
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clear_cpu_cap(c, X86_FEATURE_APIC);
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set_cpu_cap(c, X86_FEATURE_PGE);
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}
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break;
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}
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if (c->x86_model == 6 && c->x86_mask == 1) {
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const int K6_BUG_LOOP = 1000000;
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int n;
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void (*f_vide)(void);
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unsigned long d, d2;
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printk(KERN_INFO "AMD K6 stepping B detected - ");
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/*
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* It looks like AMD fixed the 2.6.2 bug and improved indirect
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* calls at the same time.
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*/
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n = K6_BUG_LOOP;
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f_vide = vide;
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rdtscl(d);
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while (n--)
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f_vide();
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rdtscl(d2);
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d = d2-d;
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if (d > 20*K6_BUG_LOOP)
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printk("system stability may be impaired when more than 32 MB are used.\n");
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else
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printk("probably OK (after B9730xxxx).\n");
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printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
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}
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/* K6 with old style WHCR */
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if (c->x86_model < 8 ||
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(c->x86_model == 8 && c->x86_mask < 8)) {
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/* We can only write allocate on the low 508Mb */
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if (mbytes > 508)
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mbytes = 508;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0x0000FFFF) == 0) {
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unsigned long flags;
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l = (1<<0)|((mbytes/4)<<1);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
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mbytes);
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}
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break;
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}
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if ((c->x86_model == 8 && c->x86_mask > 7) ||
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c->x86_model == 9 || c->x86_model == 13) {
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/* The more serious chips .. */
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if (mbytes > 4092)
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mbytes = 4092;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0xFFFF0000) == 0) {
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unsigned long flags;
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l = ((mbytes>>2)<<22)|(1<<16);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
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mbytes);
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}
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break;
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}
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if (c->x86_model == 10) {
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/* AMD Geode LX is model 10 */
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/* placeholder for any needed mods */
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break;
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}
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break;
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init_amd_k6(c);
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break;
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case 6: /* An Athlon/Duron */
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/*
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* Bit 15 of Athlon specific MSR 15, needs to be 0
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* to enable SSE on Palomino/Morgan/Barton CPU's.
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* If the BIOS didn't enable it already, enable it here.
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*/
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if (c->x86_model >= 6 && c->x86_model <= 10) {
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if (!cpu_has(c, X86_FEATURE_XMM)) {
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printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
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rdmsr(MSR_K7_HWCR, l, h);
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l &= ~0x00008000;
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wrmsr(MSR_K7_HWCR, l, h);
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set_cpu_cap(c, X86_FEATURE_XMM);
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}
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}
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/*
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* It's been determined by AMD that Athlons since model 8 stepping 1
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* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
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* As per AMD technical note 27212 0.2
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*/
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if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
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rdmsr(MSR_K7_CLK_CTL, l, h);
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if ((l & 0xfff00000) != 0x20000000) {
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printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
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((l & 0x000fffff)|0x20000000));
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wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
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}
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}
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break;
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}
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switch (c->x86) {
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case 15:
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/* Use K8 tuning for Fam10h and Fam11h */
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case 0x10:
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case 0x11:
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set_cpu_cap(c, X86_FEATURE_K8);
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init_amd_k7(c);
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break;
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case 6:
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set_cpu_cap(c, X86_FEATURE_K7);
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break;
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}
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if (c->x86 >= 6)
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set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
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display_cacheinfo(c);
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if (cpuid_eax(0x80000000) >= 0x80000008)
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c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
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#ifdef CONFIG_X86_HT
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/*
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* On a AMD multi core setup the lower bits of the APIC id
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* distinguish the cores.
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*/
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if (c->x86_max_cores > 1) {
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int cpu = smp_processor_id();
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unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
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if (bits == 0) {
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while ((1 << bits) < c->x86_max_cores)
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bits++;
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}
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c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
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c->phys_proc_id >>= bits;
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printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
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cpu, c->x86_max_cores, c->cpu_core_id);
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}
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#endif
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if (cpuid_eax(0x80000000) >= 0x80000006) {
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if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
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num_cache_leaves = 4;
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else
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num_cache_leaves = 3;
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}
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/* K6s reports MCEs but don't actually have all the MSRs */
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if (c->x86 < 6)
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clear_cpu_cap(c, X86_FEATURE_MCE);
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if (cpu_has_xmm2)
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if (c->x86 >= 6)
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set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
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if (!c->x86_model_id[0]) {
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switch (c->x86) {
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case 0xf:
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/* Should distinguish Models here, but this is only
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a fallback anyways. */
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strcpy(c->x86_model_id, "Hammer");
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break;
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}
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}
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display_cacheinfo(c);
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/* Multi core CPU? */
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if (c->extended_cpuid_level >= 0x80000008)
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amd_detect_cmp(c);
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detect_ht(c);
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if (c->extended_cpuid_level >= 0x80000006) {
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if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
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num_cache_leaves = 4;
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else
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num_cache_leaves = 3;
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}
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if (c->x86 >= 0xf && c->x86 <= 0x11)
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set_cpu_cap(c, X86_FEATURE_K8);
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if (cpu_has_xmm2) {
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/* MFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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}
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}
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static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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@ -174,17 +174,20 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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if (c->extended_cpuid_level >= 0x80000008)
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amd_detect_cmp(c);
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if (c->extended_cpuid_level >= 0x80000006 &&
|
||||
(cpuid_edx(0x80000006) & 0xf000))
|
||||
num_cache_leaves = 4;
|
||||
else
|
||||
num_cache_leaves = 3;
|
||||
if (c->extended_cpuid_level >= 0x80000006) {
|
||||
if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
|
||||
num_cache_leaves = 4;
|
||||
else
|
||||
num_cache_leaves = 3;
|
||||
}
|
||||
|
||||
if (c->x86 >= 0xf && c->x86 <= 0x11)
|
||||
set_cpu_cap(c, X86_FEATURE_K8);
|
||||
|
||||
/* MFENCE stops RDTSC speculation */
|
||||
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
|
||||
if (cpu_has_xmm2) {
|
||||
/* MFENCE stops RDTSC speculation */
|
||||
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
|
||||
}
|
||||
|
||||
if (c->x86 == 0x10) {
|
||||
/* do this for boot cpu */
|
||||
|
||||
@ -629,8 +629,8 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
|
||||
c->x86_vendor_id[0] = '\0'; /* Unset */
|
||||
c->x86_model_id[0] = '\0'; /* Unset */
|
||||
c->x86_max_cores = 1;
|
||||
#ifdef CONFIG_X86_64
|
||||
c->x86_coreid_bits = 0;
|
||||
#ifdef CONFIG_X86_64
|
||||
c->x86_clflush_size = 64;
|
||||
#else
|
||||
c->cpuid_level = -1; /* CPUID not detected */
|
||||
|
||||
@ -75,9 +75,9 @@ struct cpuinfo_x86 {
|
||||
int x86_tlbsize;
|
||||
__u8 x86_virt_bits;
|
||||
__u8 x86_phys_bits;
|
||||
#endif
|
||||
/* CPUID returned core id bits: */
|
||||
__u8 x86_coreid_bits;
|
||||
#endif
|
||||
/* Max extended CPUID function supported: */
|
||||
__u32 extended_cpuid_level;
|
||||
/* Maximum supported CPUID level, -1=no CPUID: */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user